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-rw-r--r--drivers/clk/tegra/clk-tegra20.c657
1 files changed, 255 insertions, 402 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 7c9af8e2c33b..be5bdbab78a6 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -22,8 +22,10 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/tegra.h> 23#include <linux/clk/tegra.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <dt-bindings/clock/tegra20-car.h>
25 26
26#include "clk.h" 27#include "clk.h"
28#include "clk-id.h"
27 29
28#define OSC_CTRL 0x50 30#define OSC_CTRL 0x50
29#define OSC_CTRL_OSC_FREQ_MASK (3<<30) 31#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
@@ -94,34 +96,15 @@
94 96
95#define CLK_SOURCE_I2S1 0x100 97#define CLK_SOURCE_I2S1 0x100
96#define CLK_SOURCE_I2S2 0x104 98#define CLK_SOURCE_I2S2 0x104
97#define CLK_SOURCE_SPDIF_OUT 0x108
98#define CLK_SOURCE_SPDIF_IN 0x10c
99#define CLK_SOURCE_PWM 0x110 99#define CLK_SOURCE_PWM 0x110
100#define CLK_SOURCE_SPI 0x114 100#define CLK_SOURCE_SPI 0x114
101#define CLK_SOURCE_SBC1 0x134
102#define CLK_SOURCE_SBC2 0x118
103#define CLK_SOURCE_SBC3 0x11c
104#define CLK_SOURCE_SBC4 0x1b4
105#define CLK_SOURCE_XIO 0x120 101#define CLK_SOURCE_XIO 0x120
106#define CLK_SOURCE_TWC 0x12c 102#define CLK_SOURCE_TWC 0x12c
107#define CLK_SOURCE_IDE 0x144 103#define CLK_SOURCE_IDE 0x144
108#define CLK_SOURCE_NDFLASH 0x160
109#define CLK_SOURCE_VFIR 0x168
110#define CLK_SOURCE_SDMMC1 0x150
111#define CLK_SOURCE_SDMMC2 0x154
112#define CLK_SOURCE_SDMMC3 0x1bc
113#define CLK_SOURCE_SDMMC4 0x164
114#define CLK_SOURCE_CVE 0x140
115#define CLK_SOURCE_TVO 0x188
116#define CLK_SOURCE_TVDAC 0x194
117#define CLK_SOURCE_HDMI 0x18c 104#define CLK_SOURCE_HDMI 0x18c
118#define CLK_SOURCE_DISP1 0x138 105#define CLK_SOURCE_DISP1 0x138
119#define CLK_SOURCE_DISP2 0x13c 106#define CLK_SOURCE_DISP2 0x13c
120#define CLK_SOURCE_CSITE 0x1d4 107#define CLK_SOURCE_CSITE 0x1d4
121#define CLK_SOURCE_LA 0x1f8
122#define CLK_SOURCE_OWR 0x1cc
123#define CLK_SOURCE_NOR 0x1d0
124#define CLK_SOURCE_MIPI 0x174
125#define CLK_SOURCE_I2C1 0x124 108#define CLK_SOURCE_I2C1 0x124
126#define CLK_SOURCE_I2C2 0x198 109#define CLK_SOURCE_I2C2 0x198
127#define CLK_SOURCE_I2C3 0x1b8 110#define CLK_SOURCE_I2C3 0x1b8
@@ -131,24 +114,10 @@
131#define CLK_SOURCE_UARTC 0x1a0 114#define CLK_SOURCE_UARTC 0x1a0
132#define CLK_SOURCE_UARTD 0x1c0 115#define CLK_SOURCE_UARTD 0x1c0
133#define CLK_SOURCE_UARTE 0x1c4 116#define CLK_SOURCE_UARTE 0x1c4
134#define CLK_SOURCE_3D 0x158
135#define CLK_SOURCE_2D 0x15c
136#define CLK_SOURCE_MPE 0x170
137#define CLK_SOURCE_EPP 0x16c
138#define CLK_SOURCE_HOST1X 0x180
139#define CLK_SOURCE_VDE 0x1c8
140#define CLK_SOURCE_VI 0x148
141#define CLK_SOURCE_VI_SENSOR 0x1a8
142#define CLK_SOURCE_EMC 0x19c 117#define CLK_SOURCE_EMC 0x19c
143 118
144#define AUDIO_SYNC_CLK 0x38 119#define AUDIO_SYNC_CLK 0x38
145 120
146#define PMC_CTRL 0x0
147#define PMC_CTRL_BLINK_ENB 7
148#define PMC_DPD_PADS_ORIDE 0x1c
149#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
150#define PMC_BLINK_TIMER 0x40
151
152/* Tegra CPU clock and reset control regs */ 121/* Tegra CPU clock and reset control regs */
153#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 122#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
154#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 123#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
@@ -171,57 +140,28 @@ static struct cpu_clk_suspend_context {
171static void __iomem *clk_base; 140static void __iomem *clk_base;
172static void __iomem *pmc_base; 141static void __iomem *pmc_base;
173 142
174static DEFINE_SPINLOCK(pll_div_lock); 143#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
175static DEFINE_SPINLOCK(sysrate_lock);
176
177#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
178 _clk_num, _gate_flags, _clk_id) \ 144 _clk_num, _gate_flags, _clk_id) \
179 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 145 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
180 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 146 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
181 _clk_num, \ 147 _clk_num, \
182 _gate_flags, _clk_id) 148 _gate_flags, _clk_id)
183 149
184#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 150#define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
185 _clk_num, _gate_flags, _clk_id) \
186 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
187 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, \
188 _clk_num, _gate_flags, \
189 _clk_id)
190
191#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
192 _clk_num, _gate_flags, _clk_id) \ 151 _clk_num, _gate_flags, _clk_id) \
193 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 152 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
194 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 153 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
195 _clk_num, _gate_flags, \ 154 _clk_num, _gate_flags, \
196 _clk_id) 155 _clk_id)
197 156
198#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 157#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
199 _mux_shift, _mux_width, _clk_num, \ 158 _mux_shift, _mux_width, _clk_num, \
200 _gate_flags, _clk_id) \ 159 _gate_flags, _clk_id) \
201 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 160 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
202 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \ 161 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
203 _clk_num, _gate_flags, \ 162 _clk_num, _gate_flags, \
204 _clk_id) 163 _clk_id)
205 164
206/* IDs assigned here must be in sync with DT bindings definition
207 * for Tegra20 clocks .
208 */
209enum tegra20_clk {
210 cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
211 ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
212 gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
213 kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
214 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
215 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
216 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
217 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
218 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
219 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
220 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
221 pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u,
222 pll_x, cop, audio, pll_ref, twd, clk_max,
223};
224
225static struct clk **clks; 165static struct clk **clks;
226 166
227static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 167static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
@@ -485,6 +425,157 @@ static struct tegra_clk_pll_params pll_e_params = {
485 .fixed_rate = 100000000, 425 .fixed_rate = 100000000,
486}; 426};
487 427
428static struct tegra_devclk devclks[] __initdata = {
429 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
430 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
431 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
432 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
433 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
434 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
435 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
436 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
437 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
438 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
439 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
440 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
441 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
442 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
443 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
444 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
445 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
446 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
447 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
448 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
449 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
450 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
451 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
452 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
453 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
454 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
455 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
456 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
457 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
458 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
459 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
460 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
461 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
462 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
463 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
464 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
465 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
466 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
467 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
468 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
469 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
470 { .con_id = "pcie_xclk", .dt_id = TEGRA20_CLK_PCIE_XCLK },
471 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
472 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
473 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
474 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
475 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
476 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
477 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
478 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
479 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
480 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
481 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
482 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
483 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
484 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
485 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
486 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
487 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
488 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
489 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
490 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
491 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
492 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
493 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
494 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
495 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
496 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
497 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
498 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
499 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
500 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
501 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
502 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
503 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
504 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
505 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
506 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
507 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
508 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
509 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
510 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
511 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
512 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
513 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
514 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
515 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
516 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
517 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
518 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
519 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
520 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
521 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
522 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
523 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
524};
525
526static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
527 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
528 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
529 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
530 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
531 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
532 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
533 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
534 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
535 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
536 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
537 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
538 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
539 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
540 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
541 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
542 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
543 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
544 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
545 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
546 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
547 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
548 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
549 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
550 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
551 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
552 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
553 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
554 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
555 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
556 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
557 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
558 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
559 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
560 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
561 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
562 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
563 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
564 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
565 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
566 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
567 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
568 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
569 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
570 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
571 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
572 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
573 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
574 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
575 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
576 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
577};
578
488static unsigned long tegra20_clk_measure_input_freq(void) 579static unsigned long tegra20_clk_measure_input_freq(void)
489{ 580{
490 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 581 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
@@ -545,8 +636,7 @@ static void tegra20_pll_init(void)
545 /* PLLC */ 636 /* PLLC */
546 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 637 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
547 &pll_c_params, NULL); 638 &pll_c_params, NULL);
548 clk_register_clkdev(clk, "pll_c", NULL); 639 clks[TEGRA20_CLK_PLL_C] = clk;
549 clks[pll_c] = clk;
550 640
551 /* PLLC_OUT1 */ 641 /* PLLC_OUT1 */
552 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 642 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
@@ -555,69 +645,13 @@ static void tegra20_pll_init(void)
555 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 645 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
556 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 646 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
557 0, NULL); 647 0, NULL);
558 clk_register_clkdev(clk, "pll_c_out1", NULL); 648 clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
559 clks[pll_c_out1] = clk;
560
561 /* PLLP */
562 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0,
563 &pll_p_params, NULL);
564 clk_register_clkdev(clk, "pll_p", NULL);
565 clks[pll_p] = clk;
566
567 /* PLLP_OUT1 */
568 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
569 clk_base + PLLP_OUTA, 0,
570 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
571 8, 8, 1, &pll_div_lock);
572 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
573 clk_base + PLLP_OUTA, 1, 0,
574 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
575 &pll_div_lock);
576 clk_register_clkdev(clk, "pll_p_out1", NULL);
577 clks[pll_p_out1] = clk;
578
579 /* PLLP_OUT2 */
580 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
581 clk_base + PLLP_OUTA, 0,
582 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
583 24, 8, 1, &pll_div_lock);
584 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
585 clk_base + PLLP_OUTA, 17, 16,
586 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
587 &pll_div_lock);
588 clk_register_clkdev(clk, "pll_p_out2", NULL);
589 clks[pll_p_out2] = clk;
590
591 /* PLLP_OUT3 */
592 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
593 clk_base + PLLP_OUTB, 0,
594 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
595 8, 8, 1, &pll_div_lock);
596 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
597 clk_base + PLLP_OUTB, 1, 0,
598 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
599 &pll_div_lock);
600 clk_register_clkdev(clk, "pll_p_out3", NULL);
601 clks[pll_p_out3] = clk;
602
603 /* PLLP_OUT4 */
604 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
605 clk_base + PLLP_OUTB, 0,
606 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
607 24, 8, 1, &pll_div_lock);
608 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
609 clk_base + PLLP_OUTB, 17, 16,
610 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
611 &pll_div_lock);
612 clk_register_clkdev(clk, "pll_p_out4", NULL);
613 clks[pll_p_out4] = clk;
614 649
615 /* PLLM */ 650 /* PLLM */
616 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 651 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
617 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 652 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
618 &pll_m_params, NULL); 653 &pll_m_params, NULL);
619 clk_register_clkdev(clk, "pll_m", NULL); 654 clks[TEGRA20_CLK_PLL_M] = clk;
620 clks[pll_m] = clk;
621 655
622 /* PLLM_OUT1 */ 656 /* PLLM_OUT1 */
623 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 657 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
@@ -626,38 +660,32 @@ static void tegra20_pll_init(void)
626 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 660 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
627 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 661 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
628 CLK_SET_RATE_PARENT, 0, NULL); 662 CLK_SET_RATE_PARENT, 0, NULL);
629 clk_register_clkdev(clk, "pll_m_out1", NULL); 663 clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
630 clks[pll_m_out1] = clk;
631 664
632 /* PLLX */ 665 /* PLLX */
633 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 666 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
634 &pll_x_params, NULL); 667 &pll_x_params, NULL);
635 clk_register_clkdev(clk, "pll_x", NULL); 668 clks[TEGRA20_CLK_PLL_X] = clk;
636 clks[pll_x] = clk;
637 669
638 /* PLLU */ 670 /* PLLU */
639 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 671 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
640 &pll_u_params, NULL); 672 &pll_u_params, NULL);
641 clk_register_clkdev(clk, "pll_u", NULL); 673 clks[TEGRA20_CLK_PLL_U] = clk;
642 clks[pll_u] = clk;
643 674
644 /* PLLD */ 675 /* PLLD */
645 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 676 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
646 &pll_d_params, NULL); 677 &pll_d_params, NULL);
647 clk_register_clkdev(clk, "pll_d", NULL); 678 clks[TEGRA20_CLK_PLL_D] = clk;
648 clks[pll_d] = clk;
649 679
650 /* PLLD_OUT0 */ 680 /* PLLD_OUT0 */
651 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 681 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
652 CLK_SET_RATE_PARENT, 1, 2); 682 CLK_SET_RATE_PARENT, 1, 2);
653 clk_register_clkdev(clk, "pll_d_out0", NULL); 683 clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
654 clks[pll_d_out0] = clk;
655 684
656 /* PLLA */ 685 /* PLLA */
657 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 686 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
658 &pll_a_params, NULL); 687 &pll_a_params, NULL);
659 clk_register_clkdev(clk, "pll_a", NULL); 688 clks[TEGRA20_CLK_PLL_A] = clk;
660 clks[pll_a] = clk;
661 689
662 /* PLLA_OUT0 */ 690 /* PLLA_OUT0 */
663 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 691 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
@@ -666,14 +694,12 @@ static void tegra20_pll_init(void)
666 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 694 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
667 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 695 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
668 CLK_SET_RATE_PARENT, 0, NULL); 696 CLK_SET_RATE_PARENT, 0, NULL);
669 clk_register_clkdev(clk, "pll_a_out0", NULL); 697 clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
670 clks[pll_a_out0] = clk;
671 698
672 /* PLLE */ 699 /* PLLE */
673 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 700 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
674 0, &pll_e_params, NULL); 701 0, &pll_e_params, NULL);
675 clk_register_clkdev(clk, "pll_e", NULL); 702 clks[TEGRA20_CLK_PLL_E] = clk;
676 clks[pll_e] = clk;
677} 703}
678 704
679static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 705static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
@@ -691,40 +717,17 @@ static void tegra20_super_clk_init(void)
691 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 717 clk = tegra_clk_register_super_mux("cclk", cclk_parents,
692 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 718 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
693 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 719 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
694 clk_register_clkdev(clk, "cclk", NULL); 720 clks[TEGRA20_CLK_CCLK] = clk;
695 clks[cclk] = clk;
696 721
697 /* SCLK */ 722 /* SCLK */
698 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 723 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
699 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, 724 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
700 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 725 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
701 clk_register_clkdev(clk, "sclk", NULL); 726 clks[TEGRA20_CLK_SCLK] = clk;
702 clks[sclk] = clk;
703
704 /* HCLK */
705 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
706 clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
707 &sysrate_lock);
708 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
709 clk_base + CLK_SYSTEM_RATE, 7,
710 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
711 clk_register_clkdev(clk, "hclk", NULL);
712 clks[hclk] = clk;
713
714 /* PCLK */
715 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
716 clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
717 &sysrate_lock);
718 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
719 clk_base + CLK_SYSTEM_RATE, 3,
720 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
721 clk_register_clkdev(clk, "pclk", NULL);
722 clks[pclk] = clk;
723 727
724 /* twd */ 728 /* twd */
725 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 729 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
726 clk_register_clkdev(clk, "twd", NULL); 730 clks[TEGRA20_CLK_TWD] = clk;
727 clks[twd] = clk;
728} 731}
729 732
730static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", 733static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
@@ -743,8 +746,7 @@ static void __init tegra20_audio_clk_init(void)
743 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 746 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
744 clk_base + AUDIO_SYNC_CLK, 4, 747 clk_base + AUDIO_SYNC_CLK, 4,
745 CLK_GATE_SET_TO_DISABLE, NULL); 748 CLK_GATE_SET_TO_DISABLE, NULL);
746 clk_register_clkdev(clk, "audio", NULL); 749 clks[TEGRA20_CLK_AUDIO] = clk;
747 clks[audio] = clk;
748 750
749 /* audio_2x */ 751 /* audio_2x */
750 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 752 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
@@ -753,8 +755,7 @@ static void __init tegra20_audio_clk_init(void)
753 TEGRA_PERIPH_NO_RESET, clk_base, 755 TEGRA_PERIPH_NO_RESET, clk_base,
754 CLK_SET_RATE_PARENT, 89, 756 CLK_SET_RATE_PARENT, 89,
755 periph_clk_enb_refcnt); 757 periph_clk_enb_refcnt);
756 clk_register_clkdev(clk, "audio_2x", NULL); 758 clks[TEGRA20_CLK_AUDIO_2X] = clk;
757 clks[audio_2x] = clk;
758 759
759} 760}
760 761
@@ -762,68 +763,36 @@ static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
762 "clk_m"}; 763 "clk_m"};
763static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 764static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
764 "clk_m"}; 765 "clk_m"};
765static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
766 "clk_m"};
767static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"};
768static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", 766static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
769 "clk_32k"}; 767 "clk_32k"};
770static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; 768static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
771static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"};
772static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", 769static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
773 "clk_m"}; 770 "clk_m"};
774static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 771static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
775 772
776static struct tegra_periph_init_data tegra_periph_clk_list[] = { 773static struct tegra_periph_init_data tegra_periph_clk_list[] = {
777 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, i2s1), 774 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
778 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, i2s2), 775 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
779 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, spdif_out), 776 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
780 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, spdif_in), 777 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO),
781 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, sbc1), 778 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
782 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, sbc2), 779 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE),
783 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, sbc3), 780 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
784 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, sbc4), 781 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
785 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, spi), 782 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
786 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, xio), 783 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
787 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, twc), 784 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI),
788 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, ide), 785 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
789 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, 0, ndflash),
790 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, vfir),
791 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, 0, csite),
792 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, 0, la),
793 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, owr),
794 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, mipi),
795 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, 0, vde),
796 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, 0, vi),
797 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, 0, epp),
798 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, 0, mpe),
799 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, 0, host1x),
800 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, TEGRA_PERIPH_MANUAL_RESET, gr3d),
801 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, 0, gr2d),
802 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, 0, nor),
803 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, 0, sdmmc1),
804 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, 0, sdmmc2),
805 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, 0, sdmmc3),
806 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, 0, sdmmc4),
807 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, 0, cve),
808 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, 0, tvo),
809 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, 0, tvdac),
810 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, vi_sensor),
811 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, i2c1),
812 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, i2c2),
813 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, i2c3),
814 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, dvc),
815 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, hdmi),
816 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, pwm),
817}; 786};
818 787
819static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 788static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
820 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, uarta), 789 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
821 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, uartb), 790 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
822 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, uartc), 791 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
823 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, uartd), 792 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
824 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, uarte), 793 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
825 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, disp1), 794 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1),
826 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, disp2), 795 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
827}; 796};
828 797
829static void __init tegra20_periph_clk_init(void) 798static void __init tegra20_periph_clk_init(void)
@@ -836,59 +805,12 @@ static void __init tegra20_periph_clk_init(void)
836 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 805 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
837 TEGRA_PERIPH_ON_APB, 806 TEGRA_PERIPH_ON_APB,
838 clk_base, 0, 3, periph_clk_enb_refcnt); 807 clk_base, 0, 3, periph_clk_enb_refcnt);
839 clk_register_clkdev(clk, NULL, "tegra20-ac97"); 808 clks[TEGRA20_CLK_AC97] = clk;
840 clks[ac97] = clk;
841 809
842 /* apbdma */ 810 /* apbdma */
843 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 811 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
844 0, 34, periph_clk_enb_refcnt); 812 0, 34, periph_clk_enb_refcnt);
845 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 813 clks[TEGRA20_CLK_APBDMA] = clk;
846 clks[apbdma] = clk;
847
848 /* rtc */
849 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
850 TEGRA_PERIPH_NO_RESET,
851 clk_base, 0, 4, periph_clk_enb_refcnt);
852 clk_register_clkdev(clk, NULL, "rtc-tegra");
853 clks[rtc] = clk;
854
855 /* timer */
856 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
857 0, 5, periph_clk_enb_refcnt);
858 clk_register_clkdev(clk, NULL, "timer");
859 clks[timer] = clk;
860
861 /* kbc */
862 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
863 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
864 clk_base, 0, 36, periph_clk_enb_refcnt);
865 clk_register_clkdev(clk, NULL, "tegra-kbc");
866 clks[kbc] = clk;
867
868 /* csus */
869 clk = tegra_clk_register_periph_gate("csus", "clk_m",
870 TEGRA_PERIPH_NO_RESET,
871 clk_base, 0, 92, periph_clk_enb_refcnt);
872 clk_register_clkdev(clk, "csus", "tengra_camera");
873 clks[csus] = clk;
874
875 /* vcp */
876 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0,
877 clk_base, 0, 29, periph_clk_enb_refcnt);
878 clk_register_clkdev(clk, "vcp", "tegra-avp");
879 clks[vcp] = clk;
880
881 /* bsea */
882 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0,
883 clk_base, 0, 62, periph_clk_enb_refcnt);
884 clk_register_clkdev(clk, "bsea", "tegra-avp");
885 clks[bsea] = clk;
886
887 /* bsev */
888 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0,
889 clk_base, 0, 63, periph_clk_enb_refcnt);
890 clk_register_clkdev(clk, "bsev", "tegra-aes");
891 clks[bsev] = clk;
892 814
893 /* emc */ 815 /* emc */
894 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 816 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
@@ -898,85 +820,43 @@ static void __init tegra20_periph_clk_init(void)
898 30, 2, 0, NULL); 820 30, 2, 0, NULL);
899 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 821 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
900 57, periph_clk_enb_refcnt); 822 57, periph_clk_enb_refcnt);
901 clk_register_clkdev(clk, "emc", NULL); 823 clks[TEGRA20_CLK_EMC] = clk;
902 clks[emc] = clk;
903
904 /* usbd */
905 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
906 22, periph_clk_enb_refcnt);
907 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
908 clks[usbd] = clk;
909
910 /* usb2 */
911 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
912 58, periph_clk_enb_refcnt);
913 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
914 clks[usb2] = clk;
915
916 /* usb3 */
917 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
918 59, periph_clk_enb_refcnt);
919 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
920 clks[usb3] = clk;
921 824
922 /* dsi */ 825 /* dsi */
923 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 826 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
924 48, periph_clk_enb_refcnt); 827 48, periph_clk_enb_refcnt);
925 clk_register_clkdev(clk, NULL, "dsi"); 828 clk_register_clkdev(clk, NULL, "dsi");
926 clks[dsi] = clk; 829 clks[TEGRA20_CLK_DSI] = clk;
927
928 /* csi */
929 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
930 0, 52, periph_clk_enb_refcnt);
931 clk_register_clkdev(clk, "csi", "tegra_camera");
932 clks[csi] = clk;
933
934 /* isp */
935 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
936 periph_clk_enb_refcnt);
937 clk_register_clkdev(clk, "isp", "tegra_camera");
938 clks[isp] = clk;
939 830
940 /* pex */ 831 /* pex */
941 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 832 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
942 periph_clk_enb_refcnt); 833 periph_clk_enb_refcnt);
943 clk_register_clkdev(clk, "pex", NULL); 834 clks[TEGRA20_CLK_PEX] = clk;
944 clks[pex] = clk;
945
946 /* afi */
947 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
948 periph_clk_enb_refcnt);
949 clk_register_clkdev(clk, "afi", NULL);
950 clks[afi] = clk;
951 835
952 /* pcie_xclk */ 836 /* pcie_xclk */
953 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base, 837 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
954 0, 74, periph_clk_enb_refcnt); 838 0, 74, periph_clk_enb_refcnt);
955 clk_register_clkdev(clk, "pcie_xclk", NULL); 839 clks[TEGRA20_CLK_PCIE_XCLK] = clk;
956 clks[pcie_xclk] = clk;
957 840
958 /* cdev1 */ 841 /* cdev1 */
959 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, 842 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
960 26000000); 843 26000000);
961 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, 844 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
962 clk_base, 0, 94, periph_clk_enb_refcnt); 845 clk_base, 0, 94, periph_clk_enb_refcnt);
963 clk_register_clkdev(clk, "cdev1", NULL); 846 clks[TEGRA20_CLK_CDEV1] = clk;
964 clks[cdev1] = clk;
965 847
966 /* cdev2 */ 848 /* cdev2 */
967 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, 849 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
968 26000000); 850 26000000);
969 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, 851 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
970 clk_base, 0, 93, periph_clk_enb_refcnt); 852 clk_base, 0, 93, periph_clk_enb_refcnt);
971 clk_register_clkdev(clk, "cdev2", NULL); 853 clks[TEGRA20_CLK_CDEV2] = clk;
972 clks[cdev2] = clk;
973 854
974 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 855 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
975 data = &tegra_periph_clk_list[i]; 856 data = &tegra_periph_clk_list[i];
976 clk = tegra_clk_register_periph(data->name, data->p.parent_names, 857 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
977 data->num_parents, &data->periph, 858 data->num_parents, &data->periph,
978 clk_base, data->offset, data->flags); 859 clk_base, data->offset, data->flags);
979 clk_register_clkdev(clk, data->con_id, data->dev_id);
980 clks[data->clk_id] = clk; 860 clks[data->clk_id] = clk;
981 } 861 }
982 862
@@ -986,37 +866,10 @@ static void __init tegra20_periph_clk_init(void)
986 data->p.parent_names, 866 data->p.parent_names,
987 data->num_parents, &data->periph, 867 data->num_parents, &data->periph,
988 clk_base, data->offset); 868 clk_base, data->offset);
989 clk_register_clkdev(clk, data->con_id, data->dev_id);
990 clks[data->clk_id] = clk; 869 clks[data->clk_id] = clk;
991 } 870 }
992}
993
994
995static void __init tegra20_fixed_clk_init(void)
996{
997 struct clk *clk;
998
999 /* clk_32k */
1000 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1001 32768);
1002 clk_register_clkdev(clk, "clk_32k", NULL);
1003 clks[clk_32k] = clk;
1004}
1005
1006static void __init tegra20_pmc_clk_init(void)
1007{
1008 struct clk *clk;
1009 871
1010 /* blink */ 872 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
1011 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1012 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1013 pmc_base + PMC_DPD_PADS_ORIDE,
1014 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1015 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1016 pmc_base + PMC_CTRL,
1017 PMC_CTRL_BLINK_ENB, 0, NULL);
1018 clk_register_clkdev(clk, "blink", NULL);
1019 clks[blink] = clk;
1020} 873}
1021 874
1022static void __init tegra20_osc_clk_init(void) 875static void __init tegra20_osc_clk_init(void)
@@ -1030,15 +883,13 @@ static void __init tegra20_osc_clk_init(void)
1030 /* clk_m */ 883 /* clk_m */
1031 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | 884 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
1032 CLK_IGNORE_UNUSED, input_freq); 885 CLK_IGNORE_UNUSED, input_freq);
1033 clk_register_clkdev(clk, "clk_m", NULL); 886 clks[TEGRA20_CLK_CLK_M] = clk;
1034 clks[clk_m] = clk;
1035 887
1036 /* pll_ref */ 888 /* pll_ref */
1037 pll_ref_div = tegra20_get_pll_ref_div(); 889 pll_ref_div = tegra20_get_pll_ref_div();
1038 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 890 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1039 CLK_SET_RATE_PARENT, 1, pll_ref_div); 891 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1040 clk_register_clkdev(clk, "pll_ref", NULL); 892 clks[TEGRA20_CLK_PLL_REF] = clk;
1041 clks[pll_ref] = clk;
1042} 893}
1043 894
1044/* Tegra20 CPU clock and reset control functions */ 895/* Tegra20 CPU clock and reset control functions */
@@ -1172,49 +1023,49 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1172}; 1023};
1173 1024
1174static struct tegra_clk_init_table init_table[] __initdata = { 1025static struct tegra_clk_init_table init_table[] __initdata = {
1175 {pll_p, clk_max, 216000000, 1}, 1026 {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1},
1176 {pll_p_out1, clk_max, 28800000, 1}, 1027 {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1},
1177 {pll_p_out2, clk_max, 48000000, 1}, 1028 {TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1},
1178 {pll_p_out3, clk_max, 72000000, 1}, 1029 {TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1},
1179 {pll_p_out4, clk_max, 24000000, 1}, 1030 {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1},
1180 {pll_c, clk_max, 600000000, 1}, 1031 {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1},
1181 {pll_c_out1, clk_max, 120000000, 1}, 1032 {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1},
1182 {sclk, pll_c_out1, 0, 1}, 1033 {TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1},
1183 {hclk, clk_max, 0, 1}, 1034 {TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1184 {pclk, clk_max, 60000000, 1}, 1035 {TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1},
1185 {csite, clk_max, 0, 1}, 1036 {TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1},
1186 {emc, clk_max, 0, 1}, 1037 {TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1},
1187 {cclk, clk_max, 0, 1}, 1038 {TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1188 {uarta, pll_p, 0, 0}, 1039 {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
1189 {uartb, pll_p, 0, 0}, 1040 {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
1190 {uartc, pll_p, 0, 0}, 1041 {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
1191 {uartd, pll_p, 0, 0}, 1042 {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
1192 {uarte, pll_p, 0, 0}, 1043 {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
1193 {pll_a, clk_max, 56448000, 1}, 1044 {TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1},
1194 {pll_a_out0, clk_max, 11289600, 1}, 1045 {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1},
1195 {cdev1, clk_max, 0, 1}, 1046 {TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1},
1196 {blink, clk_max, 32768, 1}, 1047 {TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1},
1197 {i2s1, pll_a_out0, 11289600, 0}, 1048 {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1198 {i2s2, pll_a_out0, 11289600, 0}, 1049 {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1199 {sdmmc1, pll_p, 48000000, 0}, 1050 {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
1200 {sdmmc3, pll_p, 48000000, 0}, 1051 {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
1201 {sdmmc4, pll_p, 48000000, 0}, 1052 {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0},
1202 {spi, pll_p, 20000000, 0}, 1053 {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0},
1203 {sbc1, pll_p, 100000000, 0}, 1054 {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0},
1204 {sbc2, pll_p, 100000000, 0}, 1055 {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0},
1205 {sbc3, pll_p, 100000000, 0}, 1056 {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0},
1206 {sbc4, pll_p, 100000000, 0}, 1057 {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0},
1207 {host1x, pll_c, 150000000, 0}, 1058 {TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0},
1208 {disp1, pll_p, 600000000, 0}, 1059 {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0},
1209 {disp2, pll_p, 600000000, 0}, 1060 {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0},
1210 {gr2d, pll_c, 300000000, 0}, 1061 {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0},
1211 {gr3d, pll_c, 300000000, 0}, 1062 {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0},
1212 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ 1063 {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */
1213}; 1064};
1214 1065
1215static void __init tegra20_clock_apply_init_table(void) 1066static void __init tegra20_clock_apply_init_table(void)
1216{ 1067{
1217 tegra_init_from_table(init_table, clks, clk_max); 1068 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1218} 1069}
1219 1070
1220/* 1071/*
@@ -1223,11 +1074,11 @@ static void __init tegra20_clock_apply_init_table(void)
1223 * table under two names. 1074 * table under two names.
1224 */ 1075 */
1225static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1076static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1226 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1077 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1227 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1078 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1228 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1079 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1229 TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"), 1080 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
1230 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */ 1081 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */
1231}; 1082};
1232 1083
1233static const struct of_device_id pmc_match[] __initconst = { 1084static const struct of_device_id pmc_match[] __initconst = {
@@ -1257,21 +1108,23 @@ static void __init tegra20_clock_init(struct device_node *np)
1257 BUG(); 1108 BUG();
1258 } 1109 }
1259 1110
1260 clks = tegra_clk_init(clk_max, TEGRA20_CLK_PERIPH_BANKS); 1111 clks = tegra_clk_init(TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_PERIPH_BANKS);
1261 if (!clks) 1112 if (!clks)
1262 return; 1113 return;
1263 1114
1264 tegra20_osc_clk_init(); 1115 tegra20_osc_clk_init();
1265 tegra20_pmc_clk_init(); 1116 tegra_fixed_clk_init(tegra20_clks);
1266 tegra20_fixed_clk_init();
1267 tegra20_pll_init(); 1117 tegra20_pll_init();
1268 tegra20_super_clk_init(); 1118 tegra20_super_clk_init();
1119 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1269 tegra20_periph_clk_init(); 1120 tegra20_periph_clk_init();
1270 tegra20_audio_clk_init(); 1121 tegra20_audio_clk_init();
1122 tegra_pmc_clk_init(pmc_base, tegra20_clks);
1271 1123
1272 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1124 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1273 1125
1274 tegra_add_of_provider(np); 1126 tegra_add_of_provider(np);
1127 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1275 1128
1276 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1129 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1277 1130
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 14:35:40 -0400