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-rw-r--r--drivers/gpu/drm/i915/intel_pm.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cdd70e654af5..bfc46529f6df 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1303,7 +1303,6 @@ static void valleyview_update_wm(struct drm_device *dev)
1303 &planeb_wm, &cursorb_wm)) 1303 &planeb_wm, &cursorb_wm))
1304 enabled |= 2; 1304 enabled |= 2;
1305 1305
1306 plane_sr = cursor_sr = 0;
1307 if (single_plane_enabled(enabled) && 1306 if (single_plane_enabled(enabled) &&
1308 g4x_compute_srwm(dev, ffs(enabled) - 1, 1307 g4x_compute_srwm(dev, ffs(enabled) - 1,
1309 sr_latency_ns, 1308 sr_latency_ns,
@@ -1314,11 +1313,13 @@ static void valleyview_update_wm(struct drm_device *dev)
1314 2*sr_latency_ns, 1313 2*sr_latency_ns,
1315 &valleyview_wm_info, 1314 &valleyview_wm_info,
1316 &valleyview_cursor_wm_info, 1315 &valleyview_cursor_wm_info,
1317 &ignore_plane_sr, &cursor_sr)) 1316 &ignore_plane_sr, &cursor_sr)) {
1318 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); 1317 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1319 else 1318 } else {
1320 I915_WRITE(FW_BLC_SELF_VLV, 1319 I915_WRITE(FW_BLC_SELF_VLV,
1321 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); 1320 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1321 plane_sr = cursor_sr = 0;
1322 }
1322 1323
1323 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1324 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1324 planea_wm, cursora_wm, 1325 planea_wm, cursora_wm,
@@ -1358,17 +1359,18 @@ static void g4x_update_wm(struct drm_device *dev)
1358 &planeb_wm, &cursorb_wm)) 1359 &planeb_wm, &cursorb_wm))
1359 enabled |= 2; 1360 enabled |= 2;
1360 1361
1361 plane_sr = cursor_sr = 0;
1362 if (single_plane_enabled(enabled) && 1362 if (single_plane_enabled(enabled) &&
1363 g4x_compute_srwm(dev, ffs(enabled) - 1, 1363 g4x_compute_srwm(dev, ffs(enabled) - 1,
1364 sr_latency_ns, 1364 sr_latency_ns,
1365 &g4x_wm_info, 1365 &g4x_wm_info,
1366 &g4x_cursor_wm_info, 1366 &g4x_cursor_wm_info,
1367 &plane_sr, &cursor_sr)) 1367 &plane_sr, &cursor_sr)) {
1368 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1368 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1369 else 1369 } else {
1370 I915_WRITE(FW_BLC_SELF, 1370 I915_WRITE(FW_BLC_SELF,
1371 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); 1371 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1372 plane_sr = cursor_sr = 0;
1373 }
1372 1374
1373 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1375 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1374 planea_wm, cursora_wm, 1376 planea_wm, cursora_wm,