2 files changed, 92 insertions, 19 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 8629e3043acd..38e2cc3b206b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -24,6 +24,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
 #include <mach/dove.h>
+#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
@@ -69,14 +70,68 @@ void __init dove_map_io(void)
 * CLK tree
 ****************************************************************************/
 static int dove_tclk;
+static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
+static struct clk __init *dove_register_gate(const char *name,
+                                             const char *parent, u8 bit_idx)
+{
+        return clk_register_gate(NULL, name, parent, 0,
+                                 (void __iomem *)CLOCK_GATING_CONTROL,
+                                 bit_idx, 0, &gating_lock);
+}
 static void __init dove_clk_init(void)
 {
+        struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+        struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+        struct clk *xor0, *xor1, *ge, *gephy;
        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
                                       dove_tclk);
-        orion_clkdev_init(tclk);
+        usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+        usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+        sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+        pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
+        pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+        sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+        sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+        nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+        camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+        i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+        i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+        crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+        ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+        pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+        xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+        xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+        gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+        ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+        orion_clkdev_add(NULL, "orion_spi.0", tclk);
+        orion_clkdev_add(NULL, "orion_spi.1", tclk);
+        orion_clkdev_add(NULL, "orion_wdt", tclk);
+        orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
+        orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+        orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+        orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
+        orion_clkdev_add("0", "sata_mv.0", sata);
+        orion_clkdev_add("0", "pcie", pex0);
+        orion_clkdev_add("1", "pcie", pex1);
+        orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+        orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+        orion_clkdev_add(NULL, "orion_nand", nand);
+        orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+        orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+        orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+        orion_clkdev_add(NULL, "mv_crypto", crypto);
+        orion_clkdev_add(NULL, "dove-ac97", ac97);
+        orion_clkdev_add(NULL, "dove-pdma", pdma);
+        orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
+        orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
 }
 /*****************************************************************************
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f946a9e8..7bcd0dfce4b1 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 #define CLOCK_GATING_CONTROL    (DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK         (1 << 0)
+#define  CLOCK_GATING_BIT_USB0          0
-#define  CLOCK_GATING_USB1_MASK         (1 << 1)
+#define  CLOCK_GATING_BIT_USB1          1
-#define  CLOCK_GATING_GBE_MASK          (1 << 2)
+#define  CLOCK_GATING_BIT_GBE           2
-#define  CLOCK_GATING_SATA_MASK         (1 << 3)
+#define  CLOCK_GATING_BIT_SATA          3
-#define  CLOCK_GATING_PCIE0_MASK        (1 << 4)
+#define  CLOCK_GATING_BIT_PCIE0         4
-#define  CLOCK_GATING_PCIE1_MASK        (1 << 5)
+#define  CLOCK_GATING_BIT_PCIE1         5
-#define  CLOCK_GATING_SDIO0_MASK        (1 << 8)
+#define  CLOCK_GATING_BIT_SDIO0         8
-#define  CLOCK_GATING_SDIO1_MASK        (1 << 9)
+#define  CLOCK_GATING_BIT_SDIO1         9
-#define  CLOCK_GATING_NAND_MASK         (1 << 10)
+#define  CLOCK_GATING_BIT_NAND          10
-#define  CLOCK_GATING_CAMERA_MASK       (1 << 11)
+#define  CLOCK_GATING_BIT_CAMERA        11
-#define  CLOCK_GATING_I2S0_MASK         (1 << 12)
+#define  CLOCK_GATING_BIT_I2S0          12
-#define  CLOCK_GATING_I2S1_MASK         (1 << 13)
+#define  CLOCK_GATING_BIT_I2S1          13
-#define  CLOCK_GATING_CRYPTO_MASK       (1 << 15)
+#define  CLOCK_GATING_BIT_CRYPTO        15
-#define  CLOCK_GATING_AC97_MASK         (1 << 21)
+#define  CLOCK_GATING_BIT_AC97          21
-#define  CLOCK_GATING_PDMA_MASK         (1 << 22)
+#define  CLOCK_GATING_BIT_PDMA          22
-#define  CLOCK_GATING_XOR0_MASK         (1 << 23)
+#define  CLOCK_GATING_BIT_XOR0          23
-#define  CLOCK_GATING_XOR1_MASK         (1 << 24)
+#define  CLOCK_GATING_BIT_XOR1          24
-#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << 30)
+#define  CLOCK_GATING_BIT_GIGA_PHY      30
+#define  CLOCK_GATING_USB0_MASK         (1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK         (1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK          (1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK         (1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK        (1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK        (1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK        (1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK        (1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK         (1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK       (1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK         (1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK         (1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK       (1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK         (1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK         (1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK         (1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK         (1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << CLOCK_GATING_BIT_GIGA_PHY)
 #define PMU_INTERRUPT_CAUSE     (DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK      (DOVE_PMU_VIRT_BASE + 0x54)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 8629e3043acd..38e2cc3b206b 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c
@@ -24,6 +24,7 @@
24	#include <asm/mach/time.h>	24	#include <asm/mach/time.h>
25	#include <asm/mach/pci.h>	25	#include <asm/mach/pci.h>
26	#include <mach/dove.h>	26	#include <mach/dove.h>
		27	#include <mach/pm.h>
27	#include <mach/bridge-regs.h>	28	#include <mach/bridge-regs.h>
28	#include <asm/mach/arch.h>	29	#include <asm/mach/arch.h>
29	#include <linux/irq.h>	30	#include <linux/irq.h>
@@ -69,14 +70,68 @@ void __init dove_map_io(void)
69	* CLK tree	70	* CLK tree
70	****************************************************************************/	71	****************************************************************************/
71	static int dove_tclk;	72	static int dove_tclk;
		73
		74	static DEFINE_SPINLOCK(gating_lock);
72	static struct clk *tclk;	75	static struct clk *tclk;
73		76
		77	static struct clk __init dove_register_gate(const char name,
		78	const char *parent, u8 bit_idx)
		79	{
		80	return clk_register_gate(NULL, name, parent, 0,
		81	(void __iomem *)CLOCK_GATING_CONTROL,
		82	bit_idx, 0, &gating_lock);
		83	}
		84
74	static void __init dove_clk_init(void)	85	static void __init dove_clk_init(void)
75	{	86	{
		87	struct clk usb0, usb1, sata, pex0, pex1, sdio0, *sdio1;
		88	struct clk nand, camera, i2s0, i2s1, crypto, ac97, *pdma;
		89	struct clk xor0, xor1, ge, gephy;
		90
76	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,	91	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
77	dove_tclk);	92	dove_tclk);
78		93
79	orion_clkdev_init(tclk);	94	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
		95	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
		96	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
		97	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
		98	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
		99	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
		100	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
		101	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
		102	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
		103	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
		104	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
		105	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
		106	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
		107	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
		108	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
		109	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
		110	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
		111	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
		112
		113	orion_clkdev_add(NULL, "orion_spi.0", tclk);
		114	orion_clkdev_add(NULL, "orion_spi.1", tclk);
		115	orion_clkdev_add(NULL, "orion_wdt", tclk);
		116	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
		117
		118	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
		119	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
		120	orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
		121	orion_clkdev_add("0", "sata_mv.0", sata);
		122	orion_clkdev_add("0", "pcie", pex0);
		123	orion_clkdev_add("1", "pcie", pex1);
		124	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
		125	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
		126	orion_clkdev_add(NULL, "orion_nand", nand);
		127	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
		128	orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
		129	orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
		130	orion_clkdev_add(NULL, "mv_crypto", crypto);
		131	orion_clkdev_add(NULL, "dove-ac97", ac97);
		132	orion_clkdev_add(NULL, "dove-pdma", pdma);
		133	orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
		134	orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
80	}	135	}
81		136
82	/*****************************************************************************	137	/*****************************************************************************


diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h index 3ad9f946a9e8..7bcd0dfce4b1 100644 --- a/arch/arm/mach-dove/include/mach/pm.h +++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
13	#include <mach/irqs.h>	13	#include <mach/irqs.h>
14		14
15	#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)	15	#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
16	#define CLOCK_GATING_USB0_MASK (1 << 0)	16	#define CLOCK_GATING_BIT_USB0 0
17	#define CLOCK_GATING_USB1_MASK (1 << 1)	17	#define CLOCK_GATING_BIT_USB1 1
18	#define CLOCK_GATING_GBE_MASK (1 << 2)	18	#define CLOCK_GATING_BIT_GBE 2
19	#define CLOCK_GATING_SATA_MASK (1 << 3)	19	#define CLOCK_GATING_BIT_SATA 3
20	#define CLOCK_GATING_PCIE0_MASK (1 << 4)	20	#define CLOCK_GATING_BIT_PCIE0 4
21	#define CLOCK_GATING_PCIE1_MASK (1 << 5)	21	#define CLOCK_GATING_BIT_PCIE1 5
22	#define CLOCK_GATING_SDIO0_MASK (1 << 8)	22	#define CLOCK_GATING_BIT_SDIO0 8
23	#define CLOCK_GATING_SDIO1_MASK (1 << 9)	23	#define CLOCK_GATING_BIT_SDIO1 9
24	#define CLOCK_GATING_NAND_MASK (1 << 10)	24	#define CLOCK_GATING_BIT_NAND 10
25	#define CLOCK_GATING_CAMERA_MASK (1 << 11)	25	#define CLOCK_GATING_BIT_CAMERA 11
26	#define CLOCK_GATING_I2S0_MASK (1 << 12)	26	#define CLOCK_GATING_BIT_I2S0 12
27	#define CLOCK_GATING_I2S1_MASK (1 << 13)	27	#define CLOCK_GATING_BIT_I2S1 13
28	#define CLOCK_GATING_CRYPTO_MASK (1 << 15)	28	#define CLOCK_GATING_BIT_CRYPTO 15
29	#define CLOCK_GATING_AC97_MASK (1 << 21)	29	#define CLOCK_GATING_BIT_AC97 21
30	#define CLOCK_GATING_PDMA_MASK (1 << 22)	30	#define CLOCK_GATING_BIT_PDMA 22
31	#define CLOCK_GATING_XOR0_MASK (1 << 23)	31	#define CLOCK_GATING_BIT_XOR0 23
32	#define CLOCK_GATING_XOR1_MASK (1 << 24)	32	#define CLOCK_GATING_BIT_XOR1 24
33	#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)	33	#define CLOCK_GATING_BIT_GIGA_PHY 30
		34	#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
		35	#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
		36	#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
		37	#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
		38	#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
		39	#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
		40	#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
		41	#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
		42	#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
		43	#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
		44	#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
		45	#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
		46	#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
		47	#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
		48	#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
		49	#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
		50	#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
		51	#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
34		52
35	#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)	53	#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
36	#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)	54	#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)