diff options
| -rw-r--r-- | arch/arm/mach-shmobile/clock-r8a7740.c | 9 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/clock-r8a7790.c | 2 |
2 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 0794f0426e70..19df9cb30495 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c | |||
| @@ -455,7 +455,7 @@ enum { | |||
| 455 | MSTP128, MSTP127, MSTP125, | 455 | MSTP128, MSTP127, MSTP125, |
| 456 | MSTP116, MSTP111, MSTP100, MSTP117, | 456 | MSTP116, MSTP111, MSTP100, MSTP117, |
| 457 | 457 | ||
| 458 | MSTP230, | 458 | MSTP230, MSTP229, |
| 459 | MSTP222, | 459 | MSTP222, |
| 460 | MSTP218, MSTP217, MSTP216, MSTP214, | 460 | MSTP218, MSTP217, MSTP216, MSTP214, |
| 461 | MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, | 461 | MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, |
| @@ -474,11 +474,12 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
| 474 | [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */ | 474 | [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */ |
| 475 | [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ | 475 | [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ |
| 476 | [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ | 476 | [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ |
| 477 | [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ | 477 | [MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */ |
| 478 | [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ | 478 | [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ |
| 479 | [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ | 479 | [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ |
| 480 | 480 | ||
| 481 | [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ | 481 | [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ |
| 482 | [MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */ | ||
| 482 | [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ | 483 | [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ |
| 483 | [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ | 484 | [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ |
| 484 | [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ | 485 | [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ |
| @@ -575,6 +576,10 @@ static struct clk_lookup lookups[] = { | |||
| 575 | CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), | 576 | CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), |
| 576 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), | 577 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), |
| 577 | CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]), | 578 | CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]), |
| 579 | CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]), | ||
| 580 | CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]), | ||
| 581 | CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]), | ||
| 582 | CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]), | ||
| 578 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), | 583 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), |
| 579 | CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]), | 584 | CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]), |
| 580 | 585 | ||
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 126ddafad526..f62265200592 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c | |||
| @@ -68,7 +68,7 @@ | |||
| 68 | 68 | ||
| 69 | #define SDCKCR 0xE6150074 | 69 | #define SDCKCR 0xE6150074 |
| 70 | #define SD2CKCR 0xE6150078 | 70 | #define SD2CKCR 0xE6150078 |
| 71 | #define SD3CKCR 0xE615007C | 71 | #define SD3CKCR 0xE615026C |
| 72 | #define MMC0CKCR 0xE6150240 | 72 | #define MMC0CKCR 0xE6150240 |
| 73 | #define MMC1CKCR 0xE6150244 | 73 | #define MMC1CKCR 0xE6150244 |
| 74 | #define SSPCKCR 0xE6150248 | 74 | #define SSPCKCR 0xE6150248 |
