diff options
| -rw-r--r-- | arch/x86/kernel/uprobes.c | 52 |
1 files changed, 17 insertions, 35 deletions
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index aa1da96d09ff..81f8adb0679e 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c | |||
| @@ -189,61 +189,43 @@ static volatile u32 good_insns_64[256 / 32] = { | |||
| 189 | * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group. | 189 | * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group. |
| 190 | * Also encodes tons of other system insns if mod=11. | 190 | * Also encodes tons of other system insns if mod=11. |
| 191 | * Some are in fact non-system: xend, xtest, rdtscp, maybe more | 191 | * Some are in fact non-system: xend, xtest, rdtscp, maybe more |
| 192 | * 0f 02 - lar (why? should be safe, it throws no exceptipons) | ||
| 193 | * 0f 03 - lsl (why? should be safe, it throws no exceptipons) | ||
| 194 | * 0f 04 - undefined | ||
| 195 | * 0f 05 - syscall | 192 | * 0f 05 - syscall |
| 196 | * 0f 06 - clts (CPL0 insn) | 193 | * 0f 06 - clts (CPL0 insn) |
| 197 | * 0f 07 - sysret | 194 | * 0f 07 - sysret |
| 198 | * 0f 08 - invd (CPL0 insn) | 195 | * 0f 08 - invd (CPL0 insn) |
| 199 | * 0f 09 - wbinvd (CPL0 insn) | 196 | * 0f 09 - wbinvd (CPL0 insn) |
| 200 | * 0f 0a - undefined | ||
| 201 | * 0f 0b - ud2 | 197 | * 0f 0b - ud2 |
| 202 | * 0f 0c - undefined | 198 | * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?) |
| 203 | * 0f 0d - prefetchFOO (amd prefetch insns) | ||
| 204 | * 0f 18 - prefetchBAR (intel prefetch insns) | ||
| 205 | * 0f 24 - mov from test regs (perhaps entire 20-27 area can be disabled (special reg ops)) | ||
| 206 | * 0f 25 - undefined | ||
| 207 | * 0f 26 - mov to test regs | ||
| 208 | * 0f 27 - undefined | ||
| 209 | * 0f 30 - wrmsr (CPL0 insn) | ||
| 210 | * 0f 34 - sysenter | 199 | * 0f 34 - sysenter |
| 211 | * 0f 35 - sysexit | 200 | * 0f 35 - sysexit |
| 212 | * 0f 36 - undefined | ||
| 213 | * 0f 37 - getsec | 201 | * 0f 37 - getsec |
| 214 | * 0f 38-3f - 3-byte opcodes (why?? all look safe) | 202 | * 0f 78 - vmread (Intel VMX. CPL0 insn) |
| 215 | * 0f 78 - vmread | 203 | * 0f 79 - vmwrite (Intel VMX. CPL0 insn) |
| 216 | * 0f 79 - vmwrite | 204 | * Note: with prefixes, these two opcodes are |
| 217 | * 0f 7a - undefined | 205 | * extrq/insertq/AVX512 convert vector ops. |
| 218 | * 0f 7b - undefined | 206 | * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt], |
| 219 | * 0f 7c - undefined | 207 | * {rd,wr}{fs,gs}base,{s,l,m}fence. |
| 220 | * 0f 7d - undefined | 208 | * Why? They are all user-executable. |
| 221 | * 0f a6 - undefined | ||
| 222 | * 0f a7 - undefined | ||
| 223 | * 0f b8 - popcnt (why?? it's an ordinary ALU op) | ||
| 224 | * 0f d0 - undefined | ||
| 225 | * 0f f0 - lddqu (why?? it's an ordinary vector load op) | ||
| 226 | * 0f ff - undefined | ||
| 227 | */ | 209 | */ |
| 228 | static volatile u32 good_2byte_insns[256 / 32] = { | 210 | static volatile u32 good_2byte_insns[256 / 32] = { |
| 229 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | 211 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 230 | /* ---------------------------------------------- */ | 212 | /* ---------------------------------------------- */ |
| 231 | W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */ | 213 | W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */ |
| 232 | W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ | 214 | W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ |
| 233 | W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ | 215 | W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ |
| 234 | W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */ | 216 | W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */ |
| 235 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ | 217 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ |
| 236 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | 218 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ |
| 237 | W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ | 219 | W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ |
| 238 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */ | 220 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */ |
| 239 | W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | 221 | W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ |
| 240 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | 222 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ |
| 241 | W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ | 223 | W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ |
| 242 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | 224 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ |
| 243 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ | 225 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ |
| 244 | W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ | 226 | W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ |
| 245 | W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ | 227 | W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ |
| 246 | W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */ | 228 | W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */ |
| 247 | /* ---------------------------------------------- */ | 229 | /* ---------------------------------------------- */ |
| 248 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | 230 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 249 | }; | 231 | }; |
