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-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c69
1 files changed, 69 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 8cf49790f3a7..75b2b6fb8594 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -27,6 +27,10 @@
27 27
28#include <media/tvp514x.h> 28#include <media/tvp514x.h>
29 29
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33
30#include <asm/mach-types.h> 34#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
32 36
@@ -34,6 +38,7 @@
34#include <mach/common.h> 38#include <mach/common.h>
35#include <mach/serial.h> 39#include <mach/serial.h>
36#include <mach/i2c.h> 40#include <mach/i2c.h>
41#include <mach/nand.h>
37 42
38#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 43#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
39 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 44 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
@@ -42,6 +47,11 @@
42#define HAS_ATA 0 47#define HAS_ATA 0
43#endif 48#endif
44 49
50#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
51#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
52
53#define NAND_BLOCK_SIZE SZ_128K
54
45/* CPLD Register 0 bits to control ATA */ 55/* CPLD Register 0 bits to control ATA */
46#define DM646X_EVM_ATA_RST BIT(0) 56#define DM646X_EVM_ATA_RST BIT(0)
47#define DM646X_EVM_ATA_PWD BIT(1) 57#define DM646X_EVM_ATA_PWD BIT(1)
@@ -77,6 +87,63 @@ static struct davinci_uart_config uart_config __initdata = {
77 .enabled_uarts = (1 << 0), 87 .enabled_uarts = (1 << 0),
78}; 88};
79 89
90/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
91 * and U-Boot environment this avoids dependency on any particular combination
92 * of UBL, U-Boot or flashing tools etc.
93 */
94static struct mtd_partition davinci_nand_partitions[] = {
95 {
96 /* UBL, U-Boot with environment */
97 .name = "bootloader",
98 .offset = MTDPART_OFS_APPEND,
99 .size = 16 * NAND_BLOCK_SIZE,
100 .mask_flags = MTD_WRITEABLE, /* force read-only */
101 }, {
102 .name = "kernel",
103 .offset = MTDPART_OFS_APPEND,
104 .size = SZ_4M,
105 .mask_flags = 0,
106 }, {
107 .name = "filesystem",
108 .offset = MTDPART_OFS_APPEND,
109 .size = MTDPART_SIZ_FULL,
110 .mask_flags = 0,
111 }
112};
113
114static struct davinci_nand_pdata davinci_nand_data = {
115 .mask_cle = 0x80000,
116 .mask_ale = 0x40000,
117 .parts = davinci_nand_partitions,
118 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
119 .ecc_mode = NAND_ECC_HW,
120 .options = 0,
121};
122
123static struct resource davinci_nand_resources[] = {
124 {
125 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
126 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
127 .flags = IORESOURCE_MEM,
128 }, {
129 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
130 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
131 .flags = IORESOURCE_MEM,
132 },
133};
134
135static struct platform_device davinci_nand_device = {
136 .name = "davinci_nand",
137 .id = 0,
138
139 .num_resources = ARRAY_SIZE(davinci_nand_resources),
140 .resource = davinci_nand_resources,
141
142 .dev = {
143 .platform_data = &davinci_nand_data,
144 },
145};
146
80/* CPLD Register 0 Client: used for I/O Control */ 147/* CPLD Register 0 Client: used for I/O Control */
81static int cpld_reg0_probe(struct i2c_client *client, 148static int cpld_reg0_probe(struct i2c_client *client,
82 const struct i2c_device_id *id) 149 const struct i2c_device_id *id)
@@ -632,6 +699,8 @@ static __init void evm_init(void)
632 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); 699 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
633 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); 700 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
634 701
702 platform_device_register(&davinci_nand_device);
703
635 if (HAS_ATA) 704 if (HAS_ATA)
636 dm646x_init_ide(); 705 dm646x_init_ide();
637 706