5 files changed, 46 insertions, 22 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ec82f6bff122..108e1ec2fa4b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1954,6 +1954,9 @@ struct drm_i915_cmd_table {
 #define IS_ULT(dev)             (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
 #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
                                  ((dev)->pdev->device & 0x00F0) == 0x0020)
+/* ULX machines are also considered ULT. */
+#define IS_HSW_ULX(dev)         ((dev)->pdev->device == 0x0A0E || \
+                                 (dev)->pdev->device == 0x0A1E)
 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
 
 /*
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 62a5c3627b90..154b0f8bb88d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -34,25 +34,35 @@ static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
 
 bool intel_enable_ppgtt(struct drm_device *dev, bool full)
 {
-        if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
+        if (i915.enable_ppgtt == 0)
                 return false;
 
         if (i915.enable_ppgtt == 1 && full)
                 return false;
 
+        return true;
+}
+
+static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
+{
+        if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
+                return 0;
+
+        if (enable_ppgtt == 1)
+                return 1;
+
+        if (enable_ppgtt == 2 && HAS_PPGTT(dev))
+                return 2;
+
 #ifdef CONFIG_INTEL_IOMMU
         /* Disable ppgtt on SNB if VT-d is on. */
         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
-                return false;
+                return 0;
         }
 #endif
 
-        /* Full ppgtt disabled by default for now due to issues. */
-        if (full)
-                return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2);
-        else
-                return HAS_ALIASING_PPGTT(dev);
+        return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
 }
 
 #define GEN6_PPGTT_PD_ENTRIES 512
@@ -2031,6 +2041,14 @@ int i915_gem_gtt_init(struct drm_device *dev)
                  gtt->base.total >> 20);
         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
+        /*
+         * i915.enable_ppgtt is read-only, so do an early pass to validate the
+         * user's requested state against the hardware/driver capabilities.  We
+         * do this now so that we can print out any log messages once rather
+         * than every time we check intel_enable_ppgtt().
+         */
+        i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
+        DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 69bcc42a0e44..48aa516a1ac0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11395,15 +11395,6 @@ void intel_modeset_init(struct drm_device *dev)
         }
 }
 
-static void
-intel_connector_break_all_links(struct intel_connector *connector)
-{
-        connector->base.dpms = DRM_MODE_DPMS_OFF;
-        connector->base.encoder = NULL;
-        connector->encoder->connectors_active = false;
-        connector->encoder->base.crtc = NULL;
-}
-
 static void intel_enable_pipe_a(struct drm_device *dev)
 {
         struct intel_connector *connector;
@@ -11485,8 +11476,17 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
                         if (connector->encoder->base.crtc != &crtc->base)
                                 continue;
 
-                        intel_connector_break_all_links(connector);
+                        connector->base.dpms = DRM_MODE_DPMS_OFF;
+                        connector->base.encoder = NULL;
                 }
+                /* multiple connectors may have the same encoder:
+                 *  handle them and break crtc link separately */
+                list_for_each_entry(connector, &dev->mode_config.connector_list,
+                                    base.head)
+                        if (connector->encoder->base.crtc == &crtc->base) {
+                                connector->encoder->base.crtc = NULL;
+                                connector->encoder->connectors_active = false;
+                        }
 
                 WARN_ON(crtc->active);
                 crtc->base.enabled = false;
@@ -11568,6 +11568,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
                                       drm_get_encoder_name(&encoder->base));
                         encoder->disable(encoder);
                 }
+                encoder->base.crtc = NULL;
+                encoder->connectors_active = false;
 
                 /* Inconsistent output/port/pipe state happens presumably due to
                  * a bug in one of the get_hw_state functions. Or someplace else
@@ -11578,8 +11580,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
                                     base.head) {
                         if (connector->encoder != encoder)
                                 continue;
-
-                        intel_connector_break_all_links(connector);
+                        connector->base.dpms = DRM_MODE_DPMS_OFF;
+                        connector->base.encoder = NULL;
                 }
         }
         /* Enabled encoders without active connectors will be fixed in
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dfa85289f28f..5ca68aa9f237 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
         case DP_LINK_BW_2_7:
                 break;
         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-                if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
+                if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
+                     INTEL_INFO(dev)->gen >= 8) &&
                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
                         max_link_bw = DP_LINK_BW_5_4;
                 else
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 940ece4934ba..012d58fa8ff0 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -191,8 +191,8 @@
         INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
         INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
         INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
-        INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
-        INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
+        INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+        INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
         INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
         INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
         INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \