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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/mach-u300/Makefile2
-rw-r--r--arch/arm/mach-u300/clock.c1504
-rw-r--r--arch/arm/mach-u300/clock.h50
-rw-r--r--arch/arm/mach-u300/core.c21
-rw-r--r--arch/arm/mach-u300/timer.c2
-rw-r--r--drivers/clk/Makefile3
-rw-r--r--drivers/clk/clk-u300.c746
-rw-r--r--include/linux/platform_data/clk-u300.h1
9 files changed, 763 insertions, 1568 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a91009c61870..c59853738967 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -888,7 +888,7 @@ config ARCH_U300
888 select ARM_VIC 888 select ARM_VIC
889 select GENERIC_CLOCKEVENTS 889 select GENERIC_CLOCKEVENTS
890 select CLKDEV_LOOKUP 890 select CLKDEV_LOOKUP
891 select HAVE_MACH_CLKDEV 891 select COMMON_CLK
892 select GENERIC_GPIO 892 select GENERIC_GPIO
893 select ARCH_REQUIRE_GPIOLIB 893 select ARCH_REQUIRE_GPIOLIB
894 help 894 help
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index fd3a5c382f47..7e47d37aeb0e 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel, U300 machine. 2# Makefile for the linux kernel, U300 machine.
3# 3#
4 4
5obj-y := core.o clock.o timer.o 5obj-y := core.o timer.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
deleted file mode 100644
index 5535dd0a78c9..000000000000
--- a/arch/arm/mach-u300/clock.c
+++ /dev/null
@@ -1,1504 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/clock.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Define clocks in the app platform.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/string.h>
19#include <linux/clk.h>
20#include <linux/mutex.h>
21#include <linux/spinlock.h>
22#include <linux/debugfs.h>
23#include <linux/device.h>
24#include <linux/init.h>
25#include <linux/timer.h>
26#include <linux/io.h>
27#include <linux/seq_file.h>
28#include <linux/clkdev.h>
29
30#include <mach/hardware.h>
31#include <mach/syscon.h>
32
33#include "clock.h"
34
35/*
36 * TODO:
37 * - move all handling of the CCR register into this file and create
38 * a spinlock for the CCR register
39 * - switch to the clkdevice lookup mechanism that maps clocks to
40 * device ID:s instead when it becomes available in kernel 2.6.29.
41 * - implement rate get/set for all clocks that need it.
42 */
43
44/*
45 * Syscon clock I/O registers lock so clock requests don't collide
46 * NOTE: this is a local lock only used to lock access to clock and
47 * reset registers in syscon.
48 */
49static DEFINE_SPINLOCK(syscon_clkreg_lock);
50static DEFINE_SPINLOCK(syscon_resetreg_lock);
51
52/*
53 * The clocking hierarchy currently looks like this.
54 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
55 * The ideas is to show dependencies, so a clock higher up in the
56 * hierarchy has to be on in order for another clock to be on. Now,
57 * both CPU and DMA can actually be on top of the hierarchy, and that
58 * is not modeled currently. Instead we have the backbone AMBA bus on
59 * top. This bus cannot be programmed in any way but conceptually it
60 * needs to be active for the bridges and devices to transport data.
61 *
62 * Please be aware that a few clocks are hw controlled, which mean that
63 * the hw itself can turn on/off or change the rate of the clock when
64 * needed!
65 *
66 * AMBA bus
67 * |
68 * +- CPU
69 * +- FSMC NANDIF NAND Flash interface
70 * +- SEMI Shared Memory interface
71 * +- ISP Image Signal Processor (U335 only)
72 * +- CDS (U335 only)
73 * +- DMA Direct Memory Access Controller
74 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
75 * +- APEX
76 * +- VIDEO_ENC AVE2/3 Video Encoder
77 * +- XGAM Graphics Accelerator Controller
78 * +- AHB
79 * |
80 * +- ahb:0 AHB Bridge
81 * | |
82 * | +- ahb:1 INTCON Interrupt controller
83 * | +- ahb:3 MSPRO Memory Stick Pro controller
84 * | +- ahb:4 EMIF External Memory interface
85 * |
86 * +- fast:0 FAST bridge
87 * | |
88 * | +- fast:1 MMCSD MMC/SD card reader controller
89 * | +- fast:2 I2S0 PCM I2S channel 0 controller
90 * | +- fast:3 I2S1 PCM I2S channel 1 controller
91 * | +- fast:4 I2C0 I2C channel 0 controller
92 * | +- fast:5 I2C1 I2C channel 1 controller
93 * | +- fast:6 SPI SPI controller
94 * | +- fast:7 UART1 Secondary UART (U335 only)
95 * |
96 * +- slow:0 SLOW bridge
97 * |
98 * +- slow:1 SYSCON (not possible to control)
99 * +- slow:2 WDOG Watchdog
100 * +- slow:3 UART0 primary UART
101 * +- slow:4 TIMER_APP Application timer - used in Linux
102 * +- slow:5 KEYPAD controller
103 * +- slow:6 GPIO controller
104 * +- slow:7 RTC controller
105 * +- slow:8 BT Bus Tracer (not used currently)
106 * +- slow:9 EH Event Handler (not used currently)
107 * +- slow:a TIMER_ACC Access style timer (not used currently)
108 * +- slow:b PPM (U335 only, what is that?)
109 */
110
111/*
112 * Reset control functions. We remember if a block has been
113 * taken out of reset and don't remove the reset assertion again
114 * and vice versa. Currently we only remove resets so the
115 * enablement function is defined out.
116 */
117static void syscon_block_reset_enable(struct clk *clk)
118{
119 u16 val;
120 unsigned long iflags;
121
122 /* Not all blocks support resetting */
123 if (!clk->res_reg || !clk->res_mask)
124 return;
125 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
126 val = readw(clk->res_reg);
127 val |= clk->res_mask;
128 writew(val, clk->res_reg);
129 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
130 clk->reset = true;
131}
132
133static void syscon_block_reset_disable(struct clk *clk)
134{
135 u16 val;
136 unsigned long iflags;
137
138 /* Not all blocks support resetting */
139 if (!clk->res_reg || !clk->res_mask)
140 return;
141 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
142 val = readw(clk->res_reg);
143 val &= ~clk->res_mask;
144 writew(val, clk->res_reg);
145 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
146 clk->reset = false;
147}
148
149int __clk_get(struct clk *clk)
150{
151 u16 val;
152
153 /* The MMC and MSPRO clocks need some special set-up */
154 if (!strcmp(clk->name, "MCLK")) {
155 /* Set default MMC clock divisor to 18.9 MHz */
156 writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
157 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
158 /* Disable the MMC feedback clock */
159 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
160 /* Disable MSPRO frequency */
161 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
162 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
163 }
164 if (!strcmp(clk->name, "MSPRO")) {
165 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
166 /* Disable the MMC feedback clock */
167 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
168 /* Enable MSPRO frequency */
169 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
170 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
171 }
172 return 1;
173}
174EXPORT_SYMBOL(__clk_get);
175
176void __clk_put(struct clk *clk)
177{
178}
179EXPORT_SYMBOL(__clk_put);
180
181static void syscon_clk_disable(struct clk *clk)
182{
183 unsigned long iflags;
184
185 /* Don't touch the hardware controlled clocks */
186 if (clk->hw_ctrld)
187 return;
188
189 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
190 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
191 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
192}
193
194static void syscon_clk_enable(struct clk *clk)
195{
196 unsigned long iflags;
197
198 /* Don't touch the hardware controlled clocks */
199 if (clk->hw_ctrld)
200 return;
201
202 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
203 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
204 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
205}
206
207static u16 syscon_clk_get_rate(void)
208{
209 u16 val;
210 unsigned long iflags;
211
212 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
213 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
214 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
215 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
216 return val;
217}
218
219#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
220static void enable_i2s0_vcxo(void)
221{
222 u16 val;
223 unsigned long iflags;
224
225 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
226 /* Set I2S0 to use the VCXO 26 MHz clock */
227 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
228 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
229 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
230 val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
231 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
232 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
233 val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
234 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
235 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
236}
237
238static void enable_i2s1_vcxo(void)
239{
240 u16 val;
241 unsigned long iflags;
242
243 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
244 /* Set I2S1 to use the VCXO 26 MHz clock */
245 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
246 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
247 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
248 val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
249 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
250 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
251 val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
252 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
253 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
254}
255
256static void disable_i2s0_vcxo(void)
257{
258 u16 val;
259 unsigned long iflags;
260
261 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
262 /* Disable I2S0 use of the VCXO 26 MHz clock */
263 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
264 val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
265 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
266 /* Deactivate VCXO if no one else is using VCXO */
267 if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
268 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
269 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
270 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
271 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
272 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
273 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
274}
275
276static void disable_i2s1_vcxo(void)
277{
278 u16 val;
279 unsigned long iflags;
280
281 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
282 /* Disable I2S1 use of the VCXO 26 MHz clock */
283 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
284 val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
285 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
286 /* Deactivate VCXO if no one else is using VCXO */
287 if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
288 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
289 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
290 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
291 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
292 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
293 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
294}
295#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
296
297
298static void syscon_clk_rate_set_mclk(unsigned long rate)
299{
300 u16 val;
301 u32 reg;
302 unsigned long iflags;
303
304 switch (rate) {
305 case 18900000:
306 val = 0x0054;
307 break;
308 case 20800000:
309 val = 0x0044;
310 break;
311 case 23100000:
312 val = 0x0043;
313 break;
314 case 26000000:
315 val = 0x0033;
316 break;
317 case 29700000:
318 val = 0x0032;
319 break;
320 case 34700000:
321 val = 0x0022;
322 break;
323 case 41600000:
324 val = 0x0021;
325 break;
326 case 52000000:
327 val = 0x0011;
328 break;
329 case 104000000:
330 val = 0x0000;
331 break;
332 default:
333 printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
334 rate);
335 return;
336 }
337
338 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
339 reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
340 ~U300_SYSCON_MMF0R_MASK;
341 writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
342 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
343}
344
345void syscon_clk_rate_set_cpuclk(unsigned long rate)
346{
347 u16 val;
348 unsigned long iflags;
349
350 switch (rate) {
351 case 13000000:
352 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
353 break;
354 case 52000000:
355 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
356 break;
357 case 104000000:
358 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
359 break;
360 case 208000000:
361 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
362 break;
363 default:
364 return;
365 }
366 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
367 val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
368 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
369 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
370 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
371}
372EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
373
374void clk_disable(struct clk *clk)
375{
376 unsigned long iflags;
377
378 spin_lock_irqsave(&clk->lock, iflags);
379 if (clk->usecount > 0 && !(--clk->usecount)) {
380 /* some blocks lack clocking registers and cannot be disabled */
381 if (clk->disable)
382 clk->disable(clk);
383 if (likely((u32)clk->parent))
384 clk_disable(clk->parent);
385 }
386#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
387 if (unlikely(!strcmp(clk->name, "I2S0")))
388 disable_i2s0_vcxo();
389 if (unlikely(!strcmp(clk->name, "I2S1")))
390 disable_i2s1_vcxo();
391#endif
392 spin_unlock_irqrestore(&clk->lock, iflags);
393}
394EXPORT_SYMBOL(clk_disable);
395
396int clk_enable(struct clk *clk)
397{
398 int ret = 0;
399 unsigned long iflags;
400
401 spin_lock_irqsave(&clk->lock, iflags);
402 if (clk->usecount++ == 0) {
403 if (likely((u32)clk->parent))
404 ret = clk_enable(clk->parent);
405
406 if (unlikely(ret != 0))
407 clk->usecount--;
408 else {
409 /* remove reset line (we never enable reset again) */
410 syscon_block_reset_disable(clk);
411 /* clocks without enable function are always on */
412 if (clk->enable)
413 clk->enable(clk);
414#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
415 if (unlikely(!strcmp(clk->name, "I2S0")))
416 enable_i2s0_vcxo();
417 if (unlikely(!strcmp(clk->name, "I2S1")))
418 enable_i2s1_vcxo();
419#endif
420 }
421 }
422 spin_unlock_irqrestore(&clk->lock, iflags);
423 return ret;
424
425}
426EXPORT_SYMBOL(clk_enable);
427
428/* Returns the clock rate in Hz */
429static unsigned long clk_get_rate_cpuclk(struct clk *clk)
430{
431 u16 val;
432
433 val = syscon_clk_get_rate();
434
435 switch (val) {
436 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
437 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
438 return 13000000;
439 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
440 return 52000000;
441 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
442 return 104000000;
443 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
444 return 208000000;
445 default:
446 break;
447 }
448 return clk->rate;
449}
450
451static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
452{
453 u16 val;
454
455 val = syscon_clk_get_rate();
456
457 switch (val) {
458 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
459 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
460 return 6500000;
461 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
462 return 26000000;
463 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
464 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
465 return 52000000;
466 default:
467 break;
468 }
469 return clk->rate;
470
471}
472
473static unsigned long clk_get_rate_emif_clk(struct clk *clk)
474{
475 u16 val;
476
477 val = syscon_clk_get_rate();
478
479 switch (val) {
480 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
481 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
482 return 13000000;
483 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
484 return 52000000;
485 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
486 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
487 return 104000000;
488 default:
489 break;
490 }
491 return clk->rate;
492
493}
494
495static unsigned long clk_get_rate_xgamclk(struct clk *clk)
496{
497 u16 val;
498
499 val = syscon_clk_get_rate();
500
501 switch (val) {
502 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
503 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
504 return 6500000;
505 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
506 return 26000000;
507 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
508 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
509 return 52000000;
510 default:
511 break;
512 }
513
514 return clk->rate;
515}
516
517static unsigned long clk_get_rate_mclk(struct clk *clk)
518{
519 u16 val;
520
521 val = syscon_clk_get_rate();
522
523 switch (val) {
524 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
525 /*
526 * Here, the 208 MHz PLL gets shut down and the always
527 * on 13 MHz PLL used for RTC etc kicks into use
528 * instead.
529 */
530 return 13000000;
531 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
532 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
533 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
534 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
535 {
536 /*
537 * This clock is under program control. The register is
538 * divided in two nybbles, bit 7-4 gives cycles-1 to count
539 * high, bit 3-0 gives cycles-1 to count low. Distribute
540 * these with no more than 1 cycle difference between
541 * low and high and add low and high to get the actual
542 * divisor. The base PLL is 208 MHz. Writing 0x00 will
543 * divide by 1 and 1 so the highest frequency possible
544 * is 104 MHz.
545 *
546 * e.g. 0x54 =>
547 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
548 */
549 u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
550 U300_SYSCON_MMF0R_MASK;
551 switch (val) {
552 case 0x0054:
553 return 18900000;
554 case 0x0044:
555 return 20800000;
556 case 0x0043:
557 return 23100000;
558 case 0x0033:
559 return 26000000;
560 case 0x0032:
561 return 29700000;
562 case 0x0022:
563 return 34700000;
564 case 0x0021:
565 return 41600000;
566 case 0x0011:
567 return 52000000;
568 case 0x0000:
569 return 104000000;
570 default:
571 break;
572 }
573 }
574 default:
575 break;
576 }
577
578 return clk->rate;
579}
580
581static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
582{
583 u16 val;
584
585 val = syscon_clk_get_rate();
586
587 switch (val) {
588 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
589 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
590 return 13000000;
591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
592 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
593 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
594 return 26000000;
595 default:
596 break;
597 }
598
599 return clk->rate;
600}
601
602unsigned long clk_get_rate(struct clk *clk)
603{
604 if (clk->get_rate)
605 return clk->get_rate(clk);
606 else
607 return clk->rate;
608}
609EXPORT_SYMBOL(clk_get_rate);
610
611static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
612{
613 if (rate <= 18900000)
614 return 18900000;
615 if (rate <= 20800000)
616 return 20800000;
617 if (rate <= 23100000)
618 return 23100000;
619 if (rate <= 26000000)
620 return 26000000;
621 if (rate <= 29700000)
622 return 29700000;
623 if (rate <= 34700000)
624 return 34700000;
625 if (rate <= 41600000)
626 return 41600000;
627 if (rate <= 52000000)
628 return 52000000;
629 return -EINVAL;
630}
631
632static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
633{
634 if (rate <= 13000000)
635 return 13000000;
636 if (rate <= 52000000)
637 return 52000000;
638 if (rate <= 104000000)
639 return 104000000;
640 if (rate <= 208000000)
641 return 208000000;
642 return -EINVAL;
643}
644
645/*
646 * This adjusts a requested rate to the closest exact rate
647 * a certain clock can provide. For a fixed clock it's
648 * mostly clk->rate.
649 */
650long clk_round_rate(struct clk *clk, unsigned long rate)
651{
652 /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */
653 /* Else default to fixed value */
654
655 if (clk->round_rate) {
656 return (long) clk->round_rate(clk, rate);
657 } else {
658 printk(KERN_ERR "clock: Failed to round rate of %s\n",
659 clk->name);
660 }
661 return (long) clk->rate;
662}
663EXPORT_SYMBOL(clk_round_rate);
664
665static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
666{
667 syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
668 return 0;
669}
670
671static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
672{
673 syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
674 return 0;
675}
676
677int clk_set_rate(struct clk *clk, unsigned long rate)
678{
679 /* TODO: set for EMIFCLK and AHBCLK */
680 /* Else assume the clock is fixed and fail */
681 if (clk->set_rate) {
682 return clk->set_rate(clk, rate);
683 } else {
684 printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
685 clk->name, rate);
686 return -EINVAL;
687 }
688}
689EXPORT_SYMBOL(clk_set_rate);
690
691/*
692 * Clock definitions. The clock parents are set to respective
693 * bridge and the clock framework makes sure that the clocks have
694 * parents activated and are brought out of reset when in use.
695 *
696 * Clocks that have hw_ctrld = true are hw controlled, and the hw
697 * can by itself turn these clocks on and off.
698 * So in other words, we don't really have to care about them.
699 */
700
701static struct clk amba_clk = {
702 .name = "AMBA",
703 .rate = 52000000, /* this varies! */
704 .hw_ctrld = true,
705 .reset = false,
706 .lock = __SPIN_LOCK_UNLOCKED(amba_clk.lock),
707};
708
709/*
710 * These blocks are connected directly to the AMBA bus
711 * with no bridge.
712 */
713
714static struct clk cpu_clk = {
715 .name = "CPU",
716 .parent = &amba_clk,
717 .rate = 208000000, /* this varies! */
718 .hw_ctrld = true,
719 .reset = true,
720 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
721 .res_mask = U300_SYSCON_RRR_CPU_RESET_EN,
722 .set_rate = clk_set_rate_cpuclk,
723 .get_rate = clk_get_rate_cpuclk,
724 .round_rate = clk_round_rate_cpuclk,
725 .lock = __SPIN_LOCK_UNLOCKED(cpu_clk.lock),
726};
727
728static struct clk nandif_clk = {
729 .name = "FSMC",
730 .parent = &amba_clk,
731 .hw_ctrld = false,
732 .reset = true,
733 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
734 .res_mask = U300_SYSCON_RRR_NANDIF_RESET_EN,
735 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
736 .enable = syscon_clk_enable,
737 .disable = syscon_clk_disable,
738 .lock = __SPIN_LOCK_UNLOCKED(nandif_clk.lock),
739};
740
741static struct clk semi_clk = {
742 .name = "SEMI",
743 .parent = &amba_clk,
744 .rate = 0, /* FIXME */
745 /* It is not possible to reset SEMI */
746 .hw_ctrld = false,
747 .reset = false,
748 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
749 .enable = syscon_clk_enable,
750 .disable = syscon_clk_disable,
751 .lock = __SPIN_LOCK_UNLOCKED(semi_clk.lock),
752};
753
754#ifdef CONFIG_MACH_U300_BS335
755static struct clk isp_clk = {
756 .name = "ISP",
757 .parent = &amba_clk,
758 .rate = 0, /* FIXME */
759 .hw_ctrld = false,
760 .reset = true,
761 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
762 .res_mask = U300_SYSCON_RRR_ISP_RESET_EN,
763 .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN,
764 .enable = syscon_clk_enable,
765 .disable = syscon_clk_disable,
766 .lock = __SPIN_LOCK_UNLOCKED(isp_clk.lock),
767};
768
769static struct clk cds_clk = {
770 .name = "CDS",
771 .parent = &amba_clk,
772 .rate = 0, /* FIXME */
773 .hw_ctrld = false,
774 .reset = true,
775 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
776 .res_mask = U300_SYSCON_RRR_CDS_RESET_EN,
777 .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN,
778 .enable = syscon_clk_enable,
779 .disable = syscon_clk_disable,
780 .lock = __SPIN_LOCK_UNLOCKED(cds_clk.lock),
781};
782#endif
783
784static struct clk dma_clk = {
785 .name = "DMA",
786 .parent = &amba_clk,
787 .rate = 52000000, /* this varies! */
788 .hw_ctrld = true,
789 .reset = true,
790 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
791 .res_mask = U300_SYSCON_RRR_DMAC_RESET_EN,
792 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
793 .enable = syscon_clk_enable,
794 .disable = syscon_clk_disable,
795 .lock = __SPIN_LOCK_UNLOCKED(dma_clk.lock),
796};
797
798static struct clk aaif_clk = {
799 .name = "AAIF",
800 .parent = &amba_clk,
801 .rate = 52000000, /* this varies! */
802 .hw_ctrld = true,
803 .reset = true,
804 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
805 .res_mask = U300_SYSCON_RRR_AAIF_RESET_EN,
806 .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN,
807 .enable = syscon_clk_enable,
808 .disable = syscon_clk_disable,
809 .lock = __SPIN_LOCK_UNLOCKED(aaif_clk.lock),
810};
811
812static struct clk apex_clk = {
813 .name = "APEX",
814 .parent = &amba_clk,
815 .rate = 0, /* FIXME */
816 .hw_ctrld = true,
817 .reset = true,
818 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
819 .res_mask = U300_SYSCON_RRR_APEX_RESET_EN,
820 .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN,
821 .enable = syscon_clk_enable,
822 .disable = syscon_clk_disable,
823 .lock = __SPIN_LOCK_UNLOCKED(apex_clk.lock),
824};
825
826static struct clk video_enc_clk = {
827 .name = "VIDEO_ENC",
828 .parent = &amba_clk,
829 .rate = 208000000, /* this varies! */
830 .hw_ctrld = false,
831 .reset = false,
832 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
833 /* This has XGAM in the name but refers to the video encoder */
834 .res_mask = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
835 .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
836 .enable = syscon_clk_enable,
837 .disable = syscon_clk_disable,
838 .lock = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock),
839};
840
841static struct clk xgam_clk = {
842 .name = "XGAMCLK",
843 .parent = &amba_clk,
844 .rate = 52000000, /* this varies! */
845 .hw_ctrld = false,
846 .reset = true,
847 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
848 .res_mask = U300_SYSCON_RRR_XGAM_RESET_EN,
849 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
850 .get_rate = clk_get_rate_xgamclk,
851 .enable = syscon_clk_enable,
852 .disable = syscon_clk_disable,
853 .lock = __SPIN_LOCK_UNLOCKED(xgam_clk.lock),
854};
855
856/* This clock is used to activate the video encoder */
857static struct clk ahb_clk = {
858 .name = "AHB",
859 .parent = &amba_clk,
860 .rate = 52000000, /* this varies! */
861 .hw_ctrld = false, /* This one is set to false due to HW bug */
862 .reset = true,
863 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
864 .res_mask = U300_SYSCON_RRR_AHB_RESET_EN,
865 .clk_val = U300_SYSCON_SBCER_AHB_CLK_EN,
866 .enable = syscon_clk_enable,
867 .disable = syscon_clk_disable,
868 .get_rate = clk_get_rate_ahb_clk,
869 .lock = __SPIN_LOCK_UNLOCKED(ahb_clk.lock),
870};
871
872
873/*
874 * Clocks on the AHB bridge
875 */
876
877static struct clk ahb_subsys_clk = {
878 .name = "AHB_SUBSYS",
879 .parent = &amba_clk,
880 .rate = 52000000, /* this varies! */
881 .hw_ctrld = true,
882 .reset = false,
883 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
884 .enable = syscon_clk_enable,
885 .disable = syscon_clk_disable,
886 .get_rate = clk_get_rate_ahb_clk,
887 .lock = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock),
888};
889
890static struct clk intcon_clk = {
891 .name = "INTCON",
892 .parent = &ahb_subsys_clk,
893 .rate = 52000000, /* this varies! */
894 .hw_ctrld = false,
895 .reset = true,
896 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
897 .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN,
898 /* INTCON can be reset but not clock-gated */
899 .lock = __SPIN_LOCK_UNLOCKED(intcon_clk.lock),
900
901};
902
903static struct clk mspro_clk = {
904 .name = "MSPRO",
905 .parent = &ahb_subsys_clk,
906 .rate = 0, /* FIXME */
907 .hw_ctrld = false,
908 .reset = true,
909 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
910 .res_mask = U300_SYSCON_RRR_MSPRO_RESET_EN,
911 .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN,
912 .enable = syscon_clk_enable,
913 .disable = syscon_clk_disable,
914 .lock = __SPIN_LOCK_UNLOCKED(mspro_clk.lock),
915};
916
917static struct clk emif_clk = {
918 .name = "EMIF",
919 .parent = &ahb_subsys_clk,
920 .rate = 104000000, /* this varies! */
921 .hw_ctrld = false,
922 .reset = true,
923 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
924 .res_mask = U300_SYSCON_RRR_EMIF_RESET_EN,
925 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
926 .enable = syscon_clk_enable,
927 .disable = syscon_clk_disable,
928 .get_rate = clk_get_rate_emif_clk,
929 .lock = __SPIN_LOCK_UNLOCKED(emif_clk.lock),
930};
931
932
933/*
934 * Clocks on the FAST bridge
935 */
936static struct clk fast_clk = {
937 .name = "FAST_BRIDGE",
938 .parent = &amba_clk,
939 .rate = 13000000, /* this varies! */
940 .hw_ctrld = true,
941 .reset = true,
942 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
943 .res_mask = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
944 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
945 .enable = syscon_clk_enable,
946 .disable = syscon_clk_disable,
947 .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock),
948};
949
950/*
951 * The MMCI apb_pclk is hardwired to the same terminal as the
952 * external MCI clock. Thus this will be referenced twice.
953 */
954static struct clk mmcsd_clk = {
955 .name = "MCLK",
956 .parent = &fast_clk,
957 .rate = 18900000, /* this varies! */
958 .hw_ctrld = false,
959 .reset = true,
960 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
961 .res_mask = U300_SYSCON_RFR_MMC_RESET_ENABLE,
962 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
963 .get_rate = clk_get_rate_mclk,
964 .set_rate = clk_set_rate_mclk,
965 .round_rate = clk_round_rate_mclk,
966 .disable = syscon_clk_disable,
967 .enable = syscon_clk_enable,
968 .lock = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock),
969};
970
971static struct clk i2s0_clk = {
972 .name = "i2s0",
973 .parent = &fast_clk,
974 .rate = 26000000, /* this varies! */
975 .hw_ctrld = true,
976 .reset = true,
977 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
978 .res_mask = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
979 .clk_val = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
980 .enable = syscon_clk_enable,
981 .disable = syscon_clk_disable,
982 .get_rate = clk_get_rate_i2s_i2c_spi,
983 .lock = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock),
984};
985
986static struct clk i2s1_clk = {
987 .name = "i2s1",
988 .parent = &fast_clk,
989 .rate = 26000000, /* this varies! */
990 .hw_ctrld = true,
991 .reset = true,
992 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
993 .res_mask = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
994 .clk_val = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
995 .enable = syscon_clk_enable,
996 .disable = syscon_clk_disable,
997 .get_rate = clk_get_rate_i2s_i2c_spi,
998 .lock = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock),
999};
1000
1001static struct clk i2c0_clk = {
1002 .name = "I2C0",
1003 .parent = &fast_clk,
1004 .rate = 26000000, /* this varies! */
1005 .hw_ctrld = false,
1006 .reset = true,
1007 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1008 .res_mask = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
1009 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
1010 .enable = syscon_clk_enable,
1011 .disable = syscon_clk_disable,
1012 .get_rate = clk_get_rate_i2s_i2c_spi,
1013 .lock = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock),
1014};
1015
1016static struct clk i2c1_clk = {
1017 .name = "I2C1",
1018 .parent = &fast_clk,
1019 .rate = 26000000, /* this varies! */
1020 .hw_ctrld = false,
1021 .reset = true,
1022 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1023 .res_mask = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
1024 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
1025 .enable = syscon_clk_enable,
1026 .disable = syscon_clk_disable,
1027 .get_rate = clk_get_rate_i2s_i2c_spi,
1028 .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock),
1029};
1030
1031/*
1032 * The SPI apb_pclk is hardwired to the same terminal as the
1033 * external SPI clock. Thus this will be referenced twice.
1034 */
1035static struct clk spi_clk = {
1036 .name = "SPI",
1037 .parent = &fast_clk,
1038 .rate = 26000000, /* this varies! */
1039 .hw_ctrld = false,
1040 .reset = true,
1041 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1042 .res_mask = U300_SYSCON_RFR_SPI_RESET_ENABLE,
1043 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
1044 .enable = syscon_clk_enable,
1045 .disable = syscon_clk_disable,
1046 .get_rate = clk_get_rate_i2s_i2c_spi,
1047 .lock = __SPIN_LOCK_UNLOCKED(spi_clk.lock),
1048};
1049
1050#ifdef CONFIG_MACH_U300_BS335
1051static struct clk uart1_pclk = {
1052 .name = "UART1_PCLK",
1053 .parent = &fast_clk,
1054 .hw_ctrld = false,
1055 .reset = true,
1056 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1057 .res_mask = U300_SYSCON_RFR_UART1_RESET_ENABLE,
1058 .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN,
1059 .enable = syscon_clk_enable,
1060 .disable = syscon_clk_disable,
1061 .lock = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock),
1062};
1063
1064/* This one is hardwired to PLL13 */
1065static struct clk uart1_clk = {
1066 .name = "UART1_CLK",
1067 .rate = 13000000,
1068 .hw_ctrld = true,
1069 .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock),
1070};
1071#endif
1072
1073
1074/*
1075 * Clocks on the SLOW bridge
1076 */
1077static struct clk slow_clk = {
1078 .name = "SLOW_BRIDGE",
1079 .parent = &amba_clk,
1080 .rate = 13000000,
1081 .hw_ctrld = true,
1082 .reset = true,
1083 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1084 .res_mask = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
1085 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
1086 .enable = syscon_clk_enable,
1087 .disable = syscon_clk_disable,
1088 .lock = __SPIN_LOCK_UNLOCKED(slow_clk.lock),
1089};
1090
1091/* TODO: implement SYSCON clock? */
1092
1093static struct clk wdog_clk = {
1094 .name = "WDOG",
1095 .parent = &slow_clk,
1096 .hw_ctrld = false,
1097 .rate = 32768,
1098 .reset = false,
1099 /* This is always on, cannot be enabled/disabled or reset */
1100 .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock),
1101};
1102
1103static struct clk uart0_pclk = {
1104 .name = "UART0_PCLK",
1105 .parent = &slow_clk,
1106 .hw_ctrld = false,
1107 .reset = true,
1108 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1109 .res_mask = U300_SYSCON_RSR_UART_RESET_EN,
1110 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
1111 .enable = syscon_clk_enable,
1112 .disable = syscon_clk_disable,
1113 .lock = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock),
1114};
1115
1116/* This one is hardwired to PLL13 */
1117static struct clk uart0_clk = {
1118 .name = "UART0_CLK",
1119 .parent = &slow_clk,
1120 .rate = 13000000,
1121 .hw_ctrld = true,
1122 .lock = __SPIN_LOCK_UNLOCKED(uart0_clk.lock),
1123};
1124
1125static struct clk keypad_clk = {
1126 .name = "KEYPAD",
1127 .parent = &slow_clk,
1128 .rate = 32768,
1129 .hw_ctrld = false,
1130 .reset = true,
1131 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1132 .res_mask = U300_SYSCON_RSR_KEYPAD_RESET_EN,
1133 .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
1134 .enable = syscon_clk_enable,
1135 .disable = syscon_clk_disable,
1136 .lock = __SPIN_LOCK_UNLOCKED(keypad_clk.lock),
1137};
1138
1139static struct clk gpio_clk = {
1140 .name = "GPIO",
1141 .parent = &slow_clk,
1142 .rate = 13000000,
1143 .hw_ctrld = true,
1144 .reset = true,
1145 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1146 .res_mask = U300_SYSCON_RSR_GPIO_RESET_EN,
1147 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
1148 .enable = syscon_clk_enable,
1149 .disable = syscon_clk_disable,
1150 .lock = __SPIN_LOCK_UNLOCKED(gpio_clk.lock),
1151};
1152
1153static struct clk rtc_clk = {
1154 .name = "RTC",
1155 .parent = &slow_clk,
1156 .rate = 32768,
1157 .hw_ctrld = true,
1158 .reset = true,
1159 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1160 .res_mask = U300_SYSCON_RSR_RTC_RESET_EN,
1161 /* This clock is always on, cannot be enabled/disabled */
1162 .lock = __SPIN_LOCK_UNLOCKED(rtc_clk.lock),
1163};
1164
1165static struct clk bustr_clk = {
1166 .name = "BUSTR",
1167 .parent = &slow_clk,
1168 .rate = 13000000,
1169 .hw_ctrld = true,
1170 .reset = true,
1171 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1172 .res_mask = U300_SYSCON_RSR_BTR_RESET_EN,
1173 .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN,
1174 .enable = syscon_clk_enable,
1175 .disable = syscon_clk_disable,
1176 .lock = __SPIN_LOCK_UNLOCKED(bustr_clk.lock),
1177};
1178
1179static struct clk evhist_clk = {
1180 .name = "EVHIST",
1181 .parent = &slow_clk,
1182 .rate = 13000000,
1183 .hw_ctrld = true,
1184 .reset = true,
1185 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1186 .res_mask = U300_SYSCON_RSR_EH_RESET_EN,
1187 .clk_val = U300_SYSCON_SBCER_EH_CLK_EN,
1188 .enable = syscon_clk_enable,
1189 .disable = syscon_clk_disable,
1190 .lock = __SPIN_LOCK_UNLOCKED(evhist_clk.lock),
1191};
1192
1193static struct clk timer_clk = {
1194 .name = "TIMER",
1195 .parent = &slow_clk,
1196 .rate = 13000000,
1197 .hw_ctrld = true,
1198 .reset = true,
1199 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1200 .res_mask = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
1201 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
1202 .enable = syscon_clk_enable,
1203 .disable = syscon_clk_disable,
1204 .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock),
1205};
1206
1207/*
1208 * There is a binary divider in the hardware that divides
1209 * the 13MHz PLL by 13 down to 1 MHz.
1210 */
1211static struct clk app_timer_clk = {
1212 .name = "TIMER_APP",
1213 .parent = &slow_clk,
1214 .rate = 1000000,
1215 .hw_ctrld = true,
1216 .reset = true,
1217 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1218 .res_mask = U300_SYSCON_RSR_APP_TMR_RESET_EN,
1219 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
1220 .enable = syscon_clk_enable,
1221 .disable = syscon_clk_disable,
1222 .lock = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock),
1223};
1224
1225#ifdef CONFIG_MACH_U300_BS335
1226static struct clk ppm_clk = {
1227 .name = "PPM",
1228 .parent = &slow_clk,
1229 .rate = 0, /* FIXME */
1230 .hw_ctrld = true, /* TODO: Look up if it is hw ctrld or not */
1231 .reset = true,
1232 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1233 .res_mask = U300_SYSCON_RSR_PPM_RESET_EN,
1234 .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN,
1235 .enable = syscon_clk_enable,
1236 .disable = syscon_clk_disable,
1237 .lock = __SPIN_LOCK_UNLOCKED(ppm_clk.lock),
1238};
1239#endif
1240
1241#define DEF_LOOKUP(devid, clkref) \
1242 { \
1243 .dev_id = devid, \
1244 .clk = clkref, \
1245 }
1246
1247#define DEF_LOOKUP_CON(devid, conid, clkref) \
1248 { \
1249 .dev_id = devid, \
1250 .con_id = conid, \
1251 .clk = clkref, \
1252 }
1253
1254/*
1255 * Here we only define clocks that are meaningful to
1256 * look up through clockdevice.
1257 */
1258static struct clk_lookup lookups[] = {
1259 /* Connected directly to the AMBA bus */
1260 DEF_LOOKUP("amba", &amba_clk),
1261 DEF_LOOKUP("cpu", &cpu_clk),
1262 DEF_LOOKUP("fsmc-nand", &nandif_clk),
1263 DEF_LOOKUP("semi", &semi_clk),
1264#ifdef CONFIG_MACH_U300_BS335
1265 DEF_LOOKUP("isp", &isp_clk),
1266 DEF_LOOKUP("cds", &cds_clk),
1267#endif
1268 DEF_LOOKUP("dma", &dma_clk),
1269 DEF_LOOKUP("msl", &aaif_clk),
1270 DEF_LOOKUP("apex", &apex_clk),
1271 DEF_LOOKUP("video_enc", &video_enc_clk),
1272 DEF_LOOKUP("xgam", &xgam_clk),
1273 DEF_LOOKUP("ahb", &ahb_clk),
1274 /* AHB bridge clocks */
1275 DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk),
1276 DEF_LOOKUP("intcon", &intcon_clk),
1277 DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk),
1278 DEF_LOOKUP("mspro", &mspro_clk),
1279 DEF_LOOKUP("pl172", &emif_clk),
1280 DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk),
1281 /* FAST bridge clocks */
1282 DEF_LOOKUP("fast", &fast_clk),
1283 DEF_LOOKUP("mmci", &mmcsd_clk),
1284 DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk),
1285 /*
1286 * The .0 and .1 identifiers on these comes from the platform device
1287 * .id field and are assigned when the platform devices are registered.
1288 */
1289 DEF_LOOKUP("i2s.0", &i2s0_clk),
1290 DEF_LOOKUP("i2s.1", &i2s1_clk),
1291 DEF_LOOKUP("stu300.0", &i2c0_clk),
1292 DEF_LOOKUP("stu300.1", &i2c1_clk),
1293 DEF_LOOKUP("pl022", &spi_clk),
1294 DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk),
1295#ifdef CONFIG_MACH_U300_BS335
1296 DEF_LOOKUP("uart1", &uart1_clk),
1297 DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk),
1298#endif
1299 /* SLOW bridge clocks */
1300 DEF_LOOKUP("slow", &slow_clk),
1301 DEF_LOOKUP("coh901327_wdog", &wdog_clk),
1302 DEF_LOOKUP("uart0", &uart0_clk),
1303 DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk),
1304 DEF_LOOKUP("apptimer", &app_timer_clk),
1305 DEF_LOOKUP("coh901461-keypad", &keypad_clk),
1306 DEF_LOOKUP("u300-gpio", &gpio_clk),
1307 DEF_LOOKUP("rtc-coh901331", &rtc_clk),
1308 DEF_LOOKUP("bustr", &bustr_clk),
1309 DEF_LOOKUP("evhist", &evhist_clk),
1310 DEF_LOOKUP("timer", &timer_clk),
1311#ifdef CONFIG_MACH_U300_BS335
1312 DEF_LOOKUP("ppm", &ppm_clk),
1313#endif
1314};
1315
1316static void __init clk_register(void)
1317{
1318 /* Register the lookups */
1319 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1320}
1321
1322#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
1323/*
1324 * The following makes it possible to view the status (especially
1325 * reference count and reset status) for the clocks in the platform
1326 * by looking into the special file <debugfs>/u300_clocks
1327 */
1328
1329/* A list of all clocks in the platform */
1330static struct clk *clks[] = {
1331 /* Top node clock for the AMBA bus */
1332 &amba_clk,
1333 /* Connected directly to the AMBA bus */
1334 &cpu_clk,
1335 &nandif_clk,
1336 &semi_clk,
1337#ifdef CONFIG_MACH_U300_BS335
1338 &isp_clk,
1339 &cds_clk,
1340#endif
1341 &dma_clk,
1342 &aaif_clk,
1343 &apex_clk,
1344 &video_enc_clk,
1345 &xgam_clk,
1346 &ahb_clk,
1347
1348 /* AHB bridge clocks */
1349 &ahb_subsys_clk,
1350 &intcon_clk,
1351 &mspro_clk,
1352 &emif_clk,
1353 /* FAST bridge clocks */
1354 &fast_clk,
1355 &mmcsd_clk,
1356 &i2s0_clk,
1357 &i2s1_clk,
1358 &i2c0_clk,
1359 &i2c1_clk,
1360 &spi_clk,
1361#ifdef CONFIG_MACH_U300_BS335
1362 &uart1_clk,
1363 &uart1_pclk,
1364#endif
1365 /* SLOW bridge clocks */
1366 &slow_clk,
1367 &wdog_clk,
1368 &uart0_clk,
1369 &uart0_pclk,
1370 &app_timer_clk,
1371 &keypad_clk,
1372 &gpio_clk,
1373 &rtc_clk,
1374 &bustr_clk,
1375 &evhist_clk,
1376 &timer_clk,
1377#ifdef CONFIG_MACH_U300_BS335
1378 &ppm_clk,
1379#endif
1380};
1381
1382static int u300_clocks_show(struct seq_file *s, void *data)
1383{
1384 struct clk *clk;
1385 int i;
1386
1387 seq_printf(s, "CLOCK DEVICE RESET STATE\t" \
1388 "ACTIVE\tUSERS\tHW CTRL FREQ\n");
1389 seq_printf(s, "---------------------------------------------" \
1390 "-----------------------------------------\n");
1391 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1392 clk = clks[i];
1393 if (clk != ERR_PTR(-ENOENT)) {
1394 /* Format clock and device name nicely */
1395 char cdp[33];
1396 int chars;
1397
1398 chars = snprintf(&cdp[0], 17, "%s", clk->name);
1399 while (chars < 16) {
1400 cdp[chars] = ' ';
1401 chars++;
1402 }
1403 chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
1404 dev_name(clk->dev) : "N/A");
1405 while (chars < 16) {
1406 cdp[chars+16] = ' ';
1407 chars++;
1408 }
1409 cdp[32] = '\0';
1410 if (clk->get_rate || clk->rate != 0)
1411 seq_printf(s,
1412 "%s%s\t%s\t%d\t%s\t%lu Hz\n",
1413 &cdp[0],
1414 clk->reset ?
1415 "ASSERTED" : "RELEASED",
1416 clk->usecount ? "ON" : "OFF",
1417 clk->usecount,
1418 clk->hw_ctrld ? "YES" : "NO ",
1419 clk_get_rate(clk));
1420 else
1421 seq_printf(s,
1422 "%s%s\t%s\t%d\t%s\t" \
1423 "(unknown rate)\n",
1424 &cdp[0],
1425 clk->reset ?
1426 "ASSERTED" : "RELEASED",
1427 clk->usecount ? "ON" : "OFF",
1428 clk->usecount,
1429 clk->hw_ctrld ? "YES" : "NO ");
1430 }
1431 }
1432 return 0;
1433}
1434
1435static int u300_clocks_open(struct inode *inode, struct file *file)
1436{
1437 return single_open(file, u300_clocks_show, NULL);
1438}
1439
1440static const struct file_operations u300_clocks_operations = {
1441 .open = u300_clocks_open,
1442 .read = seq_read,
1443 .llseek = seq_lseek,
1444 .release = single_release,
1445};
1446
1447static int __init init_clk_read_debugfs(void)
1448{
1449 /* Expose a simple debugfs interface to view all clocks */
1450 (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
1451 NULL, NULL,
1452 &u300_clocks_operations);
1453 return 0;
1454}
1455/*
1456 * This needs to come in after the core_initcall() for the
1457 * overall clocks, because debugfs is not available until
1458 * the subsystems come up.
1459 */
1460module_init(init_clk_read_debugfs);
1461#endif
1462
1463int __init u300_clock_init(void)
1464{
1465 u16 val;
1466
1467 /*
1468 * FIXME: shall all this powermanagement stuff really live here???
1469 */
1470
1471 /* Set system to run at PLL208, max performance, a known state. */
1472 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1473 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1474 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1475 /* Wait for the PLL208 to lock if not locked in yet */
1476 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1477 U300_SYSCON_CSR_PLL208_LOCK_IND));
1478
1479 /* Power management enable */
1480 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1481 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1482 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1483
1484 clk_register();
1485
1486 /*
1487 * Some of these may be on when we boot the system so make sure they
1488 * are turned OFF.
1489 */
1490 syscon_block_reset_enable(&timer_clk);
1491 timer_clk.disable(&timer_clk);
1492
1493 /*
1494 * These shall be turned on by default when we boot the system
1495 * so make sure they are ON. (Adding CPU here is a bit too much.)
1496 * These clocks will be claimed by drivers later.
1497 */
1498 syscon_block_reset_disable(&semi_clk);
1499 syscon_block_reset_disable(&emif_clk);
1500 clk_enable(&semi_clk);
1501 clk_enable(&emif_clk);
1502
1503 return 0;
1504}
diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h
deleted file mode 100644
index 4f50ca8f901e..000000000000
--- a/arch/arm/mach-u300/clock.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * arch/arm/mach-u300/include/mach/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 * Copyright (C) 2007-2009 ST-Ericsson AB
8 * Adopted to ST-Ericsson U300 platforms by
9 * Jonas Aaberg <jonas.aberg@stericsson.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#ifndef __MACH_CLOCK_H
18#define __MACH_CLOCK_H
19
20#include <linux/clk.h>
21
22struct clk {
23 struct list_head node;
24 struct module *owner;
25 struct device *dev;
26 const char *name;
27 struct clk *parent;
28
29 spinlock_t lock;
30 unsigned long rate;
31 bool reset;
32 __u16 clk_val;
33 __s8 usecount;
34 void __iomem * res_reg;
35 __u16 res_mask;
36
37 bool hw_ctrld;
38
39 void (*recalc) (struct clk *);
40 int (*set_rate) (struct clk *, unsigned long);
41 unsigned long (*get_rate) (struct clk *);
42 unsigned long (*round_rate) (struct clk *, unsigned long);
43 void (*init) (struct clk *);
44 void (*enable) (struct clk *);
45 void (*disable) (struct clk *);
46};
47
48int u300_clock_init(void);
49
50#endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 33339745d432..03acf1883ec7 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -30,6 +30,7 @@
30#include <linux/pinctrl/consumer.h> 30#include <linux/pinctrl/consumer.h>
31#include <linux/pinctrl/pinconf-generic.h> 31#include <linux/pinctrl/pinconf-generic.h>
32#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
33#include <linux/platform_data/clk-u300.h>
33 34
34#include <asm/types.h> 35#include <asm/types.h>
35#include <asm/setup.h> 36#include <asm/setup.h>
@@ -44,7 +45,6 @@
44#include <mach/dma_channels.h> 45#include <mach/dma_channels.h>
45#include <mach/gpio-u300.h> 46#include <mach/gpio-u300.h>
46 47
47#include "clock.h"
48#include "spi.h" 48#include "spi.h"
49#include "i2c.h" 49#include "i2c.h"
50#include "u300-gpio.h" 50#include "u300-gpio.h"
@@ -1658,12 +1658,20 @@ void __init u300_init_irq(void)
1658 int i; 1658 int i;
1659 1659
1660 /* initialize clocking early, we want to clock the INTCON */ 1660 /* initialize clocking early, we want to clock the INTCON */
1661 u300_clock_init(); 1661 u300_clk_init(U300_SYSCON_VBASE);
1662
1663 /* Bootstrap EMIF and SEMI clocks */
1664 clk = clk_get_sys("pl172", NULL);
1665 BUG_ON(IS_ERR(clk));
1666 clk_prepare_enable(clk);
1667 clk = clk_get_sys("semi", NULL);
1668 BUG_ON(IS_ERR(clk));
1669 clk_prepare_enable(clk);
1662 1670
1663 /* Clock the interrupt controller */ 1671 /* Clock the interrupt controller */
1664 clk = clk_get_sys("intcon", NULL); 1672 clk = clk_get_sys("intcon", NULL);
1665 BUG_ON(IS_ERR(clk)); 1673 BUG_ON(IS_ERR(clk));
1666 clk_enable(clk); 1674 clk_prepare_enable(clk);
1667 1675
1668 for (i = 0; i < U300_VIC_IRQS_END; i++) 1676 for (i = 0; i < U300_VIC_IRQS_END; i++)
1669 set_bit(i, (unsigned long *) &mask[0]); 1677 set_bit(i, (unsigned long *) &mask[0]);
@@ -1811,13 +1819,6 @@ void __init u300_init_devices(void)
1811 /* Check what platform we run and print some status information */ 1819 /* Check what platform we run and print some status information */
1812 u300_init_check_chip(); 1820 u300_init_check_chip();
1813 1821
1814 /* Set system to run at PLL208, max performance, a known state. */
1815 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1816 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1817 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1818 /* Wait for the PLL208 to lock if not locked in yet */
1819 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1820 U300_SYSCON_CSR_PLL208_LOCK_IND));
1821 /* Initialize SPI device with some board specifics */ 1822 /* Initialize SPI device with some board specifics */
1822 u300_spi_init(&pl022_device); 1823 u300_spi_init(&pl022_device);
1823 1824
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index bc1c7897e82d..56ac06d38ec1 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -354,7 +354,7 @@ static void __init u300_timer_init(void)
354 /* Clock the interrupt controller */ 354 /* Clock the interrupt controller */
355 clk = clk_get_sys("apptimer", NULL); 355 clk = clk_get_sys("apptimer", NULL);
356 BUG_ON(IS_ERR(clk)); 356 BUG_ON(IS_ERR(clk));
357 clk_enable(clk); 357 clk_prepare_enable(clk);
358 rate = clk_get_rate(clk); 358 rate = clk_get_rate(clk);
359 359
360 setup_sched_clock(u300_read_sched_clock, 32, rate); 360 setup_sched_clock(u300_read_sched_clock, 32, rate);
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b679f117f3cc..35d9fb44c814 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,10 +1,11 @@
1 1# common clock types
2obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o 2obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
3obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ 3obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
4 clk-mux.o clk-divider.o clk-fixed-factor.o 4 clk-mux.o clk-divider.o clk-fixed-factor.o
5# SoCs specific 5# SoCs specific
6obj-$(CONFIG_ARCH_MXS) += mxs/ 6obj-$(CONFIG_ARCH_MXS) += mxs/
7obj-$(CONFIG_PLAT_SPEAR) += spear/ 7obj-$(CONFIG_PLAT_SPEAR) += spear/
8obj-$(CONFIG_ARCH_U300) += clk-u300.o
8 9
9# Chip specific 10# Chip specific
10obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 11obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
new file mode 100644
index 000000000000..a15f7928fb11
--- /dev/null
+++ b/drivers/clk/clk-u300.c
@@ -0,0 +1,746 @@
1/*
2 * U300 clock implementation
3 * Copyright (C) 2007-2012 ST-Ericsson AB
4 * License terms: GNU General Public License (GPL) version 2
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7 */
8#include <linux/clk.h>
9#include <linux/clkdev.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/clk-provider.h>
13#include <linux/spinlock.h>
14#include <mach/syscon.h>
15
16/*
17 * The clocking hierarchy currently looks like this.
18 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
19 * The ideas is to show dependencies, so a clock higher up in the
20 * hierarchy has to be on in order for another clock to be on. Now,
21 * both CPU and DMA can actually be on top of the hierarchy, and that
22 * is not modeled currently. Instead we have the backbone AMBA bus on
23 * top. This bus cannot be programmed in any way but conceptually it
24 * needs to be active for the bridges and devices to transport data.
25 *
26 * Please be aware that a few clocks are hw controlled, which mean that
27 * the hw itself can turn on/off or change the rate of the clock when
28 * needed!
29 *
30 * AMBA bus
31 * |
32 * +- CPU
33 * +- FSMC NANDIF NAND Flash interface
34 * +- SEMI Shared Memory interface
35 * +- ISP Image Signal Processor (U335 only)
36 * +- CDS (U335 only)
37 * +- DMA Direct Memory Access Controller
38 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
39 * +- APEX
40 * +- VIDEO_ENC AVE2/3 Video Encoder
41 * +- XGAM Graphics Accelerator Controller
42 * +- AHB
43 * |
44 * +- ahb:0 AHB Bridge
45 * | |
46 * | +- ahb:1 INTCON Interrupt controller
47 * | +- ahb:3 MSPRO Memory Stick Pro controller
48 * | +- ahb:4 EMIF External Memory interface
49 * |
50 * +- fast:0 FAST bridge
51 * | |
52 * | +- fast:1 MMCSD MMC/SD card reader controller
53 * | +- fast:2 I2S0 PCM I2S channel 0 controller
54 * | +- fast:3 I2S1 PCM I2S channel 1 controller
55 * | +- fast:4 I2C0 I2C channel 0 controller
56 * | +- fast:5 I2C1 I2C channel 1 controller
57 * | +- fast:6 SPI SPI controller
58 * | +- fast:7 UART1 Secondary UART (U335 only)
59 * |
60 * +- slow:0 SLOW bridge
61 * |
62 * +- slow:1 SYSCON (not possible to control)
63 * +- slow:2 WDOG Watchdog
64 * +- slow:3 UART0 primary UART
65 * +- slow:4 TIMER_APP Application timer - used in Linux
66 * +- slow:5 KEYPAD controller
67 * +- slow:6 GPIO controller
68 * +- slow:7 RTC controller
69 * +- slow:8 BT Bus Tracer (not used currently)
70 * +- slow:9 EH Event Handler (not used currently)
71 * +- slow:a TIMER_ACC Access style timer (not used currently)
72 * +- slow:b PPM (U335 only, what is that?)
73 */
74
75/* Global syscon virtual base */
76static void __iomem *syscon_vbase;
77
78/**
79 * struct clk_syscon - U300 syscon clock
80 * @hw: corresponding clock hardware entry
81 * @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
82 * and does not need any magic pokes to be enabled/disabled
83 * @reset: state holder, whether this block's reset line is asserted or not
84 * @res_reg: reset line enable/disable flag register
85 * @res_bit: bit for resetting or taking this consumer out of reset
86 * @en_reg: clock line enable/disable flag register
87 * @en_bit: bit for enabling/disabling this consumer clock line
88 * @clk_val: magic value to poke in the register to enable/disable
89 * this one clock
90 */
91struct clk_syscon {
92 struct clk_hw hw;
93 bool hw_ctrld;
94 bool reset;
95 void __iomem *res_reg;
96 u8 res_bit;
97 void __iomem *en_reg;
98 u8 en_bit;
99 u16 clk_val;
100};
101
102#define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
103
104static DEFINE_SPINLOCK(syscon_resetreg_lock);
105
106/*
107 * Reset control functions. We remember if a block has been
108 * taken out of reset and don't remove the reset assertion again
109 * and vice versa. Currently we only remove resets so the
110 * enablement function is defined out.
111 */
112static void syscon_block_reset_enable(struct clk_syscon *sclk)
113{
114 unsigned long iflags;
115 u16 val;
116
117 /* Not all blocks support resetting */
118 if (!sclk->res_reg)
119 return;
120 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
121 val = readw(sclk->res_reg);
122 val |= BIT(sclk->res_bit);
123 writew(val, sclk->res_reg);
124 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
125 sclk->reset = true;
126}
127
128static void syscon_block_reset_disable(struct clk_syscon *sclk)
129{
130 unsigned long iflags;
131 u16 val;
132
133 /* Not all blocks support resetting */
134 if (!sclk->res_reg)
135 return;
136 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
137 val = readw(sclk->res_reg);
138 val &= ~BIT(sclk->res_bit);
139 writew(val, sclk->res_reg);
140 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
141 sclk->reset = false;
142}
143
144static int syscon_clk_prepare(struct clk_hw *hw)
145{
146 struct clk_syscon *sclk = to_syscon(hw);
147
148 /* If the block is in reset, bring it out */
149 if (sclk->reset)
150 syscon_block_reset_disable(sclk);
151 return 0;
152}
153
154static void syscon_clk_unprepare(struct clk_hw *hw)
155{
156 struct clk_syscon *sclk = to_syscon(hw);
157
158 /* Please don't force the console into reset */
159 if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
160 return;
161 /* When unpreparing, force block into reset */
162 if (!sclk->reset)
163 syscon_block_reset_enable(sclk);
164}
165
166static int syscon_clk_enable(struct clk_hw *hw)
167{
168 struct clk_syscon *sclk = to_syscon(hw);
169
170 /* Don't touch the hardware controlled clocks */
171 if (sclk->hw_ctrld)
172 return 0;
173 /* These cannot be controlled */
174 if (sclk->clk_val == 0xFFFFU)
175 return 0;
176
177 writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
178 return 0;
179}
180
181static void syscon_clk_disable(struct clk_hw *hw)
182{
183 struct clk_syscon *sclk = to_syscon(hw);
184
185 /* Don't touch the hardware controlled clocks */
186 if (sclk->hw_ctrld)
187 return;
188 if (sclk->clk_val == 0xFFFFU)
189 return;
190 /* Please don't disable the console port */
191 if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
192 return;
193
194 writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
195}
196
197static int syscon_clk_is_enabled(struct clk_hw *hw)
198{
199 struct clk_syscon *sclk = to_syscon(hw);
200 u16 val;
201
202 /* If no enable register defined, it's always-on */
203 if (!sclk->en_reg)
204 return 1;
205
206 val = readw(sclk->en_reg);
207 val &= BIT(sclk->en_bit);
208
209 return val ? 1 : 0;
210}
211
212static u16 syscon_get_perf(void)
213{
214 u16 val;
215
216 val = readw(syscon_vbase + U300_SYSCON_CCR);
217 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
218 return val;
219}
220
221static unsigned long
222syscon_clk_recalc_rate(struct clk_hw *hw,
223 unsigned long parent_rate)
224{
225 struct clk_syscon *sclk = to_syscon(hw);
226 u16 perf = syscon_get_perf();
227
228 switch(sclk->clk_val) {
229 case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
230 case U300_SYSCON_SBCER_I2C0_CLK_EN:
231 case U300_SYSCON_SBCER_I2C1_CLK_EN:
232 case U300_SYSCON_SBCER_MMC_CLK_EN:
233 case U300_SYSCON_SBCER_SPI_CLK_EN:
234 /* The FAST clocks have one progression */
235 switch(perf) {
236 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
237 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
238 return 13000000;
239 default:
240 return parent_rate; /* 26 MHz */
241 }
242 case U300_SYSCON_SBCER_DMAC_CLK_EN:
243 case U300_SYSCON_SBCER_NANDIF_CLK_EN:
244 case U300_SYSCON_SBCER_XGAM_CLK_EN:
245 /* AMBA interconnect peripherals */
246 switch(perf) {
247 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
248 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
249 return 6500000;
250 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
251 return 26000000;
252 default:
253 return parent_rate; /* 52 MHz */
254 }
255 case U300_SYSCON_SBCER_SEMI_CLK_EN:
256 case U300_SYSCON_SBCER_EMIF_CLK_EN:
257 /* EMIF speeds */
258 switch(perf) {
259 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
260 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
261 return 13000000;
262 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
263 return 52000000;
264 default:
265 return 104000000;
266 }
267 case U300_SYSCON_SBCER_CPU_CLK_EN:
268 /* And the fast CPU clock */
269 switch(perf) {
270 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
271 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
272 return 13000000;
273 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
274 return 52000000;
275 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
276 return 104000000;
277 default:
278 return parent_rate; /* 208 MHz */
279 }
280 default:
281 /*
282 * The SLOW clocks and default just inherit the rate of
283 * their parent (typically PLL13 13 MHz).
284 */
285 return parent_rate;
286 }
287}
288
289static long
290syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
291 unsigned long *prate)
292{
293 struct clk_syscon *sclk = to_syscon(hw);
294
295 if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
296 return *prate;
297 /* We really only support setting the rate of the CPU clock */
298 if (rate <= 13000000)
299 return 13000000;
300 if (rate <= 52000000)
301 return 52000000;
302 if (rate <= 104000000)
303 return 104000000;
304 return 208000000;
305}
306
307static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate,
308 unsigned long parent_rate)
309{
310 struct clk_syscon *sclk = to_syscon(hw);
311 u16 val;
312
313 /* We only support setting the rate of the CPU clock */
314 if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
315 return -EINVAL;
316 switch (rate) {
317 case 13000000:
318 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
319 break;
320 case 52000000:
321 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
322 break;
323 case 104000000:
324 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
325 break;
326 case 208000000:
327 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
328 break;
329 default:
330 return -EINVAL;
331 }
332 val |= readw(syscon_vbase + U300_SYSCON_CCR) &
333 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
334 writew(val, syscon_vbase + U300_SYSCON_CCR);
335 return 0;
336}
337
338static const struct clk_ops syscon_clk_ops = {
339 .prepare = syscon_clk_prepare,
340 .unprepare = syscon_clk_unprepare,
341 .enable = syscon_clk_enable,
342 .disable = syscon_clk_disable,
343 .is_enabled = syscon_clk_is_enabled,
344 .recalc_rate = syscon_clk_recalc_rate,
345 .round_rate = syscon_clk_round_rate,
346 .set_rate = syscon_clk_set_rate,
347};
348
349static struct clk * __init
350syscon_clk_register(struct device *dev, const char *name,
351 const char *parent_name, unsigned long flags,
352 bool hw_ctrld,
353 void __iomem *res_reg, u8 res_bit,
354 void __iomem *en_reg, u8 en_bit,
355 u16 clk_val)
356{
357 struct clk *clk;
358 struct clk_syscon *sclk;
359 struct clk_init_data init;
360
361 sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL);
362 if (!sclk) {
363 pr_err("could not allocate syscon clock %s\n",
364 name);
365 return ERR_PTR(-ENOMEM);
366 }
367 init.name = name;
368 init.ops = &syscon_clk_ops;
369 init.flags = flags;
370 init.parent_names = (parent_name ? &parent_name : NULL);
371 init.num_parents = (parent_name ? 1 : 0);
372 sclk->hw.init = &init;
373 sclk->hw_ctrld = hw_ctrld;
374 /* Assume the block is in reset at registration */
375 sclk->reset = true;
376 sclk->res_reg = res_reg;
377 sclk->res_bit = res_bit;
378 sclk->en_reg = en_reg;
379 sclk->en_bit = en_bit;
380 sclk->clk_val = clk_val;
381
382 clk = clk_register(dev, &sclk->hw);
383 if (IS_ERR(clk))
384 kfree(sclk);
385
386 return clk;
387}
388
389/**
390 * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
391 * @hw: corresponding clock hardware entry
392 * @is_mspro: if this is the memory stick clock rather than MMC/SD
393 */
394struct clk_mclk {
395 struct clk_hw hw;
396 bool is_mspro;
397};
398
399#define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw)
400
401static int mclk_clk_prepare(struct clk_hw *hw)
402{
403 struct clk_mclk *mclk = to_mclk(hw);
404 u16 val;
405
406 /* The MMC and MSPRO clocks need some special set-up */
407 if (!mclk->is_mspro) {
408 /* Set default MMC clock divisor to 18.9 MHz */
409 writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);
410 val = readw(syscon_vbase + U300_SYSCON_MMCR);
411 /* Disable the MMC feedback clock */
412 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
413 /* Disable MSPRO frequency */
414 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
415 writew(val, syscon_vbase + U300_SYSCON_MMCR);
416 } else {
417 val = readw(syscon_vbase + U300_SYSCON_MMCR);
418 /* Disable the MMC feedback clock */
419 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
420 /* Enable MSPRO frequency */
421 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
422 writew(val, syscon_vbase + U300_SYSCON_MMCR);
423 }
424
425 return 0;
426}
427
428static unsigned long
429mclk_clk_recalc_rate(struct clk_hw *hw,
430 unsigned long parent_rate)
431{
432 u16 perf = syscon_get_perf();
433
434 switch (perf) {
435 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
436 /*
437 * Here, the 208 MHz PLL gets shut down and the always
438 * on 13 MHz PLL used for RTC etc kicks into use
439 * instead.
440 */
441 return 13000000;
442 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
443 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
444 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
445 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
446 {
447 /*
448 * This clock is under program control. The register is
449 * divided in two nybbles, bit 7-4 gives cycles-1 to count
450 * high, bit 3-0 gives cycles-1 to count low. Distribute
451 * these with no more than 1 cycle difference between
452 * low and high and add low and high to get the actual
453 * divisor. The base PLL is 208 MHz. Writing 0x00 will
454 * divide by 1 and 1 so the highest frequency possible
455 * is 104 MHz.
456 *
457 * e.g. 0x54 =>
458 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
459 */
460 u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
461 U300_SYSCON_MMF0R_MASK;
462 switch (val) {
463 case 0x0054:
464 return 18900000;
465 case 0x0044:
466 return 20800000;
467 case 0x0043:
468 return 23100000;
469 case 0x0033:
470 return 26000000;
471 case 0x0032:
472 return 29700000;
473 case 0x0022:
474 return 34700000;
475 case 0x0021:
476 return 41600000;
477 case 0x0011:
478 return 52000000;
479 case 0x0000:
480 return 104000000;
481 default:
482 break;
483 }
484 }
485 default:
486 break;
487 }
488 return parent_rate;
489}
490
491static long
492mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
493 unsigned long *prate)
494{
495 if (rate <= 18900000)
496 return 18900000;
497 if (rate <= 20800000)
498 return 20800000;
499 if (rate <= 23100000)
500 return 23100000;
501 if (rate <= 26000000)
502 return 26000000;
503 if (rate <= 29700000)
504 return 29700000;
505 if (rate <= 34700000)
506 return 34700000;
507 if (rate <= 41600000)
508 return 41600000;
509 /* Highest rate */
510 return 52000000;
511}
512
513static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate,
514 unsigned long parent_rate)
515{
516 u16 val;
517 u16 reg;
518
519 switch (rate) {
520 case 18900000:
521 val = 0x0054;
522 break;
523 case 20800000:
524 val = 0x0044;
525 break;
526 case 23100000:
527 val = 0x0043;
528 break;
529 case 26000000:
530 val = 0x0033;
531 break;
532 case 29700000:
533 val = 0x0032;
534 break;
535 case 34700000:
536 val = 0x0022;
537 break;
538 case 41600000:
539 val = 0x0021;
540 break;
541 case 52000000:
542 val = 0x0011;
543 break;
544 case 104000000:
545 val = 0x0000;
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &
552 ~U300_SYSCON_MMF0R_MASK;
553 writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
554 return 0;
555}
556
557static const struct clk_ops mclk_ops = {
558 .prepare = mclk_clk_prepare,
559 .recalc_rate = mclk_clk_recalc_rate,
560 .round_rate = mclk_clk_round_rate,
561 .set_rate = mclk_clk_set_rate,
562};
563
564static struct clk * __init
565mclk_clk_register(struct device *dev, const char *name,
566 const char *parent_name, bool is_mspro)
567{
568 struct clk *clk;
569 struct clk_mclk *mclk;
570 struct clk_init_data init;
571
572 mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL);
573 if (!mclk) {
574 pr_err("could not allocate MMC/SD clock %s\n",
575 name);
576 return ERR_PTR(-ENOMEM);
577 }
578 init.name = "mclk";
579 init.ops = &mclk_ops;
580 init.flags = 0;
581 init.parent_names = (parent_name ? &parent_name : NULL);
582 init.num_parents = (parent_name ? 1 : 0);
583 mclk->hw.init = &init;
584 mclk->is_mspro = is_mspro;
585
586 clk = clk_register(dev, &mclk->hw);
587 if (IS_ERR(clk))
588 kfree(mclk);
589
590 return clk;
591}
592
593void __init u300_clk_init(void __iomem *base)
594{
595 u16 val;
596 struct clk *clk;
597
598 syscon_vbase = base;
599
600 /* Set system to run at PLL208, max performance, a known state. */
601 val = readw(syscon_vbase + U300_SYSCON_CCR);
602 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
603 writew(val, syscon_vbase + U300_SYSCON_CCR);
604 /* Wait for the PLL208 to lock if not locked in yet */
605 while (!(readw(syscon_vbase + U300_SYSCON_CSR) &
606 U300_SYSCON_CSR_PLL208_LOCK_IND));
607
608 /* Power management enable */
609 val = readw(syscon_vbase + U300_SYSCON_PMCR);
610 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
611 writew(val, syscon_vbase + U300_SYSCON_PMCR);
612
613 /* These are always available (RTC and PLL13) */
614 clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
615 CLK_IS_ROOT, 32768);
616 /* The watchdog sits directly on the 32 kHz clock */
617 clk_register_clkdev(clk, NULL, "coh901327_wdog");
618 clk = clk_register_fixed_rate(NULL, "pll13", NULL,
619 CLK_IS_ROOT, 13000000);
620
621 /* These derive from PLL208 */
622 clk = clk_register_fixed_rate(NULL, "pll208", NULL,
623 CLK_IS_ROOT, 208000000);
624 clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
625 0, 1, 1);
626 clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
627 0, 1, 2);
628 clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
629 0, 1, 4);
630 /* The 52 MHz is divided down to 26 MHz */
631 clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
632 0, 1, 2);
633
634 /* Directly on the AMBA interconnect */
635 clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
636 syscon_vbase + U300_SYSCON_RRR, 3,
637 syscon_vbase + U300_SYSCON_CERR, 3,
638 U300_SYSCON_SBCER_CPU_CLK_EN);
639 clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
640 syscon_vbase + U300_SYSCON_RRR, 4,
641 syscon_vbase + U300_SYSCON_CERR, 4,
642 U300_SYSCON_SBCER_DMAC_CLK_EN);
643 clk_register_clkdev(clk, NULL, "dma");
644 clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
645 syscon_vbase + U300_SYSCON_RRR, 6,
646 syscon_vbase + U300_SYSCON_CERR, 6,
647 U300_SYSCON_SBCER_NANDIF_CLK_EN);
648 clk_register_clkdev(clk, NULL, "fsmc-nand");
649 clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
650 syscon_vbase + U300_SYSCON_RRR, 8,
651 syscon_vbase + U300_SYSCON_CERR, 8,
652 U300_SYSCON_SBCER_XGAM_CLK_EN);
653 clk_register_clkdev(clk, NULL, "xgam");
654 clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
655 syscon_vbase + U300_SYSCON_RRR, 9,
656 syscon_vbase + U300_SYSCON_CERR, 9,
657 U300_SYSCON_SBCER_SEMI_CLK_EN);
658 clk_register_clkdev(clk, NULL, "semi");
659
660 /* AHB bridge clocks */
661 clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
662 syscon_vbase + U300_SYSCON_RRR, 10,
663 syscon_vbase + U300_SYSCON_CERR, 10,
664 U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
665 clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
666 syscon_vbase + U300_SYSCON_RRR, 12,
667 syscon_vbase + U300_SYSCON_CERR, 12,
668 /* Cannot be enabled, just taken out of reset */
669 0xFFFFU);
670 clk_register_clkdev(clk, NULL, "intcon");
671 clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
672 syscon_vbase + U300_SYSCON_RRR, 5,
673 syscon_vbase + U300_SYSCON_CERR, 5,
674 U300_SYSCON_SBCER_EMIF_CLK_EN);
675 clk_register_clkdev(clk, NULL, "pl172");
676
677 /* FAST bridge clocks */
678 clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
679 syscon_vbase + U300_SYSCON_RFR, 0,
680 syscon_vbase + U300_SYSCON_CEFR, 0,
681 U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
682 clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
683 syscon_vbase + U300_SYSCON_RFR, 1,
684 syscon_vbase + U300_SYSCON_CEFR, 1,
685 U300_SYSCON_SBCER_I2C0_CLK_EN);
686 clk_register_clkdev(clk, NULL, "stu300.0");
687 clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
688 syscon_vbase + U300_SYSCON_RFR, 2,
689 syscon_vbase + U300_SYSCON_CEFR, 2,
690 U300_SYSCON_SBCER_I2C1_CLK_EN);
691 clk_register_clkdev(clk, NULL, "stu300.1");
692 clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
693 syscon_vbase + U300_SYSCON_RFR, 5,
694 syscon_vbase + U300_SYSCON_CEFR, 5,
695 U300_SYSCON_SBCER_MMC_CLK_EN);
696 clk_register_clkdev(clk, "apb_pclk", "mmci");
697 clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
698 syscon_vbase + U300_SYSCON_RFR, 6,
699 syscon_vbase + U300_SYSCON_CEFR, 6,
700 U300_SYSCON_SBCER_SPI_CLK_EN);
701 /* The SPI has no external clock for the outward bus, uses the pclk */
702 clk_register_clkdev(clk, NULL, "pl022");
703 clk_register_clkdev(clk, "apb_pclk", "pl022");
704
705 /* SLOW bridge clocks */
706 clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
707 syscon_vbase + U300_SYSCON_RSR, 0,
708 syscon_vbase + U300_SYSCON_CESR, 0,
709 U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
710 clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
711 syscon_vbase + U300_SYSCON_RSR, 1,
712 syscon_vbase + U300_SYSCON_CESR, 1,
713 U300_SYSCON_SBCER_UART_CLK_EN);
714 /* Same clock is used for APB and outward bus */
715 clk_register_clkdev(clk, NULL, "uart0");
716 clk_register_clkdev(clk, "apb_pclk", "uart0");
717 clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
718 syscon_vbase + U300_SYSCON_RSR, 4,
719 syscon_vbase + U300_SYSCON_CESR, 4,
720 U300_SYSCON_SBCER_GPIO_CLK_EN);
721 clk_register_clkdev(clk, NULL, "u300-gpio");
722 clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
723 syscon_vbase + U300_SYSCON_RSR, 5,
724 syscon_vbase + U300_SYSCON_CESR, 6,
725 U300_SYSCON_SBCER_KEYPAD_CLK_EN);
726 clk_register_clkdev(clk, NULL, "coh901461-keypad");
727 clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
728 syscon_vbase + U300_SYSCON_RSR, 6,
729 /* No clock enable register bit */
730 NULL, 0, 0xFFFFU);
731 clk_register_clkdev(clk, NULL, "rtc-coh901331");
732 clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
733 syscon_vbase + U300_SYSCON_RSR, 7,
734 syscon_vbase + U300_SYSCON_CESR, 7,
735 U300_SYSCON_SBCER_APP_TMR_CLK_EN);
736 clk_register_clkdev(clk, NULL, "apptimer");
737 clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
738 syscon_vbase + U300_SYSCON_RSR, 8,
739 syscon_vbase + U300_SYSCON_CESR, 8,
740 U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
741 clk_register_clkdev(clk, NULL, "timer");
742
743 /* Then this special MMC/SD clock */
744 clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
745 clk_register_clkdev(clk, NULL, "mmci");
746}
diff --git a/include/linux/platform_data/clk-u300.h b/include/linux/platform_data/clk-u300.h
new file mode 100644
index 000000000000..8429e73911a1
--- /dev/null
+++ b/include/linux/platform_data/clk-u300.h
@@ -0,0 +1 @@
void __init u300_clk_init(void __iomem *base);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 06:22:33 -0500