2 files changed, 59 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e48d47ced57b..517a8cc27bec 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3632,6 +3632,42 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
                       I915_READ(pp_div_reg));
 }
 
+static struct drm_display_mode *
+intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
+                        struct intel_connector *intel_connector,
+                        struct drm_display_mode *fixed_mode)
+{
+        struct drm_connector *connector = &intel_connector->base;
+        struct intel_dp *intel_dp = &intel_dig_port->dp;
+        struct drm_device *dev = intel_dig_port->base.base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_display_mode *downclock_mode = NULL;
+
+        if (INTEL_INFO(dev)->gen <= 6) {
+                DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
+                return NULL;
+        }
+
+        if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
+                DRM_INFO("VBT doesn't support DRRS\n");
+                return NULL;
+        }
+
+        downclock_mode = intel_find_panel_downclock
+                                        (dev, fixed_mode, connector);
+
+        if (!downclock_mode) {
+                DRM_INFO("DRRS not supported\n");
+                return NULL;
+        }
+
+        intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
+
+        intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
+        DRM_INFO("seamless DRRS supported for eDP panel.\n");
+        return downclock_mode;
+}
+
 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
                                      struct intel_connector *intel_connector,
                                      struct edp_power_seq *power_seq)
@@ -3641,10 +3677,13 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
         struct drm_device *dev = intel_dig_port->base.base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_display_mode *fixed_mode = NULL;
+        struct drm_display_mode *downclock_mode = NULL;
         bool has_dpcd;
         struct drm_display_mode *scan;
         struct edid *edid;
 
+        intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
+
         if (!is_edp(intel_dp))
                 return true;
 
@@ -3687,6 +3726,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
         list_for_each_entry(scan, &connector->probed_modes, head) {
                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
                         fixed_mode = drm_mode_duplicate(dev, scan);
+                        downclock_mode = intel_dp_drrs_init(
+                                                intel_dig_port,
+                                                intel_connector, fixed_mode);
                         break;
                 }
         }
@@ -3700,7 +3742,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
         }
         mutex_unlock(&dev->mode_config.mutex);
 
-        intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
+        intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
         intel_panel_setup_backlight(connector);
 
         return true;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6b512607b2f5..41038d9b434f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -485,6 +485,17 @@ struct intel_hdmi {
 
 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 
+/**
+ * HIGH_RR is the highest eDP panel refresh rate read from EDID
+ * LOW_RR is the lowest eDP panel refresh rate found from EDID
+ * parsing for same resolution.
+ */
+enum edp_drrs_refresh_rate_type {
+        DRRS_HIGH_RR,
+        DRRS_LOW_RR,
+        DRRS_MAX_RR, /* RR count */
+};
+
 struct intel_dp {
         uint32_t output_reg;
         uint32_t aux_ch_ctl_reg;
@@ -523,6 +534,11 @@ struct intel_dp {
                                      bool has_aux_irq,
                                      int send_bytes,
                                      uint32_t aux_clock_divider);
+        struct {
+                enum drrs_support_type type;
+                enum edp_drrs_refresh_rate_type refresh_rate_type;
+        } drrs_state;
+
 };
 
 struct intel_digital_port {