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-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c12
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c20
2 files changed, 17 insertions, 15 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 355b08936871..e482562075ef 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -171,6 +171,12 @@
171 */ 171 */
172#define LINKS_PER_OCP_IF 2 172#define LINKS_PER_OCP_IF 2
173 173
174/*
175 * Address offset (in bytes) between the reset control and the reset
176 * status registers: 4 bytes on OMAP4
177 */
178#define OMAP4_RST_CTRL_ST_OFFSET 4
179
174/** 180/**
175 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations 181 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
176 * @enable_module: function to enable a module (via MODULEMODE) 182 * @enable_module: function to enable a module (via MODULEMODE)
@@ -3016,10 +3022,12 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
3016 if (ohri->st_shift) 3022 if (ohri->st_shift)
3017 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", 3023 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
3018 oh->name, ohri->name); 3024 oh->name, ohri->name);
3019 return omap_prm_deassert_hardreset(ohri->rst_shift, 0, 3025 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
3020 oh->clkdm->pwrdm.ptr->prcm_partition, 3026 oh->clkdm->pwrdm.ptr->prcm_partition,
3021 oh->clkdm->pwrdm.ptr->prcm_offs, 3027 oh->clkdm->pwrdm.ptr->prcm_offs,
3022 oh->prcm.omap4.rstctrl_offs, 0); 3028 oh->prcm.omap4.rstctrl_offs,
3029 oh->prcm.omap4.rstctrl_offs +
3030 OMAP4_RST_CTRL_ST_OFFSET);
3023} 3031}
3024 3032
3025/** 3033/**
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index c4859c4d3646..d0b15dbafa2e 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -87,12 +87,6 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
87 return v; 87 return v;
88} 88}
89 89
90/*
91 * Address offset (in bytes) between the reset control and the reset
92 * status registers: 4 bytes on OMAP4
93 */
94#define OMAP4_RST_CTRL_ST_OFFSET 4
95
96/** 90/**
97 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of 91 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
98 * submodules contained in the hwmod module 92 * submodules contained in the hwmod module
@@ -141,11 +135,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
141 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and 135 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
142 * wait 136 * wait
143 * @shift: register bit shift corresponding to the reset line to deassert 137 * @shift: register bit shift corresponding to the reset line to deassert
144 * @st_shift: status bit offset, not used for OMAP4+ 138 * @st_shift: status bit offset corresponding to the reset line
145 * @part: PRM partition 139 * @part: PRM partition
146 * @inst: PRM instance offset 140 * @inst: PRM instance offset
147 * @rstctrl_offs: reset register offset 141 * @rstctrl_offs: reset register offset
148 * @st_offs: reset status register offset, not used for OMAP4+ 142 * @rstst_offs: reset status register offset
149 * 143 *
150 * Some IPs like dsp, ipu or iva contain processors that require an HW 144 * Some IPs like dsp, ipu or iva contain processors that require an HW
151 * reset line to be asserted / deasserted in order to fully enable the 145 * reset line to be asserted / deasserted in order to fully enable the
@@ -157,11 +151,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
157 * of reset, or -EBUSY if the submodule did not exit reset promptly. 151 * of reset, or -EBUSY if the submodule did not exit reset promptly.
158 */ 152 */
159int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, 153int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
160 u16 rstctrl_offs, u16 st_offs) 154 u16 rstctrl_offs, u16 rstst_offs)
161{ 155{
162 int c; 156 int c;
163 u32 mask = 1 << shift; 157 u32 mask = 1 << shift;
164 u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET; 158 u32 st_mask = 1 << st_shift;
165 159
166 /* Check the current status to avoid de-asserting the line twice */ 160 /* Check the current status to avoid de-asserting the line twice */
167 if (omap4_prminst_is_hardreset_asserted(shift, part, inst, 161 if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
@@ -169,13 +163,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
169 return -EEXIST; 163 return -EEXIST;
170 164
171 /* Clear the reset status by writing 1 to the status bit */ 165 /* Clear the reset status by writing 1 to the status bit */
172 omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst, 166 omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
173 rstst_offs); 167 rstst_offs);
174 /* de-assert the reset control line */ 168 /* de-assert the reset control line */
175 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); 169 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
176 /* wait the status to be set */ 170 /* wait the status to be set */
177 omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst, 171 omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
178 rstst_offs), 172 inst, rstst_offs),
179 MAX_MODULE_HARDRESET_WAIT, c); 173 MAX_MODULE_HARDRESET_WAIT, c);
180 174
181 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; 175 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;