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-rw-r--r--drivers/gpu/drm/i915/i915_drv.h8
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c2
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c7
3 files changed, 9 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 98322053eb2a..c0cba20ea6af 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1831,6 +1831,14 @@ struct drm_i915_file_private {
1831 1831
1832/* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1832/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1833#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1833#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1834/*
1835 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1836 * even when in MSI mode. This results in spurious interrupt warnings if the
1837 * legacy irq no. is shared with another device. The kernel then disables that
1838 * interrupt source and so prevents the other device from working properly.
1839 */
1840#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1841#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1834 1842
1835/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1843/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1836 * rows, which changed the alignment requirements and fence programming. 1844 * rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c00b6e352c2b..2f517b85b3f4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -404,7 +404,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
404 int i, ret, recv_bytes; 404 int i, ret, recv_bytes;
405 uint32_t status; 405 uint32_t status;
406 int try, precharge, clock = 0; 406 int try, precharge, clock = 0;
407 bool has_aux_irq = true; 407 bool has_aux_irq = HAS_AUX_IRQ(dev);
408 uint32_t timeout; 408 uint32_t timeout;
409 409
410 /* dp aux is extremely sensitive to irq latency, hence request the 410 /* dp aux is extremely sensitive to irq latency, hence request the
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b1dc33f47899..d33b61d0dd33 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -258,13 +258,6 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
258 algo->data = bus; 258 algo->data = bus;
259} 259}
260 260
261/*
262 * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
263 * mode. This results in spurious interrupt warnings if the legacy irq no. is
264 * shared with another device. The kernel then disables that interrupt source
265 * and so prevents the other device from working properly.
266 */
267#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
268static int 261static int
269gmbus_wait_hw_status(struct drm_i915_private *dev_priv, 262gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
270 u32 gmbus2_status, 263 u32 gmbus2_status,