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-rw-r--r--Documentation/devicetree/bindings/arm/arm-boards4
-rw-r--r--arch/arm/boot/dts/integratorap.dts5
-rw-r--r--arch/arm/boot/dts/integratorcp.dts5
-rw-r--r--arch/arm/mach-integrator/Kconfig2
-rw-r--r--arch/arm/mach-integrator/common.h8
-rw-r--r--arch/arm/mach-integrator/core.c141
-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h1
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c158
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c115
-rw-r--r--arch/arm/mach-integrator/pci_v3.c32
10 files changed, 354 insertions, 117 deletions
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index fc81a7d6b0f1..db5858e32d3f 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -9,6 +9,10 @@ Required properties (in root node):
9 9
10FPGA type interrupt controllers, see the versatile-fpga-irq binding doc. 10FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
11 11
12In the root node the Integrator/CP must have a /cpcon node pointing
13to the CP control registers, and the Integrator/AP must have a
14/syscon node pointing to the Integrator/AP system controller.
15
12 16
13ARM Versatile Application and Platform Baseboards 17ARM Versatile Application and Platform Baseboards
14------------------------------------------------- 18-------------------------------------------------
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index 61767757b50a..c9c3fa344647 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -18,6 +18,11 @@
18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; 18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
19 }; 19 };
20 20
21 syscon {
22 /* AP system controller registers */
23 reg = <0x11000000 0x100>;
24 };
25
21 timer0: timer@13000000 { 26 timer0: timer@13000000 {
22 compatible = "arm,integrator-timer"; 27 compatible = "arm,integrator-timer";
23 }; 28 };
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 2dd5e4e48481..8b119399025a 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -18,6 +18,11 @@
18 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; 18 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
19 }; 19 };
20 20
21 cpcon {
22 /* CP controller registers */
23 reg = <0xcb000000 0x100>;
24 };
25
21 timer0: timer@13000000 { 26 timer0: timer@13000000 {
22 compatible = "arm,sp804", "arm,primecell"; 27 compatible = "arm,sp804", "arm,primecell";
23 }; 28 };
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 350e26636a06..abeff25532ab 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -8,6 +8,7 @@ config ARCH_INTEGRATOR_AP
8 select MIGHT_HAVE_PCI 8 select MIGHT_HAVE_PCI
9 select SERIAL_AMBA_PL010 9 select SERIAL_AMBA_PL010
10 select SERIAL_AMBA_PL010_CONSOLE 10 select SERIAL_AMBA_PL010_CONSOLE
11 select SOC_BUS
11 help 12 help
12 Include support for the ARM(R) Integrator/AP and 13 Include support for the ARM(R) Integrator/AP and
13 Integrator/PP2 platforms. 14 Integrator/PP2 platforms.
@@ -19,6 +20,7 @@ config ARCH_INTEGRATOR_CP
19 select PLAT_VERSATILE_CLCD 20 select PLAT_VERSATILE_CLCD
20 select SERIAL_AMBA_PL011 21 select SERIAL_AMBA_PL011
21 select SERIAL_AMBA_PL011_CONSOLE 22 select SERIAL_AMBA_PL011_CONSOLE
23 select SOC_BUS
22 help 24 help
23 Include support for the ARM(R) Integrator CP platform. 25 Include support for the ARM(R) Integrator CP platform.
24 26
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index c3ff21b5ea24..79197d8b34aa 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,6 +1,12 @@
1#include <linux/amba/serial.h> 1#include <linux/amba/serial.h>
2extern struct amba_pl010_data integrator_uart_data; 2#ifdef CONFIG_ARCH_INTEGRATOR_AP
3extern struct amba_pl010_data ap_uart_data;
4#else
5/* Not used without Integrator/AP support anyway */
6struct amba_pl010_data ap_uart_data {};
7#endif
3void integrator_init_early(void); 8void integrator_init_early(void);
4int integrator_init(bool is_cp); 9int integrator_init(bool is_cp);
5void integrator_reserve(void); 10void integrator_reserve(void);
6void integrator_restart(char, const char *); 11void integrator_restart(char, const char *);
12void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index ea22a17246d7..39c060f75e47 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -18,10 +18,10 @@
18#include <linux/memblock.h> 18#include <linux/memblock.h>
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <linux/smp.h> 20#include <linux/smp.h>
21#include <linux/termios.h>
22#include <linux/amba/bus.h> 21#include <linux/amba/bus.h>
23#include <linux/amba/serial.h> 22#include <linux/amba/serial.h>
24#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/stat.h>
25 25
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/platform.h> 27#include <mach/platform.h>
@@ -46,10 +46,10 @@ static AMBA_APB_DEVICE(rtc, "rtc", 0,
46 INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL); 46 INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
47 47
48static AMBA_APB_DEVICE(uart0, "uart0", 0, 48static AMBA_APB_DEVICE(uart0, "uart0", 0,
49 INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data); 49 INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, NULL);
50 50
51static AMBA_APB_DEVICE(uart1, "uart1", 0, 51static AMBA_APB_DEVICE(uart1, "uart1", 0,
52 INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data); 52 INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, NULL);
53 53
54static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL); 54static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
55static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL); 55static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
@@ -77,6 +77,8 @@ int __init integrator_init(bool is_cp)
77 uart1_device.periphid = 0x00041010; 77 uart1_device.periphid = 0x00041010;
78 kmi0_device.periphid = 0x00041050; 78 kmi0_device.periphid = 0x00041050;
79 kmi1_device.periphid = 0x00041050; 79 kmi1_device.periphid = 0x00041050;
80 uart0_device.dev.platform_data = &ap_uart_data;
81 uart1_device.dev.platform_data = &ap_uart_data;
80 } 82 }
81 83
82 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 84 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
@@ -89,49 +91,6 @@ int __init integrator_init(bool is_cp)
89 91
90#endif 92#endif
91 93
92/*
93 * On the Integrator platform, the port RTS and DTR are provided by
94 * bits in the following SC_CTRLS register bits:
95 * RTS DTR
96 * UART0 7 6
97 * UART1 5 4
98 */
99#define SC_CTRLC __io_address(INTEGRATOR_SC_CTRLC)
100#define SC_CTRLS __io_address(INTEGRATOR_SC_CTRLS)
101
102static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
103{
104 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
105 u32 phybase = dev->res.start;
106
107 if (phybase == INTEGRATOR_UART0_BASE) {
108 /* UART0 */
109 rts_mask = 1 << 4;
110 dtr_mask = 1 << 5;
111 } else {
112 /* UART1 */
113 rts_mask = 1 << 6;
114 dtr_mask = 1 << 7;
115 }
116
117 if (mctrl & TIOCM_RTS)
118 ctrlc |= rts_mask;
119 else
120 ctrls |= rts_mask;
121
122 if (mctrl & TIOCM_DTR)
123 ctrlc |= dtr_mask;
124 else
125 ctrls |= dtr_mask;
126
127 __raw_writel(ctrls, SC_CTRLS);
128 __raw_writel(ctrlc, SC_CTRLC);
129}
130
131struct amba_pl010_data integrator_uart_data = {
132 .set_mctrl = integrator_uart_set_mctrl,
133};
134
135static DEFINE_RAW_SPINLOCK(cm_lock); 94static DEFINE_RAW_SPINLOCK(cm_lock);
136 95
137/** 96/**
@@ -169,3 +128,93 @@ void integrator_restart(char mode, const char *cmd)
169{ 128{
170 cm_control(CM_CTRL_RESET, CM_CTRL_RESET); 129 cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
171} 130}
131
132static u32 integrator_id;
133
134static ssize_t intcp_get_manf(struct device *dev,
135 struct device_attribute *attr,
136 char *buf)
137{
138 return sprintf(buf, "%02x\n", integrator_id >> 24);
139}
140
141static struct device_attribute intcp_manf_attr =
142 __ATTR(manufacturer, S_IRUGO, intcp_get_manf, NULL);
143
144static ssize_t intcp_get_arch(struct device *dev,
145 struct device_attribute *attr,
146 char *buf)
147{
148 const char *arch;
149
150 switch ((integrator_id >> 16) & 0xff) {
151 case 0x00:
152 arch = "ASB little-endian";
153 break;
154 case 0x01:
155 arch = "AHB little-endian";
156 break;
157 case 0x03:
158 arch = "AHB-Lite system bus, bi-endian";
159 break;
160 case 0x04:
161 arch = "AHB";
162 break;
163 default:
164 arch = "Unknown";
165 break;
166 }
167
168 return sprintf(buf, "%s\n", arch);
169}
170
171static struct device_attribute intcp_arch_attr =
172 __ATTR(architecture, S_IRUGO, intcp_get_arch, NULL);
173
174static ssize_t intcp_get_fpga(struct device *dev,
175 struct device_attribute *attr,
176 char *buf)
177{
178 const char *fpga;
179
180 switch ((integrator_id >> 12) & 0xf) {
181 case 0x01:
182 fpga = "XC4062";
183 break;
184 case 0x02:
185 fpga = "XC4085";
186 break;
187 case 0x04:
188 fpga = "EPM7256AE (Altera PLD)";
189 break;
190 default:
191 fpga = "Unknown";
192 break;
193 }
194
195 return sprintf(buf, "%s\n", fpga);
196}
197
198static struct device_attribute intcp_fpga_attr =
199 __ATTR(fpga, S_IRUGO, intcp_get_fpga, NULL);
200
201static ssize_t intcp_get_build(struct device *dev,
202 struct device_attribute *attr,
203 char *buf)
204{
205 return sprintf(buf, "%02x\n", (integrator_id >> 4) & 0xFF);
206}
207
208static struct device_attribute intcp_build_attr =
209 __ATTR(build, S_IRUGO, intcp_get_build, NULL);
210
211
212
213void integrator_init_sysfs(struct device *parent, u32 id)
214{
215 integrator_id = id;
216 device_create_file(parent, &intcp_manf_attr);
217 device_create_file(parent, &intcp_arch_attr);
218 device_create_file(parent, &intcp_fpga_attr);
219 device_create_file(parent, &intcp_build_attr);
220}
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index efeac5d0bc9e..be5859efe10e 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -190,7 +190,6 @@
190#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C 190#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
191#define INTEGRATOR_SC_DEC_OFFSET 0x10 191#define INTEGRATOR_SC_DEC_OFFSET 0x10
192#define INTEGRATOR_SC_ARB_OFFSET 0x14 192#define INTEGRATOR_SC_ARB_OFFSET 0x14
193#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
194#define INTEGRATOR_SC_LOCK_OFFSET 0x1C 193#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
195 194
196#define INTEGRATOR_SC_BASE 0x11000000 195#define INTEGRATOR_SC_BASE 0x11000000
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index e6617c134faf..a0a7cbbb7a70 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -37,6 +37,9 @@
37#include <linux/of_irq.h> 37#include <linux/of_irq.h>
38#include <linux/of_address.h> 38#include <linux/of_address.h>
39#include <linux/of_platform.h> 39#include <linux/of_platform.h>
40#include <linux/stat.h>
41#include <linux/sys_soc.h>
42#include <linux/termios.h>
40#include <video/vga.h> 43#include <video/vga.h>
41 44
42#include <mach/hardware.h> 45#include <mach/hardware.h>
@@ -60,7 +63,10 @@
60 63
61#include "common.h" 64#include "common.h"
62 65
63/* 66/* Base address to the AP system controller */
67void __iomem *ap_syscon_base;
68
69/*
64 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx 70 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
65 * is the (PA >> 12). 71 * is the (PA >> 12).
66 * 72 *
@@ -68,7 +74,6 @@
68 * just for now). 74 * just for now).
69 */ 75 */
70#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) 76#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
71#define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
72#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE) 77#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
73#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC) 78#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
74 79
@@ -97,11 +102,6 @@ static struct map_desc ap_io_desc[] __initdata = {
97 .length = SZ_4K, 102 .length = SZ_4K,
98 .type = MT_DEVICE 103 .type = MT_DEVICE
99 }, { 104 }, {
100 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
101 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
102 .length = SZ_4K,
103 .type = MT_DEVICE
104 }, {
105 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), 105 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
106 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), 106 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
107 .length = SZ_4K, 107 .length = SZ_4K,
@@ -122,11 +122,6 @@ static struct map_desc ap_io_desc[] __initdata = {
122 .length = SZ_4K, 122 .length = SZ_4K,
123 .type = MT_DEVICE 123 .type = MT_DEVICE
124 }, { 124 }, {
125 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
126 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
127 .length = SZ_4K,
128 .type = MT_DEVICE
129 }, {
130 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), 125 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
131 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), 126 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
132 .length = SZ_4K, 127 .length = SZ_4K,
@@ -201,8 +196,6 @@ device_initcall(irq_syscore_init);
201/* 196/*
202 * Flash handling. 197 * Flash handling.
203 */ 198 */
204#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
205#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
206#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) 199#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
207#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) 200#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
208 201
@@ -210,7 +203,8 @@ static int ap_flash_init(struct platform_device *dev)
210{ 203{
211 u32 tmp; 204 u32 tmp;
212 205
213 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC); 206 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
207 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
214 208
215 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; 209 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
216 writel(tmp, EBI_CSR1); 210 writel(tmp, EBI_CSR1);
@@ -227,7 +221,8 @@ static void ap_flash_exit(struct platform_device *dev)
227{ 221{
228 u32 tmp; 222 u32 tmp;
229 223
230 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC); 224 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
225 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
231 226
232 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; 227 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
233 writel(tmp, EBI_CSR1); 228 writel(tmp, EBI_CSR1);
@@ -241,9 +236,12 @@ static void ap_flash_exit(struct platform_device *dev)
241 236
242static void ap_flash_set_vpp(struct platform_device *pdev, int on) 237static void ap_flash_set_vpp(struct platform_device *pdev, int on)
243{ 238{
244 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; 239 if (on)
245 240 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
246 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); 241 ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
242 else
243 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
244 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
247} 245}
248 246
249static struct physmap_flash_data ap_flash_data = { 247static struct physmap_flash_data ap_flash_data = {
@@ -254,6 +252,45 @@ static struct physmap_flash_data ap_flash_data = {
254}; 252};
255 253
256/* 254/*
255 * For the PL010 found in the Integrator/AP some of the UART control is
256 * implemented in the system controller and accessed using a callback
257 * from the driver.
258 */
259static void integrator_uart_set_mctrl(struct amba_device *dev,
260 void __iomem *base, unsigned int mctrl)
261{
262 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
263 u32 phybase = dev->res.start;
264
265 if (phybase == INTEGRATOR_UART0_BASE) {
266 /* UART0 */
267 rts_mask = 1 << 4;
268 dtr_mask = 1 << 5;
269 } else {
270 /* UART1 */
271 rts_mask = 1 << 6;
272 dtr_mask = 1 << 7;
273 }
274
275 if (mctrl & TIOCM_RTS)
276 ctrlc |= rts_mask;
277 else
278 ctrls |= rts_mask;
279
280 if (mctrl & TIOCM_DTR)
281 ctrlc |= dtr_mask;
282 else
283 ctrls |= dtr_mask;
284
285 __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
286 __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
287}
288
289struct amba_pl010_data ap_uart_data = {
290 .set_mctrl = integrator_uart_set_mctrl,
291};
292
293/*
257 * Where is the timer (VA)? 294 * Where is the timer (VA)?
258 */ 295 */
259#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) 296#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
@@ -450,9 +487,9 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
450 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, 487 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
451 "rtc", NULL), 488 "rtc", NULL),
452 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, 489 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
453 "uart0", &integrator_uart_data), 490 "uart0", &ap_uart_data),
454 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, 491 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
455 "uart1", &integrator_uart_data), 492 "uart1", &ap_uart_data),
456 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, 493 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
457 "kmi0", NULL), 494 "kmi0", NULL),
458 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, 495 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
@@ -465,12 +502,60 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
465static void __init ap_init_of(void) 502static void __init ap_init_of(void)
466{ 503{
467 unsigned long sc_dec; 504 unsigned long sc_dec;
505 struct device_node *root;
506 struct device_node *syscon;
507 struct device *parent;
508 struct soc_device *soc_dev;
509 struct soc_device_attribute *soc_dev_attr;
510 u32 ap_sc_id;
511 int err;
468 int i; 512 int i;
469 513
470 of_platform_populate(NULL, of_default_bus_match_table, 514 /* Here we create an SoC device for the root node */
471 ap_auxdata_lookup, NULL); 515 root = of_find_node_by_path("/");
516 if (!root)
517 return;
518 syscon = of_find_node_by_path("/syscon");
519 if (!syscon)
520 return;
521
522 ap_syscon_base = of_iomap(syscon, 0);
523 if (!ap_syscon_base)
524 return;
472 525
473 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET); 526 ap_sc_id = readl(ap_syscon_base);
527
528 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
529 if (!soc_dev_attr)
530 return;
531
532 err = of_property_read_string(root, "compatible",
533 &soc_dev_attr->soc_id);
534 if (err)
535 return;
536 err = of_property_read_string(root, "model", &soc_dev_attr->machine);
537 if (err)
538 return;
539 soc_dev_attr->family = "Integrator";
540 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
541 'A' + (ap_sc_id & 0x0f));
542
543 soc_dev = soc_device_register(soc_dev_attr);
544 if (IS_ERR_OR_NULL(soc_dev)) {
545 kfree(soc_dev_attr->revision);
546 kfree(soc_dev_attr);
547 return;
548 }
549
550 parent = soc_device_to_device(soc_dev);
551
552 if (!IS_ERR_OR_NULL(parent))
553 integrator_init_sysfs(parent, ap_sc_id);
554
555 of_platform_populate(root, of_default_bus_match_table,
556 ap_auxdata_lookup, parent);
557
558 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
474 for (i = 0; i < 4; i++) { 559 for (i = 0; i < 4; i++) {
475 struct lm_device *lmdev; 560 struct lm_device *lmdev;
476 561
@@ -514,6 +599,27 @@ MACHINE_END
514#ifdef CONFIG_ATAGS 599#ifdef CONFIG_ATAGS
515 600
516/* 601/*
602 * For the ATAG boot some static mappings are needed. This will
603 * go away with the ATAG support down the road.
604 */
605
606static struct map_desc ap_io_desc_atag[] __initdata = {
607 {
608 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
609 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
610 .length = SZ_4K,
611 .type = MT_DEVICE
612 },
613};
614
615static void __init ap_map_io_atag(void)
616{
617 iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
618 ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
619 ap_map_io();
620}
621
622/*
517 * This is where non-devicetree initialization code is collected and stashed 623 * This is where non-devicetree initialization code is collected and stashed
518 * for eventual deletion. 624 * for eventual deletion.
519 */ 625 */
@@ -581,7 +687,7 @@ static void __init ap_init(void)
581 687
582 platform_device_register(&cfi_flash_device); 688 platform_device_register(&cfi_flash_device);
583 689
584 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET); 690 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
585 for (i = 0; i < 4; i++) { 691 for (i = 0; i < 4; i++) {
586 struct lm_device *lmdev; 692 struct lm_device *lmdev;
587 693
@@ -608,7 +714,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
608 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 714 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
609 .atag_offset = 0x100, 715 .atag_offset = 0x100,
610 .reserve = integrator_reserve, 716 .reserve = integrator_reserve,
611 .map_io = ap_map_io, 717 .map_io = ap_map_io_atag,
612 .nr_irqs = NR_IRQS_INTEGRATOR_AP, 718 .nr_irqs = NR_IRQS_INTEGRATOR_AP,
613 .init_early = ap_init_early, 719 .init_early = ap_init_early,
614 .init_irq = ap_init_irq, 720 .init_irq = ap_init_irq,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 5b08e8e4cc83..29df06b35d0d 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -26,6 +26,7 @@
26#include <linux/of_irq.h> 26#include <linux/of_irq.h>
27#include <linux/of_address.h> 27#include <linux/of_address.h>
28#include <linux/of_platform.h> 28#include <linux/of_platform.h>
29#include <linux/sys_soc.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
31#include <mach/platform.h> 32#include <mach/platform.h>
@@ -51,11 +52,13 @@
51 52
52#include "common.h" 53#include "common.h"
53 54
55/* Base address to the CP controller */
56static void __iomem *intcp_con_base;
57
54#define INTCP_PA_FLASH_BASE 0x24000000 58#define INTCP_PA_FLASH_BASE 0x24000000
55 59
56#define INTCP_PA_CLCD_BASE 0xc0000000 60#define INTCP_PA_CLCD_BASE 0xc0000000
57 61
58#define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE)
59#define INTCP_FLASHPROG 0x04 62#define INTCP_FLASHPROG 0x04
60#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) 63#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
61#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) 64#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
@@ -82,11 +85,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
82 .length = SZ_4K, 85 .length = SZ_4K,
83 .type = MT_DEVICE 86 .type = MT_DEVICE
84 }, { 87 }, {
85 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
86 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
87 .length = SZ_4K,
88 .type = MT_DEVICE
89 }, {
90 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), 88 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
91 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), 89 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
92 .length = SZ_4K, 90 .length = SZ_4K,
@@ -107,11 +105,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
107 .length = SZ_4K, 105 .length = SZ_4K,
108 .type = MT_DEVICE 106 .type = MT_DEVICE
109 }, { 107 }, {
110 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
111 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
112 .length = SZ_4K,
113 .type = MT_DEVICE
114 }, {
115 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), 108 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
116 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), 109 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
117 .length = SZ_4K, 110 .length = SZ_4K,
@@ -126,11 +119,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
126 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE), 119 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
127 .length = SZ_4K, 120 .length = SZ_4K,
128 .type = MT_DEVICE 121 .type = MT_DEVICE
129 }, {
130 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
131 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
132 .length = SZ_4K,
133 .type = MT_DEVICE
134 } 122 }
135}; 123};
136 124
@@ -146,9 +134,9 @@ static int intcp_flash_init(struct platform_device *dev)
146{ 134{
147 u32 val; 135 u32 val;
148 136
149 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 137 val = readl(intcp_con_base + INTCP_FLASHPROG);
150 val |= CINTEGRATOR_FLASHPROG_FLWREN; 138 val |= CINTEGRATOR_FLASHPROG_FLWREN;
151 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 139 writel(val, intcp_con_base + INTCP_FLASHPROG);
152 140
153 return 0; 141 return 0;
154} 142}
@@ -157,21 +145,21 @@ static void intcp_flash_exit(struct platform_device *dev)
157{ 145{
158 u32 val; 146 u32 val;
159 147
160 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 148 val = readl(intcp_con_base + INTCP_FLASHPROG);
161 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN); 149 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
162 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 150 writel(val, intcp_con_base + INTCP_FLASHPROG);
163} 151}
164 152
165static void intcp_flash_set_vpp(struct platform_device *pdev, int on) 153static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
166{ 154{
167 u32 val; 155 u32 val;
168 156
169 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 157 val = readl(intcp_con_base + INTCP_FLASHPROG);
170 if (on) 158 if (on)
171 val |= CINTEGRATOR_FLASHPROG_FLVPPEN; 159 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
172 else 160 else
173 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN; 161 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
174 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 162 writel(val, intcp_con_base + INTCP_FLASHPROG);
175} 163}
176 164
177static struct physmap_flash_data intcp_flash_data = { 165static struct physmap_flash_data intcp_flash_data = {
@@ -190,7 +178,7 @@ static struct physmap_flash_data intcp_flash_data = {
190static unsigned int mmc_status(struct device *dev) 178static unsigned int mmc_status(struct device *dev)
191{ 179{
192 unsigned int status = readl(__io_address(0xca000000 + 4)); 180 unsigned int status = readl(__io_address(0xca000000 + 4));
193 writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8)); 181 writel(8, intcp_con_base + 8);
194 182
195 return status & 8; 183 return status & 8;
196} 184}
@@ -318,9 +306,9 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
318 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, 306 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
319 "rtc", NULL), 307 "rtc", NULL),
320 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, 308 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
321 "uart0", &integrator_uart_data), 309 "uart0", NULL),
322 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, 310 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
323 "uart1", &integrator_uart_data), 311 "uart1", NULL),
324 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, 312 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
325 "kmi0", NULL), 313 "kmi0", NULL),
326 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, 314 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
@@ -338,8 +326,57 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
338 326
339static void __init intcp_init_of(void) 327static void __init intcp_init_of(void)
340{ 328{
341 of_platform_populate(NULL, of_default_bus_match_table, 329 struct device_node *root;
342 intcp_auxdata_lookup, NULL); 330 struct device_node *cpcon;
331 struct device *parent;
332 struct soc_device *soc_dev;
333 struct soc_device_attribute *soc_dev_attr;
334 u32 intcp_sc_id;
335 int err;
336
337 /* Here we create an SoC device for the root node */
338 root = of_find_node_by_path("/");
339 if (!root)
340 return;
341 cpcon = of_find_node_by_path("/cpcon");
342 if (!cpcon)
343 return;
344
345 intcp_con_base = of_iomap(cpcon, 0);
346 if (!intcp_con_base)
347 return;
348
349 intcp_sc_id = readl(intcp_con_base);
350
351 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
352 if (!soc_dev_attr)
353 return;
354
355 err = of_property_read_string(root, "compatible",
356 &soc_dev_attr->soc_id);
357 if (err)
358 return;
359 err = of_property_read_string(root, "model", &soc_dev_attr->machine);
360 if (err)
361 return;
362 soc_dev_attr->family = "Integrator";
363 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
364 'A' + (intcp_sc_id & 0x0f));
365
366 soc_dev = soc_device_register(soc_dev_attr);
367 if (IS_ERR_OR_NULL(soc_dev)) {
368 kfree(soc_dev_attr->revision);
369 kfree(soc_dev_attr);
370 return;
371 }
372
373 parent = soc_device_to_device(soc_dev);
374
375 if (!IS_ERR_OR_NULL(parent))
376 integrator_init_sysfs(parent, intcp_sc_id);
377
378 of_platform_populate(root, of_default_bus_match_table,
379 intcp_auxdata_lookup, parent);
343} 380}
344 381
345static const char * intcp_dt_board_compat[] = { 382static const char * intcp_dt_board_compat[] = {
@@ -365,6 +402,28 @@ MACHINE_END
365#ifdef CONFIG_ATAGS 402#ifdef CONFIG_ATAGS
366 403
367/* 404/*
405 * For the ATAG boot some static mappings are needed. This will
406 * go away with the ATAG support down the road.
407 */
408
409static struct map_desc intcp_io_desc_atag[] __initdata = {
410 {
411 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
412 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
413 .length = SZ_4K,
414 .type = MT_DEVICE
415 },
416};
417
418static void __init intcp_map_io_atag(void)
419{
420 iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
421 intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
422 intcp_map_io();
423}
424
425
426/*
368 * This is where non-devicetree initialization code is collected and stashed 427 * This is where non-devicetree initialization code is collected and stashed
369 * for eventual deletion. 428 * for eventual deletion.
370 */ 429 */
@@ -503,7 +562,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
503 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 562 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
504 .atag_offset = 0x100, 563 .atag_offset = 0x100,
505 .reserve = integrator_reserve, 564 .reserve = integrator_reserve,
506 .map_io = intcp_map_io, 565 .map_io = intcp_map_io_atag,
507 .nr_irqs = NR_IRQS_INTEGRATOR_CP, 566 .nr_irqs = NR_IRQS_INTEGRATOR_CP,
508 .init_early = intcp_init_early, 567 .init_early = intcp_init_early,
509 .init_irq = intcp_init_irq, 568 .init_irq = intcp_init_irq,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index bbeca59df66b..be50e795536d 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -191,12 +191,9 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus,
191 /* 191 /*
192 * Trap out illegal values 192 * Trap out illegal values
193 */ 193 */
194 if (offset > 255) 194 BUG_ON(offset > 255);
195 BUG(); 195 BUG_ON(busnr > 255);
196 if (busnr > 255) 196 BUG_ON(devfn > 255);
197 BUG();
198 if (devfn > 255)
199 BUG();
200 197
201 if (busnr == 0) { 198 if (busnr == 0) {
202 int slot = PCI_SLOT(devfn); 199 int slot = PCI_SLOT(devfn);
@@ -388,9 +385,10 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
388 * means I can't get additional information on the reason for the pm2fb 385 * means I can't get additional information on the reason for the pm2fb
389 * problems. I suppose I'll just have to mind-meld with the machine. ;) 386 * problems. I suppose I'll just have to mind-meld with the machine. ;)
390 */ 387 */
391#define SC_PCI __io_address(INTEGRATOR_SC_PCIENABLE) 388static void __iomem *ap_syscon_base;
392#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20) 389#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
393#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24) 390#define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
391#define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
394 392
395static int 393static int
396v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 394v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -401,13 +399,13 @@ v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
401 char buf[128]; 399 char buf[128];
402 400
403 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", 401 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
404 addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255, 402 addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
405 v3_readb(V3_LB_ISTAT)); 403 v3_readb(V3_LB_ISTAT));
406 printk(KERN_DEBUG "%s", buf); 404 printk(KERN_DEBUG "%s", buf);
407#endif 405#endif
408 406
409 v3_writeb(V3_LB_ISTAT, 0); 407 v3_writeb(V3_LB_ISTAT, 0);
410 __raw_writel(3, SC_PCI); 408 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
411 409
412 /* 410 /*
413 * If the instruction being executed was a read, 411 * If the instruction being executed was a read,
@@ -449,15 +447,15 @@ static irqreturn_t v3_irq(int dummy, void *devid)
449 447
450 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " 448 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
451 "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr, 449 "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
452 __raw_readl(SC_LBFADDR), 450 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
453 __raw_readl(SC_LBFCODE) & 255, 451 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
454 v3_readb(V3_LB_ISTAT)); 452 v3_readb(V3_LB_ISTAT));
455 printascii(buf); 453 printascii(buf);
456#endif 454#endif
457 455
458 v3_writew(V3_PCI_STAT, 0xf000); 456 v3_writew(V3_PCI_STAT, 0xf000);
459 v3_writeb(V3_LB_ISTAT, 0); 457 v3_writeb(V3_LB_ISTAT, 0);
460 __raw_writel(3, SC_PCI); 458 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
461 459
462#ifdef CONFIG_DEBUG_LL 460#ifdef CONFIG_DEBUG_LL
463 /* 461 /*
@@ -480,6 +478,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
480 if (nr == 0) { 478 if (nr == 0) {
481 sys->mem_offset = PHYS_PCI_MEM_BASE; 479 sys->mem_offset = PHYS_PCI_MEM_BASE;
482 ret = pci_v3_setup_resources(sys); 480 ret = pci_v3_setup_resources(sys);
481 /* Remap the Integrator system controller */
482 ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
483 if (!ap_syscon_base)
484 return -EINVAL;
483 } 485 }
484 486
485 return ret; 487 return ret;
@@ -568,7 +570,7 @@ void __init pci_v3_preinit(void)
568 v3_writeb(V3_LB_ISTAT, 0); 570 v3_writeb(V3_LB_ISTAT, 0);
569 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10)); 571 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
570 v3_writeb(V3_LB_IMASK, 0x28); 572 v3_writeb(V3_LB_IMASK, 0x28);
571 __raw_writel(3, SC_PCI); 573 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
572 574
573 /* 575 /*
574 * Grab the PCI error interrupt. 576 * Grab the PCI error interrupt.
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 06:56:01 -0500