aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/configs/bonito_defconfig72
-rw-r--r--arch/arm/configs/kota2_defconfig122
-rw-r--r--arch/arm/configs/marzen_defconfig87
-rw-r--r--arch/arm/mach-shmobile/Kconfig27
-rw-r--r--arch/arm/mach-shmobile/Makefile9
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c522
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c157
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c382
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c176
-rw-r--r--arch/arm/mach-shmobile/headsmp.S2
-rw-r--r--arch/arm/mach-shmobile/hotplug.c32
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h20
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h584
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h363
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c631
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7779.c58
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7740.c2562
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7779.c2645
-rw-r--r--arch/arm/mach-shmobile/platsmp.c21
-rw-r--r--arch/arm/mach-shmobile/pm-r8a7779.c249
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c352
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c239
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c6
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c2
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c153
-rw-r--r--drivers/sh/pfc.c176
-rw-r--r--drivers/tty/serial/sh-sci.h4
-rw-r--r--include/linux/sh_pfc.h11
28 files changed, 9572 insertions, 92 deletions
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
new file mode 100644
index 000000000000..54571082d920
--- /dev/null
+++ b/arch/arm/configs/bonito_defconfig
@@ -0,0 +1,72 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6# CONFIG_UTS_NS is not set
7# CONFIG_IPC_NS is not set
8# CONFIG_USER_NS is not set
9# CONFIG_PID_NS is not set
10CONFIG_BLK_DEV_INITRD=y
11CONFIG_INITRAMFS_SOURCE=""
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_SLAB=y
14CONFIG_MODULES=y
15CONFIG_MODULE_UNLOAD=y
16CONFIG_MODULE_FORCE_UNLOAD=y
17# CONFIG_BLK_DEV_BSG is not set
18# CONFIG_IOSCHED_DEADLINE is not set
19# CONFIG_IOSCHED_CFQ is not set
20CONFIG_ARCH_SHMOBILE=y
21CONFIG_ARCH_R8A7740=y
22CONFIG_MACH_BONITO=y
23# CONFIG_SH_TIMER_TMU is not set
24CONFIG_AEABI=y
25# CONFIG_OABI_COMPAT is not set
26CONFIG_FORCE_MAX_ZONEORDER=12
27CONFIG_ZBOOT_ROM_TEXT=0x0
28CONFIG_ZBOOT_ROM_BSS=0x0
29CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
30CONFIG_KEXEC=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32# CONFIG_SUSPEND is not set
33CONFIG_PM_RUNTIME=y
34CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
35# CONFIG_FIRMWARE_IN_KERNEL is not set
36CONFIG_MTD=y
37CONFIG_MTD_CHAR=y
38CONFIG_MTD_BLOCK=y
39CONFIG_MTD_CFI=y
40CONFIG_MTD_CFI_ADV_OPTIONS=y
41CONFIG_MTD_CFI_INTELEXT=y
42CONFIG_MTD_PHYSMAP=y
43CONFIG_MTD_ARM_INTEGRATOR=y
44CONFIG_MTD_BLOCK2MTD=y
45CONFIG_SCSI=y
46CONFIG_BLK_DEV_SD=y
47# CONFIG_SCSI_LOWLEVEL is not set
48# CONFIG_INPUT_KEYBOARD is not set
49# CONFIG_INPUT_MOUSE is not set
50# CONFIG_LEGACY_PTYS is not set
51CONFIG_SERIAL_SH_SCI=y
52CONFIG_SERIAL_SH_SCI_NR_UARTS=9
53CONFIG_SERIAL_SH_SCI_CONSOLE=y
54# CONFIG_HW_RANDOM is not set
55CONFIG_I2C=y
56CONFIG_I2C_CHARDEV=y
57CONFIG_I2C_SH_MOBILE=y
58CONFIG_GPIO_SYSFS=y
59# CONFIG_HWMON is not set
60# CONFIG_MFD_SUPPORT is not set
61# CONFIG_HID_SUPPORT is not set
62# CONFIG_USB_SUPPORT is not set
63CONFIG_UIO=y
64CONFIG_UIO_PDRV=y
65CONFIG_UIO_PDRV_GENIRQ=y
66# CONFIG_DNOTIFY is not set
67# CONFIG_INOTIFY_USER is not set
68CONFIG_TMPFS=y
69# CONFIG_MISC_FILESYSTEMS is not set
70# CONFIG_ENABLE_WARN_DEPRECATED is not set
71# CONFIG_ENABLE_MUST_CHECK is not set
72# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig
new file mode 100644
index 000000000000..b7735d6347ac
--- /dev/null
+++ b/arch/arm/configs/kota2_defconfig
@@ -0,0 +1,122 @@
1# CONFIG_ARM_PATCH_PHYS_VIRT is not set
2CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=16
7CONFIG_CGROUPS=y
8CONFIG_CPUSETS=y
9CONFIG_NAMESPACES=y
10# CONFIG_UTS_NS is not set
11# CONFIG_IPC_NS is not set
12# CONFIG_USER_NS is not set
13# CONFIG_PID_NS is not set
14CONFIG_SYSCTL_SYSCALL=y
15CONFIG_EMBEDDED=y
16CONFIG_SLAB=y
17# CONFIG_BLK_DEV_BSG is not set
18# CONFIG_IOSCHED_DEADLINE is not set
19# CONFIG_IOSCHED_CFQ is not set
20CONFIG_ARCH_SHMOBILE=y
21CONFIG_KEYBOARD_GPIO_POLLED=y
22CONFIG_ARCH_SH73A0=y
23CONFIG_MACH_KOTA2=y
24CONFIG_MEMORY_SIZE=0x1e0000000
25# CONFIG_SH_TIMER_TMU is not set
26# CONFIG_SWP_EMULATE is not set
27CONFIG_CPU_BPREDICT_DISABLE=y
28CONFIG_ARM_ERRATA_460075=y
29CONFIG_ARM_ERRATA_742230=y
30CONFIG_ARM_ERRATA_742231=y
31CONFIG_PL310_ERRATA_588369=y
32CONFIG_ARM_ERRATA_720789=y
33CONFIG_PL310_ERRATA_727915=y
34CONFIG_ARM_ERRATA_743622=y
35CONFIG_ARM_ERRATA_751472=y
36CONFIG_PL310_ERRATA_753970=y
37CONFIG_ARM_ERRATA_754322=y
38CONFIG_PL310_ERRATA_769419=y
39CONFIG_NO_HZ=y
40CONFIG_SMP=y
41CONFIG_AEABI=y
42# CONFIG_OABI_COMPAT is not set
43CONFIG_HIGHMEM=y
44CONFIG_ZBOOT_ROM_TEXT=0x0
45CONFIG_ZBOOT_ROM_BSS=0x0
46CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
47CONFIG_CMDLINE_FORCE=y
48CONFIG_KEXEC=y
49CONFIG_CPU_IDLE=y
50# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
51CONFIG_PM_RUNTIME=y
52CONFIG_NET=y
53CONFIG_PACKET=y
54CONFIG_UNIX=y
55CONFIG_INET=y
56CONFIG_IP_PNP=y
57CONFIG_IP_PNP_DHCP=y
58# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
59# CONFIG_INET_XFRM_MODE_TUNNEL is not set
60# CONFIG_INET_XFRM_MODE_BEET is not set
61# CONFIG_INET_LRO is not set
62# CONFIG_INET_DIAG is not set
63# CONFIG_IPV6 is not set
64CONFIG_CFG80211=y
65CONFIG_WIRELESS_EXT_SYSFS=y
66CONFIG_MAC80211=y
67CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
68# CONFIG_BLK_DEV is not set
69CONFIG_NETDEVICES=y
70# CONFIG_NET_VENDOR_BROADCOM is not set
71# CONFIG_NET_VENDOR_CHELSIO is not set
72# CONFIG_NET_VENDOR_FARADAY is not set
73# CONFIG_NET_VENDOR_INTEL is not set
74# CONFIG_NET_VENDOR_MARVELL is not set
75# CONFIG_NET_VENDOR_MICREL is not set
76# CONFIG_NET_VENDOR_NATSEMI is not set
77# CONFIG_NET_VENDOR_SEEQ is not set
78CONFIG_SMSC911X=y
79# CONFIG_NET_VENDOR_STMICRO is not set
80CONFIG_B43=y
81CONFIG_B43_PHY_N=y
82CONFIG_B43_DEBUG=y
83CONFIG_INPUT_SPARSEKMAP=y
84# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
85CONFIG_INPUT_EVDEV=y
86# CONFIG_KEYBOARD_ATKBD is not set
87CONFIG_KEYBOARD_GPIO=y
88CONFIG_KEYBOARD_SH_KEYSC=y
89# CONFIG_INPUT_MOUSE is not set
90# CONFIG_LEGACY_PTYS is not set
91CONFIG_SERIAL_SH_SCI=y
92CONFIG_SERIAL_SH_SCI_NR_UARTS=9
93CONFIG_SERIAL_SH_SCI_CONSOLE=y
94# CONFIG_HW_RANDOM is not set
95CONFIG_I2C_SH_MOBILE=y
96# CONFIG_HWMON is not set
97CONFIG_BCMA=y
98CONFIG_BCMA_DEBUG=y
99CONFIG_FB=y
100CONFIG_FB_SH_MOBILE_LCDC=y
101CONFIG_LCD_PLATFORM=y
102CONFIG_FRAMEBUFFER_CONSOLE=y
103CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
104# CONFIG_HID_SUPPORT is not set
105# CONFIG_USB_SUPPORT is not set
106CONFIG_MMC=y
107CONFIG_MMC_SDHI=y
108CONFIG_MMC_SH_MMCIF=y
109CONFIG_NEW_LEDS=y
110CONFIG_LEDS_CLASS=y
111CONFIG_LEDS_GPIO=y
112CONFIG_LEDS_RENESAS_TPU=y
113CONFIG_LEDS_TRIGGERS=y
114# CONFIG_DNOTIFY is not set
115# CONFIG_INOTIFY_USER is not set
116CONFIG_TMPFS=y
117# CONFIG_MISC_FILESYSTEMS is not set
118CONFIG_MAGIC_SYSRQ=y
119CONFIG_DEBUG_INFO=y
120CONFIG_DEBUG_INFO_REDUCED=y
121# CONFIG_FTRACE is not set
122CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
new file mode 100644
index 000000000000..864f9a5c39dd
--- /dev/null
+++ b/arch/arm/configs/marzen_defconfig
@@ -0,0 +1,87 @@
1# CONFIG_ARM_PATCH_PHYS_VIRT is not set
2CONFIG_EXPERIMENTAL=y
3CONFIG_KERNEL_LZMA=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=16
7CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y
9CONFIG_SLAB=y
10# CONFIG_BLOCK is not set
11CONFIG_ARCH_SHMOBILE=y
12CONFIG_ARCH_R8A7779=y
13CONFIG_MACH_MARZEN=y
14CONFIG_MEMORY_START=0x60000000
15CONFIG_MEMORY_SIZE=0x10000000
16CONFIG_SHMOBILE_TIMER_HZ=1024
17# CONFIG_SH_TIMER_CMT is not set
18# CONFIG_SWP_EMULATE is not set
19CONFIG_ARM_ERRATA_430973=y
20CONFIG_ARM_ERRATA_458693=y
21CONFIG_ARM_ERRATA_460075=y
22CONFIG_ARM_ERRATA_743622=y
23CONFIG_ARM_ERRATA_754322=y
24CONFIG_NO_HZ=y
25CONFIG_SMP=y
26# CONFIG_ARM_CPU_TOPOLOGY is not set
27CONFIG_AEABI=y
28# CONFIG_OABI_COMPAT is not set
29CONFIG_HIGHMEM=y
30CONFIG_ZBOOT_ROM_TEXT=0x0
31CONFIG_ZBOOT_ROM_BSS=0x0
32CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
33CONFIG_CMDLINE_FORCE=y
34CONFIG_KEXEC=y
35# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
36CONFIG_PM_RUNTIME=y
37CONFIG_NET=y
38CONFIG_INET=y
39# CONFIG_IPV6 is not set
40# CONFIG_WIRELESS is not set
41CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
42CONFIG_DEVTMPFS=y
43CONFIG_DEVTMPFS_MOUNT=y
44# CONFIG_STANDALONE is not set
45# CONFIG_PREVENT_FIRMWARE_BUILD is not set
46# CONFIG_FW_LOADER is not set
47CONFIG_NETDEVICES=y
48# CONFIG_NET_VENDOR_BROADCOM is not set
49# CONFIG_NET_VENDOR_FARADAY is not set
50# CONFIG_NET_VENDOR_INTEL is not set
51# CONFIG_NET_VENDOR_MICREL is not set
52# CONFIG_NET_VENDOR_NATSEMI is not set
53# CONFIG_NET_VENDOR_SEEQ is not set
54CONFIG_SMC911X=y
55CONFIG_SMSC911X=y
56# CONFIG_NET_VENDOR_STMICRO is not set
57# CONFIG_WLAN is not set
58# CONFIG_INPUT_MOUSEDEV is not set
59# CONFIG_INPUT_KEYBOARD is not set
60# CONFIG_INPUT_MOUSE is not set
61# CONFIG_SERIO is not set
62# CONFIG_VT is not set
63# CONFIG_LEGACY_PTYS is not set
64# CONFIG_DEVKMEM is not set
65CONFIG_SERIAL_SH_SCI=y
66CONFIG_SERIAL_SH_SCI_NR_UARTS=6
67CONFIG_SERIAL_SH_SCI_CONSOLE=y
68# CONFIG_HW_RANDOM is not set
69CONFIG_GPIO_SYSFS=y
70# CONFIG_HWMON is not set
71CONFIG_SSB=y
72# CONFIG_HID_SUPPORT is not set
73# CONFIG_USB_SUPPORT is not set
74CONFIG_UIO=y
75CONFIG_UIO_PDRV_GENIRQ=y
76# CONFIG_IOMMU_SUPPORT is not set
77# CONFIG_FILE_LOCKING is not set
78# CONFIG_DNOTIFY is not set
79# CONFIG_INOTIFY_USER is not set
80CONFIG_TMPFS=y
81# CONFIG_MISC_FILESYSTEMS is not set
82CONFIG_MAGIC_SYSRQ=y
83CONFIG_DEBUG_INFO=y
84CONFIG_DEBUG_INFO_REDUCED=y
85# CONFIG_FTRACE is not set
86CONFIG_DEBUG_USER=y
87CONFIG_AVERAGE=y
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0828fab2b65c..060e5644c49c 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -28,6 +28,19 @@ config ARCH_SH73A0
28 select ARM_GIC 28 select ARM_GIC
29 select I2C 29 select I2C
30 30
31config ARCH_R8A7740
32 bool "R-Mobile A1 (R8A77400)"
33 select CPU_V7
34 select SH_CLK_CPG
35 select ARCH_WANT_OPTIONAL_GPIOLIB
36
37config ARCH_R8A7779
38 bool "R-Car H1 (R8A77790)"
39 select CPU_V7
40 select SH_CLK_CPG
41 select ARM_GIC
42 select ARCH_WANT_OPTIONAL_GPIOLIB
43
31comment "SH-Mobile Board Type" 44comment "SH-Mobile Board Type"
32 45
33config MACH_G3EVM 46config MACH_G3EVM
@@ -75,6 +88,16 @@ config MACH_KOTA2
75 select ARCH_REQUIRE_GPIOLIB 88 select ARCH_REQUIRE_GPIOLIB
76 depends on ARCH_SH73A0 89 depends on ARCH_SH73A0
77 90
91config MACH_BONITO
92 bool "bonito board"
93 select ARCH_REQUIRE_GPIOLIB
94 depends on ARCH_R8A7740
95
96config MACH_MARZEN
97 bool "MARZEN board"
98 depends on ARCH_R8A7779
99 select ARCH_REQUIRE_GPIOLIB
100
78comment "SH-Mobile System Configuration" 101comment "SH-Mobile System Configuration"
79 102
80menu "Memory configuration" 103menu "Memory configuration"
@@ -83,7 +106,7 @@ config MEMORY_START
83 hex "Physical memory start address" 106 hex "Physical memory start address"
84 default "0x50000000" if MACH_G3EVM 107 default "0x50000000" if MACH_G3EVM
85 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \ 108 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
86 MACH_MACKEREL 109 MACH_MACKEREL || MACH_BONITO
87 default "0x41000000" if MACH_KOTA2 110 default "0x41000000" if MACH_KOTA2
88 default "0x00000000" 111 default "0x00000000"
89 ---help--- 112 ---help---
@@ -95,7 +118,7 @@ config MEMORY_SIZE
95 hex "Physical memory size" 118 hex "Physical memory size"
96 default "0x08000000" if MACH_G3EVM 119 default "0x08000000" if MACH_G3EVM
97 default "0x08000000" if MACH_G4EVM 120 default "0x08000000" if MACH_G4EVM
98 default "0x20000000" if MACH_AG5EVM 121 default "0x20000000" if MACH_AG5EVM || MACH_BONITO
99 default "0x1e000000" if MACH_KOTA2 122 default "0x1e000000" if MACH_KOTA2
100 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL 123 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
101 default "0x04000000" 124 default "0x04000000"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 5ca1f9d66995..7ad6954c46cd 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -10,12 +10,15 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o 10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
13obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
13 15
14# SMP objects 16# SMP objects
15smp-y := platsmp.o headsmp.o 17smp-y := platsmp.o headsmp.o
16smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o 18smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
17smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o 19smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o
18smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o 20smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o
21smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
19 22
20# Pinmux setup 23# Pinmux setup
21pfc-y := 24pfc-y :=
@@ -23,16 +26,20 @@ pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
23pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o 26pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
24pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o 27pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
25pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o 28pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
29pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
30pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o
26 31
27# IRQ objects 32# IRQ objects
28obj-$(CONFIG_ARCH_SH7367) += entry-intc.o 33obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
29obj-$(CONFIG_ARCH_SH7377) += entry-intc.o 34obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
30obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 35obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
36obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
31 37
32# PM objects 38# PM objects
33obj-$(CONFIG_SUSPEND) += suspend.o 39obj-$(CONFIG_SUSPEND) += suspend.o
34obj-$(CONFIG_CPU_IDLE) += cpuidle.o 40obj-$(CONFIG_CPU_IDLE) += cpuidle.o
35obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o 41obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
42obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
36 43
37# Board objects 44# Board objects
38obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o 45obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
@@ -41,6 +48,8 @@ obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
41obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o 48obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
42obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 49obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
43obj-$(CONFIG_MACH_KOTA2) += board-kota2.o 50obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
51obj-$(CONFIG_MACH_BONITO) += board-bonito.o
52obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
44 53
45# Framework support 54# Framework support
46obj-$(CONFIG_SMP) += $(smp-y) 55obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
new file mode 100644
index 000000000000..4d2201622323
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -0,0 +1,522 @@
1/*
2 * bonito board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/platform_device.h>
28#include <linux/gpio.h>
29#include <linux/smsc911x.h>
30#include <mach/common.h>
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/time.h>
35#include <asm/hardware/cache-l2x0.h>
36#include <mach/r8a7740.h>
37#include <video/sh_mobile_lcdc.h>
38
39/*
40 * CS Address device note
41 *----------------------------------------------------------------
42 * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
43 * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
44 * 4 -
45 * 5A -
46 * 5B 0x1600_0000 SRAM (8MB)
47 * 6 0x1800_0000 FPGA (64K)
48 * 0x1801_0000 Ether (4KB)
49 * 0x1801_1000 USB (4KB)
50 */
51
52/*
53 * SW12
54 *
55 * bit1 bit2 bit3
56 *----------------------------------------------------------------------------
57 * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
58 * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
59 */
60
61/*
62 * SCIFA5 (CN42)
63 *
64 * S38.3 = ON
65 * S39.6 = ON
66 * S43.1 = ON
67 */
68
69/*
70 * LCDC0 (CN3/CN4/CN7)
71 *
72 * S38.1 = OFF
73 * S38.2 = OFF
74 */
75
76/*
77 * FPGA
78 */
79#define IRQSR0 0x0020
80#define IRQSR1 0x0022
81#define IRQMR0 0x0030
82#define IRQMR1 0x0032
83#define BUSSWMR1 0x0070
84#define BUSSWMR2 0x0072
85#define BUSSWMR3 0x0074
86#define BUSSWMR4 0x0076
87
88#define LCDCR 0x10B4
89#define DEVRSTCR1 0x10D0
90#define DEVRSTCR2 0x10D2
91#define A1MDSR 0x10E0
92#define BVERR 0x1100
93
94/* FPGA IRQ */
95#define FPGA_IRQ_BASE (512)
96#define FPGA_IRQ0 (FPGA_IRQ_BASE)
97#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
98#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
99static u16 bonito_fpga_read(u32 offset)
100{
101 return __raw_readw(0xf0003000 + offset);
102}
103
104static void bonito_fpga_write(u32 offset, u16 val)
105{
106 __raw_writew(val, 0xf0003000 + offset);
107}
108
109static void bonito_fpga_irq_disable(struct irq_data *data)
110{
111 unsigned int irq = data->irq;
112 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
113 int shift = irq % 16;
114
115 bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
116}
117
118static void bonito_fpga_irq_enable(struct irq_data *data)
119{
120 unsigned int irq = data->irq;
121 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
122 int shift = irq % 16;
123
124 bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
125}
126
127static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
128 .name = "bonito FPGA",
129 .irq_mask = bonito_fpga_irq_disable,
130 .irq_unmask = bonito_fpga_irq_enable,
131};
132
133static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
134{
135 u32 val = bonito_fpga_read(IRQSR1) << 16 |
136 bonito_fpga_read(IRQSR0);
137 u32 mask = bonito_fpga_read(IRQMR1) << 16 |
138 bonito_fpga_read(IRQMR0);
139
140 int i;
141
142 val &= ~mask;
143
144 for (i = 0; i < 32; i++) {
145 if (!(val & (1 << i)))
146 continue;
147
148 generic_handle_irq(FPGA_IRQ_BASE + i);
149 }
150}
151
152static void bonito_fpga_init(void)
153{
154 int i;
155
156 bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
157 bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
158
159 /* Device reset */
160 bonito_fpga_write(DEVRSTCR1,
161 (1 << 2)); /* Eth */
162
163 /* FPGA irq require special handling */
164 for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
165 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
166 handle_level_irq, "level");
167 set_irq_flags(i, IRQF_VALID); /* yuck */
168 }
169
170 irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
171 irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
172}
173
174/*
175* PMIC settings
176*
177* FIXME
178*
179* bonito board needs some settings by pmic which use i2c access.
180* pmic settings use device_initcall() here for use it.
181*/
182static __u8 *pmic_settings = NULL;
183static __u8 pmic_do_2A[] = {
184 0x1C, 0x09,
185 0x1A, 0x80,
186 0xff, 0xff,
187};
188
189static int __init pmic_init(void)
190{
191 struct i2c_adapter *a = i2c_get_adapter(0);
192 struct i2c_msg msg;
193 __u8 buf[2];
194 int i, ret;
195
196 if (!pmic_settings)
197 return 0;
198 if (!a)
199 return 0;
200
201 msg.addr = 0x46;
202 msg.buf = buf;
203 msg.len = 2;
204 msg.flags = 0;
205
206 for (i = 0; ; i += 2) {
207 buf[0] = pmic_settings[i + 0];
208 buf[1] = pmic_settings[i + 1];
209
210 if ((0xff == buf[0]) && (0xff == buf[1]))
211 break;
212
213 ret = i2c_transfer(a, &msg, 1);
214 if (ret < 0) {
215 pr_err("i2c transfer fail\n");
216 break;
217 }
218 }
219
220 return 0;
221}
222device_initcall(pmic_init);
223
224/*
225 * LCDC0
226 */
227static const struct fb_videomode lcdc0_mode = {
228 .name = "WVGA Panel",
229 .xres = 800,
230 .yres = 480,
231 .left_margin = 88,
232 .right_margin = 40,
233 .hsync_len = 128,
234 .upper_margin = 20,
235 .lower_margin = 5,
236 .vsync_len = 5,
237 .sync = 0,
238};
239
240static struct sh_mobile_lcdc_info lcdc0_info = {
241 .clock_source = LCDC_CLK_BUS,
242 .ch[0] = {
243 .chan = LCDC_CHAN_MAINLCD,
244 .bpp = 16,
245 .interface_type = RGB24,
246 .clock_divider = 5,
247 .flags = 0,
248 .lcd_cfg = &lcdc0_mode,
249 .num_cfg = 1,
250 .lcd_size_cfg = {
251 .width = 152,
252 .height = 91,
253 },
254 },
255};
256
257static struct resource lcdc0_resources[] = {
258 [0] = {
259 .name = "LCDC0",
260 .start = 0xfe940000,
261 .end = 0xfe943fff,
262 .flags = IORESOURCE_MEM,
263 },
264 [1] = {
265 .start = intcs_evt2irq(0x0580),
266 .flags = IORESOURCE_IRQ,
267 },
268};
269
270static struct platform_device lcdc0_device = {
271 .name = "sh_mobile_lcdc_fb",
272 .id = 0,
273 .resource = lcdc0_resources,
274 .num_resources = ARRAY_SIZE(lcdc0_resources),
275 .dev = {
276 .platform_data = &lcdc0_info,
277 .coherent_dma_mask = ~0,
278 },
279};
280
281/*
282 * SMSC 9221
283 */
284static struct resource smsc_resources[] = {
285 [0] = {
286 .start = 0x18010000,
287 .end = 0x18011000 - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = FPGA_ETH_IRQ,
292 .flags = IORESOURCE_IRQ,
293 },
294};
295
296static struct smsc911x_platform_config smsc_platdata = {
297 .flags = SMSC911X_USE_16BIT,
298 .phy_interface = PHY_INTERFACE_MODE_MII,
299 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
300 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
301};
302
303static struct platform_device smsc_device = {
304 .name = "smsc911x",
305 .dev = {
306 .platform_data = &smsc_platdata,
307 },
308 .resource = smsc_resources,
309 .num_resources = ARRAY_SIZE(smsc_resources),
310};
311
312/*
313 * core board devices
314 */
315static struct platform_device *bonito_core_devices[] __initdata = {
316};
317
318/*
319 * base board devices
320 */
321static struct platform_device *bonito_base_devices[] __initdata = {
322 &lcdc0_device,
323 &smsc_device,
324};
325
326/*
327 * map I/O
328 */
329static struct map_desc bonito_io_desc[] __initdata = {
330 /*
331 * for CPGA/INTC/PFC
332 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
333 */
334 {
335 .virtual = 0xe6000000,
336 .pfn = __phys_to_pfn(0xe6000000),
337 .length = 160 << 20,
338 .type = MT_DEVICE_NONSHARED
339 },
340#ifdef CONFIG_CACHE_L2X0
341 /*
342 * for l2x0_init()
343 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
344 */
345 {
346 .virtual = 0xf0002000,
347 .pfn = __phys_to_pfn(0xf0100000),
348 .length = PAGE_SIZE,
349 .type = MT_DEVICE_NONSHARED
350 },
351#endif
352 /*
353 * for FPGA (0x1800000-0x19ffffff)
354 * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
355 */
356 {
357 .virtual = 0xf0003000,
358 .pfn = __phys_to_pfn(0x18000000),
359 .length = PAGE_SIZE * 2,
360 .type = MT_DEVICE_NONSHARED
361 }
362};
363
364static void __init bonito_map_io(void)
365{
366 iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
367
368 /* setup early devices and console here as well */
369 r8a7740_add_early_devices();
370 shmobile_setup_console();
371}
372
373/*
374 * board init
375 */
376#define BIT_ON(sw, bit) (sw & (1 << bit))
377#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
378
379#define VCCQ1CR 0xE6058140
380#define VCCQ1LCDCR 0xE6058186
381
382static void __init bonito_init(void)
383{
384 u16 val;
385
386 r8a7740_pinmux_init();
387 bonito_fpga_init();
388
389 pmic_settings = pmic_do_2A;
390
391 /*
392 * core board settings
393 */
394
395#ifdef CONFIG_CACHE_L2X0
396 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
397 l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
398#endif
399
400 r8a7740_add_standard_devices();
401
402 platform_add_devices(bonito_core_devices,
403 ARRAY_SIZE(bonito_core_devices));
404
405 /*
406 * base board settings
407 */
408 gpio_request(GPIO_PORT176, NULL);
409 gpio_direction_input(GPIO_PORT176);
410 if (!gpio_get_value(GPIO_PORT176)) {
411 u16 bsw2;
412 u16 bsw3;
413 u16 bsw4;
414
415 /*
416 * FPGA
417 */
418 gpio_request(GPIO_FN_CS5B, NULL);
419 gpio_request(GPIO_FN_CS6A, NULL);
420 gpio_request(GPIO_FN_CS5A_PORT105, NULL);
421 gpio_request(GPIO_FN_IRQ10, NULL);
422
423 val = bonito_fpga_read(BVERR);
424 pr_info("bonito version: cpu %02x, base %02x\n",
425 ((val >> 8) & 0xFF),
426 ((val >> 0) & 0xFF));
427
428 bsw2 = bonito_fpga_read(BUSSWMR2);
429 bsw3 = bonito_fpga_read(BUSSWMR3);
430 bsw4 = bonito_fpga_read(BUSSWMR4);
431
432 /*
433 * SCIFA5 (CN42)
434 */
435 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
436 BIT_OFF(bsw3, 9) && /* S39.6 = ON */
437 BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
438 gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
439 gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
440 }
441
442 /*
443 * LCDC0 (CN3)
444 */
445 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
446 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
447 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
448 gpio_request(GPIO_FN_LCD0_D0, NULL);
449 gpio_request(GPIO_FN_LCD0_D1, NULL);
450 gpio_request(GPIO_FN_LCD0_D2, NULL);
451 gpio_request(GPIO_FN_LCD0_D3, NULL);
452 gpio_request(GPIO_FN_LCD0_D4, NULL);
453 gpio_request(GPIO_FN_LCD0_D5, NULL);
454 gpio_request(GPIO_FN_LCD0_D6, NULL);
455 gpio_request(GPIO_FN_LCD0_D7, NULL);
456 gpio_request(GPIO_FN_LCD0_D8, NULL);
457 gpio_request(GPIO_FN_LCD0_D9, NULL);
458 gpio_request(GPIO_FN_LCD0_D10, NULL);
459 gpio_request(GPIO_FN_LCD0_D11, NULL);
460 gpio_request(GPIO_FN_LCD0_D12, NULL);
461 gpio_request(GPIO_FN_LCD0_D13, NULL);
462 gpio_request(GPIO_FN_LCD0_D14, NULL);
463 gpio_request(GPIO_FN_LCD0_D15, NULL);
464 gpio_request(GPIO_FN_LCD0_D16, NULL);
465 gpio_request(GPIO_FN_LCD0_D17, NULL);
466 gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
467 gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
468 gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
469 gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
470 gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
471 gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
472 gpio_request(GPIO_FN_LCD0_DCK, NULL);
473 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
474 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
475 gpio_request(GPIO_FN_LCD0_DISP, NULL);
476 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
477
478 gpio_request(GPIO_PORT61, NULL); /* LCDDON */
479 gpio_direction_output(GPIO_PORT61, 1);
480
481 /* backlight on */
482 bonito_fpga_write(LCDCR, 1);
483
484 /* drivability Max */
485 __raw_writew(0x00FF , VCCQ1LCDCR);
486 __raw_writew(0xFFFF , VCCQ1CR);
487 }
488
489 platform_add_devices(bonito_base_devices,
490 ARRAY_SIZE(bonito_base_devices));
491 }
492}
493
494static void __init bonito_timer_init(void)
495{
496 u16 val;
497 u8 md_ck = 0;
498
499 /* read MD_CK value */
500 val = bonito_fpga_read(A1MDSR);
501 if (val & (1 << 10))
502 md_ck |= MD_CK2;
503 if (val & (1 << 9))
504 md_ck |= MD_CK1;
505 if (val & (1 << 8))
506 md_ck |= MD_CK0;
507
508 r8a7740_clock_init(md_ck);
509 shmobile_timer.init();
510}
511
512struct sys_timer bonito_timer = {
513 .init = bonito_timer_init,
514};
515
516MACHINE_START(BONITO, "bonito")
517 .map_io = bonito_map_io,
518 .init_irq = r8a7740_init_irq,
519 .handle_irq = shmobile_handle_irq_intc,
520 .init_machine = bonito_init,
521 .timer = &bonito_timer,
522MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
new file mode 100644
index 000000000000..f0e02c0ce99f
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -0,0 +1,157 @@
1/*
2 * marzen board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/gpio.h>
29#include <linux/dma-mapping.h>
30#include <linux/smsc911x.h>
31#include <mach/hardware.h>
32#include <mach/r8a7779.h>
33#include <mach/common.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/time.h>
38#include <asm/hardware/gic.h>
39#include <asm/traps.h>
40
41/* SMSC LAN89218 */
42static struct resource smsc911x_resources[] = {
43 [0] = {
44 .start = 0x18000000, /* ExCS0 */
45 .end = 0x180000ff, /* A1->A7 */
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = gic_spi(28), /* IRQ 1 */
50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct smsc911x_platform_config smsc911x_platdata = {
55 .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
56 .phy_interface = PHY_INTERFACE_MODE_MII,
57 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
58 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
59};
60
61static struct platform_device eth_device = {
62 .name = "smsc911x",
63 .id = 0,
64 .dev = {
65 .platform_data = &smsc911x_platdata,
66 },
67 .resource = smsc911x_resources,
68 .num_resources = ARRAY_SIZE(smsc911x_resources),
69};
70
71static struct platform_device *marzen_devices[] __initdata = {
72 &eth_device,
73};
74
75static struct map_desc marzen_io_desc[] __initdata = {
76 /* 2M entity map for 0xf0000000 (MPCORE) */
77 {
78 .virtual = 0xf0000000,
79 .pfn = __phys_to_pfn(0xf0000000),
80 .length = SZ_2M,
81 .type = MT_DEVICE_NONSHARED
82 },
83 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
84 {
85 .virtual = 0xfe000000,
86 .pfn = __phys_to_pfn(0xfe000000),
87 .length = SZ_16M,
88 .type = MT_DEVICE_NONSHARED
89 },
90};
91
92static void __init marzen_map_io(void)
93{
94 iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
95}
96
97static void __init marzen_init_early(void)
98{
99 r8a7779_add_early_devices();
100
101 /* Early serial console setup is not included here due to
102 * memory map collisions. The SCIF serial ports in r8a7779
103 * are difficult to entity map 1:1 due to collision with the
104 * virtual memory range used by the coherent DMA code on ARM.
105 *
106 * Anyone wanting to debug early can remove UPF_IOREMAP from
107 * the sh-sci serial console platform data, adjust mapbase
108 * to a static M:N virt:phys mapping that needs to be added to
109 * the mappings passed with iotable_init() above.
110 *
111 * Then add a call to shmobile_setup_console() from this function.
112 *
113 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
114 * command line.
115 */
116}
117
118static void __init marzen_init(void)
119{
120 r8a7779_pinmux_init();
121
122 /* SCIF2 (CN18: DEBUG0) */
123 gpio_request(GPIO_FN_TX2_C, NULL);
124 gpio_request(GPIO_FN_RX2_C, NULL);
125
126 /* SCIF4 (CN19: DEBUG1) */
127 gpio_request(GPIO_FN_TX4, NULL);
128 gpio_request(GPIO_FN_RX4, NULL);
129
130 /* LAN89218 */
131 gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
132 gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
133
134 r8a7779_add_standard_devices();
135 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
136}
137
138static void __init marzen_timer_init(void)
139{
140 r8a7779_clock_init();
141 shmobile_timer.init();
142 return;
143}
144
145struct sys_timer marzen_timer = {
146 .init = marzen_timer_init,
147};
148
149MACHINE_START(MARZEN, "marzen")
150 .map_io = marzen_map_io,
151 .init_early = marzen_init_early,
152 .nr_irqs = NR_IRQS_LEGACY,
153 .init_irq = r8a7779_init_irq,
154 .handle_irq = gic_handle_irq,
155 .init_machine = marzen_init,
156 .timer = &marzen_timer,
157MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
new file mode 100644
index 000000000000..3b35b9afc001
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -0,0 +1,382 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26#include <mach/r8a7740.h>
27
28/*
29 * | MDx | XTAL1/EXTAL1 | System | EXTALR |
30 * Clock |-------+-----------------+ clock | 32.768 | RCLK
31 * Mode | 2/1/0 | src MHz | source | KHz | source
32 * -------+-------+-----------------+-----------+--------+----------
33 * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
34 * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
35 * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
36 * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
37 * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
38 * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
39 * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
40 * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
41 */
42
43/* CPG registers */
44#define FRQCRA 0xe6150000
45#define FRQCRB 0xe6150004
46#define FRQCRC 0xe61500e0
47#define PLLC01CR 0xe6150028
48
49#define SUBCKCR 0xe6150080
50
51#define MSTPSR0 0xe6150030
52#define MSTPSR1 0xe6150038
53#define MSTPSR2 0xe6150040
54#define MSTPSR3 0xe6150048
55#define MSTPSR4 0xe615004c
56#define SMSTPCR0 0xe6150130
57#define SMSTPCR1 0xe6150134
58#define SMSTPCR2 0xe6150138
59#define SMSTPCR3 0xe615013c
60#define SMSTPCR4 0xe6150140
61
62/* Fixed 32 KHz root clock from EXTALR pin */
63static struct clk extalr_clk = {
64 .rate = 32768,
65};
66
67/*
68 * 25MHz default rate for the EXTAL1 root input clock.
69 * If needed, reset this with clk_set_rate() from the platform code.
70 */
71static struct clk extal1_clk = {
72 .rate = 25000000,
73};
74
75/*
76 * 48MHz default rate for the EXTAL2 root input clock.
77 * If needed, reset this with clk_set_rate() from the platform code.
78 */
79static struct clk extal2_clk = {
80 .rate = 48000000,
81};
82
83/*
84 * 27MHz default rate for the DV_CLKI root input clock.
85 * If needed, reset this with clk_set_rate() from the platform code.
86 */
87static struct clk dv_clk = {
88 .rate = 27000000,
89};
90
91static unsigned long div_recalc(struct clk *clk)
92{
93 return clk->parent->rate / (int)(clk->priv);
94}
95
96static struct clk_ops div_clk_ops = {
97 .recalc = div_recalc,
98};
99
100/* extal1 / 2 */
101static struct clk extal1_div2_clk = {
102 .ops = &div_clk_ops,
103 .priv = (void *)2,
104 .parent = &extal1_clk,
105};
106
107/* extal1 / 1024 */
108static struct clk extal1_div1024_clk = {
109 .ops = &div_clk_ops,
110 .priv = (void *)1024,
111 .parent = &extal1_clk,
112};
113
114/* extal1 / 2 / 1024 */
115static struct clk extal1_div2048_clk = {
116 .ops = &div_clk_ops,
117 .priv = (void *)1024,
118 .parent = &extal1_div2_clk,
119};
120
121/* extal2 / 2 */
122static struct clk extal2_div2_clk = {
123 .ops = &div_clk_ops,
124 .priv = (void *)2,
125 .parent = &extal2_clk,
126};
127
128static struct clk_ops followparent_clk_ops = {
129 .recalc = followparent_recalc,
130};
131
132/* Main clock */
133static struct clk system_clk = {
134 .ops = &followparent_clk_ops,
135};
136
137static struct clk system_div2_clk = {
138 .ops = &div_clk_ops,
139 .priv = (void *)2,
140 .parent = &system_clk,
141};
142
143/* r_clk */
144static struct clk r_clk = {
145 .ops = &followparent_clk_ops,
146};
147
148/* PLLC0/PLLC1 */
149static unsigned long pllc01_recalc(struct clk *clk)
150{
151 unsigned long mult = 1;
152
153 if (__raw_readl(PLLC01CR) & (1 << 14))
154 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
155
156 return clk->parent->rate * mult;
157}
158
159static struct clk_ops pllc01_clk_ops = {
160 .recalc = pllc01_recalc,
161};
162
163static struct clk pllc0_clk = {
164 .ops = &pllc01_clk_ops,
165 .flags = CLK_ENABLE_ON_INIT,
166 .parent = &system_clk,
167 .enable_reg = (void __iomem *)FRQCRC,
168};
169
170static struct clk pllc1_clk = {
171 .ops = &pllc01_clk_ops,
172 .flags = CLK_ENABLE_ON_INIT,
173 .parent = &system_div2_clk,
174 .enable_reg = (void __iomem *)FRQCRA,
175};
176
177/* PLLC1 / 2 */
178static struct clk pllc1_div2_clk = {
179 .ops = &div_clk_ops,
180 .priv = (void *)2,
181 .parent = &pllc1_clk,
182};
183
184struct clk *main_clks[] = {
185 &extalr_clk,
186 &extal1_clk,
187 &extal2_clk,
188 &extal1_div2_clk,
189 &extal1_div1024_clk,
190 &extal1_div2048_clk,
191 &extal2_div2_clk,
192 &dv_clk,
193 &system_clk,
194 &system_div2_clk,
195 &r_clk,
196 &pllc0_clk,
197 &pllc1_clk,
198 &pllc1_div2_clk,
199};
200
201static void div4_kick(struct clk *clk)
202{
203 unsigned long value;
204
205 /* set KICK bit in FRQCRB to update hardware setting */
206 value = __raw_readl(FRQCRB);
207 value |= (1 << 31);
208 __raw_writel(value, FRQCRB);
209}
210
211static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
212 24, 32, 36, 48, 0, 72, 96, 0 };
213
214static struct clk_div_mult_table div4_div_mult_table = {
215 .divisors = divisors,
216 .nr_divisors = ARRAY_SIZE(divisors),
217};
218
219static struct clk_div4_table div4_table = {
220 .div_mult_table = &div4_div_mult_table,
221 .kick = div4_kick,
222};
223
224enum {
225 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
226 DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
227 DIV4_NR
228};
229
230struct clk div4_clks[DIV4_NR] = {
231 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
232 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
233 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
234 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
235 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
236 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
237 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
238 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
239 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
240 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
241};
242
243enum {
244 DIV6_SUB,
245 DIV6_NR
246};
247
248static struct clk div6_clks[DIV6_NR] = {
249 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
250};
251
252enum {
253 MSTP125,
254 MSTP116, MSTP111, MSTP100, MSTP117,
255
256 MSTP230,
257 MSTP222,
258 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
259
260 MSTP329, MSTP323,
261
262 MSTP_NR
263};
264
265static struct clk mstp_clks[MSTP_NR] = {
266 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
267 [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
268 [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
269 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
270 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
271
272 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
273 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
274 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
275 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
276 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
277 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
278 [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
279 [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
280 [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
281
282 [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
283 [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
284};
285
286static struct clk_lookup lookups[] = {
287 /* main clocks */
288 CLKDEV_CON_ID("extalr", &extalr_clk),
289 CLKDEV_CON_ID("extal1", &extal1_clk),
290 CLKDEV_CON_ID("extal2", &extal2_clk),
291 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
292 CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
293 CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
294 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
295 CLKDEV_CON_ID("dv_clk", &dv_clk),
296 CLKDEV_CON_ID("system_clk", &system_clk),
297 CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
298 CLKDEV_CON_ID("r_clk", &r_clk),
299 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
300 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
301 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
302
303 /* DIV4 clocks */
304 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
305 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
306 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
307 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
308 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
309 CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
310 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
311 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
312 CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
313 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
314
315 /* DIV6 clocks */
316 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
317
318 /* MSTP32 clocks */
319 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
320 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
321 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
322 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
323 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
324
325 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
326 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
327 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
328 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
329 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
330 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
331 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
332
333 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
334 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
335
336 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
337 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
338};
339
340void __init r8a7740_clock_init(u8 md_ck)
341{
342 int k, ret = 0;
343
344 /* detect system clock parent */
345 if (md_ck & MD_CK1)
346 system_clk.parent = &extal1_div2_clk;
347 else
348 system_clk.parent = &extal1_clk;
349
350 /* detect RCLK parent */
351 switch (md_ck & (MD_CK2 | MD_CK1)) {
352 case MD_CK2 | MD_CK1:
353 r_clk.parent = &extal1_div2048_clk;
354 break;
355 case MD_CK2:
356 r_clk.parent = &extal1_div1024_clk;
357 break;
358 case MD_CK1:
359 default:
360 r_clk.parent = &extalr_clk;
361 break;
362 }
363
364 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
365 ret = clk_register(main_clks[k]);
366
367 if (!ret)
368 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
369
370 if (!ret)
371 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
372
373 if (!ret)
374 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
375
376 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
377
378 if (!ret)
379 clk_init();
380 else
381 panic("failed to setup r8a7740 clocks\n");
382}
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
new file mode 100644
index 000000000000..b4b0e8cd096d
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -0,0 +1,176 @@
1/*
2 * r8a7779 clock framework support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define FRQMR 0xffc80014
28#define MSTPCR0 0xffc80030
29#define MSTPCR1 0xffc80034
30#define MSTPCR3 0xffc8003c
31#define MSTPSR1 0xffc80044
32#define MSTPSR4 0xffc80048
33#define MSTPSR6 0xffc8004c
34#define MSTPCR4 0xffc80050
35#define MSTPCR5 0xffc80054
36#define MSTPCR6 0xffc80058
37#define MSTPCR7 0xffc80040
38
39/* ioremap() through clock mapping mandatory to avoid
40 * collision with ARM coherent DMA virtual memory range.
41 */
42
43static struct clk_mapping cpg_mapping = {
44 .phys = 0xffc80000,
45 .len = 0x80,
46};
47
48/*
49 * Default rate for the root input clock, reset this with clk_set_rate()
50 * from the platform code.
51 */
52static struct clk plla_clk = {
53 .rate = 1500000000,
54 .mapping = &cpg_mapping,
55};
56
57static struct clk *main_clks[] = {
58 &plla_clk,
59};
60
61static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 };
62
63static struct clk_div_mult_table div4_div_mult_table = {
64 .divisors = divisors,
65 .nr_divisors = ARRAY_SIZE(divisors),
66};
67
68static struct clk_div4_table div4_table = {
69 .div_mult_table = &div4_div_mult_table,
70};
71
72enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
73
74static struct clk div4_clks[DIV4_NR] = {
75 [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
76 0x0018, CLK_ENABLE_ON_INIT),
77 [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
78 0x0700, CLK_ENABLE_ON_INIT),
79 [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
80 0x0040, CLK_ENABLE_ON_INIT),
81 [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
82 0x0010, CLK_ENABLE_ON_INIT),
83 [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
84 0x0060, CLK_ENABLE_ON_INIT),
85 [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
86 0x0300, CLK_ENABLE_ON_INIT),
87};
88
89enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
90 MSTP016, MSTP015, MSTP014,
91 MSTP_NR };
92
93static struct clk mstp_clks[MSTP_NR] = {
94 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
95 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
96 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
97 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
98 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
99 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
100 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
101 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
102 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
103};
104
105static unsigned long mul4_recalc(struct clk *clk)
106{
107 return clk->parent->rate * 4;
108}
109
110static struct clk_ops mul4_clk_ops = {
111 .recalc = mul4_recalc,
112};
113
114struct clk clkz_clk = {
115 .ops = &mul4_clk_ops,
116 .parent = &div4_clks[DIV4_S],
117};
118
119struct clk clkzs_clk = {
120 /* clks x 4 / 4 = clks */
121 .parent = &div4_clks[DIV4_S],
122};
123
124static struct clk *late_main_clks[] = {
125 &clkz_clk,
126 &clkzs_clk,
127};
128
129static struct clk_lookup lookups[] = {
130 /* main clocks */
131 CLKDEV_CON_ID("plla_clk", &plla_clk),
132 CLKDEV_CON_ID("clkz_clk", &clkz_clk),
133 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
134
135 /* DIV4 clocks */
136 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
137 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]),
138 CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]),
139 CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]),
140 CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]),
141 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
142
143 /* MSTP32 clocks */
144 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
145 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
146 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
147 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
148 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
149 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
150 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
151 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
152};
153
154void __init r8a7779_clock_init(void)
155{
156 int k, ret = 0;
157
158 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
159 ret = clk_register(main_clks[k]);
160
161 if (!ret)
162 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
163
164 if (!ret)
165 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
166
167 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
168 ret = clk_register(late_main_clks[k]);
169
170 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
171
172 if (!ret)
173 clk_init();
174 else
175 panic("failed to setup r8a7779 clocks\n");
176}
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 26079d933d91..6ac015c89206 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -14,7 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/memory.h> 15#include <asm/memory.h>
16 16
17 __INIT 17 __CPUINIT
18 18
19/* 19/*
20 * Reset vector for secondary CPUs. 20 * Reset vector for secondary CPUs.
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
index 238a0d97d2d5..828d22f3af57 100644
--- a/arch/arm/mach-shmobile/hotplug.c
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -12,14 +12,43 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/smp.h> 14#include <linux/smp.h>
15#include <linux/cpumask.h>
16#include <linux/delay.h>
17#include <mach/common.h>
18#include <asm/cacheflush.h>
19
20static cpumask_t dead_cpus;
15 21
16int platform_cpu_kill(unsigned int cpu) 22int platform_cpu_kill(unsigned int cpu)
17{ 23{
18 return 1; 24 int k;
25
26 /* this function is running on another CPU than the offline target,
27 * here we need wait for shutdown code in platform_cpu_die() to
28 * finish before asking SoC-specific code to power off the CPU core.
29 */
30 for (k = 0; k < 1000; k++) {
31 if (cpumask_test_cpu(cpu, &dead_cpus))
32 return shmobile_platform_cpu_kill(cpu);
33
34 mdelay(1);
35 }
36
37 return 0;
19} 38}
20 39
21void platform_cpu_die(unsigned int cpu) 40void platform_cpu_die(unsigned int cpu)
22{ 41{
42 /* hardware shutdown code running on the CPU that is being offlined */
43 flush_cache_all();
44 dsb();
45
46 /* notify platform_cpu_kill() that hardware shutdown is finished */
47 cpumask_set_cpu(cpu, &dead_cpus);
48
49 /* wait for SoC code in platform_cpu_kill() to shut off CPU core
50 * power. CPU bring up starts from the reset vector.
51 */
23 while (1) { 52 while (1) {
24 /* 53 /*
25 * here's the WFI 54 * here's the WFI
@@ -33,6 +62,7 @@ void platform_cpu_die(unsigned int cpu)
33 62
34int platform_cpu_disable(unsigned int cpu) 63int platform_cpu_disable(unsigned int cpu)
35{ 64{
65 cpumask_clear_cpu(cpu, &dead_cpus);
36 /* 66 /*
37 * we don't allow CPU 0 to be shutdown (it is still too special 67 * we don't allow CPU 0 to be shutdown (it is still too special
38 * e.g. clock tick interrupts) 68 * e.g. clock tick interrupts)
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 13a18d343ecb..e4b945e271e7 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -4,6 +4,7 @@
4extern struct sys_timer shmobile_timer; 4extern struct sys_timer shmobile_timer;
5extern void shmobile_setup_console(void); 5extern void shmobile_setup_console(void);
6extern void shmobile_secondary_vector(void); 6extern void shmobile_secondary_vector(void);
7extern int shmobile_platform_cpu_kill(unsigned int cpu);
7struct clk; 8struct clk;
8extern int clk_init(void); 9extern int clk_init(void);
9extern void shmobile_handle_irq_intc(struct pt_regs *); 10extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -54,4 +55,23 @@ extern void sh73a0_secondary_init(unsigned int cpu);
54extern int sh73a0_boot_secondary(unsigned int cpu); 55extern int sh73a0_boot_secondary(unsigned int cpu);
55extern void sh73a0_smp_prepare_cpus(void); 56extern void sh73a0_smp_prepare_cpus(void);
56 57
58extern void r8a7740_init_irq(void);
59extern void r8a7740_add_early_devices(void);
60extern void r8a7740_add_standard_devices(void);
61extern void r8a7740_clock_init(u8 md_ck);
62extern void r8a7740_pinmux_init(void);
63
64extern void r8a7779_init_irq(void);
65extern void r8a7779_add_early_devices(void);
66extern void r8a7779_add_standard_devices(void);
67extern void r8a7779_clock_init(void);
68extern void r8a7779_pinmux_init(void);
69extern void r8a7779_pm_init(void);
70
71extern unsigned int r8a7779_get_core_count(void);
72extern int r8a7779_platform_cpu_kill(unsigned int cpu);
73extern void r8a7779_secondary_init(unsigned int cpu);
74extern int r8a7779_boot_secondary(unsigned int cpu);
75extern void r8a7779_smp_prepare_cpus(void);
76
57#endif /* __ARCH_MACH_COMMON_H */ 77#endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
new file mode 100644
index 000000000000..9d447abb969c
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -0,0 +1,584 @@
1/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_R8A7740_H__
20#define __ASM_R8A7740_H__
21
22/*
23 * MD_CKx pin
24 */
25#define MD_CK2 (1 << 2)
26#define MD_CK1 (1 << 1)
27#define MD_CK0 (1 << 0)
28
29/*
30 * Pin Function Controller:
31 * GPIO_FN_xx - GPIO used to select pin function
32 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
33 */
34enum {
35 /* PORT */
36 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
37 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
38
39 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
40 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
41
42 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
43 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
44
45 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
46 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
47
48 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
49 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
50
51 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
52 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
53
54 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
55 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
56
57 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
58 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
59
60 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
61 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
62
63 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
64 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
65
66 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
67 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
68
69 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
70 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
71
72 GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
73 GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
74
75 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
76 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
77
78 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
79 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
80
81 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
82 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
83
84 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
85 GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
86
87 GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
88 GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
89
90 GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
91 GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
92
93 GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
94 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
95
96 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
97 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
98
99 GPIO_PORT210, GPIO_PORT211,
100
101 /* IRQ */
102 GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
103 GPIO_FN_IRQ1,
104 GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
105 GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
106 GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
107 GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
108 GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
109 GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
110 GPIO_FN_IRQ8,
111 GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
112 GPIO_FN_IRQ10,
113 GPIO_FN_IRQ11,
114 GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
115 GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
116 GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
117 GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
118 GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
119 GPIO_FN_IRQ17,
120 GPIO_FN_IRQ18,
121 GPIO_FN_IRQ19,
122 GPIO_FN_IRQ20,
123 GPIO_FN_IRQ21,
124 GPIO_FN_IRQ22,
125 GPIO_FN_IRQ23,
126 GPIO_FN_IRQ24,
127 GPIO_FN_IRQ25,
128 GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
129 GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
130 GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
131 GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
132 GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
133 GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
134
135 /* Function */
136
137 /* DBGT */
138 GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
139 GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
140 GPIO_FN_DBGMD21,
141
142 /* FSI */
143 GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
144 GPIO_FN_FSIAISLD_PORT5,
145 GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
146 GPIO_FN_FSIASPDIF_PORT18,
147 GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
148 GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
149 GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
150 GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
151 GPIO_FN_FSIAIBT,
152
153 /* FMSI */
154 GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
155 GPIO_FN_FMSISLD_PORT6,
156 GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
157 GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
158 GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
159 GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
160 GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
161 GPIO_FN_FMSOCK,
162
163 /* SCIFA0 */
164 GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
165 GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
166 GPIO_FN_SCIFA0_TXD,
167
168 /* SCIFA1 */
169 GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
170 GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
171 GPIO_FN_SCIFA1_RTS,
172
173 /* SCIFA2 */
174 GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
175 GPIO_FN_SCIFA2_SCK_PORT199,
176 GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
177 GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
178
179 /* SCIFA3 */
180 GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
181 GPIO_FN_SCIFA3_SCK_PORT116,
182 GPIO_FN_SCIFA3_CTS_PORT117,
183 GPIO_FN_SCIFA3_RXD_PORT174,
184 GPIO_FN_SCIFA3_TXD_PORT175,
185
186 GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
187 GPIO_FN_SCIFA3_SCK_PORT158,
188 GPIO_FN_SCIFA3_CTS_PORT162,
189 GPIO_FN_SCIFA3_RXD_PORT159,
190 GPIO_FN_SCIFA3_TXD_PORT160,
191
192 /* SCIFA4 */
193 GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
194 GPIO_FN_SCIFA4_TXD_PORT13,
195
196 GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
197 GPIO_FN_SCIFA4_TXD_PORT203,
198
199 GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
200 GPIO_FN_SCIFA4_TXD_PORT93,
201
202 GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
203 GPIO_FN_SCIFA4_SCK_PORT205,
204
205 /* SCIFA5 */
206 GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
207 GPIO_FN_SCIFA5_RXD_PORT10,
208
209 GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
210 GPIO_FN_SCIFA5_TXD_PORT208,
211
212 GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
213 GPIO_FN_SCIFA5_RXD_PORT92,
214
215 GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
216 GPIO_FN_SCIFA5_SCK_PORT206,
217
218 /* SCIFA6 */
219 GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
220
221 /* SCIFA7 */
222 GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
223
224 /* SCIFAB */
225 GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
226 GPIO_FN_SCIFB_RXD_PORT191,
227 GPIO_FN_SCIFB_TXD_PORT192,
228 GPIO_FN_SCIFB_RTS_PORT186,
229 GPIO_FN_SCIFB_CTS_PORT187,
230
231 GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
232 GPIO_FN_SCIFB_RXD_PORT3,
233 GPIO_FN_SCIFB_TXD_PORT4,
234 GPIO_FN_SCIFB_RTS_PORT172,
235 GPIO_FN_SCIFB_CTS_PORT173,
236
237 /* LCD0 */
238 GPIO_FN_LCDC0_SELECT,
239 GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
240 GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
241 GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
242 GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
243 GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
244 GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
245 GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
246
247 GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
248 GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
249
250 GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
251 GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
252
253 GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
254 GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
255 GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
256 GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
257
258 GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
259 GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
260 GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
261 GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
262
263 /* LCD1 */
264 GPIO_FN_LCDC1_SELECT,
265 GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
266 GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
267 GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
268 GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
269 GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
270 GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
271 GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
272 GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
273 GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
274 GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
275
276 GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
277 GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
278
279 GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
280 GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
281
282 /* RSPI */
283 GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
284 GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
285 GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
286 GPIO_FN_RSPI_CK_A,
287
288 /* VIO CKO */
289 GPIO_FN_VIO_CKO1,
290 GPIO_FN_VIO_CKO2,
291 GPIO_FN_VIO_CKO_1,
292 GPIO_FN_VIO_CKO,
293
294 /* VIO0 */
295 GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
296 GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
297 GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
298 GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
299 GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
300 GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
301
302 GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
303 GPIO_FN_VIO0_D14_PORT25,
304 GPIO_FN_VIO0_D15_PORT24,
305
306 GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
307 GPIO_FN_VIO0_D14_PORT95,
308 GPIO_FN_VIO0_D15_PORT96,
309
310 /* VIO1 */
311 GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
312 GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
313 GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
314 GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
315
316 /* TPU0 */
317 GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
318 GPIO_FN_TPU0TO3,
319 GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
320 GPIO_FN_TPU0TO2_PORT202,
321
322 /* SSP1 0 */
323 GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
324 GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
325 GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
326 GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
327
328 /* SSP1 1 */
329 GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
330 GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
331 GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
332
333 GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
334 GPIO_FN_STP1_IPEN_PORT187,
335
336 GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
337 GPIO_FN_STP1_IPEN_PORT193,
338
339 /* SIM */
340 GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
341 GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
342 GPIO_FN_SIM_D_PORT199,
343
344 /* SDHI0 */
345 GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
346 GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
347 GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
348
349 /* SDHI1 */
350 GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
351 GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
352 GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
353
354 /* SDHI2 */
355 GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
356 GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
357
358 GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
359 GPIO_FN_SDHI2_WP_PORT25,
360
361 GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
362 GPIO_FN_SDHI2_CD_PORT202,
363
364 /* MSIOF2 */
365 GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
366 GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
367 GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
368 GPIO_FN_MSIOF2_RSCK,
369
370 /* KEYSC */
371 GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
372 GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
373 GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
374 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
375 GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
376
377 GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
378 GPIO_FN_KEYIN1_PORT44,
379 GPIO_FN_KEYIN2_PORT45,
380 GPIO_FN_KEYIN3_PORT46,
381
382 GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
383 GPIO_FN_KEYIN1_PORT57,
384 GPIO_FN_KEYIN2_PORT56,
385 GPIO_FN_KEYIN3_PORT55,
386
387 /* VOU */
388 GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
389 GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
390 GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
391 GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
392 GPIO_FN_DV_CLK,
393 GPIO_FN_DV_VSYNC,
394 GPIO_FN_DV_HSYNC,
395
396 /* MEMC */
397 GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
398 GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
399 GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
400 GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
401 GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
402 GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
403 GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
404
405 GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
406 GPIO_FN_MEMC_ADV,
407 GPIO_FN_MEMC_WAIT,
408 GPIO_FN_MEMC_BUSCLK,
409
410 GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
411 GPIO_FN_MEMC_DREQ0,
412 GPIO_FN_MEMC_DREQ1,
413 GPIO_FN_MEMC_A0,
414
415 /* MMC */
416 GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
417 GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
418 GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
419 GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
420 GPIO_FN_MMC0_CLK_PORT66,
421 GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
422
423 GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
424 GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
425 GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
426 GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
427 GPIO_FN_MMC1_CLK_PORT103,
428 GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
429
430 /* MSIOF0 */
431 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
432 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
433 GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
434 GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
435 GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
436
437 /* MSIOF1 */
438 GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
439 GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
440
441 GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
442 GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
443 GPIO_FN_MSIOF1_TSYNC_PORT120,
444 GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
445
446 GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
447 GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
448 GPIO_FN_MSIOF1_RXD_PORT75,
449 GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
450
451 /* GPIO */
452 GPIO_FN_GPO0, GPIO_FN_GPI0,
453 GPIO_FN_GPO1, GPIO_FN_GPI1,
454
455 /* USB0 */
456 GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
457
458 /* USB1 */
459 GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
460
461 /* BBIF1 */
462 GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
463 GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
464 GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
465
466 /* BBIF2 */
467 GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
468 GPIO_FN_BBIF2_RXD2_PORT60,
469 GPIO_FN_BBIF2_TSYNC2_PORT6,
470 GPIO_FN_BBIF2_TSCK2_PORT59,
471
472 GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
473 GPIO_FN_BBIF2_TXD2_PORT183,
474 GPIO_FN_BBIF2_TSCK2_PORT89,
475 GPIO_FN_BBIF2_TSYNC2_PORT184,
476
477 /* BSC / FLCTL / PCMCIA */
478 GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
479 GPIO_FN_CS5B, GPIO_FN_CS6A,
480 GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
481 GPIO_FN_CS5A_PORT19,
482 GPIO_FN_IOIS16, /* ? */
483
484 GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
485 GPIO_FN_A4_FOE, /* share with FLCTL */
486 GPIO_FN_A5_FCDE, /* share with FLCTL */
487 GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
488 GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
489 GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
490 GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
491 GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
492 GPIO_FN_A26,
493
494 GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
495 GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
496 GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
497 GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
498 GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
499 GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
500 GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
501 GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
502
503 GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
504 GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
505 GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
506 GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
507
508 GPIO_FN_WE0_FWE, /* share with FLCTL */
509 GPIO_FN_WE1,
510 GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
511 GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
512 GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
513 GPIO_FN_RD_FSC, /* share with FLCTL */
514 GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
515 GPIO_FN_WAIT_PORT90,
516
517 GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
518
519 /* IRDA */
520 GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
521
522 /* ATAPI */
523 GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
524 GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
525 GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
526 GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
527 GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
528 GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
529 GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
530 GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
531 GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
532 GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
533
534 /* RMII */
535 GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
536 GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
537 GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
538 GPIO_FN_RMII_REF50CK, /* for RMII */
539 GPIO_FN_RMII_REF125CK, /* for GMII */
540
541 /* GEther */
542 GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
543 GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
544 GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
545 GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
546 GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
547 GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
548 GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
549 GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
550 GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
551 GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
552 GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
553 GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
554 GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
555 GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
556
557 /* DMA0 */
558 GPIO_FN_DREQ0, GPIO_FN_DACK0,
559
560 /* DMA1 */
561 GPIO_FN_DREQ1, GPIO_FN_DACK1,
562
563 /* SYSC */
564 GPIO_FN_RESETOUTS,
565 GPIO_FN_RESETP_PULLUP,
566 GPIO_FN_RESETP_PLAIN,
567
568 /* SDENC */
569 GPIO_FN_SDENC_CPG,
570 GPIO_FN_SDENC_DV_CLKI,
571
572 /* IRREM */
573 GPIO_FN_IROUT,
574
575 /* DEBUG */
576 GPIO_FN_EDEBGREQ_PULLDOWN,
577 GPIO_FN_EDEBGREQ_PULLUP,
578
579 GPIO_FN_TRACEAUD_FROM_VIO,
580 GPIO_FN_TRACEAUD_FROM_LCDC0,
581 GPIO_FN_TRACEAUD_FROM_MEMC,
582};
583
584#endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
new file mode 100644
index 000000000000..b07ad318eb2e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -0,0 +1,363 @@
1#ifndef __ASM_R8A7779_H__
2#define __ASM_R8A7779_H__
3
4#include <linux/sh_clk.h>
5#include <linux/pm_domain.h>
6
7/* Pin Function Controller:
8 * GPIO_FN_xx - GPIO used to select pin function
9 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
10 */
11enum {
12 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
13 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
14 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
15 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
16 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
17 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
18 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
19 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
20
21 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
22 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
23 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
24 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
25 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
26 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
27 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
28 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
29
30 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
31 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
32 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
33 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
34 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
35 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
36 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
37 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
38
39 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
40 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
41 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
42 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
43 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
44 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
45 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
46 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
47
48 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
49 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
50 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
51 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
52 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
53 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
54 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
55 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
56
57 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
58 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
59 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
60 GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
61 GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
62 GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
63 GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
64 GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
65
66 GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
67 GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
68 GPIO_GP_6_8,
69
70 GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
71 GPIO_FN_A19,
72
73 /* IPSR0 */
74 GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
75 GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
76 GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
77 GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
78 GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
79 GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
80 GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
81 GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
82 GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
83 GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
84 GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
85 GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
86 GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
87 GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
88 GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
89 GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
90
91 /* IPSR1 */
92 GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
93 GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
94 GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
95 GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
96 GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
97 GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
98 GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
99 GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
100 GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
101 GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
102 GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
103 GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
104 GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
105 GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
106 GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
107 GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
108 GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
109
110 /* IPSR2 */
111 GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
112 GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
113 GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
114 GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
115 GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
116 GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
117 GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
118 GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
119 GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
120 GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
121 GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
122 GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
123 GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
124 GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
125 GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
126 GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
127 GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
128 GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
129 GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
130 GPIO_FN_AUDATA2,
131
132 /* IPSR3 */
133 GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
134 GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
135 GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
136 GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
137 GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
138 GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
139 GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
140 GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
141 GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
142 GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
143 GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
144 GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
145 GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
146 GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
147 GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
148 GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
149 GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
150 GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
151 GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
152
153 /* IPSR4 */
154 GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
155 GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
156 GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
157 GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
158 GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
159 GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
160 GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
161 GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
162 GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
163 GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
164 GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
165 GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
166 GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
167 GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
168 GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
169 GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
170 GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
171 GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
172 GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
173
174 /* IPSR5 */
175 GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
176 GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
177 GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
178 GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
179 GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
180 GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
181 GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
182 GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
183 GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
184 GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
185 GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
186 GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
187 GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
188 GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
189 GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
190 GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
191 GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
192 GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
193 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
194 GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
195 GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
196 GPIO_FN_MOUT0,
197
198 /* IPSR6 */
199 GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
200 GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
201 GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
202 GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
203 GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
204 GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
205 GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
206 GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
207 GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
208 GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
209 GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
210 GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
211 GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
212 GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
213 GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
214 GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
215
216 /* IPSR7 */
217 GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
218 GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
219 GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
220 GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
221 GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
222 GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
223 GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
224 GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
225 GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
226 GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
227 GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
228 GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
229 GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
230 GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
231 GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
232 GPIO_FN_CTS1_B,
233
234 /* IPSR8 */
235 GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
236 GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
237 GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
238 GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
239 GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
240 GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
241 GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
242 GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
243 GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
244 GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
245 GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
246 GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
247 GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
248 GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
249 GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
250 GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
251 GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
252 GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
253 GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
254
255 /* IPSR9 */
256 GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
257 GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
258 GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
259 GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
260 GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
261 GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
262 GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
263 GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
264 GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
265 GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
266 GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
267 GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
268 GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
269 GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
270 GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
271 GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
272 GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
273 GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
274
275 /* IPSR10 */
276 GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
277 GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
278 GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
279 GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
280 GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
281 GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
282 GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
283 GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
284 GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
285 GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
286 GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
287 GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
288 GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
289 GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
290 GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
291 GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
292 GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
293 GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
294 GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
295
296 /* IPSR11 */
297 GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
298 GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
299 GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
300 GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
301 GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
302 GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
303 GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
304 GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
305 GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
306 GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
307 GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
308 GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
309 GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
310 GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
311 GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
312 GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
313 GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
314 GPIO_FN_HRTS0_B,
315
316 /* IPSR12 */
317 GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
318 GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
319 GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
320 GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
321 GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
322 GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
323 GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
324 GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
325 GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
326};
327
328struct platform_device;
329
330struct r8a7779_pm_ch {
331 unsigned long chan_offs;
332 unsigned int chan_bit;
333 unsigned int isr_bit;
334};
335
336struct r8a7779_pm_domain {
337 struct generic_pm_domain genpd;
338 struct r8a7779_pm_ch ch;
339};
340
341static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
342{
343 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
344}
345
346extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
347extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
348
349#ifdef CONFIG_PM
350extern struct r8a7779_pm_domain r8a7779_sh4a;
351extern struct r8a7779_pm_domain r8a7779_sgx;
352extern struct r8a7779_pm_domain r8a7779_vdp1;
353extern struct r8a7779_pm_domain r8a7779_impx3;
354
355extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd);
356extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
357 struct platform_device *pdev);
358#else
359#define r8a7779_init_pm_domain(pd) do { } while (0)
360#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
361#endif /* CONFIG_PM */
362
363#endif /* __ASM_R8A7779_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
new file mode 100644
index 000000000000..272c84c20c83
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -0,0 +1,631 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/sh_intc.h>
27#include <mach/intc.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31/*
32 * INTCA
33 */
34enum {
35 UNUSED_INTCA = 0,
36
37 /* interrupt sources INTCA */
38 DIRC,
39 ATAPI,
40 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
41 AP_ARM_COMMTX, AP_ARM_COMMRX,
42 MFI, MFIS,
43 BBIF1, BBIF2,
44 USBHSDMAC,
45 USBF_OUL_SOF, USBF_IXL_INT,
46 SGX540,
47 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
48 CMT2,
49 CMT3,
50 KEYSC,
51 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
52 MSIOF2, MSIOF1,
53 SCIFA4, SCIFA5, SCIFB,
54 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
55 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
56 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
57 AP_ARM_L2CINT,
58 IRDA,
59 TPU0,
60 SCIFA6, SCIFA7,
61 GbEther,
62 ICBS0,
63 DDM,
64 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
65 RWDT0,
66 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
67 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
72 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
73 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
74 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
75 SPU2_0, SPU2_1,
76 FSI, FMSI,
77 IPMMU,
78 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
79 MFIS2,
80 CPORTR2S,
81 CMT14, CMT15,
82 MMCIF_0, MMCIF_1, MMCIF_2,
83 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
84 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
85
86 /* interrupt groups INTCA */
87 DMAC1_1, DMAC1_2,
88 DMAC2_1, DMAC2_2,
89 DMAC3_1, DMAC3_2,
90 AP_ARM1, AP_ARM2,
91 SDHI0, SDHI1, SDHI2,
92 SHWYSTAT,
93 USBF, USBH1, USBH2,
94 RSPI, SPU2, FLCTL, IIC1,
95};
96
97static struct intc_vect intca_vectors[] __initdata = {
98 INTC_VECT(DIRC, 0x0560),
99 INTC_VECT(ATAPI, 0x05E0),
100 INTC_VECT(IIC1_ALI, 0x0780),
101 INTC_VECT(IIC1_TACKI, 0x07A0),
102 INTC_VECT(IIC1_WAITI, 0x07C0),
103 INTC_VECT(IIC1_DTEI, 0x07E0),
104 INTC_VECT(AP_ARM_COMMTX, 0x0840),
105 INTC_VECT(AP_ARM_COMMRX, 0x0860),
106 INTC_VECT(MFI, 0x0900),
107 INTC_VECT(MFIS, 0x0920),
108 INTC_VECT(BBIF1, 0x0940),
109 INTC_VECT(BBIF2, 0x0960),
110 INTC_VECT(USBHSDMAC, 0x0A00),
111 INTC_VECT(USBF_OUL_SOF, 0x0A20),
112 INTC_VECT(USBF_IXL_INT, 0x0A40),
113 INTC_VECT(SGX540, 0x0A60),
114 INTC_VECT(CMT1_0, 0x0B00),
115 INTC_VECT(CMT1_1, 0x0B20),
116 INTC_VECT(CMT1_2, 0x0B40),
117 INTC_VECT(CMT1_3, 0x0B60),
118 INTC_VECT(CMT2, 0x0B80),
119 INTC_VECT(CMT3, 0x0BA0),
120 INTC_VECT(KEYSC, 0x0BE0),
121 INTC_VECT(SCIFA0, 0x0C00),
122 INTC_VECT(SCIFA1, 0x0C20),
123 INTC_VECT(SCIFA2, 0x0C40),
124 INTC_VECT(SCIFA3, 0x0C60),
125 INTC_VECT(MSIOF2, 0x0C80),
126 INTC_VECT(MSIOF1, 0x0D00),
127 INTC_VECT(SCIFA4, 0x0D20),
128 INTC_VECT(SCIFA5, 0x0D40),
129 INTC_VECT(SCIFB, 0x0D60),
130 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
131 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
132 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
133 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
134 INTC_VECT(SDHI0_0, 0x0E00),
135 INTC_VECT(SDHI0_1, 0x0E20),
136 INTC_VECT(SDHI0_2, 0x0E40),
137 INTC_VECT(SDHI0_3, 0x0E60),
138 INTC_VECT(SDHI1_0, 0x0E80),
139 INTC_VECT(SDHI1_1, 0x0EA0),
140 INTC_VECT(SDHI1_2, 0x0EC0),
141 INTC_VECT(SDHI1_3, 0x0EE0),
142 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
143 INTC_VECT(IRDA, 0x0480),
144 INTC_VECT(TPU0, 0x04A0),
145 INTC_VECT(SCIFA6, 0x04C0),
146 INTC_VECT(SCIFA7, 0x04E0),
147 INTC_VECT(GbEther, 0x0500),
148 INTC_VECT(ICBS0, 0x0540),
149 INTC_VECT(DDM, 0x1140),
150 INTC_VECT(SDHI2_0, 0x1200),
151 INTC_VECT(SDHI2_1, 0x1220),
152 INTC_VECT(SDHI2_2, 0x1240),
153 INTC_VECT(SDHI2_3, 0x1260),
154 INTC_VECT(RWDT0, 0x1280),
155 INTC_VECT(DMAC1_1_DEI0, 0x2000),
156 INTC_VECT(DMAC1_1_DEI1, 0x2020),
157 INTC_VECT(DMAC1_1_DEI2, 0x2040),
158 INTC_VECT(DMAC1_1_DEI3, 0x2060),
159 INTC_VECT(DMAC1_2_DEI4, 0x2080),
160 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
161 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
162 INTC_VECT(DMAC2_1_DEI0, 0x2100),
163 INTC_VECT(DMAC2_1_DEI1, 0x2120),
164 INTC_VECT(DMAC2_1_DEI2, 0x2140),
165 INTC_VECT(DMAC2_1_DEI3, 0x2160),
166 INTC_VECT(DMAC2_2_DEI4, 0x2180),
167 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
168 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
169 INTC_VECT(DMAC3_1_DEI0, 0x2200),
170 INTC_VECT(DMAC3_1_DEI1, 0x2220),
171 INTC_VECT(DMAC3_1_DEI2, 0x2240),
172 INTC_VECT(DMAC3_1_DEI3, 0x2260),
173 INTC_VECT(DMAC3_2_DEI4, 0x2280),
174 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
175 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
176 INTC_VECT(SHWYSTAT_RT, 0x1300),
177 INTC_VECT(SHWYSTAT_HS, 0x1320),
178 INTC_VECT(SHWYSTAT_COM, 0x1340),
179 INTC_VECT(USBH_INT, 0x1540),
180 INTC_VECT(USBH_OHCI, 0x1560),
181 INTC_VECT(USBH_EHCI, 0x1580),
182 INTC_VECT(USBH_PME, 0x15A0),
183 INTC_VECT(USBH_BIND, 0x15C0),
184 INTC_VECT(RSPI_OVRF, 0x1780),
185 INTC_VECT(RSPI_SPTEF, 0x17A0),
186 INTC_VECT(RSPI_SPRF, 0x17C0),
187 INTC_VECT(SPU2_0, 0x1800),
188 INTC_VECT(SPU2_1, 0x1820),
189 INTC_VECT(FSI, 0x1840),
190 INTC_VECT(FMSI, 0x1860),
191 INTC_VECT(IPMMU, 0x1920),
192 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
193 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
194 INTC_VECT(MFIS2, 0x1A00),
195 INTC_VECT(CPORTR2S, 0x1A20),
196 INTC_VECT(CMT14, 0x1A40),
197 INTC_VECT(CMT15, 0x1A60),
198 INTC_VECT(MMCIF_0, 0x1AA0),
199 INTC_VECT(MMCIF_1, 0x1AC0),
200 INTC_VECT(MMCIF_2, 0x1AE0),
201 INTC_VECT(SIM_ERI, 0x1C00),
202 INTC_VECT(SIM_RXI, 0x1C20),
203 INTC_VECT(SIM_TXI, 0x1C40),
204 INTC_VECT(SIM_TEI, 0x1C60),
205 INTC_VECT(STPRO_0, 0x1C80),
206 INTC_VECT(STPRO_1, 0x1CA0),
207 INTC_VECT(STPRO_2, 0x1CC0),
208 INTC_VECT(STPRO_3, 0x1CE0),
209 INTC_VECT(STPRO_4, 0x1D00),
210};
211
212static struct intc_group intca_groups[] __initdata = {
213 INTC_GROUP(DMAC1_1,
214 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
215 INTC_GROUP(DMAC1_2,
216 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
217 INTC_GROUP(DMAC2_1,
218 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
219 INTC_GROUP(DMAC2_2,
220 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
221 INTC_GROUP(DMAC3_1,
222 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
223 INTC_GROUP(DMAC3_2,
224 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
225 INTC_GROUP(AP_ARM1,
226 AP_ARM_COMMTX, AP_ARM_COMMRX),
227 INTC_GROUP(AP_ARM2,
228 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
229 INTC_GROUP(USBF,
230 USBF_OUL_SOF, USBF_IXL_INT),
231 INTC_GROUP(SDHI0,
232 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
233 INTC_GROUP(SDHI1,
234 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
235 INTC_GROUP(SDHI2,
236 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
237 INTC_GROUP(SHWYSTAT,
238 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
239 INTC_GROUP(USBH1, /* FIXME */
240 USBH_INT, USBH_OHCI),
241 INTC_GROUP(USBH2, /* FIXME */
242 USBH_EHCI,
243 USBH_PME, USBH_BIND),
244 INTC_GROUP(RSPI,
245 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
246 INTC_GROUP(SPU2,
247 SPU2_0, SPU2_1),
248 INTC_GROUP(FLCTL,
249 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
250 INTC_GROUP(IIC1,
251 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
252};
253
254static struct intc_mask_reg intca_mask_registers[] __initdata = {
255 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
256 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
257 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
258 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
259 { ATAPI, 0, DIRC, 0,
260 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
261 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
262 { 0, 0, 0, 0,
263 BBIF1, BBIF2, MFIS, MFI } },
264 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
265 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
266 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
267 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
268 { DDM, 0, 0, 0,
269 0, 0, 0, 0 } },
270 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
271 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
272 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
273 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
274 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
275 0, 0, MSIOF2, 0 } },
276 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
277 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
278 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
279 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
280 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
281 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
282 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
283 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
284 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
285 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
286 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
287 0, 0, 0, 0 } },
288 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
289 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
290 ICBS0, 0, 0, 0 } },
291 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
292 { 0, 0, TPU0, SCIFA6,
293 SCIFA7, GbEther, 0, 0 } },
294 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
295 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
296 0, CMT3, 0, RWDT0 } },
297 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
298 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
299 0, 0, 0, 0 } },
300 /* IMR1A3 / IMCR1A3 */
301 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
302 { 0, 0, USBH_INT, USBH_OHCI,
303 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
304 /* IMR3A3 / IMCR3A3 */
305 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
306 { 0, 0, 0, 0,
307 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
308 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
309 { SPU2_0, SPU2_1, FSI, FMSI,
310 0, 0, 0, 0 } },
311 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
312 { 0, IPMMU, 0, 0,
313 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
314 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
315 { MFIS2, CPORTR2S, CMT14, CMT15,
316 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
317 /* IMR8A3 / IMCR8A3 */
318 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
319 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
320 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
321 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
322 { STPRO_4, 0, 0, 0,
323 0, 0, 0, 0 } },
324};
325
326static struct intc_prio_reg intca_prio_registers[] __initdata = {
327 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
328 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
329 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
330 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
331 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
332 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
333 SGX540, CMT1_0 } },
334 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
335 SCIFA2, SCIFA3 } },
336 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
337 FLCTL, SDHI0 } },
338 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
339 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
340 AP_ARM_L2CINT, 0 } },
341 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
342 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
343 SCIFA7, GbEther } },
344 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
345 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
346 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
347 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
348 /* IPRBA3 */
349 /* IPRCA3 */
350 /* IPRDA3 */
351 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
352 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
353 /* IPRGA3 */
354 /* IPRHA3 */
355 /* IPRIA3 */
356 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
357 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
358 /* IPRLA3 */
359 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
360 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
361 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
362 CMT14, CMT15 } },
363 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
364 /* IPRQA3 */
365 /* IPRRA3 */
366 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
367 SIM_TXI, SIM_TEI } },
368 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
369 STPRO_2, STPRO_3 } },
370 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
371};
372
373static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
374 intca_vectors, intca_groups,
375 intca_mask_registers, intca_prio_registers,
376 NULL);
377
378INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
379 INTC_VECT, "r8a7740-intca-irq-pins");
380
381
382/*
383 * INTCS
384 */
385enum {
386 UNUSED_INTCS = 0,
387
388 INTCS,
389
390 /* interrupt sources INTCS */
391
392 /* HUDI */
393 /* STPRO */
394 /* RTDMAC(1) */
395 VPU5HA2,
396 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
397 /* MFI */
398 /* BBIF2 */
399 VPU5F,
400 _2DG_BRK_INT,
401 /* SGX540 */
402 /* 2DDMAC */
403 /* IPMMU */
404 /* RTDMAC 2 */
405 /* KEYSC */
406 /* MSIOF */
407 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
408 TMU0_0, TMU0_1, TMU0_2,
409 CMT0,
410 /* CMT2 */
411 LMB,
412 CTI,
413 VOU,
414 /* RWDT0 */
415 ICB,
416 VIO6C,
417 CEU20, CEU21,
418 JPU,
419 LCDC0,
420 LCRC,
421 /* RTDMAC2(1) */
422 /* RTDMAC2(2) */
423 LCDC1,
424 /* SPU2 */
425 /* FSI */
426 /* FMSI */
427 TMU1_0, TMU1_1, TMU1_2,
428 CMT4,
429 DISP,
430 DSRV,
431 /* MFIS2 */
432 CPORTS2R,
433
434 /* interrupt groups INTCS */
435 _2DG1,
436 IIC0, TMU1,
437};
438
439static struct intc_vect intcs_vectors[] = {
440 /* HUDI */
441 /* STPRO */
442 /* RTDMAC(1) */
443 INTCS_VECT(VPU5HA2, 0x0880),
444 INTCS_VECT(_2DG_TRAP, 0x08A0),
445 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
446 INTCS_VECT(_2DG_CER_INT, 0x08E0),
447 /* MFI */
448 /* BBIF2 */
449 INTCS_VECT(VPU5F, 0x0980),
450 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
451 /* SGX540 */
452 /* 2DDMAC */
453 /* IPMMU */
454 /* RTDMAC(2) */
455 /* KEYSC */
456 /* MSIOF */
457 INTCS_VECT(IIC0_ALI, 0x0E00),
458 INTCS_VECT(IIC0_TACKI, 0x0E20),
459 INTCS_VECT(IIC0_WAITI, 0x0E40),
460 INTCS_VECT(IIC0_DTEI, 0x0E60),
461 INTCS_VECT(TMU0_0, 0x0E80),
462 INTCS_VECT(TMU0_1, 0x0EA0),
463 INTCS_VECT(TMU0_2, 0x0EC0),
464 INTCS_VECT(CMT0, 0x0F00),
465 /* CMT2 */
466 INTCS_VECT(LMB, 0x0F60),
467 INTCS_VECT(CTI, 0x0400),
468 INTCS_VECT(VOU, 0x0420),
469 /* RWDT0 */
470 INTCS_VECT(ICB, 0x0480),
471 INTCS_VECT(VIO6C, 0x04E0),
472 INTCS_VECT(CEU20, 0x0500),
473 INTCS_VECT(CEU21, 0x0520),
474 INTCS_VECT(JPU, 0x0560),
475 INTCS_VECT(LCDC0, 0x0580),
476 INTCS_VECT(LCRC, 0x05A0),
477 /* RTDMAC2(1) */
478 /* RTDMAC2(2) */
479 INTCS_VECT(LCDC1, 0x1780),
480 /* SPU2 */
481 /* FSI */
482 /* FMSI */
483 INTCS_VECT(TMU1_0, 0x1900),
484 INTCS_VECT(TMU1_1, 0x1920),
485 INTCS_VECT(TMU1_2, 0x1940),
486 INTCS_VECT(CMT4, 0x1980),
487 INTCS_VECT(DISP, 0x19A0),
488 INTCS_VECT(DSRV, 0x19C0),
489 /* MFIS2 */
490 INTCS_VECT(CPORTS2R, 0x1A20),
491
492 INTC_VECT(INTCS, 0xf80),
493};
494
495static struct intc_group intcs_groups[] __initdata = {
496 INTC_GROUP(_2DG1, /*FIXME*/
497 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
498 INTC_GROUP(IIC0,
499 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
500 INTC_GROUP(TMU1,
501 TMU1_0, TMU1_1, TMU1_2),
502};
503
504static struct intc_mask_reg intcs_mask_registers[] = {
505 /* IMR0SA / IMCR0SA */ /* all 0 */
506 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
507 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
508 0, 0, 0, 0 /*STPRO*/ } },
509 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
510 { 0/*STPRO*/, 0, CEU21, VPU5F,
511 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
512 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
513 { 0, 0, 0, 0, /*2DDMAC*/
514 VIO6C, 0, 0, ICB } },
515 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
516 { 0, 0, VOU, CTI,
517 JPU, 0, LCRC, LCDC0 } },
518 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
519 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
520 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
521 { 0, TMU0_2, TMU0_1, TMU0_0,
522 0, 0, 0, 0 } },
523 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
524 { 0, 0, 0, 0,
525 CEU20, 0, 0, 0 } },
526 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
527 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
528 0, 0, 0, 0 } },
529 /* IMR10SA / IMCR10SA */ /*IPMMU*/
530 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
531 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
532 0, _2DG_BRK_INT, LMB, 0 } },
533 /* IMR12SA / IMCR12SA */
534 /* IMR13SA / IMCR13SA */
535 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
536 /* IMR1SA3 / IMCR1SA3 */
537 /* IMR2SA3 / IMCR2SA3 */
538 /* IMR3SA3 / IMCR3SA3 */
539 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
540 { 0, 0, 0, 0,
541 LCDC1, 0, 0, 0 } },
542 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
543 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
544 { TMU1_0, TMU1_1, TMU1_2, 0,
545 CMT4, DISP, DSRV, 0 } },
546 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
547 { 0/*MFIS2*/, CPORTS2R, 0, 0,
548 0, 0, 0, 0 } },
549 { /* INTAMASK */ 0xffd20104, 0, 16,
550 { 0, 0, 0, 0, 0, 0, 0, 0,
551 0, 0, 0, 0, 0, 0, 0, INTCS } },
552};
553
554/* Priority is needed for INTCA to receive the INTCS interrupt */
555static struct intc_prio_reg intcs_prio_registers[] = {
556 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
557 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
558 /* IPRCS */ /*BBIF2*/
559 /* IPRDS */
560 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
561 0/*MFI*/, VPU5F } },
562 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
563 0/*CMT2*/, CMT0 } },
564 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
565 TMU0_2, _2DG1 } },
566 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
567 _2DG_BRK_INT/*FIXME*/ } },
568 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
569 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
570 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
571 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
572 /* IPRMS */ /*RWDT0*/
573 /* IPRAS3 */ /*RTDMAC2(1)*/
574 /* IPRBS3 */ /*RTDMAC2(2)*/
575 /* IPRCS3 */
576 /* IPRDS3 */
577 /* IPRES3 */
578 /* IPRFS3 */
579 /* IPRGS3 */
580 /* IPRHS3 */
581 /* IPRIS3 */
582 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
583 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
584 /* IPRLS3 */
585 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
586 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
587 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
588 /* IPRPS3 */
589};
590
591static struct resource intcs_resources[] __initdata = {
592 [0] = {
593 .start = 0xffd20000,
594 .end = 0xffd201ff,
595 .flags = IORESOURCE_MEM,
596 },
597 [1] = {
598 .start = 0xffd50000,
599 .end = 0xffd501ff,
600 .flags = IORESOURCE_MEM,
601 }
602};
603
604static struct intc_desc intcs_desc __initdata = {
605 .name = "r8a7740-intcs",
606 .resource = intcs_resources,
607 .num_resources = ARRAY_SIZE(intcs_resources),
608 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
609 intcs_prio_registers, NULL, NULL),
610};
611
612static void intcs_demux(unsigned int irq, struct irq_desc *desc)
613{
614 void __iomem *reg = (void *)irq_get_handler_data(irq);
615 unsigned int evtcodeas = ioread32(reg);
616
617 generic_handle_irq(intcs_evt2irq(evtcodeas));
618}
619
620void __init r8a7740_init_irq(void)
621{
622 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
623
624 register_intc_controller(&intca_desc);
625 register_intc_controller(&intca_irq_pins_desc);
626 register_intc_controller(&intcs_desc);
627
628 /* demux using INTEVTSA */
629 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
630 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
631}
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
new file mode 100644
index 000000000000..5d92fcde2bc3
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -0,0 +1,58 @@
1/*
2 * r8a7779 processor support - INTC hardware block
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/io.h>
25#include <mach/common.h>
26#include <mach/intc.h>
27#include <mach/r8a7779.h>
28#include <asm/hardware/gic.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32#define INT2SMSKCR0 0xfe7822a0
33#define INT2SMSKCR1 0xfe7822a4
34#define INT2SMSKCR2 0xfe7822a8
35#define INT2SMSKCR3 0xfe7822ac
36#define INT2SMSKCR4 0xfe7822b0
37
38static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
39{
40 return 0; /* always allow wakeup */
41}
42
43void __init r8a7779_init_irq(void)
44{
45 void __iomem *gic_dist_base = __io(0xf0001000);
46 void __iomem *gic_cpu_base = __io(0xf0000100);
47
48 /* use GIC to handle interrupts */
49 gic_init(0, 29, gic_dist_base, gic_cpu_base);
50 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
51
52 /* unmask all known interrupts in INTCS2 */
53 __raw_writel(0xfffffff0, INT2SMSKCR0);
54 __raw_writel(0xfff7ffff, INT2SMSKCR1);
55 __raw_writel(0xfffbffdf, INT2SMSKCR2);
56 __raw_writel(0xbffffffc, INT2SMSKCR3);
57 __raw_writel(0x003fee3f, INT2SMSKCR4);
58}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
new file mode 100644
index 000000000000..a4fff6950b03
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -0,0 +1,2562 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/gpio.h>
24#include <mach/r8a7740.h>
25
26#define CPU_ALL_PORT(fn, pfx, sfx) \
27 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
28 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
29 PORT_10(fn, pfx##20, sfx), \
30 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
31
32enum {
33 PINMUX_RESERVED = 0,
34
35 /* PORT0_DATA -> PORT211_DATA */
36 PINMUX_DATA_BEGIN,
37 PORT_ALL(DATA),
38 PINMUX_DATA_END,
39
40 /* PORT0_IN -> PORT211_IN */
41 PINMUX_INPUT_BEGIN,
42 PORT_ALL(IN),
43 PINMUX_INPUT_END,
44
45 /* PORT0_IN_PU -> PORT211_IN_PU */
46 PINMUX_INPUT_PULLUP_BEGIN,
47 PORT_ALL(IN_PU),
48 PINMUX_INPUT_PULLUP_END,
49
50 /* PORT0_IN_PD -> PORT211_IN_PD */
51 PINMUX_INPUT_PULLDOWN_BEGIN,
52 PORT_ALL(IN_PD),
53 PINMUX_INPUT_PULLDOWN_END,
54
55 /* PORT0_OUT -> PORT211_OUT */
56 PINMUX_OUTPUT_BEGIN,
57 PORT_ALL(OUT),
58 PINMUX_OUTPUT_END,
59
60 PINMUX_FUNCTION_BEGIN,
61 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
62 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
63 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
64 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
65 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
66 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
67 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
68 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
69 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
70 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
71
72 MSEL1CR_31_0, MSEL1CR_31_1,
73 MSEL1CR_30_0, MSEL1CR_30_1,
74 MSEL1CR_29_0, MSEL1CR_29_1,
75 MSEL1CR_28_0, MSEL1CR_28_1,
76 MSEL1CR_27_0, MSEL1CR_27_1,
77 MSEL1CR_26_0, MSEL1CR_26_1,
78 MSEL1CR_16_0, MSEL1CR_16_1,
79 MSEL1CR_15_0, MSEL1CR_15_1,
80 MSEL1CR_14_0, MSEL1CR_14_1,
81 MSEL1CR_13_0, MSEL1CR_13_1,
82 MSEL1CR_12_0, MSEL1CR_12_1,
83 MSEL1CR_9_0, MSEL1CR_9_1,
84 MSEL1CR_7_0, MSEL1CR_7_1,
85 MSEL1CR_6_0, MSEL1CR_6_1,
86 MSEL1CR_5_0, MSEL1CR_5_1,
87 MSEL1CR_4_0, MSEL1CR_4_1,
88 MSEL1CR_3_0, MSEL1CR_3_1,
89 MSEL1CR_2_0, MSEL1CR_2_1,
90 MSEL1CR_0_0, MSEL1CR_0_1,
91
92 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
93 MSEL3CR_6_0, MSEL3CR_6_1,
94
95 MSEL4CR_19_0, MSEL4CR_19_1,
96 MSEL4CR_18_0, MSEL4CR_18_1,
97 MSEL4CR_15_0, MSEL4CR_15_1,
98 MSEL4CR_10_0, MSEL4CR_10_1,
99 MSEL4CR_6_0, MSEL4CR_6_1,
100 MSEL4CR_4_0, MSEL4CR_4_1,
101 MSEL4CR_1_0, MSEL4CR_1_1,
102
103 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
104 MSEL5CR_30_0, MSEL5CR_30_1,
105 MSEL5CR_29_0, MSEL5CR_29_1,
106 MSEL5CR_27_0, MSEL5CR_27_1,
107 MSEL5CR_25_0, MSEL5CR_25_1,
108 MSEL5CR_23_0, MSEL5CR_23_1,
109 MSEL5CR_21_0, MSEL5CR_21_1,
110 MSEL5CR_19_0, MSEL5CR_19_1,
111 MSEL5CR_17_0, MSEL5CR_17_1,
112 MSEL5CR_15_0, MSEL5CR_15_1,
113 MSEL5CR_14_0, MSEL5CR_14_1,
114 MSEL5CR_13_0, MSEL5CR_13_1,
115 MSEL5CR_12_0, MSEL5CR_12_1,
116 MSEL5CR_11_0, MSEL5CR_11_1,
117 MSEL5CR_10_0, MSEL5CR_10_1,
118 MSEL5CR_8_0, MSEL5CR_8_1,
119 MSEL5CR_7_0, MSEL5CR_7_1,
120 MSEL5CR_6_0, MSEL5CR_6_1,
121 MSEL5CR_5_0, MSEL5CR_5_1,
122 MSEL5CR_4_0, MSEL5CR_4_1,
123 MSEL5CR_3_0, MSEL5CR_3_1,
124 MSEL5CR_2_0, MSEL5CR_2_1,
125 MSEL5CR_0_0, MSEL5CR_0_1,
126 PINMUX_FUNCTION_END,
127
128 PINMUX_MARK_BEGIN,
129
130 /* IRQ */
131 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
132 IRQ1_MARK,
133 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
134 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
135 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
136 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
137 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
138 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
139 IRQ8_MARK,
140 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
141 IRQ10_MARK,
142 IRQ11_MARK,
143 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
144 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
145 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
146 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
147 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
148 IRQ17_MARK,
149 IRQ18_MARK,
150 IRQ19_MARK,
151 IRQ20_MARK,
152 IRQ21_MARK,
153 IRQ22_MARK,
154 IRQ23_MARK,
155 IRQ24_MARK,
156 IRQ25_MARK,
157 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
158 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
159 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
160 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
161 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
162 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
163
164 /* Function */
165
166 /* DBGT */
167 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
168 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
169 DBGMD21_MARK,
170
171 /* FSI */
172 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
173 FSIAISLD_PORT5_MARK,
174 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
175 FSIASPDIF_PORT18_MARK,
176 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
177 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
178 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
179
180 /* FMSI */
181 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
182 FMSISLD_PORT6_MARK,
183 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
184 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
185 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
186
187 /* SCIFA0 */
188 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
189 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
190
191 /* SCIFA1 */
192 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
193 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
194
195 /* SCIFA2 */
196 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
197 SCIFA2_SCK_PORT199_MARK,
198 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
199 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
200
201 /* SCIFA3 */
202 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
203 SCIFA3_SCK_PORT116_MARK,
204 SCIFA3_CTS_PORT117_MARK,
205 SCIFA3_RXD_PORT174_MARK,
206 SCIFA3_TXD_PORT175_MARK,
207
208 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
209 SCIFA3_SCK_PORT158_MARK,
210 SCIFA3_CTS_PORT162_MARK,
211 SCIFA3_RXD_PORT159_MARK,
212 SCIFA3_TXD_PORT160_MARK,
213
214 /* SCIFA4 */
215 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
216 SCIFA4_TXD_PORT13_MARK,
217
218 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
219 SCIFA4_TXD_PORT203_MARK,
220
221 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
222 SCIFA4_TXD_PORT93_MARK,
223
224 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
225 SCIFA4_SCK_PORT205_MARK,
226
227 /* SCIFA5 */
228 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
229 SCIFA5_RXD_PORT10_MARK,
230
231 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
232 SCIFA5_TXD_PORT208_MARK,
233
234 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
235 SCIFA5_RXD_PORT92_MARK,
236
237 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
238 SCIFA5_SCK_PORT206_MARK,
239
240 /* SCIFA6 */
241 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
242
243 /* SCIFA7 */
244 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
245
246 /* SCIFAB */
247 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
248 SCIFB_RXD_PORT191_MARK,
249 SCIFB_TXD_PORT192_MARK,
250 SCIFB_RTS_PORT186_MARK,
251 SCIFB_CTS_PORT187_MARK,
252
253 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
254 SCIFB_RXD_PORT3_MARK,
255 SCIFB_TXD_PORT4_MARK,
256 SCIFB_RTS_PORT172_MARK,
257 SCIFB_CTS_PORT173_MARK,
258
259 /* LCD0 */
260 LCDC0_SELECT_MARK,
261
262 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
263 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
264 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
265 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
266 LCD0_D16_MARK, LCD0_D17_MARK,
267 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
268 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
269 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
270 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
271 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
272
273 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
274 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
275 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
276 LCD0_LCLK_PORT165_MARK,
277
278 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
279 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
280 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
281 LCD0_LCLK_PORT102_MARK,
282
283 /* LCD1 */
284 LCDC1_SELECT_MARK,
285
286 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
287 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
288 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
289 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
290 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
291 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
292 LCD1_DON_MARK, LCD1_VCPWC_MARK,
293 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
294
295 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
296 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
297 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
298 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
299
300 /* RSPI */
301 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
302 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
303 RSPI_MISO_A_MARK,
304
305 /* VIO CKO */
306 VIO_CKO1_MARK, /* needs fixup */
307 VIO_CKO2_MARK,
308 VIO_CKO_1_MARK,
309 VIO_CKO_MARK,
310
311 /* VIO0 */
312 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
313 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
314 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
315 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
316 VIO0_FIELD_MARK,
317
318 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
319 VIO0_D14_PORT25_MARK,
320 VIO0_D15_PORT24_MARK,
321
322 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
323 VIO0_D14_PORT95_MARK,
324 VIO0_D15_PORT96_MARK,
325
326 /* VIO1 */
327 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
328 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
329 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
330
331 /* TPU0 */
332 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
333 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
334 TPU0TO2_PORT202_MARK,
335
336 /* SSP1 0 */
337 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
338 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
339 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
340
341 /* SSP1 1 */
342 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
343 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
344 STP1_IPSYNC_MARK,
345
346 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
347 STP1_IPEN_PORT187_MARK,
348
349 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
350 STP1_IPEN_PORT193_MARK,
351
352 /* SIM */
353 SIM_RST_MARK, SIM_CLK_MARK,
354 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
355 SIM_D_PORT199_MARK,
356
357 /* SDHI0 */
358 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
359 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
360
361 /* SDHI1 */
362 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
363 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
364
365 /* SDHI2 */
366 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
367 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
368
369 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
370 SDHI2_WP_PORT25_MARK,
371
372 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
373 SDHI2_CD_PORT202_MARK,
374
375 /* MSIOF2 */
376 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
377 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
378 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
379 MSIOF2_RSCK_MARK,
380
381 /* KEYSC */
382 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
383 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
384 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
385
386 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
387 KEYIN1_PORT44_MARK,
388 KEYIN2_PORT45_MARK,
389 KEYIN3_PORT46_MARK,
390
391 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
392 KEYIN1_PORT57_MARK,
393 KEYIN2_PORT56_MARK,
394 KEYIN3_PORT55_MARK,
395
396 /* VOU */
397 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
398 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
399 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
400 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
401 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
402
403 /* MEMC */
404 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
405 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
406 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
407 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
408 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
409
410 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
411 MEMC_ADV_MARK,
412 MEMC_WAIT_MARK,
413 MEMC_BUSCLK_MARK,
414
415 MEMC_A1_MARK, /* MSEL4CR_6_1 */
416 MEMC_DREQ0_MARK,
417 MEMC_DREQ1_MARK,
418 MEMC_A0_MARK,
419
420 /* MMC */
421 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
422 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
423 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
424 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
425
426 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
427 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
428 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
429 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
430
431 /* MSIOF0 */
432 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
433 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
434 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
435 MSIOF0_TSYNC_MARK,
436
437 /* MSIOF1 */
438 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
439 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
440
441 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
442 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
443 MSIOF1_TSYNC_PORT120_MARK,
444 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
445
446 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
447 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
448 MSIOF1_RXD_PORT75_MARK,
449 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
450
451 /* GPIO */
452 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
453
454 /* USB0 */
455 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
456
457 /* USB1 */
458 USB1_OCI_MARK, USB1_PPON_MARK,
459
460 /* BBIF1 */
461 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
462 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
463 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
464
465 /* BBIF2 */
466 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
467 BBIF2_RXD2_PORT60_MARK,
468 BBIF2_TSYNC2_PORT6_MARK,
469 BBIF2_TSCK2_PORT59_MARK,
470
471 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
472 BBIF2_TXD2_PORT183_MARK,
473 BBIF2_TSCK2_PORT89_MARK,
474 BBIF2_TSYNC2_PORT184_MARK,
475
476 /* BSC / FLCTL / PCMCIA */
477 CS0_MARK, CS2_MARK, CS4_MARK,
478 CS5B_MARK, CS6A_MARK,
479 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
480 CS5A_PORT19_MARK,
481 IOIS16_MARK, /* ? */
482
483 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
484 A4_FOE_MARK, /* share with FLCTL */
485 A5_FCDE_MARK, /* share with FLCTL */
486 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
487 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
488 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
489 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
490 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
491 A26_MARK,
492
493 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
494 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
495 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
496 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
497 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
498 D15_NAF15_MARK, /* share with FLCTL */
499 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
500 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
501 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
502 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
503
504 WE0_FWE_MARK, /* share with FLCTL */
505 WE1_MARK,
506 WE2_ICIORD_MARK, /* share with PCMCIA */
507 WE3_ICIOWR_MARK, /* share with PCMCIA */
508 CKO_MARK, BS_MARK, RDWR_MARK,
509 RD_FSC_MARK, /* share with FLCTL */
510 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
511 WAIT_PORT90_MARK,
512
513 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
514
515 /* IRDA */
516 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
517
518 /* ATAPI */
519 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
520 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
521 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
522 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
523 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
524 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
525 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
526 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
527
528 /* RMII */
529 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
530 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
531 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
532 RMII_REF50CK_MARK, /* for RMII */
533 RMII_REF125CK_MARK, /* for GMII */
534
535 /* GEther */
536 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
537 ET_ETXD2_MARK, ET_ETXD3_MARK,
538 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
539 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
540 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
541 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
542 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
543 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
544 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
545 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
546
547 /* DMA0 */
548 DREQ0_MARK, DACK0_MARK,
549
550 /* DMA1 */
551 DREQ1_MARK, DACK1_MARK,
552
553 /* SYSC */
554 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
555
556 /* IRREM */
557 IROUT_MARK,
558
559 /* SDENC */
560 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
561
562 /* DEBUG */
563 EDEBGREQ_PULLUP_MARK, /* for JTAG */
564 EDEBGREQ_PULLDOWN_MARK,
565
566 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
567 TRACEAUD_FROM_LCDC0_MARK,
568 TRACEAUD_FROM_MEMC_MARK,
569
570 PINMUX_MARK_END,
571};
572
573static pinmux_enum_t pinmux_data[] = {
574 /* specify valid pin states for each pin in GPIO mode */
575
576 /* I/O and Pull U/D */
577 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
578 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
579 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
580 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
581 PORT_DATA_IO(8), PORT_DATA_IO(9),
582
583 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
584 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
585 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
586 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
587 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
588
589 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
590 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
591 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
592 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
593 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
594
595 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
596 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
597 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
598 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
599 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
600
601 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
602 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
603 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
604 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
605 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
606
607 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
608 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
609 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
610 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
611 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
612
613 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
614 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
615 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
616 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
617 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
618
619 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
620 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
621 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
622 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
623 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
624
625 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
626 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
627 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
628 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
629 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
630
631 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
632 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
633 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
634 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
635 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
636
637 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
638 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
639 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
640 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
641 PORT_DATA_IO(108), PORT_DATA_IO(109),
642
643 PORT_DATA_IO(110), PORT_DATA_IO(111),
644 PORT_DATA_IO(112), PORT_DATA_IO(113),
645 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
646 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
647 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
648
649 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
650 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
651 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
652 PORT_DATA_IO(126), PORT_DATA_IO(127),
653 PORT_DATA_IO(128), PORT_DATA_IO(129),
654
655 PORT_DATA_IO(130), PORT_DATA_IO(131),
656 PORT_DATA_IO(132), PORT_DATA_IO(133),
657 PORT_DATA_IO(134), PORT_DATA_IO(135),
658 PORT_DATA_IO(136), PORT_DATA_IO(137),
659 PORT_DATA_IO(138), PORT_DATA_IO(139),
660
661 PORT_DATA_IO(140), PORT_DATA_IO(141),
662 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
663 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
664 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
665 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
666
667 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
668 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
669 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
670 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
671 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
672
673 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
674 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
675 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
676 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
677 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
678
679 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
680 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
681 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
682 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
683 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
684
685 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
686 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
687 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
688 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
689 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
690
691 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
692 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
693 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
694 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
695 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
696
697 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
698 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
699 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
700 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
701 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
702
703 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
704
705 /* Port0 */
706 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
707 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
708 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
709 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
710 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
711 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
712 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
713
714 /* Port1 */
715 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
716 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
717 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
718 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
719 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
720 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
721 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
722
723 /* Port2 */
724 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
725 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
726 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
727 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
728 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
729
730 /* Port3 */
731 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
732 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
733 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
734 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
735
736 /* Port4 */
737 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
738 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
739 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
740 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
741
742 /* Port5 */
743 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
744 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
745 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
746 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
747 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
748
749 /* Port6 */
750 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
751 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
752 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
753 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
754 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
755
756 /* Port7 */
757 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
758
759 /* Port8 */
760 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
761
762 /* Port9 */
763 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
764 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
765
766 /* Port10 */
767 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
768 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
769 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
770
771 /* Port11 */
772 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
773 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
774
775 /* Port12 */
776 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
777 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
778 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
779 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
780 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
781
782 /* Port13 */
783 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
784 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
785 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
786 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
787
788 /* Port14 */
789 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
790 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
791 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
792 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
793 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
794
795 /* Port15 */
796 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
797 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
798 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
799 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
800 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
801
802 /* Port16 */
803 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
804 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
805
806 /* Port17 */
807 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
808 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
809
810 /* Port18 */
811 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
812 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
813
814 /* Port19 */
815 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
816 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
817 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
818
819 /* Port20 */
820 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
821 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
822 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
823
824 /* Port21 */
825 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
826 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
827 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
828 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
829 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
830 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
831
832 /* Port22 */
833 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
834 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
835 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
836
837 /* Port23 */
838 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
839 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
840 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
841 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
842 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
843 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
844
845 /* Port24 */
846 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
847 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
848 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
849 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
850
851 /* Port25 */
852 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
853 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
854 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
855 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
856
857 /* Port26 */
858 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
859 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
860 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
861
862 /* Port27 - Port39 Function */
863 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
864 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
865 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
866 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
867 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
868 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
869 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
870 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
871 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
872 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
873 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
874 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
875 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
876
877 /* Port38 IRQ */
878 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
879
880 /* Port40 */
881 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
882 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
883 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
884
885 /* Port41 */
886 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
887 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
888 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
889
890 /* Port42 */
891 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
892 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
893 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
894
895 /* Port43 */
896 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
897 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
898 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
899 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
900
901 /* Port44 */
902 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
903 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
904 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
905 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
906
907 /* Port45 */
908 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
909 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
910 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
911 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
912
913 /* Port46 */
914 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
915 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
916 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
917
918 /* Port47 */
919 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
920 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
921 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
922
923 /* Port48 */
924 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
925 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
926 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
927
928 /* Port49 */
929 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
930 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
931 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
932 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
933
934 /* Port50 */
935 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
936 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
937 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
938 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
939
940 /* Port51 */
941 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
942 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
943 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
944
945 /* Port52 */
946 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
947 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
948 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
949
950 /* Port53 */
951 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
952 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
953 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
954
955 /* Port54 */
956 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
957 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
958 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
959
960 /* Port55 */
961 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
962 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
963 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
964 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
965
966 /* Port56 */
967 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
968 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
969 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
970 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
971 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
972
973 /* Port57 */
974 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
975 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
976 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
977 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
978 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
979
980 /* Port58 */
981 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
982 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
983 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
984 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
985 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
986
987 /* Port59 */
988 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
989 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
990 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
991
992 /* Port60 */
993 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
994 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
995 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
996
997 /* Port61 */
998 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
999 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
1000
1001 /* Port62 */
1002 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
1003 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
1004 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
1005 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
1006
1007 /* Port63 */
1008 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
1009 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
1010 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
1011
1012 /* Port64 */
1013 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
1014 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
1015 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
1016 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
1017
1018 /* Port65 */
1019 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
1020 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
1021 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
1022
1023 /* Port66 */
1024 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
1025 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
1026 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
1027 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
1028
1029 /* Port67 - Port73 Function1 */
1030 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
1031 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
1032 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
1033 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
1034 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
1035 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
1036 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
1037
1038 /* Port67 - Port73 Function2 */
1039 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
1040 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
1041 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
1042 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
1043 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
1044 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
1045 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
1046
1047 /* Port67 - Port73 Function4 */
1048 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
1049 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
1050 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
1051 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
1052 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
1053 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
1054 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
1055
1056 /* Port67 - Port73 Function6 */
1057 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
1058 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
1059 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
1060 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
1061 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
1062 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
1063 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
1064
1065 /* Port67 - Port71 IRQ */
1066 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
1067 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
1068 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
1069 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
1070 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
1071
1072 /* Port74 */
1073 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
1074 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
1075 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
1076 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
1077 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
1078
1079 /* Port75 */
1080 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
1081 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
1082 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
1083 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
1084 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
1085
1086 /* Port76 - Port80 Function */
1087 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
1088 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
1089 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
1090 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
1091 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
1092
1093 /* Port81 */
1094 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
1095 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
1096
1097 /* Port82 - Port88 Function */
1098 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
1099 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
1100 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
1101 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
1102 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
1103 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
1104 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
1105
1106 /* Port89 */
1107 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
1108 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
1109 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
1110
1111 /* Port90 */
1112 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1113 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1114 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1115 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1116
1117 /* Port91 */
1118 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1119 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1120 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1121 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1122
1123 /* Port92 */
1124 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1125 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1126 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1127 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1128 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1129
1130 /* Port93 */
1131 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1132 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1133 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1134 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1135 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1136
1137 /* Port94 */
1138 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1139 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1140 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1141 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1142 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1143
1144 /* Port95 */
1145 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1146 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1147
1148 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1149 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1150 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1151 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1152
1153 /* Port96 */
1154 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1155 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1156
1157 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1158 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1159 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1160 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1161
1162 /* Port97 */
1163 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1164 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1165 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1166 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1167 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1168
1169 /* Port98 */
1170 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1171 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1172 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1173 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1174
1175 /* Port99 */
1176 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1177 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1178 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1179 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1180 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1181
1182 /* Port100 */
1183 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1184 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1185 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1186 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1187
1188 /* Port101 */
1189 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1190
1191 /* Port102 */
1192 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1193 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1194
1195 /* Port103 */
1196 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1197 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1198 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1199
1200 /* Port104 */
1201 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1202 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1203 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1204
1205 /* Port105 */
1206 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1207 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1208
1209 /* Port106 */
1210 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1211 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1212
1213 /* Port107 - Port115 Function */
1214 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1215 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1216 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1217 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1218 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1219 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1220 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1221 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1222 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1223
1224 /* Port116 */
1225 PINMUX_DATA(A25_MARK, PORT116_FN1),
1226 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1227 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1228 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1229 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1230
1231 /* Port117 */
1232 PINMUX_DATA(A24_MARK, PORT117_FN1),
1233 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1234 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1235 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1236 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1237
1238 /* Port118 */
1239 PINMUX_DATA(A23_MARK, PORT118_FN1),
1240 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1241 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1242 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1243 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1244
1245 /* Port119 */
1246 PINMUX_DATA(A22_MARK, PORT119_FN1),
1247 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1248 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1249 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1250 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1251
1252 /* Port120 */
1253 PINMUX_DATA(A21_MARK, PORT120_FN1),
1254 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1255 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1256 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0),
1257
1258 /* Port121 */
1259 PINMUX_DATA(A20_MARK, PORT121_FN1),
1260 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1261 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1262 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1263
1264 /* Port122 */
1265 PINMUX_DATA(A19_MARK, PORT122_FN1),
1266 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1267
1268 /* Port123 */
1269 PINMUX_DATA(A18_MARK, PORT123_FN1),
1270 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1271
1272 /* Port124 */
1273 PINMUX_DATA(A17_MARK, PORT124_FN1),
1274 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1275
1276 /* Port125 - Port141 Function */
1277 PINMUX_DATA(A16_MARK, PORT125_FN1),
1278 PINMUX_DATA(A15_MARK, PORT126_FN1),
1279 PINMUX_DATA(A14_MARK, PORT127_FN1),
1280 PINMUX_DATA(A13_MARK, PORT128_FN1),
1281 PINMUX_DATA(A12_MARK, PORT129_FN1),
1282 PINMUX_DATA(A11_MARK, PORT130_FN1),
1283 PINMUX_DATA(A10_MARK, PORT131_FN1),
1284 PINMUX_DATA(A9_MARK, PORT132_FN1),
1285 PINMUX_DATA(A8_MARK, PORT133_FN1),
1286 PINMUX_DATA(A7_MARK, PORT134_FN1),
1287 PINMUX_DATA(A6_MARK, PORT135_FN1),
1288 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1289 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1290 PINMUX_DATA(A3_MARK, PORT138_FN1),
1291 PINMUX_DATA(A2_MARK, PORT139_FN1),
1292 PINMUX_DATA(A1_MARK, PORT140_FN1),
1293 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1294
1295 /* Port142 - Port157 Function1 */
1296 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1297 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1298 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1299 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1300 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1301 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1302 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1303 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1304 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1305 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1306 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1307 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1308 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1309 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1310 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1311 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1312
1313 /* Port142 - Port149 Function3 */
1314 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1315 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1316 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1317 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1318 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1319 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1320 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1321 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1322
1323 /* Port158 */
1324 PINMUX_DATA(D31_MARK, PORT158_FN1),
1325 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1326 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1327 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1328 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1329 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1330
1331 /* Port159 */
1332 PINMUX_DATA(D30_MARK, PORT159_FN1),
1333 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1334 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1335 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1336 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1337
1338 /* Port160 */
1339 PINMUX_DATA(D29_MARK, PORT160_FN1),
1340 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1341 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1342 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1343 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1344
1345 /* Port161 */
1346 PINMUX_DATA(D28_MARK, PORT161_FN1),
1347 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1348 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1349 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1350 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1351 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1352
1353 /* Port162 */
1354 PINMUX_DATA(D27_MARK, PORT162_FN1),
1355 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1356 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1357 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1358 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1359
1360 /* Port163 */
1361 PINMUX_DATA(D26_MARK, PORT163_FN1),
1362 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1363 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1364 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1365 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1366 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1367
1368 /* Port164 */
1369 PINMUX_DATA(D25_MARK, PORT164_FN1),
1370 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1371 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1372 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1373 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1374
1375 /* Port165 */
1376 PINMUX_DATA(D24_MARK, PORT165_FN1),
1377 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1378 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1379 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1380
1381 /* Port166 - Port171 Function1 */
1382 PINMUX_DATA(D21_MARK, PORT166_FN1),
1383 PINMUX_DATA(D20_MARK, PORT167_FN1),
1384 PINMUX_DATA(D19_MARK, PORT168_FN1),
1385 PINMUX_DATA(D18_MARK, PORT169_FN1),
1386 PINMUX_DATA(D17_MARK, PORT170_FN1),
1387 PINMUX_DATA(D16_MARK, PORT171_FN1),
1388
1389 /* Port166 - Port171 Function3 */
1390 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1391 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1392 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1393 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1394 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1395 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1396
1397 /* Port166 - Port171 Function6 */
1398 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1399 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1400 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1401 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1402 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1403 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1404
1405 /* Port167 - Port171 IRQ */
1406 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1407 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1408 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1409 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1410 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1411
1412 /* Port172 */
1413 PINMUX_DATA(D23_MARK, PORT172_FN1),
1414 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1415 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1416 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1417 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1418
1419 /* Port173 */
1420 PINMUX_DATA(D22_MARK, PORT173_FN1),
1421 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1422 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1423 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1424 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1425
1426 /* Port174 */
1427 PINMUX_DATA(A26_MARK, PORT174_FN1),
1428 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1429 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1430 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1431
1432 /* Port175 */
1433 PINMUX_DATA(A0_MARK, PORT175_FN1),
1434 PINMUX_DATA(BS_MARK, PORT175_FN2),
1435 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1436 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1437
1438 /* Port176 */
1439 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1440
1441 /* Port177 */
1442 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1443 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1444 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1445 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1446
1447 /* Port178 */
1448 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1449 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1450 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1451
1452 /* Port179 */
1453 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1454 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1455 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1456
1457 /* Port180 */
1458 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1459 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1460 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1461 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1462 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1463
1464 /* Port181 */
1465 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1466 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1467 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1468
1469 /* Port182 */
1470 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1471 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1472 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1473
1474 /* Port183 */
1475 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1476 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1477 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1478
1479 /* Port184 */
1480 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1481 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1482 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1483
1484 /* Port185 - Port192 Function1 */
1485 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1486 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1487 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1488 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1489 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1490 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1491 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1492
1493 /* Port185 - Port192 Function3 */
1494 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1495 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1496 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1497 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1498 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1499 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1500 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1501 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1502
1503 /* Port185 - Port192 Function6 */
1504 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1505 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1506 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1507 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1508 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1509 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1510 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1511 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1512
1513 /* Port193 */
1514 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1515 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1516 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1517 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1518
1519 /* Port194 */
1520 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1521 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1522 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1523 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1524
1525 /* Port195 */
1526 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1527 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1528 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1529 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1530
1531 /* Port196 */
1532 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1533 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1534 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1535 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1536
1537 /* Port197 */
1538 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1539 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1540 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1541 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1542
1543 /* Port198 */
1544 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1545 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1546 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1547 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1548
1549 /* Port199 */
1550 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1551 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1552 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1553 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1554 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1555 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1556
1557 /* Port200 */
1558 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1559 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1560 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1561 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1562 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1563
1564 /* Port201 */
1565 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1566 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1567
1568 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1569 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1570 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1571 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1572
1573 /* Port202 */
1574 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1575 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1576
1577 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1578 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1579 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1580 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1581 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1582 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1583
1584 /* Port203 - Port208 Function1 */
1585 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1586 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1587 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1588 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1589 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1590 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1591
1592 /* Port203 - Port208 Function3 */
1593 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1594 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1595 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1596 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1597 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1598 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1599
1600 /* Port203 - Port208 Function6 */
1601 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1602 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1603 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1604 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1605 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1606 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1607
1608 /* Port203 - Port208 Function7 */
1609 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1610 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1611 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1612 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1613 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1614 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1615
1616 /* Port209 */
1617 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1618 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
1619
1620 /* Port210 */
1621 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1622
1623 /* Port211 */
1624 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1625
1626 /* LCDC select */
1627 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
1628 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
1629
1630 /* SDENC */
1631 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1632 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1633
1634 /* SYSC */
1635 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1636 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1637
1638 /* DEBUG */
1639 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1640 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1641
1642 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1643 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1644 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1645};
1646
1647static struct pinmux_gpio pinmux_gpios[] = {
1648
1649 /* PORT */
1650 GPIO_PORT_ALL(),
1651
1652 /* IRQ */
1653 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
1654 GPIO_FN(IRQ1),
1655 GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
1656 GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
1657 GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
1658 GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
1659 GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
1660 GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
1661 GPIO_FN(IRQ8),
1662 GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
1663 GPIO_FN(IRQ10),
1664 GPIO_FN(IRQ11),
1665 GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
1666 GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
1667 GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
1668 GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
1669 GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
1670 GPIO_FN(IRQ17),
1671 GPIO_FN(IRQ18),
1672 GPIO_FN(IRQ19),
1673 GPIO_FN(IRQ20),
1674 GPIO_FN(IRQ21),
1675 GPIO_FN(IRQ22),
1676 GPIO_FN(IRQ23),
1677 GPIO_FN(IRQ24),
1678 GPIO_FN(IRQ25),
1679 GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
1680 GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
1681 GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
1682 GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
1683 GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
1684 GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
1685
1686 /* Function */
1687
1688 /* DBGT */
1689 GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
1690 GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
1691 GPIO_FN(DBGMD21),
1692
1693 /* FSI */
1694 GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
1695 GPIO_FN(FSIAISLD_PORT5),
1696 GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
1697 GPIO_FN(FSIASPDIF_PORT18),
1698 GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
1699 GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
1700 GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
1701
1702 /* FMSI */
1703 GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
1704 GPIO_FN(FMSISLD_PORT6),
1705 GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
1706 GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
1707 GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
1708 GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
1709
1710 /* SCIFA0 */
1711 GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
1712 GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
1713
1714 /* SCIFA1 */
1715 GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
1716 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
1717
1718 /* SCIFA2 */
1719 GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
1720 GPIO_FN(SCIFA2_SCK_PORT199),
1721 GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
1722 GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
1723
1724 /* SCIFA3 */
1725 GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
1726 GPIO_FN(SCIFA3_SCK_PORT116),
1727 GPIO_FN(SCIFA3_CTS_PORT117),
1728 GPIO_FN(SCIFA3_RXD_PORT174),
1729 GPIO_FN(SCIFA3_TXD_PORT175),
1730
1731 GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
1732 GPIO_FN(SCIFA3_SCK_PORT158),
1733 GPIO_FN(SCIFA3_CTS_PORT162),
1734 GPIO_FN(SCIFA3_RXD_PORT159),
1735 GPIO_FN(SCIFA3_TXD_PORT160),
1736
1737 /* SCIFA4 */
1738 GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
1739 GPIO_FN(SCIFA4_TXD_PORT13),
1740
1741 GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
1742 GPIO_FN(SCIFA4_TXD_PORT203),
1743
1744 GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
1745 GPIO_FN(SCIFA4_TXD_PORT93),
1746
1747 GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
1748 GPIO_FN(SCIFA4_SCK_PORT205),
1749
1750 /* SCIFA5 */
1751 GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
1752 GPIO_FN(SCIFA5_RXD_PORT10),
1753
1754 GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
1755 GPIO_FN(SCIFA5_TXD_PORT208),
1756
1757 GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
1758 GPIO_FN(SCIFA5_RXD_PORT92),
1759
1760 GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
1761 GPIO_FN(SCIFA5_SCK_PORT206),
1762
1763 /* SCIFA6 */
1764 GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
1765
1766 /* SCIFA7 */
1767 GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
1768
1769 /* SCIFAB */
1770 GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
1771 GPIO_FN(SCIFB_RXD_PORT191),
1772 GPIO_FN(SCIFB_TXD_PORT192),
1773 GPIO_FN(SCIFB_RTS_PORT186),
1774 GPIO_FN(SCIFB_CTS_PORT187),
1775
1776 GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
1777 GPIO_FN(SCIFB_RXD_PORT3),
1778 GPIO_FN(SCIFB_TXD_PORT4),
1779 GPIO_FN(SCIFB_RTS_PORT172),
1780 GPIO_FN(SCIFB_CTS_PORT173),
1781
1782 /* LCD0 */
1783 GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
1784 GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
1785 GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
1786 GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
1787 GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
1788 GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
1789 GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
1790 GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
1791 GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
1792 GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
1793 GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
1794
1795 GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
1796 GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
1797 GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
1798 GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
1799
1800 GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
1801 GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
1802 GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
1803 GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
1804
1805 /* LCD1 */
1806 GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
1807 GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
1808 GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
1809 GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
1810 GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
1811 GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
1812 GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
1813 GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
1814 GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
1815 GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
1816 GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
1817 GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
1818
1819 /* RSPI */
1820 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
1821 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
1822 GPIO_FN(RSPI_MISO_A),
1823
1824 /* VIO CKO */
1825 GPIO_FN(VIO_CKO1),
1826 GPIO_FN(VIO_CKO2),
1827 GPIO_FN(VIO_CKO_1),
1828 GPIO_FN(VIO_CKO),
1829
1830 /* VIO0 */
1831 GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
1832 GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
1833 GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
1834 GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
1835 GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
1836 GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
1837
1838 GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
1839 GPIO_FN(VIO0_D14_PORT25),
1840 GPIO_FN(VIO0_D15_PORT24),
1841
1842 GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
1843 GPIO_FN(VIO0_D14_PORT95),
1844 GPIO_FN(VIO0_D15_PORT96),
1845
1846 /* VIO1 */
1847 GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
1848 GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
1849 GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
1850 GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
1851
1852 /* TPU0 */
1853 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
1854 GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
1855 GPIO_FN(TPU0TO2_PORT202),
1856
1857 /* SSP1 0 */
1858 GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
1859 GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
1860 GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
1861 GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
1862
1863 /* SSP1 1 */
1864 GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
1865 GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
1866 GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
1867
1868 GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
1869 GPIO_FN(STP1_IPEN_PORT187),
1870
1871 GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
1872 GPIO_FN(STP1_IPEN_PORT193),
1873
1874 /* SIM */
1875 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
1876 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
1877 GPIO_FN(SIM_D_PORT199),
1878
1879 /* SDHI0 */
1880 GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
1881 GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
1882 GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
1883
1884 /* SDHI1 */
1885 GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
1886 GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
1887 GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
1888
1889 /* SDHI2 */
1890 GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
1891 GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
1892
1893 GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
1894 GPIO_FN(SDHI2_WP_PORT25),
1895
1896 GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
1897 GPIO_FN(SDHI2_CD_PORT202),
1898
1899 /* MSIOF2 */
1900 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
1901 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
1902 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
1903 GPIO_FN(MSIOF2_RSCK),
1904
1905 /* KEYSC */
1906 GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
1907 GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
1908 GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
1909 GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
1910 GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
1911
1912 GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
1913 GPIO_FN(KEYIN1_PORT44),
1914 GPIO_FN(KEYIN2_PORT45),
1915 GPIO_FN(KEYIN3_PORT46),
1916
1917 GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
1918 GPIO_FN(KEYIN1_PORT57),
1919 GPIO_FN(KEYIN2_PORT56),
1920 GPIO_FN(KEYIN3_PORT55),
1921
1922 /* VOU */
1923 GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
1924 GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
1925 GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
1926 GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
1927 GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
1928 GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
1929 GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
1930
1931 /* MEMC */
1932 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
1933 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
1934 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
1935 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
1936 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
1937 GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
1938 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
1939 GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
1940 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
1941 GPIO_FN(MEMC_A0),
1942
1943 /* MMC */
1944 GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
1945 GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
1946 GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
1947 GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
1948 GPIO_FN(MMC0_CLK_PORT66),
1949 GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
1950
1951 GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
1952 GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
1953 GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
1954 GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
1955 GPIO_FN(MMC1_CLK_PORT103),
1956 GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
1957
1958 /* MSIOF0 */
1959 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
1960 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
1961 GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
1962 GPIO_FN(MSIOF0_TSYNC),
1963
1964 /* MSIOF1 */
1965 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
1966 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1967
1968 GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
1969 GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
1970 GPIO_FN(MSIOF1_TSYNC_PORT120),
1971 GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
1972
1973 GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
1974 GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
1975 GPIO_FN(MSIOF1_RXD_PORT75),
1976 GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
1977
1978 /* GPIO */
1979 GPIO_FN(GPO0), GPIO_FN(GPI0),
1980 GPIO_FN(GPO1), GPIO_FN(GPI1),
1981
1982 /* USB0 */
1983 GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
1984
1985 /* USB1 */
1986 GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
1987
1988 /* BBIF1 */
1989 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
1990 GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
1991 GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
1992
1993 /* BBIF2 */
1994 GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
1995 GPIO_FN(BBIF2_RXD2_PORT60),
1996 GPIO_FN(BBIF2_TSYNC2_PORT6),
1997 GPIO_FN(BBIF2_TSCK2_PORT59),
1998
1999 GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
2000 GPIO_FN(BBIF2_TXD2_PORT183),
2001 GPIO_FN(BBIF2_TSCK2_PORT89),
2002 GPIO_FN(BBIF2_TSYNC2_PORT184),
2003
2004 /* BSC / FLCTL / PCMCIA */
2005 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
2006 GPIO_FN(CS5B), GPIO_FN(CS6A),
2007 GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
2008 GPIO_FN(CS5A_PORT19),
2009 GPIO_FN(IOIS16), /* ? */
2010
2011 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
2012 GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
2013 GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
2014 GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
2015 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
2016 GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
2017 GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
2018 GPIO_FN(A26),
2019
2020 GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
2021 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
2022 GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
2023 GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
2024 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
2025 GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
2026 GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
2027 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
2028 GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
2029 GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
2030 GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
2031 GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
2032
2033 GPIO_FN(WE0_FWE), /* share with FLCTL */
2034 GPIO_FN(WE1),
2035 GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
2036 GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
2037 GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
2038 GPIO_FN(RD_FSC), /* share with FLCTL */
2039 GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
2040 GPIO_FN(WAIT_PORT90),
2041
2042 GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
2043
2044 /* IRDA */
2045 GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
2046
2047 /* ATAPI */
2048 GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
2049 GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
2050 GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
2051 GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
2052 GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
2053 GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
2054 GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
2055 GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
2056 GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
2057 GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
2058
2059 /* RMII */
2060 GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
2061 GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
2062 GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
2063 GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
2064
2065 /* GEther */
2066 GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
2067 GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
2068 GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
2069 GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
2070 GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
2071 GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
2072 GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
2073 GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
2074 GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
2075 GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
2076 GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
2077 GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
2078
2079 /* DMA0 */
2080 GPIO_FN(DREQ0), GPIO_FN(DACK0),
2081
2082 /* DMA1 */
2083 GPIO_FN(DREQ1), GPIO_FN(DACK1),
2084
2085 /* SYSC */
2086 GPIO_FN(RESETOUTS),
2087
2088 /* IRREM */
2089 GPIO_FN(IROUT),
2090
2091 /* LCDC */
2092 GPIO_FN(LCDC0_SELECT),
2093 GPIO_FN(LCDC1_SELECT),
2094
2095 /* SDENC */
2096 GPIO_FN(SDENC_CPG),
2097 GPIO_FN(SDENC_DV_CLKI),
2098
2099 /* SYSC */
2100 GPIO_FN(RESETP_PULLUP),
2101 GPIO_FN(RESETP_PLAIN),
2102
2103 /* DEBUG */
2104 GPIO_FN(EDEBGREQ_PULLDOWN),
2105 GPIO_FN(EDEBGREQ_PULLUP),
2106
2107 GPIO_FN(TRACEAUD_FROM_VIO),
2108 GPIO_FN(TRACEAUD_FROM_LCDC0),
2109 GPIO_FN(TRACEAUD_FROM_MEMC),
2110};
2111
2112static struct pinmux_cfg_reg pinmux_config_regs[] = {
2113 PORTCR(0, 0xe6050000), /* PORT0CR */
2114 PORTCR(1, 0xe6050001), /* PORT1CR */
2115 PORTCR(2, 0xe6050002), /* PORT2CR */
2116 PORTCR(3, 0xe6050003), /* PORT3CR */
2117 PORTCR(4, 0xe6050004), /* PORT4CR */
2118 PORTCR(5, 0xe6050005), /* PORT5CR */
2119 PORTCR(6, 0xe6050006), /* PORT6CR */
2120 PORTCR(7, 0xe6050007), /* PORT7CR */
2121 PORTCR(8, 0xe6050008), /* PORT8CR */
2122 PORTCR(9, 0xe6050009), /* PORT9CR */
2123 PORTCR(10, 0xe605000a), /* PORT10CR */
2124 PORTCR(11, 0xe605000b), /* PORT11CR */
2125 PORTCR(12, 0xe605000c), /* PORT12CR */
2126 PORTCR(13, 0xe605000d), /* PORT13CR */
2127 PORTCR(14, 0xe605000e), /* PORT14CR */
2128 PORTCR(15, 0xe605000f), /* PORT15CR */
2129 PORTCR(16, 0xe6050010), /* PORT16CR */
2130 PORTCR(17, 0xe6050011), /* PORT17CR */
2131 PORTCR(18, 0xe6050012), /* PORT18CR */
2132 PORTCR(19, 0xe6050013), /* PORT19CR */
2133 PORTCR(20, 0xe6050014), /* PORT20CR */
2134 PORTCR(21, 0xe6050015), /* PORT21CR */
2135 PORTCR(22, 0xe6050016), /* PORT22CR */
2136 PORTCR(23, 0xe6050017), /* PORT23CR */
2137 PORTCR(24, 0xe6050018), /* PORT24CR */
2138 PORTCR(25, 0xe6050019), /* PORT25CR */
2139 PORTCR(26, 0xe605001a), /* PORT26CR */
2140 PORTCR(27, 0xe605001b), /* PORT27CR */
2141 PORTCR(28, 0xe605001c), /* PORT28CR */
2142 PORTCR(29, 0xe605001d), /* PORT29CR */
2143 PORTCR(30, 0xe605001e), /* PORT30CR */
2144 PORTCR(31, 0xe605001f), /* PORT31CR */
2145 PORTCR(32, 0xe6050020), /* PORT32CR */
2146 PORTCR(33, 0xe6050021), /* PORT33CR */
2147 PORTCR(34, 0xe6050022), /* PORT34CR */
2148 PORTCR(35, 0xe6050023), /* PORT35CR */
2149 PORTCR(36, 0xe6050024), /* PORT36CR */
2150 PORTCR(37, 0xe6050025), /* PORT37CR */
2151 PORTCR(38, 0xe6050026), /* PORT38CR */
2152 PORTCR(39, 0xe6050027), /* PORT39CR */
2153 PORTCR(40, 0xe6050028), /* PORT40CR */
2154 PORTCR(41, 0xe6050029), /* PORT41CR */
2155 PORTCR(42, 0xe605002a), /* PORT42CR */
2156 PORTCR(43, 0xe605002b), /* PORT43CR */
2157 PORTCR(44, 0xe605002c), /* PORT44CR */
2158 PORTCR(45, 0xe605002d), /* PORT45CR */
2159 PORTCR(46, 0xe605002e), /* PORT46CR */
2160 PORTCR(47, 0xe605002f), /* PORT47CR */
2161 PORTCR(48, 0xe6050030), /* PORT48CR */
2162 PORTCR(49, 0xe6050031), /* PORT49CR */
2163 PORTCR(50, 0xe6050032), /* PORT50CR */
2164 PORTCR(51, 0xe6050033), /* PORT51CR */
2165 PORTCR(52, 0xe6050034), /* PORT52CR */
2166 PORTCR(53, 0xe6050035), /* PORT53CR */
2167 PORTCR(54, 0xe6050036), /* PORT54CR */
2168 PORTCR(55, 0xe6050037), /* PORT55CR */
2169 PORTCR(56, 0xe6050038), /* PORT56CR */
2170 PORTCR(57, 0xe6050039), /* PORT57CR */
2171 PORTCR(58, 0xe605003a), /* PORT58CR */
2172 PORTCR(59, 0xe605003b), /* PORT59CR */
2173 PORTCR(60, 0xe605003c), /* PORT60CR */
2174 PORTCR(61, 0xe605003d), /* PORT61CR */
2175 PORTCR(62, 0xe605003e), /* PORT62CR */
2176 PORTCR(63, 0xe605003f), /* PORT63CR */
2177 PORTCR(64, 0xe6050040), /* PORT64CR */
2178 PORTCR(65, 0xe6050041), /* PORT65CR */
2179 PORTCR(66, 0xe6050042), /* PORT66CR */
2180 PORTCR(67, 0xe6050043), /* PORT67CR */
2181 PORTCR(68, 0xe6050044), /* PORT68CR */
2182 PORTCR(69, 0xe6050045), /* PORT69CR */
2183 PORTCR(70, 0xe6050046), /* PORT70CR */
2184 PORTCR(71, 0xe6050047), /* PORT71CR */
2185 PORTCR(72, 0xe6050048), /* PORT72CR */
2186 PORTCR(73, 0xe6050049), /* PORT73CR */
2187 PORTCR(74, 0xe605004a), /* PORT74CR */
2188 PORTCR(75, 0xe605004b), /* PORT75CR */
2189 PORTCR(76, 0xe605004c), /* PORT76CR */
2190 PORTCR(77, 0xe605004d), /* PORT77CR */
2191 PORTCR(78, 0xe605004e), /* PORT78CR */
2192 PORTCR(79, 0xe605004f), /* PORT79CR */
2193 PORTCR(80, 0xe6050050), /* PORT80CR */
2194 PORTCR(81, 0xe6050051), /* PORT81CR */
2195 PORTCR(82, 0xe6050052), /* PORT82CR */
2196 PORTCR(83, 0xe6050053), /* PORT83CR */
2197
2198 PORTCR(84, 0xe6051054), /* PORT84CR */
2199 PORTCR(85, 0xe6051055), /* PORT85CR */
2200 PORTCR(86, 0xe6051056), /* PORT86CR */
2201 PORTCR(87, 0xe6051057), /* PORT87CR */
2202 PORTCR(88, 0xe6051058), /* PORT88CR */
2203 PORTCR(89, 0xe6051059), /* PORT89CR */
2204 PORTCR(90, 0xe605105a), /* PORT90CR */
2205 PORTCR(91, 0xe605105b), /* PORT91CR */
2206 PORTCR(92, 0xe605105c), /* PORT92CR */
2207 PORTCR(93, 0xe605105d), /* PORT93CR */
2208 PORTCR(94, 0xe605105e), /* PORT94CR */
2209 PORTCR(95, 0xe605105f), /* PORT95CR */
2210 PORTCR(96, 0xe6051060), /* PORT96CR */
2211 PORTCR(97, 0xe6051061), /* PORT97CR */
2212 PORTCR(98, 0xe6051062), /* PORT98CR */
2213 PORTCR(99, 0xe6051063), /* PORT99CR */
2214 PORTCR(100, 0xe6051064), /* PORT100CR */
2215 PORTCR(101, 0xe6051065), /* PORT101CR */
2216 PORTCR(102, 0xe6051066), /* PORT102CR */
2217 PORTCR(103, 0xe6051067), /* PORT103CR */
2218 PORTCR(104, 0xe6051068), /* PORT104CR */
2219 PORTCR(105, 0xe6051069), /* PORT105CR */
2220 PORTCR(106, 0xe605106a), /* PORT106CR */
2221 PORTCR(107, 0xe605106b), /* PORT107CR */
2222 PORTCR(108, 0xe605106c), /* PORT108CR */
2223 PORTCR(109, 0xe605106d), /* PORT109CR */
2224 PORTCR(110, 0xe605106e), /* PORT110CR */
2225 PORTCR(111, 0xe605106f), /* PORT111CR */
2226 PORTCR(112, 0xe6051070), /* PORT112CR */
2227 PORTCR(113, 0xe6051071), /* PORT113CR */
2228 PORTCR(114, 0xe6051072), /* PORT114CR */
2229
2230 PORTCR(115, 0xe6052073), /* PORT115CR */
2231 PORTCR(116, 0xe6052074), /* PORT116CR */
2232 PORTCR(117, 0xe6052075), /* PORT117CR */
2233 PORTCR(118, 0xe6052076), /* PORT118CR */
2234 PORTCR(119, 0xe6052077), /* PORT119CR */
2235 PORTCR(120, 0xe6052078), /* PORT120CR */
2236 PORTCR(121, 0xe6052079), /* PORT121CR */
2237 PORTCR(122, 0xe605207a), /* PORT122CR */
2238 PORTCR(123, 0xe605207b), /* PORT123CR */
2239 PORTCR(124, 0xe605207c), /* PORT124CR */
2240 PORTCR(125, 0xe605207d), /* PORT125CR */
2241 PORTCR(126, 0xe605207e), /* PORT126CR */
2242 PORTCR(127, 0xe605207f), /* PORT127CR */
2243 PORTCR(128, 0xe6052080), /* PORT128CR */
2244 PORTCR(129, 0xe6052081), /* PORT129CR */
2245 PORTCR(130, 0xe6052082), /* PORT130CR */
2246 PORTCR(131, 0xe6052083), /* PORT131CR */
2247 PORTCR(132, 0xe6052084), /* PORT132CR */
2248 PORTCR(133, 0xe6052085), /* PORT133CR */
2249 PORTCR(134, 0xe6052086), /* PORT134CR */
2250 PORTCR(135, 0xe6052087), /* PORT135CR */
2251 PORTCR(136, 0xe6052088), /* PORT136CR */
2252 PORTCR(137, 0xe6052089), /* PORT137CR */
2253 PORTCR(138, 0xe605208a), /* PORT138CR */
2254 PORTCR(139, 0xe605208b), /* PORT139CR */
2255 PORTCR(140, 0xe605208c), /* PORT140CR */
2256 PORTCR(141, 0xe605208d), /* PORT141CR */
2257 PORTCR(142, 0xe605208e), /* PORT142CR */
2258 PORTCR(143, 0xe605208f), /* PORT143CR */
2259 PORTCR(144, 0xe6052090), /* PORT144CR */
2260 PORTCR(145, 0xe6052091), /* PORT145CR */
2261 PORTCR(146, 0xe6052092), /* PORT146CR */
2262 PORTCR(147, 0xe6052093), /* PORT147CR */
2263 PORTCR(148, 0xe6052094), /* PORT148CR */
2264 PORTCR(149, 0xe6052095), /* PORT149CR */
2265 PORTCR(150, 0xe6052096), /* PORT150CR */
2266 PORTCR(151, 0xe6052097), /* PORT151CR */
2267 PORTCR(152, 0xe6052098), /* PORT152CR */
2268 PORTCR(153, 0xe6052099), /* PORT153CR */
2269 PORTCR(154, 0xe605209a), /* PORT154CR */
2270 PORTCR(155, 0xe605209b), /* PORT155CR */
2271 PORTCR(156, 0xe605209c), /* PORT156CR */
2272 PORTCR(157, 0xe605209d), /* PORT157CR */
2273 PORTCR(158, 0xe605209e), /* PORT158CR */
2274 PORTCR(159, 0xe605209f), /* PORT159CR */
2275 PORTCR(160, 0xe60520a0), /* PORT160CR */
2276 PORTCR(161, 0xe60520a1), /* PORT161CR */
2277 PORTCR(162, 0xe60520a2), /* PORT162CR */
2278 PORTCR(163, 0xe60520a3), /* PORT163CR */
2279 PORTCR(164, 0xe60520a4), /* PORT164CR */
2280 PORTCR(165, 0xe60520a5), /* PORT165CR */
2281 PORTCR(166, 0xe60520a6), /* PORT166CR */
2282 PORTCR(167, 0xe60520a7), /* PORT167CR */
2283 PORTCR(168, 0xe60520a8), /* PORT168CR */
2284 PORTCR(169, 0xe60520a9), /* PORT169CR */
2285 PORTCR(170, 0xe60520aa), /* PORT170CR */
2286 PORTCR(171, 0xe60520ab), /* PORT171CR */
2287 PORTCR(172, 0xe60520ac), /* PORT172CR */
2288 PORTCR(173, 0xe60520ad), /* PORT173CR */
2289 PORTCR(174, 0xe60520ae), /* PORT174CR */
2290 PORTCR(175, 0xe60520af), /* PORT175CR */
2291 PORTCR(176, 0xe60520b0), /* PORT176CR */
2292 PORTCR(177, 0xe60520b1), /* PORT177CR */
2293 PORTCR(178, 0xe60520b2), /* PORT178CR */
2294 PORTCR(179, 0xe60520b3), /* PORT179CR */
2295 PORTCR(180, 0xe60520b4), /* PORT180CR */
2296 PORTCR(181, 0xe60520b5), /* PORT181CR */
2297 PORTCR(182, 0xe60520b6), /* PORT182CR */
2298 PORTCR(183, 0xe60520b7), /* PORT183CR */
2299 PORTCR(184, 0xe60520b8), /* PORT184CR */
2300 PORTCR(185, 0xe60520b9), /* PORT185CR */
2301 PORTCR(186, 0xe60520ba), /* PORT186CR */
2302 PORTCR(187, 0xe60520bb), /* PORT187CR */
2303 PORTCR(188, 0xe60520bc), /* PORT188CR */
2304 PORTCR(189, 0xe60520bd), /* PORT189CR */
2305 PORTCR(190, 0xe60520be), /* PORT190CR */
2306 PORTCR(191, 0xe60520bf), /* PORT191CR */
2307 PORTCR(192, 0xe60520c0), /* PORT192CR */
2308 PORTCR(193, 0xe60520c1), /* PORT193CR */
2309 PORTCR(194, 0xe60520c2), /* PORT194CR */
2310 PORTCR(195, 0xe60520c3), /* PORT195CR */
2311 PORTCR(196, 0xe60520c4), /* PORT196CR */
2312 PORTCR(197, 0xe60520c5), /* PORT197CR */
2313 PORTCR(198, 0xe60520c6), /* PORT198CR */
2314 PORTCR(199, 0xe60520c7), /* PORT199CR */
2315 PORTCR(200, 0xe60520c8), /* PORT200CR */
2316 PORTCR(201, 0xe60520c9), /* PORT201CR */
2317 PORTCR(202, 0xe60520ca), /* PORT202CR */
2318 PORTCR(203, 0xe60520cb), /* PORT203CR */
2319 PORTCR(204, 0xe60520cc), /* PORT204CR */
2320 PORTCR(205, 0xe60520cd), /* PORT205CR */
2321 PORTCR(206, 0xe60520ce), /* PORT206CR */
2322 PORTCR(207, 0xe60520cf), /* PORT207CR */
2323 PORTCR(208, 0xe60520d0), /* PORT208CR */
2324 PORTCR(209, 0xe60520d1), /* PORT209CR */
2325
2326 PORTCR(210, 0xe60530d2), /* PORT210CR */
2327 PORTCR(211, 0xe60530d3), /* PORT211CR */
2328
2329 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2330 MSEL1CR_31_0, MSEL1CR_31_1,
2331 MSEL1CR_30_0, MSEL1CR_30_1,
2332 MSEL1CR_29_0, MSEL1CR_29_1,
2333 MSEL1CR_28_0, MSEL1CR_28_1,
2334 MSEL1CR_27_0, MSEL1CR_27_1,
2335 MSEL1CR_26_0, MSEL1CR_26_1,
2336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2337 0, 0, 0, 0, 0, 0, 0, 0,
2338 MSEL1CR_16_0, MSEL1CR_16_1,
2339 MSEL1CR_15_0, MSEL1CR_15_1,
2340 MSEL1CR_14_0, MSEL1CR_14_1,
2341 MSEL1CR_13_0, MSEL1CR_13_1,
2342 MSEL1CR_12_0, MSEL1CR_12_1,
2343 0, 0, 0, 0,
2344 MSEL1CR_9_0, MSEL1CR_9_1,
2345 0, 0,
2346 MSEL1CR_7_0, MSEL1CR_7_1,
2347 MSEL1CR_6_0, MSEL1CR_6_1,
2348 MSEL1CR_5_0, MSEL1CR_5_1,
2349 MSEL1CR_4_0, MSEL1CR_4_1,
2350 MSEL1CR_3_0, MSEL1CR_3_1,
2351 MSEL1CR_2_0, MSEL1CR_2_1,
2352 0, 0,
2353 MSEL1CR_0_0, MSEL1CR_0_1,
2354 }
2355 },
2356 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2357 0, 0, 0, 0, 0, 0, 0, 0,
2358 0, 0, 0, 0, 0, 0, 0, 0,
2359 0, 0, 0, 0, 0, 0, 0, 0,
2360 0, 0, 0, 0, 0, 0, 0, 0,
2361 MSEL3CR_15_0, MSEL3CR_15_1,
2362 0, 0, 0, 0, 0, 0, 0, 0,
2363 0, 0, 0, 0, 0, 0, 0, 0,
2364 MSEL3CR_6_0, MSEL3CR_6_1,
2365 0, 0, 0, 0, 0, 0, 0, 0,
2366 0, 0, 0, 0,
2367 }
2368 },
2369 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2370 0, 0, 0, 0, 0, 0, 0, 0,
2371 0, 0, 0, 0, 0, 0, 0, 0,
2372 0, 0, 0, 0, 0, 0, 0, 0,
2373 MSEL4CR_19_0, MSEL4CR_19_1,
2374 MSEL4CR_18_0, MSEL4CR_18_1,
2375 0, 0, 0, 0,
2376 MSEL4CR_15_0, MSEL4CR_15_1,
2377 0, 0, 0, 0, 0, 0, 0, 0,
2378 MSEL4CR_10_0, MSEL4CR_10_1,
2379 0, 0, 0, 0, 0, 0,
2380 MSEL4CR_6_0, MSEL4CR_6_1,
2381 0, 0,
2382 MSEL4CR_4_0, MSEL4CR_4_1,
2383 0, 0, 0, 0,
2384 MSEL4CR_1_0, MSEL4CR_1_1,
2385 0, 0,
2386 }
2387 },
2388 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
2389 MSEL5CR_31_0, MSEL5CR_31_1,
2390 MSEL5CR_30_0, MSEL5CR_30_1,
2391 MSEL5CR_29_0, MSEL5CR_29_1,
2392 0, 0,
2393 MSEL5CR_27_0, MSEL5CR_27_1,
2394 0, 0,
2395 MSEL5CR_25_0, MSEL5CR_25_1,
2396 0, 0,
2397 MSEL5CR_23_0, MSEL5CR_23_1,
2398 0, 0,
2399 MSEL5CR_21_0, MSEL5CR_21_1,
2400 0, 0,
2401 MSEL5CR_19_0, MSEL5CR_19_1,
2402 0, 0,
2403 MSEL5CR_17_0, MSEL5CR_17_1,
2404 0, 0,
2405 MSEL5CR_15_0, MSEL5CR_15_1,
2406 MSEL5CR_14_0, MSEL5CR_14_1,
2407 MSEL5CR_13_0, MSEL5CR_13_1,
2408 MSEL5CR_12_0, MSEL5CR_12_1,
2409 MSEL5CR_11_0, MSEL5CR_11_1,
2410 MSEL5CR_10_0, MSEL5CR_10_1,
2411 0, 0,
2412 MSEL5CR_8_0, MSEL5CR_8_1,
2413 MSEL5CR_7_0, MSEL5CR_7_1,
2414 MSEL5CR_6_0, MSEL5CR_6_1,
2415 MSEL5CR_5_0, MSEL5CR_5_1,
2416 MSEL5CR_4_0, MSEL5CR_4_1,
2417 MSEL5CR_3_0, MSEL5CR_3_1,
2418 MSEL5CR_2_0, MSEL5CR_2_1,
2419 0, 0,
2420 MSEL5CR_0_0, MSEL5CR_0_1,
2421 }
2422 },
2423 { },
2424};
2425
2426static struct pinmux_data_reg pinmux_data_regs[] = {
2427 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
2428 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2429 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2430 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2431 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2432 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2433 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2434 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2435 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
2436 },
2437 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
2438 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2439 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2440 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2441 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2442 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
2443 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2444 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2445 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
2446 },
2447 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
2448 0, 0, 0, 0,
2449 0, 0, 0, 0,
2450 0, 0, 0, 0,
2451 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2452 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2453 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2454 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2455 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
2456 },
2457 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
2458 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2459 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2460 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2461 0, 0, 0, 0,
2462 0, 0, 0, 0,
2463 0, 0, 0, 0,
2464 0, 0, 0, 0,
2465 0, 0, 0, 0 }
2466 },
2467 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
2468 0, 0, 0, 0,
2469 0, 0, 0, 0,
2470 0, 0, 0, 0,
2471 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2472 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2473 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2474 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2475 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
2476 },
2477 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
2478 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2479 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2480 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2481 PORT115_DATA, 0, 0, 0,
2482 0, 0, 0, 0,
2483 0, 0, 0, 0,
2484 0, 0, 0, 0,
2485 0, 0, 0, 0 }
2486 },
2487 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
2488 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2489 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2490 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2491 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2492 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2493 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2494 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2495 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
2496 },
2497 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
2498 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
2499 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2500 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2501 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2502 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2503 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2504 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2505 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
2506 },
2507 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
2508 0, 0, 0, 0,
2509 0, 0, 0, 0,
2510 0, 0, 0, 0,
2511 0, 0, PORT209_DATA, PORT208_DATA,
2512 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2513 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2514 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2515 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
2516 },
2517 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
2518 0, 0, 0, 0,
2519 0, 0, 0, 0,
2520 0, 0, 0, 0,
2521 PORT211_DATA, PORT210_DATA, 0, 0,
2522 0, 0, 0, 0,
2523 0, 0, 0, 0,
2524 0, 0, 0, 0,
2525 0, 0, 0, 0 }
2526 },
2527 { },
2528};
2529
2530static struct pinmux_info r8a7740_pinmux_info = {
2531 .name = "r8a7740_pfc",
2532 .reserved_id = PINMUX_RESERVED,
2533 .data = { PINMUX_DATA_BEGIN,
2534 PINMUX_DATA_END },
2535 .input = { PINMUX_INPUT_BEGIN,
2536 PINMUX_INPUT_END },
2537 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
2538 PINMUX_INPUT_PULLUP_END },
2539 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
2540 PINMUX_INPUT_PULLDOWN_END },
2541 .output = { PINMUX_OUTPUT_BEGIN,
2542 PINMUX_OUTPUT_END },
2543 .mark = { PINMUX_MARK_BEGIN,
2544 PINMUX_MARK_END },
2545 .function = { PINMUX_FUNCTION_BEGIN,
2546 PINMUX_FUNCTION_END },
2547
2548 .first_gpio = GPIO_PORT0,
2549 .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
2550
2551 .gpios = pinmux_gpios,
2552 .cfg_regs = pinmux_config_regs,
2553 .data_regs = pinmux_data_regs,
2554
2555 .gpio_data = pinmux_data,
2556 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2557};
2558
2559void r8a7740_pinmux_init(void)
2560{
2561 register_pinmux(&r8a7740_pinmux_info);
2562}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
new file mode 100644
index 000000000000..963532f2b2c4
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -0,0 +1,2645 @@
1/*
2 * r8a7779 processor support - PFC hardware block
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/gpio.h>
23#include <linux/ioport.h>
24#include <mach/r8a7779.h>
25
26#define CPU_32_PORT(fn, pfx, sfx) \
27 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
28 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
29 PORT_1(fn, pfx##31, sfx)
30
31#define CPU_32_PORT6(fn, pfx, sfx) \
32 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
33 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
34 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
35 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
36 PORT_1(fn, pfx##8, sfx)
37
38#define CPU_ALL_PORT(fn, pfx, sfx) \
39 CPU_32_PORT(fn, pfx##_0_, sfx), \
40 CPU_32_PORT(fn, pfx##_1_, sfx), \
41 CPU_32_PORT(fn, pfx##_2_, sfx), \
42 CPU_32_PORT(fn, pfx##_3_, sfx), \
43 CPU_32_PORT(fn, pfx##_4_, sfx), \
44 CPU_32_PORT(fn, pfx##_5_, sfx), \
45 CPU_32_PORT6(fn, pfx##_6_, sfx)
46
47#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
48#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
49 GP##pfx##_IN, GP##pfx##_OUT)
50
51#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
52#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
53
54#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
55#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
56#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
57
58
59#define PORT_10_REV(fn, pfx, sfx) \
60 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
61 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
62 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
63 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
64 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
65
66#define CPU_32_PORT_REV(fn, pfx, sfx) \
67 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
68 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
69 PORT_10_REV(fn, pfx, sfx)
70
71#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
72#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
73
74#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
75#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
76 FN_##ipsr, FN_##fn)
77
78enum {
79 PINMUX_RESERVED = 0,
80
81 PINMUX_DATA_BEGIN,
82 GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
83 PINMUX_DATA_END,
84
85 PINMUX_INPUT_BEGIN,
86 GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
87 PINMUX_INPUT_END,
88
89 PINMUX_OUTPUT_BEGIN,
90 GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
91 PINMUX_OUTPUT_END,
92
93 PINMUX_FUNCTION_BEGIN,
94 GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
95
96 /* GPSR0 */
97 FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
98 FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
99 FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
100 FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
101 FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
102 FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
103 FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
104 FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
105
106 /* GPSR1 */
107 FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
108 FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
109 FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
110 FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
111 FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
112 FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
113 FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
114 FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
115
116 /* GPSR2 */
117 FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
118 FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
119 FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
120 FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
121 FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
122 FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
123 FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
124 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
125
126 /* GPSR3 */
127 FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
128 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
129 FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
130 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
131 FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
132 FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
133 FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
134 FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
135
136 /* GPSR4 */
137 FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
138 FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
139 FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
140 FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
141 FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
142 FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
143 FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
144 FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
145
146 /* GPSR5 */
147 FN_A1, FN_A2, FN_A3, FN_A4,
148 FN_A5, FN_A6, FN_A7, FN_A8,
149 FN_A9, FN_A10, FN_A11, FN_A12,
150 FN_A13, FN_A14, FN_A15, FN_A16,
151 FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
152 FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
153 FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
154 FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
155
156 /* GPSR6 */
157 FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
158 FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
159 FN_IP3_20,
160
161 /* IPSR0 */
162 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
163 FN_HRTS1, FN_RX4_C,
164 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
165 FN_CS0, FN_HSPI_CS2_B,
166 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
167 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
168 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
169 FN_CTS0_B,
170 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
171 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
172 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
173 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
174 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
175 FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
176 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
177 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
178 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
179 FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
180 FN_SCIF_CLK, FN_TCLK0_C,
181
182 /* IPSR1 */
183 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
184 FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
185 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
186 FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
187 FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
188 FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
189 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
190 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
191 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
192 FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
193 FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
194 FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
195 FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
196 FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
197 FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
198 FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
199
200 /* IPSR2 */
201 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
202 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
203 FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
204 FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
205 FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
206 FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
207 FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
208 FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
209 FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
210 FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
211 FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
212 FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
213 FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
214 FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
215 FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
216 FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
217 FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
218 FN_DREQ1, FN_SCL2, FN_AUDATA2,
219
220 /* IPSR3 */
221 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
222 FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
223 FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
224 FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
225 FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
226 FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
227 FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
228 FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
229 FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
230 FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
231 FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
232 FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
233 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
234 FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
235 FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
236 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
237 FN_TX2_C, FN_SCL2_C, FN_REMOCON,
238
239 /* IPSR4 */
240 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
241 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
242 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
243 FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
244 FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
245 FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
246 FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
247 FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
248 FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
249 FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
250 FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
251 FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
252 FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
253 FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
254 FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
255 FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
256 FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
257 FN_SCK0_D,
258
259 /* IPSR5 */
260 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
261 FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
262 FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
263 FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
264 FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
265 FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
266 FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
267 FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
268 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
269 FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
270 FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
271 FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
272 FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
273 FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
274 FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
275 FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
276 FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
277 FN_CAN_DEBUGOUT0, FN_MOUT0,
278
279 /* IPSR6 */
280 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
281 FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
282 FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
283 FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
284 FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
285 FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
286 FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
287 FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
288 FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
289 FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
290 FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
291 FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
292 FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
293
294 /* IPSR7 */
295 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
296 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
297 FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
298 FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
299 FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
300 FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
301 FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
302 FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
303 FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
304 FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
305 FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
306 FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
307 FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
308 FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
309
310 /* IPSR8 */
311 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
312 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
313 FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
314 FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
315 FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
316 FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
317 FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
318 FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
319 FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
320 FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
321 FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
322 FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
323 FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
324 FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
325 FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
326 FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
327
328 /* IPSR9 */
329 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
330 FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
331 FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
332 FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
333 FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
334 FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
335 FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
336 FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
337 FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
338 FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
339 FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
340 FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
341 FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
342 FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
343
344 /* IPSR10 */
345 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
346 FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
347 FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
348 FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
349 FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
350 FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
351 FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
352 FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
353 FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
354 FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
355 FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
356 FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
357 FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
358 FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
359 FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
360 FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
361
362 /* IPSR11 */
363 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
364 FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
365 FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
366 FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
367 FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
368 FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
369 FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
370 FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
371 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
372 FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
373 FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
374 FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
375 FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
376 FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
377
378 /* IPSR12 */
379 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
380 FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
381 FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
382 FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
383 FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
384 FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
385 FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
386 FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
387 FN_GPS_MAG, FN_FCE, FN_SCK4_B,
388
389 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
390 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
391 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
392 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
393 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
394 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
395 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
396 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
397 FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
398 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
399 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
400 FN_SEL_VI0_0, FN_SEL_VI0_1,
401 FN_SEL_SD2_0, FN_SEL_SD2_1,
402 FN_SEL_INT3_0, FN_SEL_INT3_1,
403 FN_SEL_INT2_0, FN_SEL_INT2_1,
404 FN_SEL_INT1_0, FN_SEL_INT1_1,
405 FN_SEL_INT0_0, FN_SEL_INT0_1,
406 FN_SEL_IE_0, FN_SEL_IE_1,
407 FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
408 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
409 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
410
411 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
412 FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
413 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
414 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
415 FN_SEL_CAN0_0, FN_SEL_CAN0_1,
416 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
417 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
418 FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
419 FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
420 FN_SEL_ADI_0, FN_SEL_ADI_1,
421 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
422 FN_SEL_SIM_0, FN_SEL_SIM_1,
423 FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
424 FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
425 FN_SEL_I2C3_0, FN_SEL_I2C3_1,
426 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
427 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
428 PINMUX_FUNCTION_END,
429
430 PINMUX_MARK_BEGIN,
431 AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
432 A19_MARK,
433
434 RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
435 HRTS1_MARK, RX4_C_MARK,
436 CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
437 CS0_MARK, HSPI_CS2_B_MARK,
438 CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
439 A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
440 HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
441 A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
442 HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
443 A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
444 A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
445 A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
446 A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
447 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
448 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
449 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
450 PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
451 SCIF_CLK_MARK, TCLK0_C_MARK,
452
453 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
454 FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
455 EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
456 ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
457 FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
458 HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
459 EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
460 ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
461 TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
462 SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
463 VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
464 SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
465 MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
466 PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
467 SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
468 CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
469
470 HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
471 SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
472 CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
473 MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
474 SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
475 CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
476 STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
477 SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
478 RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
479 CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
480 CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
481 GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
482 LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
483 AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
484 DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
485 DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
486 DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
487 DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
488
489 DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
490 AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
491 LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
492 LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
493 LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
494 SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
495 LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
496 AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
497 DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
498 DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
499 DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
500 TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
501 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
502 SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
503 QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
504 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
505 TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
506
507 DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
508 DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
509 DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
510 VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
511 AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
512 PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
513 CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
514 VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
515 VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
516 VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
517 SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
518 DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
519 SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
520 VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
521 VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
522 VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
523 VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
524 SCK0_D_MARK,
525
526 DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
527 RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
528 DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
529 DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
530 DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
531 HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
532 SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
533 VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
534 VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
535 TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
536 VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
537 GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
538 QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
539 GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
540 RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
541 VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
542 GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
543 USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
544
545 SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
546 CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
547 MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
548 SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
549 CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
550 SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
551 SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
552 CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
553 SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
554 ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
555 SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
556 SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
557 SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
558
559 SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
560 SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
561 SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
562 HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
563 SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
564 IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
565 VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
566 ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
567 TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
568 RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
569 SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
570 TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
571 RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
572 RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
573
574 HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
575 CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
576 CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
577 AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
578 CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
579 CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
580 CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
581 CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
582 AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
583 CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
584 PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
585 VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
586 MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
587 VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
588 MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
589 RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
590
591 VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
592 VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
593 VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
594 MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
595 VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
596 MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
597 MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
598 IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
599 IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
600 MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
601 ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
602 VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
603 VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
604 VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
605 VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
606
607 VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
608 ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
609 DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
610 VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
611 ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
612 IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
613 SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
614 TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
615 HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
616 VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
617 TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
618 ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
619 TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
620 VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
621 PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
622 SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
623
624 VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
625 ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
626 SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
627 SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
628 VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
629 ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
630 SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
631 VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
632 HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
633 MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
634 SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
635 VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
636 DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
637 VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
638 DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
639
640 VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
641 SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
642 SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
643 VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
644 SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
645 GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
646 VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
647 RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
648 GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
649 PINMUX_MARK_END,
650};
651
652static pinmux_enum_t pinmux_data[] = {
653 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
654
655 PINMUX_DATA(AVS1_MARK, FN_AVS1),
656 PINMUX_DATA(AVS1_MARK, FN_AVS1),
657 PINMUX_DATA(A17_MARK, FN_A17),
658 PINMUX_DATA(A18_MARK, FN_A18),
659 PINMUX_DATA(A19_MARK, FN_A19),
660
661 PINMUX_IPSR_DATA(IP0_2_0, PENC2),
662 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
663 PINMUX_IPSR_DATA(IP0_2_0, PWM1),
664 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
665 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
666 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
667 PINMUX_IPSR_DATA(IP0_5_3, BS),
668 PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
669 PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
670 PINMUX_IPSR_DATA(IP0_5_3, FD2),
671 PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
672 PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
673 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
674 PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
675 PINMUX_IPSR_DATA(IP0_7_6, A0),
676 PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
677 PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
678 PINMUX_IPSR_DATA(IP0_7_6, FD3),
679 PINMUX_IPSR_DATA(IP0_9_8, A20),
680 PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
681 PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
682 PINMUX_IPSR_DATA(IP0_11_10, A21),
683 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
684 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
685 PINMUX_IPSR_DATA(IP0_13_12, A22),
686 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
687 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
688 PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
689 PINMUX_IPSR_DATA(IP0_15_14, A23),
690 PINMUX_IPSR_DATA(IP0_15_14, FCLE),
691 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
692 PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
693 PINMUX_IPSR_DATA(IP0_18_16, A24),
694 PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
695 PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
696 PINMUX_IPSR_DATA(IP0_18_16, FD4),
697 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
698 PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
699 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
700 PINMUX_IPSR_DATA(IP0_22_19, A25),
701 PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
702 PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
703 PINMUX_IPSR_DATA(IP0_22_19, FD5),
704 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
705 PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
706 PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
707 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
708 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
709 PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
710 PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
711 PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
712 PINMUX_IPSR_DATA(IP0_25, CS0),
713 PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
714 PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
715 PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
716 PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
717 PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
718 PINMUX_IPSR_DATA(IP0_30_28, FWE),
719 PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
720 PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
721 PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
722 PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
723
724 PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
725 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
726 PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
727 PINMUX_IPSR_DATA(IP1_1_0, FD6),
728 PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
729 PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
730 PINMUX_IPSR_DATA(IP1_3_2, FD7),
731 PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
732 PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
733 PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
734 PINMUX_IPSR_DATA(IP1_6_4, FALE),
735 PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
736 PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
737 PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
738 PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
739 PINMUX_IPSR_DATA(IP1_10_7, FRE),
740 PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
741 PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
742 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
743 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
744 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
745 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
746 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
747 PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
748 PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
749 PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
750 PINMUX_IPSR_DATA(IP1_14_11, FD0),
751 PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
752 PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
753 PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
754 PINMUX_IPSR_DATA(IP1_14_11, HTX1),
755 PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
756 PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
757 PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
758 PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
759 PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
760 PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
761 PINMUX_IPSR_DATA(IP1_18_15, FD1),
762 PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
763 PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
764 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
765 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
766 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
767 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
768 PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
769 PINMUX_IPSR_DATA(IP1_20_19, PWM2),
770 PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
771 PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
772 PINMUX_IPSR_DATA(IP1_22_21, PWM3),
773 PINMUX_IPSR_DATA(IP1_22_21, TX4),
774 PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
775 PINMUX_IPSR_DATA(IP1_24_23, PWM4),
776 PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
777 PINMUX_IPSR_DATA(IP1_28_25, HTX0),
778 PINMUX_IPSR_DATA(IP1_28_25, TX1),
779 PINMUX_IPSR_DATA(IP1_28_25, SDATA),
780 PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
781 PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
782 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
783 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
784 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
785 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
786 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
787
788 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
789 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
790 PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
791 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
792 PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
793 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
794 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
795 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
796 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
797 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
798 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
799 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
800 PINMUX_IPSR_DATA(IP2_7_4, MTS),
801 PINMUX_IPSR_DATA(IP2_7_4, PWM5),
802 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
803 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
804 PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
805 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
806 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
807 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
808 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
809 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
810 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
811 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
812 PINMUX_IPSR_DATA(IP2_11_8, STM),
813 PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
814 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
815 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
816 PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
817 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
818 PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
819 PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
820 PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
821 PINMUX_IPSR_DATA(IP2_15_12, MDATA),
822 PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
823 PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
824 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
825 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
826 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
827 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
828 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
829 PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
830 PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
831 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
832 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
833 PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
834 PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
835 PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
836 PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
837 PINMUX_IPSR_DATA(IP2_21_19, DACK0),
838 PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
839 PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
840 PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
841 PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
842 PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
843 PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
844 PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
845 PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
846 PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
847 PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
848 PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
849 PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
850 PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
851 PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
852 PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
853 PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
854 PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
855 PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
856 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
857 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
858 PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
859
860 PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
861 PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
862 PINMUX_IPSR_DATA(IP3_2_0, DACK1),
863 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
864 PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
865 PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
866 PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
867 PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
868 PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
869 PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
870 PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
871 PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
872 PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
873 PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
874 PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
875 PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
876 PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
877 PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
878 PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
879 PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
880 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
881 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
882 PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
883 PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
884 PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
885 PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
886 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
887 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
888 PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
889 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
890 PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
891 PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
892 PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
893 PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
894 PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
895 PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
896 PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
897 PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
898 PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
899 PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
900 PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
901 PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
902 PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
903 PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
904 PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
905 PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
906 PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
907 PINMUX_IPSR_DATA(IP3_23, QCLK),
908 PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
909 PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
910 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
911 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
912 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
913 PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
914 PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
915 PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
916 PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
917 PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
918 PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
919 PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
920 PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
921 PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
922 PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
923 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
924 PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
925
926 PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
927 PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
928 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
929 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
930 PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
931 PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
932 PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
933 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
934 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
935 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
936 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
937 PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
938 PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
939 PINMUX_IPSR_DATA(IP4_7_5, PWM6),
940 PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
941 PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
942 PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
943 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
944 PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
945 PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
946 PINMUX_IPSR_DATA(IP4_10_8, PWM0),
947 PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
948 PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
949 PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
950 PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
951 PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
952 PINMUX_IPSR_DATA(IP4_11, VI2_G0),
953 PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
954 PINMUX_IPSR_DATA(IP4_12, VI2_G1),
955 PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
956 PINMUX_IPSR_DATA(IP4_13, VI2_G2),
957 PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
958 PINMUX_IPSR_DATA(IP4_14, VI2_G3),
959 PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
960 PINMUX_IPSR_DATA(IP4_15, VI2_G4),
961 PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
962 PINMUX_IPSR_DATA(IP4_16, VI2_G5),
963 PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
964 PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
965 PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
966 PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
967 PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
968 PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
969 PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
970 PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
971 PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
972 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
973 PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
974 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
975 PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
976 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
977 PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
978 PINMUX_IPSR_DATA(IP4_23, VI2_G6),
979 PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
980 PINMUX_IPSR_DATA(IP4_24, VI2_G7),
981 PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
982 PINMUX_IPSR_DATA(IP4_25, VI2_R0),
983 PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
984 PINMUX_IPSR_DATA(IP4_26, VI2_R1),
985 PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
986 PINMUX_IPSR_DATA(IP4_27, VI2_R2),
987 PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
988 PINMUX_IPSR_DATA(IP4_28, VI2_R3),
989 PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
990 PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
991 PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
992 PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
993 PINMUX_IPSR_DATA(IP4_31_29, TX5),
994 PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
995
996 PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
997 PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
998 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
999 PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
1000 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
1001 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
1002 PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
1003 PINMUX_IPSR_DATA(IP5_3, VI2_R4),
1004 PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
1005 PINMUX_IPSR_DATA(IP5_4, VI2_R5),
1006 PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
1007 PINMUX_IPSR_DATA(IP5_5, VI2_R6),
1008 PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
1009 PINMUX_IPSR_DATA(IP5_6, VI2_R7),
1010 PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
1011 PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
1012 PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
1013 PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
1014 PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
1015 PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
1016 PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
1017 PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
1018 PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
1019 PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
1020 PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
1021 PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
1022 PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
1023 PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
1024 PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
1025 PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
1026 PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
1027 PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1028 PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
1029 PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
1030 PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
1031 PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
1032 PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
1033 PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
1034 PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
1035 PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
1036 PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
1037 PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
1038 PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
1039 PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
1040 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
1041 PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
1042 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
1043 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
1044 PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
1045 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
1046 PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
1047 PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
1048 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1049 PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
1050 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1051 PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
1052 PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
1053 PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
1054 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
1055 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1056 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1057 PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
1058 PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
1059 PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
1060 PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
1061 PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
1062 PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
1063
1064 PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
1065 PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
1066 PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
1067 PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
1068 PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
1069 PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
1070 PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
1071 PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
1072 PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
1073 PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
1074 PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
1075 PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
1076 PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
1077 PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
1078 PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
1079 PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
1080 PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
1081 PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
1082 PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1083 PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
1084 PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
1085 PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1086 PINMUX_IPSR_DATA(IP6_14_12, IETX),
1087 PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1088 PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
1089 PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
1090 PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
1091 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1092 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
1093 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1094 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1095 PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
1096 PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
1097 PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1098 PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
1099 PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
1100 PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
1101 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
1102 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1103 PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
1104 PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1105 PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
1106 PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
1107 PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
1108 PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
1109 PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
1110 PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1111 PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
1112 PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
1113 PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
1114 PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
1115
1116 PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
1117 PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
1118 PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1119 PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
1120 PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
1121 PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
1122 PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1123 PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
1124 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1125 PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
1126 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
1127 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1128 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1129 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1130 PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
1131 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
1132 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1133 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1134 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1135 PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
1136 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
1137 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1138 PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
1139 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1140 PINMUX_IPSR_DATA(IP7_14_13, VSP),
1141 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
1142 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1143 PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
1144 PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
1145 PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1146 PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
1147 PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
1148 PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
1149 PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
1150 PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
1151 PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
1152 PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
1153 PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
1154 PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
1155 PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
1156 PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1157 PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
1158 PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
1159 PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
1160 PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
1161 PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
1162 PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
1163 PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
1164 PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
1165 PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
1166 PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
1167 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1168 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1169 PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
1170 PINMUX_IPSR_DATA(IP7_30_29, DACK2),
1171 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1172
1173 PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
1174 PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
1175 PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
1176 PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
1177 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
1178 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
1179 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
1180 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
1181 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
1182 PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
1183 PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1184 PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
1185 PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
1186 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
1187 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
1188 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
1189 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
1190 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
1191 PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
1192 PINMUX_IPSR_DATA(IP8_11_8, TX0),
1193 PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1194 PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
1195 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
1196 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
1197 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
1198 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
1199 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
1200 PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
1201 PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
1202 PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
1203 PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
1204 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
1205 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
1206 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
1207 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
1208 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
1209 PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
1210 PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
1211 PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
1212 PINMUX_IPSR_DATA(IP8_18, BPFCLK),
1213 PINMUX_IPSR_DATA(IP8_18, PCMWE),
1214 PINMUX_IPSR_DATA(IP8_19, FMIN),
1215 PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
1216 PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
1217 PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
1218 PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
1219 PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
1220 PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
1221 PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
1222 PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
1223 PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
1224 PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1225 PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
1226 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1227 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1228 PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
1229 PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
1230 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1231 PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
1232 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1233 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1234 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
1235 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1236
1237 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1238 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1239 PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
1240 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1241 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1242 PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
1243 PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
1244 PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
1245 PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
1246 PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
1247 PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
1248 PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
1249 PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
1250 PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
1251 PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
1252 PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
1253 PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
1254 PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
1255 PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
1256 PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
1257 PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
1258 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1259 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
1260 PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
1261 PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
1262 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1263 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
1264 PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
1265 PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
1266 PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
1267 PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
1268 PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
1269 PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
1270 PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
1271 PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
1272 PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
1273 PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
1274 PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
1275 PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
1276 PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
1277 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1278 PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
1279 PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
1280 PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
1281 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1282 PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
1283 PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
1284 PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
1285 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1286 PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
1287 PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
1288 PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1290 PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
1291
1292 PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
1293 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1294 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1295 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1296 PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
1297 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1298 PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
1299 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1300 PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
1301 PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
1302 PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
1303 PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
1304 PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
1305 PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1306 PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
1307 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
1308 PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
1309 PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
1310 PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
1311 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1312 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
1313 PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
1314 PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
1315 PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
1316 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1317 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1318 PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
1319 PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
1320 PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
1321 PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
1322 PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
1323 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1324 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1325 PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
1326 PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
1327 PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
1328 PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
1329 PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
1330 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1331 PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
1332 PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
1333 PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
1334 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1335 PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
1336 PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
1337 PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
1338 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1339 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1340 PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
1341 PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
1342 PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
1343 PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
1344 PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
1345 PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
1346 PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
1347 PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1349 PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1350 PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
1351 PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
1352 PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
1353 PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1355 PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
1357
1358 PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
1359 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1360 PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
1361 PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
1362 PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
1363 PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
1364 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1365 PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
1366 PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
1367 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1368 PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
1369 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1370 PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
1371 PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
1372 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1373 PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
1374 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1375 PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
1376 PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
1377 PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
1378 PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
1379 PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
1380 PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
1381 PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
1382 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1383 PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
1384 PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
1385 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
1386 PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
1387 PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
1388 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1389 PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
1390 PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
1391 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
1392 PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
1393 PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
1394 PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
1395 PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
1396 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
1397 PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
1398 PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
1399 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1400 PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1401 PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1402 PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
1403 PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1404 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1405 PINMUX_IPSR_DATA(IP11_26_24, TX2),
1406 PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
1407 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1408 PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
1409 PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
1410 PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
1411 PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
1412 PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
1413 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
1414 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1415
1416 PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
1417 PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
1418 PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
1419 PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
1420 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
1421 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1422 PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
1423 PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
1424 PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
1425 PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
1426 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
1427 PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
1428 PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
1429 PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
1430 PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
1431 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
1432 PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
1433 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1434 PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
1435 PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
1436 PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
1437 PINMUX_IPSR_DATA(IP12_11_9, FSE),
1438 PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
1439 PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
1440 PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
1441 PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
1442 PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1443 PINMUX_IPSR_DATA(IP12_14_12, FRB),
1444 PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
1445 PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
1446 PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
1447 PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
1448 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
1449 PINMUX_IPSR_DATA(IP12_17_15, FCE),
1450 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1451};
1452
1453static struct pinmux_gpio pinmux_gpios[] = {
1454 PINMUX_GPIO_GP_ALL(),
1455 GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
1456 GPIO_FN(A19),
1457
1458 /* IPSR0 */
1459 GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
1460 GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
1461 GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
1462 GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
1463 GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
1464 GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
1465 GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
1466 GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
1467 GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
1468 GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
1469 GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
1470 GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
1471 GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
1472 GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
1473 GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
1474 GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
1475 GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
1476
1477 /* IPSR1 */
1478 GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
1479 GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
1480 GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
1481 GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
1482 GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
1483 GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
1484 GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
1485 GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
1486 GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
1487 GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
1488 GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
1489 GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
1490 GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
1491 GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
1492 GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
1493 GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
1494 GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
1495 GPIO_FN(CC5_STATE34),
1496
1497 /* IPSR2 */
1498 GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
1499 GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
1500 GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
1501 GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
1502 GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
1503 GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
1504 GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
1505 GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
1506 GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
1507 GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
1508 GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
1509 GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
1510 GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
1511 GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
1512 GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
1513 GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
1514 GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
1515 GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
1516 GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
1517 GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
1518 GPIO_FN(AUDATA2),
1519
1520 /* IPSR3 */
1521 GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
1522 GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
1523 GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
1524 GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
1525 GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
1526 GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
1527 GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
1528 GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
1529 GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
1530 GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
1531 GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
1532 GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
1533 GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
1534 GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
1535 GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
1536 GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
1537 GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
1538 GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
1539 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
1540 GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
1541 GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
1542
1543 /* IPSR4 */
1544 GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
1545 GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
1546 GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
1547 GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
1548 GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
1549 GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
1550 GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
1551 GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
1552 GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
1553 GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
1554 GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
1555 GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
1556 GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
1557 GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
1558 GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
1559 GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
1560 GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
1561 GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
1562 GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
1563 GPIO_FN(TX5), GPIO_FN(SCK0_D),
1564
1565 /* IPSR5 */
1566 GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
1567 GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
1568 GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
1569 GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
1570 GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
1571 GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
1572 GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
1573 GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
1574 GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
1575 GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
1576 GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
1577 GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
1578 GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
1579 GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
1580 GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
1581 GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
1582 GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
1583 GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
1584 GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
1585 GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
1586 GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
1587 GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
1588
1589 /* IPSR6 */
1590 GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
1591 GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
1592 GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
1593 GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
1594 GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
1595 GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
1596 GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
1597 GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
1598 GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
1599 GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
1600 GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
1601 GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
1602 GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
1603 GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
1604 GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
1605 GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
1606 GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
1607
1608 /* IPSR7 */
1609 GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
1610 GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
1611 GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
1612 GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
1613 GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
1614 GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
1615 GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
1616 GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
1617 GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
1618 GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
1619 GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
1620 GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
1621 GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
1622 GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
1623 GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
1624 GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
1625 GPIO_FN(CTS1_B),
1626
1627 /* IPSR8 */
1628 GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
1629 GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
1630 GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
1631 GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
1632 GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
1633 GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
1634 GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
1635 GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
1636 GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
1637 GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
1638 GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
1639 GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
1640 GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
1641 GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
1642 GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
1643 GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
1644 GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
1645 GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
1646 GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
1647 GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
1648
1649 /* IPSR9 */
1650 GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
1651 GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
1652 GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
1653 GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
1654 GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
1655 GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
1656 GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
1657 GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
1658 GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
1659 GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
1660 GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
1661 GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
1662 GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
1663 GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
1664 GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
1665 GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
1666 GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
1667 GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
1668
1669 /* IPSR10 */
1670 GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
1671 GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
1672 GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
1673 GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
1674 GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
1675 GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
1676 GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
1677 GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
1678 GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
1679 GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
1680 GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
1681 GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
1682 GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
1683 GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
1684 GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
1685 GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
1686 GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
1687 GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
1688 GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
1689 GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
1690 GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
1691
1692 /* IPSR11 */
1693 GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
1694 GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
1695 GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
1696 GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
1697 GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
1698 GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
1699 GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
1700 GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
1701 GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
1702 GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
1703 GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
1704 GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
1705 GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
1706 GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
1707 GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
1708 GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
1709 GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
1710 GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
1711 GPIO_FN(HRTS0_B),
1712
1713 /* IPSR12 */
1714 GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
1715 GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
1716 GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
1717 GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
1718 GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
1719 GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
1720 GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
1721 GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
1722 GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
1723 GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
1724};
1725
1726static struct pinmux_cfg_reg pinmux_config_regs[] = {
1727 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
1728 GP_0_31_FN, FN_IP3_31_29,
1729 GP_0_30_FN, FN_IP3_26_24,
1730 GP_0_29_FN, FN_IP3_22_21,
1731 GP_0_28_FN, FN_IP3_14_12,
1732 GP_0_27_FN, FN_IP3_11_9,
1733 GP_0_26_FN, FN_IP3_2_0,
1734 GP_0_25_FN, FN_IP2_30_28,
1735 GP_0_24_FN, FN_IP2_21_19,
1736 GP_0_23_FN, FN_IP2_18_16,
1737 GP_0_22_FN, FN_IP0_30_28,
1738 GP_0_21_FN, FN_IP0_5_3,
1739 GP_0_20_FN, FN_IP1_18_15,
1740 GP_0_19_FN, FN_IP1_14_11,
1741 GP_0_18_FN, FN_IP1_10_7,
1742 GP_0_17_FN, FN_IP1_6_4,
1743 GP_0_16_FN, FN_IP1_3_2,
1744 GP_0_15_FN, FN_IP1_1_0,
1745 GP_0_14_FN, FN_IP0_27_26,
1746 GP_0_13_FN, FN_IP0_25,
1747 GP_0_12_FN, FN_IP0_24_23,
1748 GP_0_11_FN, FN_IP0_22_19,
1749 GP_0_10_FN, FN_IP0_18_16,
1750 GP_0_9_FN, FN_IP0_15_14,
1751 GP_0_8_FN, FN_IP0_13_12,
1752 GP_0_7_FN, FN_IP0_11_10,
1753 GP_0_6_FN, FN_IP0_9_8,
1754 GP_0_5_FN, FN_A19,
1755 GP_0_4_FN, FN_A18,
1756 GP_0_3_FN, FN_A17,
1757 GP_0_2_FN, FN_IP0_7_6,
1758 GP_0_1_FN, FN_AVS2,
1759 GP_0_0_FN, FN_AVS1 }
1760 },
1761 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
1762 GP_1_31_FN, FN_IP5_23_21,
1763 GP_1_30_FN, FN_IP5_20_17,
1764 GP_1_29_FN, FN_IP5_16_15,
1765 GP_1_28_FN, FN_IP5_14_13,
1766 GP_1_27_FN, FN_IP5_12_11,
1767 GP_1_26_FN, FN_IP5_10_9,
1768 GP_1_25_FN, FN_IP5_8,
1769 GP_1_24_FN, FN_IP5_7,
1770 GP_1_23_FN, FN_IP5_6,
1771 GP_1_22_FN, FN_IP5_5,
1772 GP_1_21_FN, FN_IP5_4,
1773 GP_1_20_FN, FN_IP5_3,
1774 GP_1_19_FN, FN_IP5_2_0,
1775 GP_1_18_FN, FN_IP4_31_29,
1776 GP_1_17_FN, FN_IP4_28,
1777 GP_1_16_FN, FN_IP4_27,
1778 GP_1_15_FN, FN_IP4_26,
1779 GP_1_14_FN, FN_IP4_25,
1780 GP_1_13_FN, FN_IP4_24,
1781 GP_1_12_FN, FN_IP4_23,
1782 GP_1_11_FN, FN_IP4_22_20,
1783 GP_1_10_FN, FN_IP4_19_17,
1784 GP_1_9_FN, FN_IP4_16,
1785 GP_1_8_FN, FN_IP4_15,
1786 GP_1_7_FN, FN_IP4_14,
1787 GP_1_6_FN, FN_IP4_13,
1788 GP_1_5_FN, FN_IP4_12,
1789 GP_1_4_FN, FN_IP4_11,
1790 GP_1_3_FN, FN_IP4_10_8,
1791 GP_1_2_FN, FN_IP4_7_5,
1792 GP_1_1_FN, FN_IP4_4_2,
1793 GP_1_0_FN, FN_IP4_1_0 }
1794 },
1795 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
1796 GP_2_31_FN, FN_IP10_28_26,
1797 GP_2_30_FN, FN_IP10_25_24,
1798 GP_2_29_FN, FN_IP10_23_21,
1799 GP_2_28_FN, FN_IP10_20_18,
1800 GP_2_27_FN, FN_IP10_17_15,
1801 GP_2_26_FN, FN_IP10_14_12,
1802 GP_2_25_FN, FN_IP10_11_9,
1803 GP_2_24_FN, FN_IP10_8_6,
1804 GP_2_23_FN, FN_IP10_5_3,
1805 GP_2_22_FN, FN_IP10_2_0,
1806 GP_2_21_FN, FN_IP9_29_28,
1807 GP_2_20_FN, FN_IP9_27_26,
1808 GP_2_19_FN, FN_IP9_25_24,
1809 GP_2_18_FN, FN_IP9_23_22,
1810 GP_2_17_FN, FN_IP9_21_19,
1811 GP_2_16_FN, FN_IP9_18_16,
1812 GP_2_15_FN, FN_IP9_15_14,
1813 GP_2_14_FN, FN_IP9_13_12,
1814 GP_2_13_FN, FN_IP9_11_10,
1815 GP_2_12_FN, FN_IP9_9_8,
1816 GP_2_11_FN, FN_IP9_7,
1817 GP_2_10_FN, FN_IP9_6,
1818 GP_2_9_FN, FN_IP9_5,
1819 GP_2_8_FN, FN_IP9_4,
1820 GP_2_7_FN, FN_IP9_3_2,
1821 GP_2_6_FN, FN_IP9_1_0,
1822 GP_2_5_FN, FN_IP8_30_28,
1823 GP_2_4_FN, FN_IP8_27_25,
1824 GP_2_3_FN, FN_IP8_24_23,
1825 GP_2_2_FN, FN_IP8_22_21,
1826 GP_2_1_FN, FN_IP8_20,
1827 GP_2_0_FN, FN_IP5_27_24 }
1828 },
1829 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
1830 GP_3_31_FN, FN_IP6_3_2,
1831 GP_3_30_FN, FN_IP6_1_0,
1832 GP_3_29_FN, FN_IP5_30_29,
1833 GP_3_28_FN, FN_IP5_28,
1834 GP_3_27_FN, FN_IP1_24_23,
1835 GP_3_26_FN, FN_IP1_22_21,
1836 GP_3_25_FN, FN_IP1_20_19,
1837 GP_3_24_FN, FN_IP7_26_25,
1838 GP_3_23_FN, FN_IP7_24_23,
1839 GP_3_22_FN, FN_IP7_22_21,
1840 GP_3_21_FN, FN_IP7_20_19,
1841 GP_3_20_FN, FN_IP7_30_29,
1842 GP_3_19_FN, FN_IP7_28_27,
1843 GP_3_18_FN, FN_IP7_18_17,
1844 GP_3_17_FN, FN_IP7_16_15,
1845 GP_3_16_FN, FN_IP12_17_15,
1846 GP_3_15_FN, FN_IP12_14_12,
1847 GP_3_14_FN, FN_IP12_11_9,
1848 GP_3_13_FN, FN_IP12_8_6,
1849 GP_3_12_FN, FN_IP12_5_3,
1850 GP_3_11_FN, FN_IP12_2_0,
1851 GP_3_10_FN, FN_IP11_29_27,
1852 GP_3_9_FN, FN_IP11_26_24,
1853 GP_3_8_FN, FN_IP11_23_21,
1854 GP_3_7_FN, FN_IP11_20_18,
1855 GP_3_6_FN, FN_IP11_17_15,
1856 GP_3_5_FN, FN_IP11_14_12,
1857 GP_3_4_FN, FN_IP11_11_9,
1858 GP_3_3_FN, FN_IP11_8_6,
1859 GP_3_2_FN, FN_IP11_5_3,
1860 GP_3_1_FN, FN_IP11_2_0,
1861 GP_3_0_FN, FN_IP10_31_29 }
1862 },
1863 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
1864 GP_4_31_FN, FN_IP8_19,
1865 GP_4_30_FN, FN_IP8_18,
1866 GP_4_29_FN, FN_IP8_17_16,
1867 GP_4_28_FN, FN_IP0_2_0,
1868 GP_4_27_FN, FN_PENC1,
1869 GP_4_26_FN, FN_PENC0,
1870 GP_4_25_FN, FN_IP8_15_12,
1871 GP_4_24_FN, FN_IP8_11_8,
1872 GP_4_23_FN, FN_IP8_7_4,
1873 GP_4_22_FN, FN_IP8_3_0,
1874 GP_4_21_FN, FN_IP2_3_0,
1875 GP_4_20_FN, FN_IP1_28_25,
1876 GP_4_19_FN, FN_IP2_15_12,
1877 GP_4_18_FN, FN_IP2_11_8,
1878 GP_4_17_FN, FN_IP2_7_4,
1879 GP_4_16_FN, FN_IP7_14_13,
1880 GP_4_15_FN, FN_IP7_12_10,
1881 GP_4_14_FN, FN_IP7_9_7,
1882 GP_4_13_FN, FN_IP7_6_4,
1883 GP_4_12_FN, FN_IP7_3_2,
1884 GP_4_11_FN, FN_IP7_1_0,
1885 GP_4_10_FN, FN_IP6_30_29,
1886 GP_4_9_FN, FN_IP6_26_25,
1887 GP_4_8_FN, FN_IP6_24_23,
1888 GP_4_7_FN, FN_IP6_22_20,
1889 GP_4_6_FN, FN_IP6_19_18,
1890 GP_4_5_FN, FN_IP6_17_15,
1891 GP_4_4_FN, FN_IP6_14_12,
1892 GP_4_3_FN, FN_IP6_11_9,
1893 GP_4_2_FN, FN_IP6_8,
1894 GP_4_1_FN, FN_IP6_7_6,
1895 GP_4_0_FN, FN_IP6_5_4 }
1896 },
1897 { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
1898 GP_5_31_FN, FN_IP3_5,
1899 GP_5_30_FN, FN_IP3_4,
1900 GP_5_29_FN, FN_IP3_3,
1901 GP_5_28_FN, FN_IP2_27,
1902 GP_5_27_FN, FN_IP2_26,
1903 GP_5_26_FN, FN_IP2_25,
1904 GP_5_25_FN, FN_IP2_24,
1905 GP_5_24_FN, FN_IP2_23,
1906 GP_5_23_FN, FN_IP2_22,
1907 GP_5_22_FN, FN_IP3_28,
1908 GP_5_21_FN, FN_IP3_27,
1909 GP_5_20_FN, FN_IP3_23,
1910 GP_5_19_FN, FN_EX_WAIT0,
1911 GP_5_18_FN, FN_WE1,
1912 GP_5_17_FN, FN_WE0,
1913 GP_5_16_FN, FN_RD,
1914 GP_5_15_FN, FN_A16,
1915 GP_5_14_FN, FN_A15,
1916 GP_5_13_FN, FN_A14,
1917 GP_5_12_FN, FN_A13,
1918 GP_5_11_FN, FN_A12,
1919 GP_5_10_FN, FN_A11,
1920 GP_5_9_FN, FN_A10,
1921 GP_5_8_FN, FN_A9,
1922 GP_5_7_FN, FN_A8,
1923 GP_5_6_FN, FN_A7,
1924 GP_5_5_FN, FN_A6,
1925 GP_5_4_FN, FN_A5,
1926 GP_5_3_FN, FN_A4,
1927 GP_5_2_FN, FN_A3,
1928 GP_5_1_FN, FN_A2,
1929 GP_5_0_FN, FN_A1 }
1930 },
1931 { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
1932 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1933 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1934 0, 0, 0, 0, 0, 0, 0, 0,
1935 0, 0,
1936 0, 0,
1937 0, 0,
1938 GP_6_8_FN, FN_IP3_20,
1939 GP_6_7_FN, FN_IP3_19,
1940 GP_6_6_FN, FN_IP3_18,
1941 GP_6_5_FN, FN_IP3_17,
1942 GP_6_4_FN, FN_IP3_16,
1943 GP_6_3_FN, FN_IP3_15,
1944 GP_6_2_FN, FN_IP3_8,
1945 GP_6_1_FN, FN_IP3_7,
1946 GP_6_0_FN, FN_IP3_6 }
1947 },
1948
1949 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
1950 1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
1951 /* IP0_31 [1] */
1952 0, 0,
1953 /* IP0_30_28 [3] */
1954 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
1955 FN_HRTS1, FN_RX4_C, 0, 0,
1956 /* IP0_27_26 [2] */
1957 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
1958 /* IP0_25 [1] */
1959 FN_CS0, FN_HSPI_CS2_B,
1960 /* IP0_24_23 [2] */
1961 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
1962 /* IP0_22_19 [4] */
1963 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
1964 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
1965 FN_CTS0_B, 0, 0, 0,
1966 0, 0, 0, 0,
1967 /* IP0_18_16 [3] */
1968 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
1969 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
1970 /* IP0_15_14 [2] */
1971 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
1972 /* IP0_13_12 [2] */
1973 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
1974 /* IP0_11_10 [2] */
1975 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
1976 /* IP0_9_8 [2] */
1977 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
1978 /* IP0_7_6 [2] */
1979 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
1980 /* IP0_5_3 [3] */
1981 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
1982 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
1983 /* IP0_2_0 [3] */
1984 FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
1985 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
1986 },
1987 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
1988 3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
1989 /* IP1_31_29 [3] */
1990 0, 0, 0, 0, 0, 0, 0, 0,
1991 /* IP1_28_25 [4] */
1992 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
1993 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
1994 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
1995 0, 0, 0, 0,
1996 /* IP1_24_23 [2] */
1997 FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
1998 /* IP1_22_21 [2] */
1999 FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
2000 /* IP1_20_19 [2] */
2001 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
2002 /* IP1_18_15 [4] */
2003 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
2004 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
2005 FN_RX0_B, FN_SSI_WS9, 0, 0,
2006 0, 0, 0, 0,
2007 /* IP1_14_11 [4] */
2008 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
2009 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
2010 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
2011 0, 0, 0, 0,
2012 /* IP1_10_7 [4] */
2013 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
2014 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
2015 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
2016 0, 0, 0, 0,
2017 /* IP1_6_4 [3] */
2018 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
2019 FN_ATACS00, 0, 0, 0,
2020 /* IP1_3_2 [2] */
2021 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
2022 /* IP1_1_0 [2] */
2023 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
2024 },
2025 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2026 1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
2027 /* IP2_31 [1] */
2028 0, 0,
2029 /* IP2_30_28 [3] */
2030 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
2031 FN_AUDATA2, 0, 0, 0,
2032 /* IP2_27 [1] */
2033 FN_DU0_DR7, FN_LCDOUT7,
2034 /* IP2_26 [1] */
2035 FN_DU0_DR6, FN_LCDOUT6,
2036 /* IP2_25 [1] */
2037 FN_DU0_DR5, FN_LCDOUT5,
2038 /* IP2_24 [1] */
2039 FN_DU0_DR4, FN_LCDOUT4,
2040 /* IP2_23 [1] */
2041 FN_DU0_DR3, FN_LCDOUT3,
2042 /* IP2_22 [1] */
2043 FN_DU0_DR2, FN_LCDOUT2,
2044 /* IP2_21_19 [3] */
2045 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
2046 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
2047 /* IP2_18_16 [3] */
2048 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
2049 FN_AUDATA0, FN_TX5_C, 0, 0,
2050 /* IP2_15_12 [4] */
2051 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
2052 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
2053 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
2054 0, 0, 0, 0,
2055 /* IP2_11_8 [4] */
2056 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
2057 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
2058 FN_CC5_OSCOUT, 0, 0, 0,
2059 0, 0, 0, 0,
2060 /* IP2_7_4 [4] */
2061 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
2062 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
2063 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
2064 0, 0, 0, 0,
2065 /* IP2_3_0 [4] */
2066 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
2067 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
2068 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
2069 0, 0, 0, 0 }
2070 },
2071 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2072 3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
2073 1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
2074 /* IP3_31_29 [3] */
2075 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
2076 FN_SCL2_C, FN_REMOCON, 0, 0,
2077 /* IP3_28 [1] */
2078 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
2079 /* IP3_27 [1] */
2080 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
2081 /* IP3_26_24 [3] */
2082 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
2083 FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
2084 /* IP3_23 [1] */
2085 FN_DU0_DOTCLKOUT0, FN_QCLK,
2086 /* IP3_22_21 [2] */
2087 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
2088 /* IP3_20 [1] */
2089 FN_DU0_DB7, FN_LCDOUT23,
2090 /* IP3_19 [1] */
2091 FN_DU0_DB6, FN_LCDOUT22,
2092 /* IP3_18 [1] */
2093 FN_DU0_DB5, FN_LCDOUT21,
2094 /* IP3_17 [1] */
2095 FN_DU0_DB4, FN_LCDOUT20,
2096 /* IP3_16 [1] */
2097 FN_DU0_DB3, FN_LCDOUT19,
2098 /* IP3_15 [1] */
2099 FN_DU0_DB2, FN_LCDOUT18,
2100 /* IP3_14_12 [3] */
2101 FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
2102 FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
2103 /* IP3_11_9 [3] */
2104 FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
2105 FN_TCLK1, FN_AUDATA4, 0, 0,
2106 /* IP3_8 [1] */
2107 FN_DU0_DG7, FN_LCDOUT15,
2108 /* IP3_7 [1] */
2109 FN_DU0_DG6, FN_LCDOUT14,
2110 /* IP3_6 [1] */
2111 FN_DU0_DG5, FN_LCDOUT13,
2112 /* IP3_5 [1] */
2113 FN_DU0_DG4, FN_LCDOUT12,
2114 /* IP3_4 [1] */
2115 FN_DU0_DG3, FN_LCDOUT11,
2116 /* IP3_3 [1] */
2117 FN_DU0_DG2, FN_LCDOUT10,
2118 /* IP3_2_0 [3] */
2119 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
2120 FN_AUDATA3, 0, 0, 0 }
2121 },
2122 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2123 3, 1, 1, 1, 1, 1, 1, 3, 3, 1,
2124 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
2125 /* IP4_31_29 [3] */
2126 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
2127 FN_TX5, FN_SCK0_D, 0, 0,
2128 /* IP4_28 [1] */
2129 FN_DU1_DG7, FN_VI2_R3,
2130 /* IP4_27 [1] */
2131 FN_DU1_DG6, FN_VI2_R2,
2132 /* IP4_26 [1] */
2133 FN_DU1_DG5, FN_VI2_R1,
2134 /* IP4_25 [1] */
2135 FN_DU1_DG4, FN_VI2_R0,
2136 /* IP4_24 [1] */
2137 FN_DU1_DG3, FN_VI2_G7,
2138 /* IP4_23 [1] */
2139 FN_DU1_DG2, FN_VI2_G6,
2140 /* IP4_22_20 [3] */
2141 FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
2142 FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
2143 /* IP4_19_17 [3] */
2144 FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
2145 FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
2146 /* IP4_16 [1] */
2147 FN_DU1_DR7, FN_VI2_G5,
2148 /* IP4_15 [1] */
2149 FN_DU1_DR6, FN_VI2_G4,
2150 /* IP4_14 [1] */
2151 FN_DU1_DR5, FN_VI2_G3,
2152 /* IP4_13 [1] */
2153 FN_DU1_DR4, FN_VI2_G2,
2154 /* IP4_12 [1] */
2155 FN_DU1_DR3, FN_VI2_G1,
2156 /* IP4_11 [1] */
2157 FN_DU1_DR2, FN_VI2_G0,
2158 /* IP4_10_8 [3] */
2159 FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
2160 FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
2161 /* IP4_7_5 [3] */
2162 FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
2163 FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
2164 /* IP4_4_2 [3] */
2165 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
2166 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
2167 /* IP4_1_0 [2] */
2168 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
2169 },
2170 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2171 1, 2, 1, 4, 3, 4, 2, 2,
2172 2, 2, 1, 1, 1, 1, 1, 1, 3) {
2173 /* IP5_31 [1] */
2174 0, 0,
2175 /* IP5_30_29 [2] */
2176 FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
2177 /* IP5_28 [1] */
2178 FN_AUDIO_CLKA, FN_CAN_TXCLK,
2179 /* IP5_27_24 [4] */
2180 FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
2181 FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
2182 FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
2183 0, 0, 0, 0,
2184 /* IP5_23_21 [3] */
2185 FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
2186 FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
2187 /* IP5_20_17 [4] */
2188 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
2189 FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
2190 FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
2191 0, 0, 0, 0,
2192 /* IP5_16_15 [2] */
2193 FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
2194 /* IP5_14_13 [2] */
2195 FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
2196 /* IP5_12_11 [2] */
2197 FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
2198 /* IP5_10_9 [2] */
2199 FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
2200 /* IP5_8 [1] */
2201 FN_DU1_DB7, FN_SDA2_D,
2202 /* IP5_7 [1] */
2203 FN_DU1_DB6, FN_SCL2_D,
2204 /* IP5_6 [1] */
2205 FN_DU1_DB5, FN_VI2_R7,
2206 /* IP5_5 [1] */
2207 FN_DU1_DB4, FN_VI2_R6,
2208 /* IP5_4 [1] */
2209 FN_DU1_DB3, FN_VI2_R5,
2210 /* IP5_3 [1] */
2211 FN_DU1_DB2, FN_VI2_R4,
2212 /* IP5_2_0 [3] */
2213 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
2214 FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
2215 },
2216 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2217 1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
2218 /* IP6_31 [1] */
2219 0, 0,
2220 /* IP6_30_29 [2] */
2221 FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
2222 /* IP_28_27 [2] */
2223 0, 0, 0, 0,
2224 /* IP6_26_25 [2] */
2225 FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
2226 /* IP6_24_23 [2] */
2227 FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
2228 /* IP6_22_20 [3] */
2229 FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
2230 FN_TCLK0_D, 0, 0, 0,
2231 /* IP6_19_18 [2] */
2232 FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
2233 /* IP6_17_15 [3] */
2234 FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
2235 FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
2236 /* IP6_14_12 [3] */
2237 FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
2238 FN_SSI_WS9_C, 0, 0, 0,
2239 /* IP6_11_9 [3] */
2240 FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
2241 FN_SSI_SCK9_C, 0, 0, 0,
2242 /* IP6_8 [1] */
2243 FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
2244 /* IP6_7_6 [2] */
2245 FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
2246 /* IP6_5_4 [2] */
2247 FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
2248 /* IP6_3_2 [2] */
2249 FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
2250 /* IP6_1_0 [2] */
2251 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
2252 },
2253 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2254 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
2255 /* IP7_31 [1] */
2256 0, 0,
2257 /* IP7_30_29 [2] */
2258 FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
2259 /* IP7_28_27 [2] */
2260 FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
2261 /* IP7_26_25 [2] */
2262 FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
2263 /* IP7_24_23 [2] */
2264 FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
2265 /* IP7_22_21 [2] */
2266 FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
2267 /* IP7_20_19 [2] */
2268 FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
2269 /* IP7_18_17 [2] */
2270 FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
2271 /* IP7_16_15 [2] */
2272 FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
2273 /* IP7_14_13 [2] */
2274 FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
2275 /* IP7_12_10 [3] */
2276 FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
2277 FN_HSPI_TX1_C, 0, 0, 0,
2278 /* IP7_9_7 [3] */
2279 FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
2280 FN_HSPI_CS1_C, 0, 0, 0,
2281 /* IP7_6_4 [3] */
2282 FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
2283 FN_HSPI_CLK1_C, 0, 0, 0,
2284 /* IP7_3_2 [2] */
2285 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
2286 /* IP7_1_0 [2] */
2287 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
2288 },
2289 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2290 1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
2291 /* IP8_31 [1] */
2292 0, 0,
2293 /* IP8_30_28 [3] */
2294 FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
2295 FN_PWMFSW0_C, 0, 0, 0,
2296 /* IP8_27_25 [3] */
2297 FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
2298 FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
2299 /* IP8_24_23 [2] */
2300 FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
2301 /* IP8_22_21 [2] */
2302 FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
2303 /* IP8_20 [1] */
2304 FN_VI0_CLK, FN_MMC1_CLK,
2305 /* IP8_19 [1] */
2306 FN_FMIN, FN_RDS_DATA,
2307 /* IP8_18 [1] */
2308 FN_BPFCLK, FN_PCMWE,
2309 /* IP8_17_16 [2] */
2310 FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
2311 /* IP8_15_12 [4] */
2312 FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
2313 FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
2314 FN_CC5_STATE39, 0, 0, 0,
2315 0, 0, 0, 0,
2316 /* IP8_11_8 [4] */
2317 FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
2318 FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
2319 FN_CC5_STATE38, 0, 0, 0,
2320 0, 0, 0, 0,
2321 /* IP8_7_4 [4] */
2322 FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
2323 FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
2324 FN_CC5_STATE37, 0, 0, 0,
2325 0, 0, 0, 0,
2326 /* IP8_3_0 [4] */
2327 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
2328 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
2329 FN_CC5_STATE36, 0, 0, 0,
2330 0, 0, 0, 0 }
2331 },
2332 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2333 2, 2, 2, 2, 2, 3, 3, 2, 2,
2334 2, 2, 1, 1, 1, 1, 2, 2) {
2335 /* IP9_31_30 [2] */
2336 0, 0, 0, 0,
2337 /* IP9_29_28 [2] */
2338 FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
2339 /* IP9_27_26 [2] */
2340 FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
2341 /* IP9_25_24 [2] */
2342 FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
2343 /* IP9_23_22 [2] */
2344 FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
2345 /* IP9_21_19 [3] */
2346 FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
2347 FN_TS_SDAT0, 0, 0, 0,
2348 /* IP9_18_16 [3] */
2349 FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
2350 FN_TS_SPSYNC0, 0, 0, 0,
2351 /* IP9_15_14 [2] */
2352 FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
2353 /* IP9_13_12 [2] */
2354 FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
2355 /* IP9_11_10 [2] */
2356 FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
2357 /* IP9_9_8 [2] */
2358 FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
2359 /* IP9_7 [1] */
2360 FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
2361 /* IP9_6 [1] */
2362 FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
2363 /* IP9_5 [1] */
2364 FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
2365 /* IP9_4 [1] */
2366 FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
2367 /* IP9_3_2 [2] */
2368 FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
2369 /* IP9_1_0 [2] */
2370 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
2371 },
2372 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2373 3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
2374 /* IP10_31_29 [3] */
2375 FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
2376 FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
2377 /* IP10_28_26 [3] */
2378 FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
2379 FN_PWMFSW0_E, 0, 0, 0,
2380 /* IP10_25_24 [2] */
2381 FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
2382 /* IP10_23_21 [3] */
2383 FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
2384 FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
2385 /* IP10_20_18 [3] */
2386 FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
2387 FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
2388 /* IP10_17_15 [3] */
2389 FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
2390 FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
2391 /* IP10_14_12 [3] */
2392 FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
2393 FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
2394 /* IP10_11_9 [3] */
2395 FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
2396 FN_ARM_TRACEDATA_13, 0, 0, 0,
2397 /* IP10_8_6 [3] */
2398 FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
2399 FN_ARM_TRACEDATA_12, 0, 0, 0,
2400 /* IP10_5_3 [3] */
2401 FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
2402 FN_DACK0_C, FN_DRACK0_C, 0, 0,
2403 /* IP10_2_0 [3] */
2404 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
2405 FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
2406 },
2407 { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
2408 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2409 /* IP11_31_30 [2] */
2410 0, 0, 0, 0,
2411 /* IP11_29_27 [3] */
2412 FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
2413 FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
2414 /* IP11_26_24 [3] */
2415 FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
2416 FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
2417 /* IP11_23_21 [3] */
2418 FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
2419 FN_HSPI_RX1_D, 0, 0, 0,
2420 /* IP11_20_18 [3] */
2421 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
2422 FN_HSPI_TX1_D, 0, 0, 0,
2423 /* IP11_17_15 [3] */
2424 FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
2425 FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
2426 /* IP11_14_12 [3] */
2427 FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
2428 FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
2429 /* IP11_11_9 [3] */
2430 FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
2431 FN_ADICHS0_B, 0, 0, 0,
2432 /* IP11_8_6 [3] */
2433 FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
2434 FN_ADIDATA_B, 0, 0, 0,
2435 /* IP11_5_3 [3] */
2436 FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
2437 FN_ADICS_B_SAMP_B, 0, 0, 0,
2438 /* IP11_2_0 [3] */
2439 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
2440 FN_ADICLK_B, 0, 0, 0 }
2441 },
2442 { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
2443 4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
2444 /* IP12_31_28 [4] */
2445 0, 0, 0, 0, 0, 0, 0, 0,
2446 0, 0, 0, 0, 0, 0, 0, 0,
2447 /* IP12_27_24 [4] */
2448 0, 0, 0, 0, 0, 0, 0, 0,
2449 0, 0, 0, 0, 0, 0, 0, 0,
2450 /* IP12_23_20 [4] */
2451 0, 0, 0, 0, 0, 0, 0, 0,
2452 0, 0, 0, 0, 0, 0, 0, 0,
2453 /* IP12_19_18 [2] */
2454 0, 0, 0, 0,
2455 /* IP12_17_15 [3] */
2456 FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
2457 FN_SCK4_B, 0, 0, 0,
2458 /* IP12_14_12 [3] */
2459 FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
2460 FN_RX4_B, FN_SIM_CLK_B, 0, 0,
2461 /* IP12_11_9 [3] */
2462 FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
2463 FN_TX4_B, FN_SIM_D_B, 0, 0,
2464 /* IP12_8_6 [3] */
2465 FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
2466 FN_SIM_RST_B, FN_HRX0_B, 0, 0,
2467 /* IP12_5_3 [3] */
2468 FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
2469 FN_SCL1_C, FN_HTX0_B, 0, 0,
2470 /* IP12_2_0 [3] */
2471 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
2472 FN_SCK2, FN_HSCK0_B, 0, 0 }
2473 },
2474 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
2475 2, 2, 3, 3, 2, 2, 2, 2, 2,
2476 1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
2477 /* SEL_SCIF5 [2] */
2478 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
2479 /* SEL_SCIF4 [2] */
2480 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
2481 /* SEL_SCIF3 [3] */
2482 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
2483 FN_SEL_SCIF3_4, 0, 0, 0,
2484 /* SEL_SCIF2 [3] */
2485 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
2486 FN_SEL_SCIF2_4, 0, 0, 0,
2487 /* SEL_SCIF1 [2] */
2488 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
2489 /* SEL_SCIF0 [2] */
2490 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
2491 /* SEL_SSI9 [2] */
2492 FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
2493 /* SEL_SSI8 [2] */
2494 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
2495 /* SEL_SSI7 [2] */
2496 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
2497 /* SEL_VI0 [1] */
2498 FN_SEL_VI0_0, FN_SEL_VI0_1,
2499 /* SEL_SD2 [1] */
2500 FN_SEL_SD2_0, FN_SEL_SD2_1,
2501 /* SEL_INT3 [1] */
2502 FN_SEL_INT3_0, FN_SEL_INT3_1,
2503 /* SEL_INT2 [1] */
2504 FN_SEL_INT2_0, FN_SEL_INT2_1,
2505 /* SEL_INT1 [1] */
2506 FN_SEL_INT1_0, FN_SEL_INT1_1,
2507 /* SEL_INT0 [1] */
2508 FN_SEL_INT0_0, FN_SEL_INT0_1,
2509 /* SEL_IE [1] */
2510 FN_SEL_IE_0, FN_SEL_IE_1,
2511 /* SEL_EXBUS2 [2] */
2512 FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
2513 /* SEL_EXBUS1 [1] */
2514 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
2515 /* SEL_EXBUS0 [2] */
2516 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
2517 },
2518 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
2519 2, 2, 2, 2, 1, 1, 1, 3, 1,
2520 2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
2521 /* SEL_TMU1 [2] */
2522 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
2523 /* SEL_TMU0 [2] */
2524 FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
2525 /* SEL_SCIF [2] */
2526 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
2527 /* SEL_CANCLK [2] */
2528 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
2529 /* SEL_CAN0 [1] */
2530 FN_SEL_CAN0_0, FN_SEL_CAN0_1,
2531 /* SEL_HSCIF1 [1] */
2532 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
2533 /* SEL_HSCIF0 [1] */
2534 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
2535 /* SEL_PWMFSW [3] */
2536 FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
2537 FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
2538 /* SEL_ADI [1] */
2539 FN_SEL_ADI_0, FN_SEL_ADI_1,
2540 /* [2] */
2541 0, 0, 0, 0,
2542 /* [2] */
2543 0, 0, 0, 0,
2544 /* [2] */
2545 0, 0, 0, 0,
2546 /* SEL_GPS [2] */
2547 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
2548 /* SEL_SIM [1] */
2549 FN_SEL_SIM_0, FN_SEL_SIM_1,
2550 /* SEL_HSPI2 [1] */
2551 FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
2552 /* SEL_HSPI1 [2] */
2553 FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
2554 /* SEL_I2C3 [1] */
2555 FN_SEL_I2C3_0, FN_SEL_I2C3_1,
2556 /* SEL_I2C2 [2] */
2557 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
2558 /* SEL_I2C1 [2] */
2559 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
2560 },
2561 { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
2562 { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
2563 { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
2564 { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
2565 { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
2566 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
2567 { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
2568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2570 0, 0, 0, 0, 0, 0, 0, 0,
2571 0, 0,
2572 0, 0,
2573 0, 0,
2574 GP_6_8_IN, GP_6_8_OUT,
2575 GP_6_7_IN, GP_6_7_OUT,
2576 GP_6_6_IN, GP_6_6_OUT,
2577 GP_6_5_IN, GP_6_5_OUT,
2578 GP_6_4_IN, GP_6_4_OUT,
2579 GP_6_3_IN, GP_6_3_OUT,
2580 GP_6_2_IN, GP_6_2_OUT,
2581 GP_6_1_IN, GP_6_1_OUT,
2582 GP_6_0_IN, GP_6_0_OUT, }
2583 },
2584 { },
2585};
2586
2587static struct pinmux_data_reg pinmux_data_regs[] = {
2588 { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
2589 { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
2590 { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
2591 { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
2592 { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
2593 { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
2594 { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
2595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2596 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
2597 GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
2598 GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
2599 },
2600 { },
2601};
2602
2603static struct resource r8a7779_pfc_resources[] = {
2604 [0] = {
2605 .start = 0xfffc0000,
2606 .end = 0xfffc023b,
2607 .flags = IORESOURCE_MEM,
2608 },
2609 [1] = {
2610 .start = 0xffc40000,
2611 .end = 0xffc46fff,
2612 .flags = IORESOURCE_MEM,
2613 }
2614};
2615
2616static struct pinmux_info r8a7779_pinmux_info = {
2617 .name = "r8a7779_pfc",
2618
2619 .resource = r8a7779_pfc_resources,
2620 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
2621
2622 .unlock_reg = 0xfffc0000, /* PMMR */
2623
2624 .reserved_id = PINMUX_RESERVED,
2625 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2626 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2627 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2628 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2629 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2630
2631 .first_gpio = GPIO_GP_0_0,
2632 .last_gpio = GPIO_FN_SCK4_B,
2633
2634 .gpios = pinmux_gpios,
2635 .cfg_regs = pinmux_config_regs,
2636 .data_regs = pinmux_data_regs,
2637
2638 .gpio_data = pinmux_data,
2639 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2640};
2641
2642void r8a7779_pinmux_init(void)
2643{
2644 register_pinmux(&r8a7779_pinmux_info);
2645}
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index c49a833bf9bb..993381257f69 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -22,12 +22,16 @@
22#include <mach/common.h> 22#include <mach/common.h>
23 23
24#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2()) 24#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2())
25#define is_r8a7779() machine_is_marzen()
25 26
26static unsigned int __init shmobile_smp_get_core_count(void) 27static unsigned int __init shmobile_smp_get_core_count(void)
27{ 28{
28 if (is_sh73a0()) 29 if (is_sh73a0())
29 return sh73a0_get_core_count(); 30 return sh73a0_get_core_count();
30 31
32 if (is_r8a7779())
33 return r8a7779_get_core_count();
34
31 return 1; 35 return 1;
32} 36}
33 37
@@ -35,6 +39,17 @@ static void __init shmobile_smp_prepare_cpus(void)
35{ 39{
36 if (is_sh73a0()) 40 if (is_sh73a0())
37 sh73a0_smp_prepare_cpus(); 41 sh73a0_smp_prepare_cpus();
42
43 if (is_r8a7779())
44 r8a7779_smp_prepare_cpus();
45}
46
47int shmobile_platform_cpu_kill(unsigned int cpu)
48{
49 if (is_r8a7779())
50 return r8a7779_platform_cpu_kill(cpu);
51
52 return 1;
38} 53}
39 54
40void __cpuinit platform_secondary_init(unsigned int cpu) 55void __cpuinit platform_secondary_init(unsigned int cpu)
@@ -43,6 +58,9 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
43 58
44 if (is_sh73a0()) 59 if (is_sh73a0())
45 sh73a0_secondary_init(cpu); 60 sh73a0_secondary_init(cpu);
61
62 if (is_r8a7779())
63 r8a7779_secondary_init(cpu);
46} 64}
47 65
48int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 66int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -50,6 +68,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
50 if (is_sh73a0()) 68 if (is_sh73a0())
51 return sh73a0_boot_secondary(cpu); 69 return sh73a0_boot_secondary(cpu);
52 70
71 if (is_r8a7779())
72 return r8a7779_boot_secondary(cpu);
73
53 return -ENOSYS; 74 return -ENOSYS;
54} 75}
55 76
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
new file mode 100644
index 000000000000..c38ba7b43ef8
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -0,0 +1,249 @@
1/*
2 * r8a7779 Power management support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/pm.h>
13#include <linux/suspend.h>
14#include <linux/err.h>
15#include <linux/pm_clock.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/console.h>
21#include <asm/system.h>
22#include <asm/io.h>
23#include <mach/common.h>
24#include <mach/r8a7779.h>
25
26static void __iomem *r8a7779_sysc_base;
27
28/* SYSC */
29#define SYSCSR 0x00
30#define SYSCISR 0x04
31#define SYSCISCR 0x08
32#define SYSCIER 0x0c
33#define SYSCIMR 0x10
34#define PWRSR0 0x40
35#define PWRSR1 0x80
36#define PWRSR2 0xc0
37#define PWRSR3 0x100
38#define PWRSR4 0x140
39
40#define PWRSR_OFFS 0x00
41#define PWROFFCR_OFFS 0x04
42#define PWRONCR_OFFS 0x0c
43#define PWRER_OFFS 0x14
44
45#define SYSCSR_RETRIES 100
46#define SYSCSR_DELAY_US 1
47
48#define SYSCISR_RETRIES 1000
49#define SYSCISR_DELAY_US 1
50
51#if defined(CONFIG_PM) || defined(CONFIG_SMP)
52
53static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
54
55static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
56 int sr_bit, int reg_offs)
57{
58 int k;
59
60 for (k = 0; k < SYSCSR_RETRIES; k++) {
61 if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit))
62 break;
63 udelay(SYSCSR_DELAY_US);
64 }
65
66 if (k == SYSCSR_RETRIES)
67 return -EAGAIN;
68
69 iowrite32(1 << r8a7779_ch->chan_bit,
70 r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs);
71
72 return 0;
73}
74
75static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch)
76{
77 return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS);
78}
79
80static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch)
81{
82 return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS);
83}
84
85static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
86 int (*on_off_fn)(struct r8a7779_pm_ch *))
87{
88 unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
89 unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
90 unsigned int status;
91 unsigned long flags;
92 int ret = 0;
93 int k;
94
95 spin_lock_irqsave(&r8a7779_sysc_lock, flags);
96
97 iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
98
99 do {
100 ret = on_off_fn(r8a7779_ch);
101 if (ret)
102 goto out;
103
104 status = ioread32(r8a7779_sysc_base +
105 r8a7779_ch->chan_offs + PWRER_OFFS);
106 } while (status & chan_mask);
107
108 for (k = 0; k < SYSCISR_RETRIES; k++) {
109 if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask)
110 break;
111 udelay(SYSCISR_DELAY_US);
112 }
113
114 if (k == SYSCISR_RETRIES)
115 ret = -EIO;
116
117 iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
118
119 out:
120 spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
121
122 pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
123 r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
124 ioread32(r8a7779_sysc_base + PWRSR1),
125 ioread32(r8a7779_sysc_base + PWRSR2),
126 ioread32(r8a7779_sysc_base + PWRSR3),
127 ioread32(r8a7779_sysc_base + PWRSR4), ret);
128 return ret;
129}
130
131int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
132{
133 return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
134}
135
136int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
137{
138 return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
139}
140
141static void __init r8a7779_sysc_init(void)
142{
143 r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE);
144 if (!r8a7779_sysc_base)
145 panic("unable to ioremap r8a7779 SYSC hardware block\n");
146
147 /* enable all interrupt sources, but do not use interrupt handler */
148 iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER);
149 iowrite32(0, r8a7779_sysc_base + SYSCIMR);
150}
151
152#else /* CONFIG_PM || CONFIG_SMP */
153
154static inline void r8a7779_sysc_init(void) {}
155
156#endif /* CONFIG_PM || CONFIG_SMP */
157
158#ifdef CONFIG_PM
159
160static int pd_power_down(struct generic_pm_domain *genpd)
161{
162 return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
163}
164
165static int pd_power_up(struct generic_pm_domain *genpd)
166{
167 return r8a7779_sysc_power_up(to_r8a7779_ch(genpd));
168}
169
170static bool pd_is_off(struct generic_pm_domain *genpd)
171{
172 struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd);
173 unsigned int st;
174
175 st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS);
176 if (st & (1 << r8a7779_ch->chan_bit))
177 return true;
178
179 return false;
180}
181
182static bool pd_active_wakeup(struct device *dev)
183{
184 return true;
185}
186
187void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
188{
189 struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
190
191 pm_genpd_init(genpd, NULL, false);
192 genpd->dev_ops.stop = pm_clk_suspend;
193 genpd->dev_ops.start = pm_clk_resume;
194 genpd->dev_ops.active_wakeup = pd_active_wakeup;
195 genpd->dev_irq_safe = true;
196 genpd->power_off = pd_power_down;
197 genpd->power_on = pd_power_up;
198
199 if (pd_is_off(&r8a7779_pd->genpd))
200 pd_power_up(&r8a7779_pd->genpd);
201}
202
203void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
204 struct platform_device *pdev)
205{
206 struct device *dev = &pdev->dev;
207
208 pm_genpd_add_device(&r8a7779_pd->genpd, dev);
209 if (pm_clk_no_clocks(dev))
210 pm_clk_add(dev, NULL);
211}
212
213struct r8a7779_pm_domain r8a7779_sh4a = {
214 .ch = {
215 .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
216 .isr_bit = 16, /* SH4A */
217 }
218};
219
220struct r8a7779_pm_domain r8a7779_sgx = {
221 .ch = {
222 .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
223 .isr_bit = 20, /* SGX */
224 }
225};
226
227struct r8a7779_pm_domain r8a7779_vdp1 = {
228 .ch = {
229 .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
230 .isr_bit = 21, /* VDP */
231 }
232};
233
234struct r8a7779_pm_domain r8a7779_impx3 = {
235 .ch = {
236 .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
237 .isr_bit = 24, /* IMP */
238 }
239};
240
241#endif /* CONFIG_PM */
242
243void __init r8a7779_pm_init(void)
244{
245 static int once;
246
247 if (!once++)
248 r8a7779_sysc_init();
249}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
new file mode 100644
index 000000000000..986dca6b3fad
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -0,0 +1,352 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/delay.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/platform_device.h>
25#include <linux/serial_sci.h>
26#include <linux/sh_timer.h>
27#include <mach/r8a7740.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31/* SCIFA0 */
32static struct plat_sci_port scif0_platform_data = {
33 .mapbase = 0xe6c40000,
34 .flags = UPF_BOOT_AUTOCONF,
35 .scscr = SCSCR_RE | SCSCR_TE,
36 .scbrr_algo_id = SCBRR_ALGO_4,
37 .type = PORT_SCIFA,
38 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
39};
40
41static struct platform_device scif0_device = {
42 .name = "sh-sci",
43 .id = 0,
44 .dev = {
45 .platform_data = &scif0_platform_data,
46 },
47};
48
49/* SCIFA1 */
50static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xe6c50000,
52 .flags = UPF_BOOT_AUTOCONF,
53 .scscr = SCSCR_RE | SCSCR_TE,
54 .scbrr_algo_id = SCBRR_ALGO_4,
55 .type = PORT_SCIFA,
56 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
57};
58
59static struct platform_device scif1_device = {
60 .name = "sh-sci",
61 .id = 1,
62 .dev = {
63 .platform_data = &scif1_platform_data,
64 },
65};
66
67/* SCIFA2 */
68static struct plat_sci_port scif2_platform_data = {
69 .mapbase = 0xe6c60000,
70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE,
72 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIFA,
74 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
75};
76
77static struct platform_device scif2_device = {
78 .name = "sh-sci",
79 .id = 2,
80 .dev = {
81 .platform_data = &scif2_platform_data,
82 },
83};
84
85/* SCIFA3 */
86static struct plat_sci_port scif3_platform_data = {
87 .mapbase = 0xe6c70000,
88 .flags = UPF_BOOT_AUTOCONF,
89 .scscr = SCSCR_RE | SCSCR_TE,
90 .scbrr_algo_id = SCBRR_ALGO_4,
91 .type = PORT_SCIFA,
92 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
93};
94
95static struct platform_device scif3_device = {
96 .name = "sh-sci",
97 .id = 3,
98 .dev = {
99 .platform_data = &scif3_platform_data,
100 },
101};
102
103/* SCIFA4 */
104static struct plat_sci_port scif4_platform_data = {
105 .mapbase = 0xe6c80000,
106 .flags = UPF_BOOT_AUTOCONF,
107 .scscr = SCSCR_RE | SCSCR_TE,
108 .scbrr_algo_id = SCBRR_ALGO_4,
109 .type = PORT_SCIFA,
110 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
111};
112
113static struct platform_device scif4_device = {
114 .name = "sh-sci",
115 .id = 4,
116 .dev = {
117 .platform_data = &scif4_platform_data,
118 },
119};
120
121/* SCIFA5 */
122static struct plat_sci_port scif5_platform_data = {
123 .mapbase = 0xe6cb0000,
124 .flags = UPF_BOOT_AUTOCONF,
125 .scscr = SCSCR_RE | SCSCR_TE,
126 .scbrr_algo_id = SCBRR_ALGO_4,
127 .type = PORT_SCIFA,
128 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
129};
130
131static struct platform_device scif5_device = {
132 .name = "sh-sci",
133 .id = 5,
134 .dev = {
135 .platform_data = &scif5_platform_data,
136 },
137};
138
139/* SCIFA6 */
140static struct plat_sci_port scif6_platform_data = {
141 .mapbase = 0xe6cc0000,
142 .flags = UPF_BOOT_AUTOCONF,
143 .scscr = SCSCR_RE | SCSCR_TE,
144 .scbrr_algo_id = SCBRR_ALGO_4,
145 .type = PORT_SCIFA,
146 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
147};
148
149static struct platform_device scif6_device = {
150 .name = "sh-sci",
151 .id = 6,
152 .dev = {
153 .platform_data = &scif6_platform_data,
154 },
155};
156
157/* SCIFA7 */
158static struct plat_sci_port scif7_platform_data = {
159 .mapbase = 0xe6cd0000,
160 .flags = UPF_BOOT_AUTOCONF,
161 .scscr = SCSCR_RE | SCSCR_TE,
162 .scbrr_algo_id = SCBRR_ALGO_4,
163 .type = PORT_SCIFA,
164 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
165};
166
167static struct platform_device scif7_device = {
168 .name = "sh-sci",
169 .id = 7,
170 .dev = {
171 .platform_data = &scif7_platform_data,
172 },
173};
174
175/* SCIFB */
176static struct plat_sci_port scifb_platform_data = {
177 .mapbase = 0xe6c30000,
178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RE | SCSCR_TE,
180 .scbrr_algo_id = SCBRR_ALGO_4,
181 .type = PORT_SCIFB,
182 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
183};
184
185static struct platform_device scifb_device = {
186 .name = "sh-sci",
187 .id = 8,
188 .dev = {
189 .platform_data = &scifb_platform_data,
190 },
191};
192
193/* CMT */
194static struct sh_timer_config cmt10_platform_data = {
195 .name = "CMT10",
196 .channel_offset = 0x10,
197 .timer_bit = 0,
198 .clockevent_rating = 125,
199 .clocksource_rating = 125,
200};
201
202static struct resource cmt10_resources[] = {
203 [0] = {
204 .name = "CMT10",
205 .start = 0xe6138010,
206 .end = 0xe613801b,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = evt2irq(0x0b00),
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct platform_device cmt10_device = {
216 .name = "sh_cmt",
217 .id = 10,
218 .dev = {
219 .platform_data = &cmt10_platform_data,
220 },
221 .resource = cmt10_resources,
222 .num_resources = ARRAY_SIZE(cmt10_resources),
223};
224
225static struct platform_device *r8a7740_early_devices[] __initdata = {
226 &scif0_device,
227 &scif1_device,
228 &scif2_device,
229 &scif3_device,
230 &scif4_device,
231 &scif5_device,
232 &scif6_device,
233 &scif7_device,
234 &scifb_device,
235 &cmt10_device,
236};
237
238/* I2C */
239static struct resource i2c0_resources[] = {
240 [0] = {
241 .name = "IIC0",
242 .start = 0xfff20000,
243 .end = 0xfff20425 - 1,
244 .flags = IORESOURCE_MEM,
245 },
246 [1] = {
247 .start = intcs_evt2irq(0xe00),
248 .end = intcs_evt2irq(0xe60),
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct resource i2c1_resources[] = {
254 [0] = {
255 .name = "IIC1",
256 .start = 0xe6c20000,
257 .end = 0xe6c20425 - 1,
258 .flags = IORESOURCE_MEM,
259 },
260 [1] = {
261 .start = evt2irq(0x780), /* IIC1_ALI1 */
262 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
263 .flags = IORESOURCE_IRQ,
264 },
265};
266
267static struct platform_device i2c0_device = {
268 .name = "i2c-sh_mobile",
269 .id = 0,
270 .resource = i2c0_resources,
271 .num_resources = ARRAY_SIZE(i2c0_resources),
272};
273
274static struct platform_device i2c1_device = {
275 .name = "i2c-sh_mobile",
276 .id = 1,
277 .resource = i2c1_resources,
278 .num_resources = ARRAY_SIZE(i2c1_resources),
279};
280
281static struct platform_device *r8a7740_late_devices[] __initdata = {
282 &i2c0_device,
283 &i2c1_device,
284};
285
286#define ICCR 0x0004
287#define ICSTART 0x0070
288
289#define i2c_read(reg, offset) ioread8(reg + offset)
290#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
291
292/*
293 * r8a7740 chip has lasting errata on I2C I/O pad reset.
294 * this is work-around for it.
295 */
296static void r8a7740_i2c_workaround(struct platform_device *pdev)
297{
298 struct resource *res;
299 void __iomem *reg;
300
301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
302 if (unlikely(!res)) {
303 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
304 return;
305 }
306
307 reg = ioremap(res->start, resource_size(res));
308 if (unlikely(!reg)) {
309 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
310 return;
311 }
312
313 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
314 i2c_read(reg, ICCR); /* dummy read */
315
316 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
317 i2c_read(reg, ICSTART); /* dummy read */
318
319 mdelay(100);
320
321 i2c_write(reg, ICCR, 0x01);
322 i2c_read(reg, ICCR);
323 i2c_write(reg, ICSTART, 0x00);
324 i2c_read(reg, ICSTART);
325
326 i2c_write(reg, ICCR, 0x10);
327 mdelay(100);
328 i2c_write(reg, ICCR, 0x00);
329 mdelay(100);
330 i2c_write(reg, ICCR, 0x10);
331 mdelay(100);
332
333 iounmap(reg);
334}
335
336void __init r8a7740_add_standard_devices(void)
337{
338 /* I2C work-around */
339 r8a7740_i2c_workaround(&i2c0_device);
340 r8a7740_i2c_workaround(&i2c1_device);
341
342 platform_add_devices(r8a7740_early_devices,
343 ARRAY_SIZE(r8a7740_early_devices));
344 platform_add_devices(r8a7740_late_devices,
345 ARRAY_SIZE(r8a7740_late_devices));
346}
347
348void __init r8a7740_add_early_devices(void)
349{
350 early_platform_add_devices(r8a7740_early_devices,
351 ARRAY_SIZE(r8a7740_early_devices));
352}
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
new file mode 100644
index 000000000000..4725663bd032
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -0,0 +1,239 @@
1/*
2 * r8a7779 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/input.h>
27#include <linux/io.h>
28#include <linux/serial_sci.h>
29#include <linux/sh_intc.h>
30#include <linux/sh_timer.h>
31#include <mach/hardware.h>
32#include <mach/r8a7779.h>
33#include <mach/common.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36
37static struct plat_sci_port scif0_platform_data = {
38 .mapbase = 0xffe40000,
39 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF,
43 .irqs = { gic_spi(88), gic_spi(88),
44 gic_spi(88), gic_spi(88) },
45};
46
47static struct platform_device scif0_device = {
48 .name = "sh-sci",
49 .id = 0,
50 .dev = {
51 .platform_data = &scif0_platform_data,
52 },
53};
54
55static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xffe41000,
57 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
58 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
59 .scbrr_algo_id = SCBRR_ALGO_2,
60 .type = PORT_SCIF,
61 .irqs = { gic_spi(89), gic_spi(89),
62 gic_spi(89), gic_spi(89) },
63};
64
65static struct platform_device scif1_device = {
66 .name = "sh-sci",
67 .id = 1,
68 .dev = {
69 .platform_data = &scif1_platform_data,
70 },
71};
72
73static struct plat_sci_port scif2_platform_data = {
74 .mapbase = 0xffe42000,
75 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
76 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
77 .scbrr_algo_id = SCBRR_ALGO_2,
78 .type = PORT_SCIF,
79 .irqs = { gic_spi(90), gic_spi(90),
80 gic_spi(90), gic_spi(90) },
81};
82
83static struct platform_device scif2_device = {
84 .name = "sh-sci",
85 .id = 2,
86 .dev = {
87 .platform_data = &scif2_platform_data,
88 },
89};
90
91static struct plat_sci_port scif3_platform_data = {
92 .mapbase = 0xffe43000,
93 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
94 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
95 .scbrr_algo_id = SCBRR_ALGO_2,
96 .type = PORT_SCIF,
97 .irqs = { gic_spi(91), gic_spi(91),
98 gic_spi(91), gic_spi(91) },
99};
100
101static struct platform_device scif3_device = {
102 .name = "sh-sci",
103 .id = 3,
104 .dev = {
105 .platform_data = &scif3_platform_data,
106 },
107};
108
109static struct plat_sci_port scif4_platform_data = {
110 .mapbase = 0xffe44000,
111 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
113 .scbrr_algo_id = SCBRR_ALGO_2,
114 .type = PORT_SCIF,
115 .irqs = { gic_spi(92), gic_spi(92),
116 gic_spi(92), gic_spi(92) },
117};
118
119static struct platform_device scif4_device = {
120 .name = "sh-sci",
121 .id = 4,
122 .dev = {
123 .platform_data = &scif4_platform_data,
124 },
125};
126
127static struct plat_sci_port scif5_platform_data = {
128 .mapbase = 0xffe45000,
129 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
130 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
131 .scbrr_algo_id = SCBRR_ALGO_2,
132 .type = PORT_SCIF,
133 .irqs = { gic_spi(93), gic_spi(93),
134 gic_spi(93), gic_spi(93) },
135};
136
137static struct platform_device scif5_device = {
138 .name = "sh-sci",
139 .id = 5,
140 .dev = {
141 .platform_data = &scif5_platform_data,
142 },
143};
144
145/* TMU */
146static struct sh_timer_config tmu00_platform_data = {
147 .name = "TMU00",
148 .channel_offset = 0x4,
149 .timer_bit = 0,
150 .clockevent_rating = 200,
151};
152
153static struct resource tmu00_resources[] = {
154 [0] = {
155 .name = "TMU00",
156 .start = 0xffd80008,
157 .end = 0xffd80013,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = gic_spi(32),
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device tmu00_device = {
167 .name = "sh_tmu",
168 .id = 0,
169 .dev = {
170 .platform_data = &tmu00_platform_data,
171 },
172 .resource = tmu00_resources,
173 .num_resources = ARRAY_SIZE(tmu00_resources),
174};
175
176static struct sh_timer_config tmu01_platform_data = {
177 .name = "TMU01",
178 .channel_offset = 0x10,
179 .timer_bit = 1,
180 .clocksource_rating = 200,
181};
182
183static struct resource tmu01_resources[] = {
184 [0] = {
185 .name = "TMU01",
186 .start = 0xffd80014,
187 .end = 0xffd8001f,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = gic_spi(33),
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
196static struct platform_device tmu01_device = {
197 .name = "sh_tmu",
198 .id = 1,
199 .dev = {
200 .platform_data = &tmu01_platform_data,
201 },
202 .resource = tmu01_resources,
203 .num_resources = ARRAY_SIZE(tmu01_resources),
204};
205
206static struct platform_device *r8a7779_early_devices[] __initdata = {
207 &scif0_device,
208 &scif1_device,
209 &scif2_device,
210 &scif3_device,
211 &scif4_device,
212 &scif5_device,
213 &tmu00_device,
214 &tmu01_device,
215};
216
217static struct platform_device *r8a7779_late_devices[] __initdata = {
218};
219
220void __init r8a7779_add_standard_devices(void)
221{
222 r8a7779_pm_init();
223
224 r8a7779_init_pm_domain(&r8a7779_sh4a);
225 r8a7779_init_pm_domain(&r8a7779_sgx);
226 r8a7779_init_pm_domain(&r8a7779_vdp1);
227 r8a7779_init_pm_domain(&r8a7779_impx3);
228
229 platform_add_devices(r8a7779_early_devices,
230 ARRAY_SIZE(r8a7779_early_devices));
231 platform_add_devices(r8a7779_late_devices,
232 ARRAY_SIZE(r8a7779_late_devices));
233}
234
235void __init r8a7779_add_early_devices(void)
236{
237 early_platform_add_devices(r8a7779_early_devices,
238 ARRAY_SIZE(r8a7779_early_devices));
239}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index c197f9d29d04..1ea89be63e29 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -504,7 +504,7 @@ static struct resource sh7372_dmae0_resources[] = {
504 .flags = IORESOURCE_MEM, 504 .flags = IORESOURCE_MEM,
505 }, 505 },
506 { 506 {
507 /* DMA error IRQ */ 507 .name = "error_irq",
508 .start = evt2irq(0x20c0), 508 .start = evt2irq(0x20c0),
509 .end = evt2irq(0x20c0), 509 .end = evt2irq(0x20c0),
510 .flags = IORESOURCE_IRQ, 510 .flags = IORESOURCE_IRQ,
@@ -532,7 +532,7 @@ static struct resource sh7372_dmae1_resources[] = {
532 .flags = IORESOURCE_MEM, 532 .flags = IORESOURCE_MEM,
533 }, 533 },
534 { 534 {
535 /* DMA error IRQ */ 535 .name = "error_irq",
536 .start = evt2irq(0x21c0), 536 .start = evt2irq(0x21c0),
537 .end = evt2irq(0x21c0), 537 .end = evt2irq(0x21c0),
538 .flags = IORESOURCE_IRQ, 538 .flags = IORESOURCE_IRQ,
@@ -560,7 +560,7 @@ static struct resource sh7372_dmae2_resources[] = {
560 .flags = IORESOURCE_MEM, 560 .flags = IORESOURCE_MEM,
561 }, 561 },
562 { 562 {
563 /* DMA error IRQ */ 563 .name = "error_irq",
564 .start = evt2irq(0x22c0), 564 .start = evt2irq(0x22c0),
565 .end = evt2irq(0x22c0), 565 .end = evt2irq(0x22c0),
566 .flags = IORESOURCE_IRQ, 566 .flags = IORESOURCE_IRQ,
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index e46821c0a62e..20e71e5cace4 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -607,7 +607,7 @@ static struct resource sh73a0_dmae_resources[] = {
607 .flags = IORESOURCE_MEM, 607 .flags = IORESOURCE_MEM,
608 }, 608 },
609 { 609 {
610 /* DMA error IRQ */ 610 .name = "error_irq",
611 .start = gic_spi(129), 611 .start = gic_spi(129),
612 .end = gic_spi(129), 612 .end = gic_spi(129),
613 .flags = IORESOURCE_IRQ, 613 .flags = IORESOURCE_IRQ,
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
new file mode 100644
index 000000000000..cc97ef892d1b
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -0,0 +1,153 @@
1/*
2 * SMP support for R-Mobile / SH-Mobile - r8a7779 portion
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/smp.h>
23#include <linux/spinlock.h>
24#include <linux/io.h>
25#include <linux/delay.h>
26#include <mach/common.h>
27#include <mach/r8a7779.h>
28#include <asm/smp_scu.h>
29#include <asm/smp_twd.h>
30#include <asm/hardware/gic.h>
31
32#define AVECR 0xfe700040
33
34static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
35 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
36 .chan_bit = 1, /* ARM1 */
37 .isr_bit = 1, /* ARM1 */
38};
39
40static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
41 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
42 .chan_bit = 2, /* ARM2 */
43 .isr_bit = 2, /* ARM2 */
44};
45
46static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
47 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
48 .chan_bit = 3, /* ARM3 */
49 .isr_bit = 3, /* ARM3 */
50};
51
52static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
53 [1] = &r8a7779_ch_cpu1,
54 [2] = &r8a7779_ch_cpu2,
55 [3] = &r8a7779_ch_cpu3,
56};
57
58static void __iomem *scu_base_addr(void)
59{
60 return (void __iomem *)0xf0000000;
61}
62
63static DEFINE_SPINLOCK(scu_lock);
64static unsigned long tmp;
65
66static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
67{
68 void __iomem *scu_base = scu_base_addr();
69
70 spin_lock(&scu_lock);
71 tmp = __raw_readl(scu_base + 8);
72 tmp &= ~clr;
73 tmp |= set;
74 spin_unlock(&scu_lock);
75
76 /* disable cache coherency after releasing the lock */
77 __raw_writel(tmp, scu_base + 8);
78}
79
80unsigned int __init r8a7779_get_core_count(void)
81{
82 void __iomem *scu_base = scu_base_addr();
83
84#ifdef CONFIG_HAVE_ARM_TWD
85 /* twd_base needs to be initialized before percpu_timer_setup() */
86 twd_base = (void __iomem *)0xf0000600;
87#endif
88
89 return scu_get_core_count(scu_base);
90}
91
92int r8a7779_platform_cpu_kill(unsigned int cpu)
93{
94 struct r8a7779_pm_ch *ch = NULL;
95 int ret = -EIO;
96
97 cpu = cpu_logical_map(cpu);
98
99 /* disable cache coherency */
100 modify_scu_cpu_psr(3 << (cpu * 8), 0);
101
102 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
103 ch = r8a7779_ch_cpu[cpu];
104
105 if (ch)
106 ret = r8a7779_sysc_power_down(ch);
107
108 return ret ? ret : 1;
109}
110
111void __cpuinit r8a7779_secondary_init(unsigned int cpu)
112{
113 gic_secondary_init(0);
114}
115
116int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
117{
118 struct r8a7779_pm_ch *ch = NULL;
119 int ret = -EIO;
120
121 cpu = cpu_logical_map(cpu);
122
123 /* enable cache coherency */
124 modify_scu_cpu_psr(0, 3 << (cpu * 8));
125
126 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
127 ch = r8a7779_ch_cpu[cpu];
128
129 if (ch)
130 ret = r8a7779_sysc_power_up(ch);
131
132 return ret;
133}
134
135void __init r8a7779_smp_prepare_cpus(void)
136{
137 int cpu = cpu_logical_map(0);
138
139 scu_enable(scu_base_addr());
140
141 /* Map the reset vector (in headsmp.S) */
142 __raw_writel(__pa(shmobile_secondary_vector), __io(AVECR));
143
144 /* enable cache coherency on CPU0 */
145 modify_scu_cpu_psr(0, 3 << (cpu * 8));
146
147 r8a7779_pm_init();
148
149 /* power off secondary CPUs */
150 r8a7779_platform_cpu_kill(1);
151 r8a7779_platform_cpu_kill(2);
152 r8a7779_platform_cpu_kill(3);
153}
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c
index e7d127a9c1c5..522c6c46d1be 100644
--- a/drivers/sh/pfc.c
+++ b/drivers/sh/pfc.c
@@ -135,6 +135,19 @@ static void gpio_write_raw_reg(void __iomem *mapped_reg,
135 BUG(); 135 BUG();
136} 136}
137 137
138static int gpio_read_bit(struct pinmux_data_reg *dr,
139 unsigned long in_pos)
140{
141 unsigned long pos;
142
143 pos = dr->reg_width - (in_pos + 1);
144
145 pr_debug("read_bit: addr = %lx, pos = %ld, "
146 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
147
148 return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
149}
150
138static void gpio_write_bit(struct pinmux_data_reg *dr, 151static void gpio_write_bit(struct pinmux_data_reg *dr,
139 unsigned long in_pos, unsigned long value) 152 unsigned long in_pos, unsigned long value)
140{ 153{
@@ -154,51 +167,69 @@ static void gpio_write_bit(struct pinmux_data_reg *dr,
154 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); 167 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
155} 168}
156 169
157static int gpio_read_reg(void __iomem *mapped_reg, unsigned long reg_width, 170static void config_reg_helper(struct pinmux_info *gpioc,
158 unsigned long field_width, unsigned long in_pos, 171 struct pinmux_cfg_reg *crp,
159 unsigned long reg) 172 unsigned long in_pos,
173 void __iomem **mapped_regp,
174 unsigned long *maskp,
175 unsigned long *posp)
160{ 176{
161 unsigned long data, mask, pos; 177 int k;
162 178
163 data = 0; 179 *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
164 mask = (1 << field_width) - 1;
165 pos = reg_width - ((in_pos + 1) * field_width);
166 180
167 pr_debug("read_reg: addr = %lx, pos = %ld, " 181 if (crp->field_width) {
182 *maskp = (1 << crp->field_width) - 1;
183 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
184 } else {
185 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
186 *posp = crp->reg_width;
187 for (k = 0; k <= in_pos; k++)
188 *posp -= crp->var_field_width[k];
189 }
190}
191
192static int read_config_reg(struct pinmux_info *gpioc,
193 struct pinmux_cfg_reg *crp,
194 unsigned long field)
195{
196 void __iomem *mapped_reg;
197 unsigned long mask, pos;
198
199 config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
200
201 pr_debug("read_reg: addr = %lx, field = %ld, "
168 "r_width = %ld, f_width = %ld\n", 202 "r_width = %ld, f_width = %ld\n",
169 reg, pos, reg_width, field_width); 203 crp->reg, field, crp->reg_width, crp->field_width);
170 204
171 data = gpio_read_raw_reg(mapped_reg, reg_width); 205 return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
172 return (data >> pos) & mask;
173} 206}
174 207
175static void gpio_write_reg(void __iomem *mapped_reg, unsigned long reg_width, 208static void write_config_reg(struct pinmux_info *gpioc,
176 unsigned long field_width, unsigned long in_pos, 209 struct pinmux_cfg_reg *crp,
177 unsigned long value, unsigned long reg) 210 unsigned long field, unsigned long value)
178{ 211{
179 unsigned long mask, pos; 212 void __iomem *mapped_reg;
213 unsigned long mask, pos, data;
180 214
181 mask = (1 << field_width) - 1; 215 config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
182 pos = reg_width - ((in_pos + 1) * field_width);
183 216
184 pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, " 217 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
185 "r_width = %ld, f_width = %ld\n", 218 "r_width = %ld, f_width = %ld\n",
186 reg, value, pos, reg_width, field_width); 219 crp->reg, value, field, crp->reg_width, crp->field_width);
187 220
188 mask = ~(mask << pos); 221 mask = ~(mask << pos);
189 value = value << pos; 222 value = value << pos;
190 223
191 switch (reg_width) { 224 data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
192 case 8: 225 data &= mask;
193 iowrite8((ioread8(mapped_reg) & mask) | value, mapped_reg); 226 data |= value;
194 break; 227
195 case 16: 228 if (gpioc->unlock_reg)
196 iowrite16((ioread16(mapped_reg) & mask) | value, mapped_reg); 229 gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
197 break; 230 32, ~data);
198 case 32: 231
199 iowrite32((ioread32(mapped_reg) & mask) | value, mapped_reg); 232 gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
200 break;
201 }
202} 233}
203 234
204static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio) 235static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
@@ -274,12 +305,13 @@ static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
274} 305}
275 306
276static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, 307static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
277 struct pinmux_cfg_reg **crp, int *indexp, 308 struct pinmux_cfg_reg **crp,
309 int *fieldp, int *valuep,
278 unsigned long **cntp) 310 unsigned long **cntp)
279{ 311{
280 struct pinmux_cfg_reg *config_reg; 312 struct pinmux_cfg_reg *config_reg;
281 unsigned long r_width, f_width; 313 unsigned long r_width, f_width, curr_width, ncomb;
282 int k, n; 314 int k, m, n, pos, bit_pos;
283 315
284 k = 0; 316 k = 0;
285 while (1) { 317 while (1) {
@@ -290,13 +322,27 @@ static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
290 322
291 if (!r_width) 323 if (!r_width)
292 break; 324 break;
293 for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) { 325
294 if (config_reg->enum_ids[n] == enum_id) { 326 pos = 0;
295 *crp = config_reg; 327 m = 0;
296 *indexp = n; 328 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
297 *cntp = &config_reg->cnt[n / (1 << f_width)]; 329 if (f_width)
298 return 0; 330 curr_width = f_width;
331 else
332 curr_width = config_reg->var_field_width[m];
333
334 ncomb = 1 << curr_width;
335 for (n = 0; n < ncomb; n++) {
336 if (config_reg->enum_ids[pos + n] == enum_id) {
337 *crp = config_reg;
338 *fieldp = m;
339 *valuep = n;
340 *cntp = &config_reg->cnt[m];
341 return 0;
342 }
299 } 343 }
344 pos += ncomb;
345 m++;
300 } 346 }
301 k++; 347 k++;
302 } 348 }
@@ -334,43 +380,6 @@ static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
334 return -1; 380 return -1;
335} 381}
336 382
337static void write_config_reg(struct pinmux_info *gpioc,
338 struct pinmux_cfg_reg *crp,
339 int index)
340{
341 unsigned long ncomb, pos, value;
342 void __iomem *mapped_reg;
343
344 ncomb = 1 << crp->field_width;
345 pos = index / ncomb;
346 value = index % ncomb;
347
348 mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
349
350 gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width,
351 pos, value, crp->reg);
352}
353
354static int check_config_reg(struct pinmux_info *gpioc,
355 struct pinmux_cfg_reg *crp,
356 int index)
357{
358 unsigned long ncomb, pos, value;
359 void __iomem *mapped_reg;
360
361 ncomb = 1 << crp->field_width;
362 pos = index / ncomb;
363 value = index % ncomb;
364
365 mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
366
367 if (gpio_read_reg(mapped_reg, crp->reg_width,
368 crp->field_width, pos, crp->reg) == value)
369 return 0;
370
371 return -1;
372}
373
374enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; 383enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
375 384
376static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, 385static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
@@ -379,7 +388,7 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
379 struct pinmux_cfg_reg *cr = NULL; 388 struct pinmux_cfg_reg *cr = NULL;
380 pinmux_enum_t enum_id; 389 pinmux_enum_t enum_id;
381 struct pinmux_range *range; 390 struct pinmux_range *range;
382 int in_range, pos, index; 391 int in_range, pos, field, value;
383 unsigned long *cntp; 392 unsigned long *cntp;
384 393
385 switch (pinmux_type) { 394 switch (pinmux_type) {
@@ -410,7 +419,8 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
410 419
411 pos = 0; 420 pos = 0;
412 enum_id = 0; 421 enum_id = 0;
413 index = 0; 422 field = 0;
423 value = 0;
414 while (1) { 424 while (1) {
415 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id); 425 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
416 if (pos <= 0) 426 if (pos <= 0)
@@ -457,17 +467,19 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
457 if (!in_range) 467 if (!in_range)
458 continue; 468 continue;
459 469
460 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0) 470 if (get_config_reg(gpioc, enum_id, &cr,
471 &field, &value, &cntp) != 0)
461 goto out_err; 472 goto out_err;
462 473
463 switch (cfg_mode) { 474 switch (cfg_mode) {
464 case GPIO_CFG_DRYRUN: 475 case GPIO_CFG_DRYRUN:
465 if (!*cntp || !check_config_reg(gpioc, cr, index)) 476 if (!*cntp ||
477 (read_config_reg(gpioc, cr, field) != value))
466 continue; 478 continue;
467 break; 479 break;
468 480
469 case GPIO_CFG_REQ: 481 case GPIO_CFG_REQ:
470 write_config_reg(gpioc, cr, index); 482 write_config_reg(gpioc, cr, field, value);
471 *cntp = *cntp + 1; 483 *cntp = *cntp + 1;
472 break; 484 break;
473 485
@@ -644,7 +656,7 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
644 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) 656 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
645 return -EINVAL; 657 return -EINVAL;
646 658
647 return gpio_read_reg(dr->mapped_reg, dr->reg_width, 1, bit, dr->reg); 659 return gpio_read_bit(dr, bit);
648} 660}
649 661
650static int sh_gpio_get(struct gpio_chip *chip, unsigned offset) 662static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index e9bed038aa1f..a1a2d364f92b 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -17,7 +17,9 @@
17 defined(CONFIG_ARCH_SH73A0) || \ 17 defined(CONFIG_ARCH_SH73A0) || \
18 defined(CONFIG_ARCH_SH7367) || \ 18 defined(CONFIG_ARCH_SH7367) || \
19 defined(CONFIG_ARCH_SH7377) || \ 19 defined(CONFIG_ARCH_SH7377) || \
20 defined(CONFIG_ARCH_SH7372) 20 defined(CONFIG_ARCH_SH7372) || \
21 defined(CONFIG_ARCH_R8A7740)
22
21# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 23# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
22# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 24# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
23# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 25# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
diff --git a/include/linux/sh_pfc.h b/include/linux/sh_pfc.h
index 91666a58529d..5c15aed9c4b2 100644
--- a/include/linux/sh_pfc.h
+++ b/include/linux/sh_pfc.h
@@ -45,12 +45,19 @@ struct pinmux_cfg_reg {
45 unsigned long reg, reg_width, field_width; 45 unsigned long reg, reg_width, field_width;
46 unsigned long *cnt; 46 unsigned long *cnt;
47 pinmux_enum_t *enum_ids; 47 pinmux_enum_t *enum_ids;
48 unsigned long *var_field_width;
48}; 49};
49 50
50#define PINMUX_CFG_REG(name, r, r_width, f_width) \ 51#define PINMUX_CFG_REG(name, r, r_width, f_width) \
51 .reg = r, .reg_width = r_width, .field_width = f_width, \ 52 .reg = r, .reg_width = r_width, .field_width = f_width, \
52 .cnt = (unsigned long [r_width / f_width]) {}, \ 53 .cnt = (unsigned long [r_width / f_width]) {}, \
53 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \ 54 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
55
56#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
57 .reg = r, .reg_width = r_width, \
58 .cnt = (unsigned long [r_width]) {}, \
59 .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
60 .enum_ids = (pinmux_enum_t [])
54 61
55struct pinmux_data_reg { 62struct pinmux_data_reg {
56 unsigned long reg, reg_width, reg_shadow; 63 unsigned long reg, reg_width, reg_shadow;
@@ -109,6 +116,8 @@ struct pinmux_info {
109 unsigned int num_resources; 116 unsigned int num_resources;
110 struct pfc_window *window; 117 struct pfc_window *window;
111 118
119 unsigned long unlock_reg;
120
112 struct gpio_chip chip; 121 struct gpio_chip chip;
113}; 122};
114 123
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 11:56:45 -0500