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-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c51
1 files changed, 49 insertions, 2 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index c8227b334e61..3e1b6b699184 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -61,6 +61,7 @@
61 61
62#define MSTPSR1 IOMEM(0xe6150038) 62#define MSTPSR1 IOMEM(0xe6150038)
63#define MSTPSR2 IOMEM(0xe6150040) 63#define MSTPSR2 IOMEM(0xe6150040)
64#define MSTPSR3 IOMEM(0xe6150048)
64#define MSTPSR5 IOMEM(0xe615003c) 65#define MSTPSR5 IOMEM(0xe615003c)
65#define MSTPSR7 IOMEM(0xe61501c4) 66#define MSTPSR7 IOMEM(0xe61501c4)
66#define MSTPSR8 IOMEM(0xe61509a0) 67#define MSTPSR8 IOMEM(0xe61509a0)
@@ -69,8 +70,8 @@
69 70
70#define MODEMR 0xE6160060 71#define MODEMR 0xE6160060
71#define SDCKCR 0xE6150074 72#define SDCKCR 0xE6150074
72#define SD2CKCR 0xE6150078 73#define SD1CKCR 0xE6150078
73#define SD3CKCR 0xE615007C 74#define SD2CKCR 0xE615026c
74#define MMC0CKCR 0xE6150240 75#define MMC0CKCR 0xE6150240
75#define MMC1CKCR 0xE6150244 76#define MMC1CKCR 0xE6150244
76#define SSPCKCR 0xE6150248 77#define SSPCKCR 0xE6150248
@@ -134,6 +135,39 @@ static struct clk *main_clks[] = {
134 &zs_clk, 135 &zs_clk,
135}; 136};
136 137
138/* SDHI (DIV4) clock */
139static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
140
141static struct clk_div_mult_table div4_div_mult_table = {
142 .divisors = divisors,
143 .nr_divisors = ARRAY_SIZE(divisors),
144};
145
146static struct clk_div4_table div4_table = {
147 .div_mult_table = &div4_div_mult_table,
148};
149
150enum {
151 DIV4_SDH, DIV4_SD0,
152 DIV4_NR
153};
154
155static struct clk div4_clks[DIV4_NR] = {
156 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
157 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
158};
159
160/* DIV6 clocks */
161enum {
162 DIV6_SD1, DIV6_SD2,
163 DIV6_NR
164};
165
166static struct clk div6_clks[DIV6_NR] = {
167 [DIV6_SD1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
168 [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
169};
170
137/* MSTP */ 171/* MSTP */
138enum { 172enum {
139 MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925, 173 MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
@@ -144,6 +178,7 @@ enum {
144 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720, 178 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
145 MSTP719, MSTP718, MSTP715, MSTP714, 179 MSTP719, MSTP718, MSTP715, MSTP714,
146 MSTP522, 180 MSTP522,
181 MSTP314, MSTP312, MSTP311,
147 MSTP216, MSTP207, MSTP206, 182 MSTP216, MSTP207, MSTP206,
148 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, 183 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
149 MSTP124, 184 MSTP124,
@@ -174,6 +209,9 @@ static struct clk mstp_clks[MSTP_NR] = {
174 [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */ 209 [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
175 [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */ 210 [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
176 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */ 211 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
212 [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
213 [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
214 [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
177 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */ 215 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
178 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */ 216 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
179 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */ 217 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
@@ -224,6 +262,9 @@ static struct clk_lookup lookups[] = {
224 CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */ 262 CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
225 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ 263 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
226 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ 264 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
265 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
266 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
267 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
227 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 268 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
228 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), 269 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
229 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), 270 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -286,6 +327,12 @@ void __init r8a7791_clock_init(void)
286 ret = clk_register(main_clks[k]); 327 ret = clk_register(main_clks[k]);
287 328
288 if (!ret) 329 if (!ret)
330 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
331
332 if (!ret)
333 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
334
335 if (!ret)
289 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 336 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
290 337
291 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 338 clkdev_add_table(lookups, ARRAY_SIZE(lookups));