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-rw-r--r--arch/arm/configs/at91sam9g45_defconfig175
-rw-r--r--arch/arm/configs/at91sam9rl_defconfig92
-rw-r--r--arch/arm/configs/at91x40_defconfig48
-rw-r--r--arch/arm/mach-at91/Kconfig20
-rw-r--r--arch/arm/mach-at91/Kconfig.non_dt58
-rw-r--r--arch/arm/mach-at91/Makefile12
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c450
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c1915
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c373
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c1260
-rw-r--r--arch/arm/mach-at91/at91x40.c93
-rw-r--r--arch/arm/mach-at91/at91x40_time.c85
-rw-r--r--arch/arm/mach-at91/board-eb01.c52
-rw-r--r--arch/arm/mach-at91/board-sam9m10g45ek.c527
-rw-r--r--arch/arm/mach-at91/board-sam9rlek.c333
-rw-r--r--arch/arm/mach-at91/generic.h3
-rw-r--r--arch/arm/mach-at91/include/mach/at91_dbgu.h3
-rw-r--r--arch/arm/mach-at91/include/mach/at91x40.h60
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h1
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-at91/include/mach/uncompress.h7
-rw-r--r--arch/arm/mach-at91/setup.c2
-rw-r--r--drivers/rtc/Kconfig2
23 files changed, 5 insertions, 5571 deletions
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
deleted file mode 100644
index f66d1a1b64bf..000000000000
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ /dev/null
@@ -1,175 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_SYSFS_DEPRECATED=y
6CONFIG_SYSFS_DEPRECATED_V2=y
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_CC_OPTIMIZE_FOR_SIZE=y
9CONFIG_EMBEDDED=y
10CONFIG_SLAB=y
11CONFIG_MODULES=y
12CONFIG_MODULE_UNLOAD=y
13# CONFIG_LBDAF is not set
14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_DEADLINE is not set
16# CONFIG_IOSCHED_CFQ is not set
17CONFIG_ARCH_AT91=y
18CONFIG_ARCH_AT91SAM9G45=y
19CONFIG_MACH_AT91SAM9M10G45EK=y
20CONFIG_MACH_AT91SAM9_DT=y
21CONFIG_AT91_SLOW_CLOCK=y
22CONFIG_AEABI=y
23CONFIG_UACCESS_WITH_MEMCPY=y
24CONFIG_ZBOOT_ROM_TEXT=0x0
25CONFIG_ZBOOT_ROM_BSS=0x0
26CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw"
27CONFIG_AUTO_ZRELADDR=y
28# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
29CONFIG_NET=y
30CONFIG_PACKET=y
31CONFIG_UNIX=y
32CONFIG_INET=y
33CONFIG_IP_MULTICAST=y
34CONFIG_IP_PNP=y
35CONFIG_IP_PNP_DHCP=y
36CONFIG_IP_PNP_BOOTP=y
37# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
38# CONFIG_INET_XFRM_MODE_TUNNEL is not set
39# CONFIG_INET_XFRM_MODE_BEET is not set
40# CONFIG_INET_DIAG is not set
41CONFIG_IPV6=y
42# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET6_XFRM_MODE_BEET is not set
45CONFIG_IPV6_SIT_6RD=y
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
47CONFIG_DEVTMPFS=y
48CONFIG_DEVTMPFS_MOUNT=y
49# CONFIG_STANDALONE is not set
50# CONFIG_PREVENT_FIRMWARE_BUILD is not set
51CONFIG_MTD=y
52CONFIG_MTD_CMDLINE_PARTS=y
53CONFIG_MTD_BLOCK=y
54CONFIG_MTD_DATAFLASH=y
55CONFIG_MTD_NAND=y
56CONFIG_MTD_NAND_ATMEL=y
57CONFIG_MTD_UBI=y
58CONFIG_MTD_UBI_GLUEBI=y
59CONFIG_BLK_DEV_LOOP=y
60CONFIG_BLK_DEV_RAM=y
61CONFIG_BLK_DEV_RAM_COUNT=4
62CONFIG_BLK_DEV_RAM_SIZE=8192
63CONFIG_ATMEL_TCLIB=y
64CONFIG_ATMEL_SSC=y
65CONFIG_SCSI=y
66CONFIG_BLK_DEV_SD=y
67# CONFIG_SCSI_LOWLEVEL is not set
68CONFIG_NETDEVICES=y
69CONFIG_MACB=y
70CONFIG_DAVICOM_PHY=y
71# CONFIG_INPUT_MOUSEDEV is not set
72CONFIG_INPUT_JOYDEV=y
73CONFIG_INPUT_EVDEV=y
74# CONFIG_KEYBOARD_ATKBD is not set
75CONFIG_KEYBOARD_QT1070=y
76CONFIG_KEYBOARD_QT2160=y
77CONFIG_KEYBOARD_GPIO=y
78# CONFIG_INPUT_MOUSE is not set
79CONFIG_INPUT_TOUCHSCREEN=y
80CONFIG_TOUCHSCREEN_ATMEL_MXT=m
81# CONFIG_SERIO is not set
82# CONFIG_LEGACY_PTYS is not set
83CONFIG_SERIAL_ATMEL=y
84CONFIG_SERIAL_ATMEL_CONSOLE=y
85CONFIG_HW_RANDOM=y
86CONFIG_I2C=y
87CONFIG_I2C_CHARDEV=y
88CONFIG_I2C_GPIO=y
89CONFIG_SPI=y
90CONFIG_SPI_ATMEL=y
91CONFIG_POWER_SUPPLY=y
92CONFIG_POWER_RESET=y
93# CONFIG_HWMON is not set
94CONFIG_WATCHDOG=y
95CONFIG_WATCHDOG_NOWAYOUT=y
96CONFIG_AT91SAM9X_WATCHDOG=y
97CONFIG_FB=y
98CONFIG_FB_ATMEL=y
99CONFIG_BACKLIGHT_LCD_SUPPORT=y
100CONFIG_LCD_CLASS_DEVICE=y
101CONFIG_BACKLIGHT_CLASS_DEVICE=y
102CONFIG_BACKLIGHT_ATMEL_LCDC=y
103# CONFIG_BACKLIGHT_GENERIC is not set
104CONFIG_BACKLIGHT_PWM=y
105CONFIG_FRAMEBUFFER_CONSOLE=y
106CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
107CONFIG_LOGO=y
108CONFIG_SOUND=y
109CONFIG_SND=y
110CONFIG_SND_SEQUENCER=y
111CONFIG_SND_MIXER_OSS=y
112CONFIG_SND_PCM_OSS=y
113# CONFIG_SND_SUPPORT_OLD_API is not set
114# CONFIG_SND_VERBOSE_PROCFS is not set
115# CONFIG_SND_DRIVERS is not set
116# CONFIG_SND_ARM is not set
117CONFIG_SND_ATMEL_AC97C=y
118# CONFIG_SND_SPI is not set
119# CONFIG_SND_USB is not set
120# CONFIG_USB_HID is not set
121CONFIG_USB=y
122CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
123CONFIG_USB_EHCI_HCD=y
124CONFIG_USB_OHCI_HCD=y
125CONFIG_USB_ACM=y
126CONFIG_USB_STORAGE=y
127CONFIG_USB_GADGET=y
128CONFIG_USB_ATMEL_USBA=y
129CONFIG_USB_G_MULTI=y
130CONFIG_USB_G_MULTI_CDC=y
131CONFIG_MMC=y
132# CONFIG_MMC_BLOCK_BOUNCE is not set
133CONFIG_MMC_ATMELMCI=y
134CONFIG_NEW_LEDS=y
135CONFIG_LEDS_CLASS=y
136CONFIG_LEDS_GPIO=y
137CONFIG_LEDS_PWM=y
138CONFIG_LEDS_TRIGGERS=y
139CONFIG_LEDS_TRIGGER_TIMER=y
140CONFIG_LEDS_TRIGGER_HEARTBEAT=y
141CONFIG_LEDS_TRIGGER_GPIO=y
142CONFIG_RTC_CLASS=y
143CONFIG_RTC_DRV_AT91RM9200=y
144CONFIG_DMADEVICES=y
145CONFIG_AT_HDMAC=y
146CONFIG_DMATEST=m
147# CONFIG_IOMMU_SUPPORT is not set
148CONFIG_IIO=y
149CONFIG_AT91_ADC=y
150CONFIG_PWM=y
151CONFIG_PWM_ATMEL=y
152CONFIG_EXT4_FS=y
153CONFIG_FANOTIFY=y
154CONFIG_VFAT_FS=y
155CONFIG_TMPFS=y
156CONFIG_UBIFS_FS=y
157CONFIG_UBIFS_FS_ADVANCED_COMPR=y
158CONFIG_NFS_FS=y
159CONFIG_ROOT_NFS=y
160CONFIG_NLS_CODEPAGE_437=y
161CONFIG_NLS_CODEPAGE_850=y
162CONFIG_NLS_ISO8859_1=y
163CONFIG_STRIP_ASM_SYMS=y
164CONFIG_DEBUG_MEMORY_INIT=y
165# CONFIG_SCHED_DEBUG is not set
166# CONFIG_FTRACE is not set
167CONFIG_DEBUG_USER=y
168CONFIG_DEBUG_LL=y
169CONFIG_EARLY_PRINTK=y
170CONFIG_CRYPTO_ECB=y
171# CONFIG_CRYPTO_ANSI_CPRNG is not set
172CONFIG_CRYPTO_USER_API_HASH=m
173CONFIG_CRYPTO_USER_API_SKCIPHER=m
174# CONFIG_CRYPTO_HW is not set
175CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
deleted file mode 100644
index 4c26d344ae88..000000000000
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ /dev/null
@@ -1,92 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_BLK_DEV_INITRD=y
6CONFIG_EMBEDDED=y
7CONFIG_SLAB=y
8CONFIG_MODULES=y
9CONFIG_MODULE_UNLOAD=y
10# CONFIG_BLK_DEV_BSG is not set
11# CONFIG_IOSCHED_DEADLINE is not set
12# CONFIG_IOSCHED_CFQ is not set
13CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91SAM9RL=y
15CONFIG_MACH_AT91SAM9RLEK=y
16# CONFIG_ARM_THUMB is not set
17CONFIG_AEABI=y
18CONFIG_ZBOOT_ROM_TEXT=0x0
19CONFIG_ZBOOT_ROM_BSS=0x0
20CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,17105363 root=/dev/ram0 rw"
21CONFIG_AUTO_ZRELADDR=y
22CONFIG_NET=y
23CONFIG_UNIX=y
24CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
25CONFIG_DEVTMPFS=y
26CONFIG_DEVTMPFS_MOUNT=y
27CONFIG_MTD=y
28CONFIG_MTD_CMDLINE_PARTS=y
29CONFIG_MTD_BLOCK=y
30CONFIG_MTD_DATAFLASH=y
31CONFIG_MTD_NAND=y
32CONFIG_MTD_NAND_ATMEL=y
33CONFIG_MTD_UBI=y
34CONFIG_BLK_DEV_LOOP=y
35CONFIG_BLK_DEV_RAM=y
36CONFIG_BLK_DEV_RAM_COUNT=4
37CONFIG_BLK_DEV_RAM_SIZE=24576
38CONFIG_SCSI=y
39CONFIG_BLK_DEV_SD=y
40# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
41CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
42CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
43CONFIG_INPUT_EVDEV=y
44# CONFIG_INPUT_KEYBOARD is not set
45# CONFIG_INPUT_MOUSE is not set
46CONFIG_INPUT_TOUCHSCREEN=y
47# CONFIG_SERIO is not set
48CONFIG_SERIAL_ATMEL=y
49CONFIG_SERIAL_ATMEL_CONSOLE=y
50# CONFIG_HW_RANDOM is not set
51CONFIG_I2C=y
52CONFIG_I2C_CHARDEV=y
53CONFIG_I2C_GPIO=y
54CONFIG_SPI=y
55CONFIG_SPI_ATMEL=y
56CONFIG_POWER_SUPPLY=y
57CONFIG_POWER_RESET=y
58# CONFIG_HWMON is not set
59CONFIG_WATCHDOG=y
60CONFIG_WATCHDOG_NOWAYOUT=y
61CONFIG_AT91SAM9X_WATCHDOG=y
62CONFIG_FB=y
63CONFIG_FB_ATMEL=y
64CONFIG_USB_GADGET=y
65CONFIG_USB_ATMEL_USBA=y
66CONFIG_MMC=y
67CONFIG_MMC_ATMELMCI=m
68CONFIG_NEW_LEDS=y
69CONFIG_LEDS_CLASS=y
70CONFIG_LEDS_GPIO=y
71CONFIG_LEDS_PWM=y
72CONFIG_LEDS_TRIGGERS=y
73CONFIG_LEDS_TRIGGER_HEARTBEAT=y
74CONFIG_RTC_CLASS=y
75CONFIG_RTC_DRV_AT91SAM9=y
76CONFIG_IIO=y
77CONFIG_AT91_ADC=y
78CONFIG_PWM=y
79CONFIG_PWM_ATMEL=y
80CONFIG_EXT4_FS=y
81CONFIG_VFAT_FS=y
82CONFIG_TMPFS=y
83CONFIG_UBIFS_FS=y
84CONFIG_CRAMFS=y
85CONFIG_NLS_CODEPAGE_437=y
86CONFIG_NLS_CODEPAGE_850=y
87CONFIG_NLS_ISO8859_1=y
88CONFIG_NLS_ISO8859_15=y
89CONFIG_NLS_UTF8=y
90CONFIG_DEBUG_INFO=y
91CONFIG_DEBUG_USER=y
92CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/at91x40_defconfig b/arch/arm/configs/at91x40_defconfig
deleted file mode 100644
index c55e9212fcbb..000000000000
--- a/arch/arm/configs/at91x40_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOG_BUF_SHIFT=14
3CONFIG_EMBEDDED=y
4# CONFIG_HOTPLUG is not set
5# CONFIG_ELF_CORE is not set
6# CONFIG_FUTEX is not set
7# CONFIG_TIMERFD is not set
8# CONFIG_VM_EVENT_COUNTERS is not set
9# CONFIG_COMPAT_BRK is not set
10CONFIG_SLAB=y
11# CONFIG_LBDAF is not set
12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set
15# CONFIG_MMU is not set
16CONFIG_ARCH_AT91=y
17CONFIG_ARCH_AT91X40=y
18CONFIG_MACH_AT91EB01=y
19CONFIG_AT91_EARLY_USART0=y
20CONFIG_CPU_ARM7TDMI=y
21CONFIG_SET_MEM_PARAM=y
22CONFIG_DRAM_BASE=0x01000000
23CONFIG_DRAM_SIZE=0x00400000
24CONFIG_FLASH_MEM_BASE=0x01400000
25CONFIG_PROCESSOR_ID=0x14000040
26CONFIG_ZBOOT_ROM_TEXT=0x0
27CONFIG_ZBOOT_ROM_BSS=0x0
28CONFIG_BINFMT_FLAT=y
29# CONFIG_SUSPEND is not set
30# CONFIG_FW_LOADER is not set
31CONFIG_MTD=y
32CONFIG_MTD_PARTITIONS=y
33CONFIG_MTD_CHAR=y
34CONFIG_MTD_BLOCK=y
35CONFIG_MTD_RAM=y
36CONFIG_MTD_ROM=y
37CONFIG_BLK_DEV_RAM=y
38# CONFIG_INPUT is not set
39# CONFIG_SERIO is not set
40# CONFIG_VT is not set
41# CONFIG_DEVKMEM is not set
42# CONFIG_HW_RANDOM is not set
43# CONFIG_HWMON is not set
44# CONFIG_USB_SUPPORT is not set
45CONFIG_EXT2_FS=y
46# CONFIG_DNOTIFY is not set
47CONFIG_ROMFS_FS=y
48# CONFIG_ENABLE_MUST_CHECK is not set
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0e6d548b70d9..a82ee4e7e980 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -18,18 +18,14 @@ config HAVE_AT91_DBGU2
18config AT91_USE_OLD_CLK 18config AT91_USE_OLD_CLK
19 bool 19 bool
20 20
21config AT91_PMC_UNIT
22 bool
23 default !ARCH_AT91X40
24
25config COMMON_CLK_AT91 21config COMMON_CLK_AT91
26 bool 22 bool
27 default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK 23 default USE_OF && !AT91_USE_OLD_CLK
28 select COMMON_CLK 24 select COMMON_CLK
29 25
30config OLD_CLK_AT91 26config OLD_CLK_AT91
31 bool 27 bool
32 default AT91_PMC_UNIT && AT91_USE_OLD_CLK 28 default AT91_USE_OLD_CLK
33 29
34config OLD_IRQ_AT91 30config OLD_IRQ_AT91
35 bool 31 bool
@@ -65,16 +61,6 @@ choice
65 61
66 prompt "Core type" 62 prompt "Core type"
67 63
68config ARCH_AT91X40
69 bool "ARM7 AT91X40"
70 depends on !MMU
71 select CPU_ARM7TDMI
72 select ARCH_USES_GETTIMEOFFSET
73 select OLD_IRQ_AT91
74
75 help
76 Select this if you are using one of Atmel's AT91X40 SoC.
77
78config SOC_SAM_V4_V5 64config SOC_SAM_V4_V5
79 bool "ARM9 AT91SAM9/AT91RM9200" 65 bool "ARM9 AT91SAM9/AT91RM9200"
80 help 66 help
@@ -199,7 +185,7 @@ config SOC_AT91SAM9N12
199endif # SOC_SAM_V4_V5 185endif # SOC_SAM_V4_V5
200 186
201 187
202if SOC_SAM_V4_V5 || ARCH_AT91X40 188if SOC_SAM_V4_V5
203source arch/arm/mach-at91/Kconfig.non_dt 189source arch/arm/mach-at91/Kconfig.non_dt
204endif 190endif
205 191
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index d8e88219edb4..22963a829e5c 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -5,7 +5,6 @@ config HAVE_AT91_DATAFLASH_CARD
5 5
6choice 6choice
7 prompt "Atmel AT91 Processor Devices for non DT boards" 7 prompt "Atmel AT91 Processor Devices for non DT boards"
8 depends on !ARCH_AT91X40
9 8
10config ARCH_AT91_NONE 9config ARCH_AT91_NONE
11 bool "None" 10 bool "None"
@@ -34,18 +33,6 @@ config ARCH_AT91SAM9263
34 select AT91_USE_OLD_CLK 33 select AT91_USE_OLD_CLK
35 select OLD_IRQ_AT91 34 select OLD_IRQ_AT91
36 35
37config ARCH_AT91SAM9RL
38 bool "AT91SAM9RL"
39 select SOC_AT91SAM9RL
40 select AT91_USE_OLD_CLK
41 select OLD_IRQ_AT91
42
43config ARCH_AT91SAM9G45
44 bool "AT91SAM9G45"
45 select SOC_AT91SAM9G45
46 select AT91_USE_OLD_CLK
47 select OLD_IRQ_AT91
48
49endchoice 36endchoice
50 37
51config ARCH_AT91SAM9G20 38config ARCH_AT91SAM9G20
@@ -288,51 +275,6 @@ endif
288 275
289# ---------------------------------------------------------- 276# ----------------------------------------------------------
290 277
291if ARCH_AT91SAM9RL
292
293comment "AT91SAM9RL Board Type"
294
295config MACH_AT91SAM9RLEK
296 bool "Atmel AT91SAM9RL-EK Evaluation Kit"
297 help
298 Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
299
300endif
301
302# ----------------------------------------------------------
303
304if ARCH_AT91SAM9G45
305
306comment "AT91SAM9G45 Board Type"
307
308config MACH_AT91SAM9M10G45EK
309 bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
310 help
311 Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
312 Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
313 families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
314 <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
315
316endif
317
318# ----------------------------------------------------------
319
320if ARCH_AT91X40
321
322comment "AT91X40 Board Type"
323
324config MACH_AT91EB01
325 bool "Atmel AT91EB01 Evaluation Kit"
326 help
327 Select this if you are using Atmel's AT91EB01 Evaluation Kit.
328 It is also a popular target for simulators such as GDB's
329 ARM simulator (commonly known as the ARMulator) and the
330 Skyeye simulator.
331
332endif
333
334# ----------------------------------------------------------
335
336comment "AT91 Board Options" 278comment "AT91 Board Options"
337 279
338config MTD_AT91_DATAFLASH_CARD 280config MTD_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 1b9ae0257a6e..df48363d7384 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -24,9 +24,6 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
24obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o 24obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
25obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o 25obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o
26obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o 26obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o
27obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o
28obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o
29obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
30 27
31# AT91RM9200 board-specific support 28# AT91RM9200 board-specific support
32obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 29obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
@@ -58,9 +55,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
58# AT91SAM9263 board-specific support 55# AT91SAM9263 board-specific support
59obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o 56obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
60 57
61# AT91SAM9RL board-specific support
62obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
63
64# AT91SAM9G20 board-specific support 58# AT91SAM9G20 board-specific support
65obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o 59obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
66obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o 60obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
@@ -72,9 +66,6 @@ obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o
72# AT91SAM9260/AT91SAM9G20 board-specific support 66# AT91SAM9260/AT91SAM9G20 board-specific support
73obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o 67obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
74 68
75# AT91SAM9G45 board-specific support
76obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
77
78# AT91SAM board with device-tree 69# AT91SAM board with device-tree
79obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o 70obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
80obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o 71obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
@@ -82,9 +73,6 @@ obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
82# SAMA5 board with device-tree 73# SAMA5 board with device-tree
83obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o 74obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o
84 75
85# AT91X40 board-specific support
86obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
87
88# Drivers 76# Drivers
89obj-y += leds.o 77obj-y += leds.o
90 78
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9c4c4cebfdf1..dd03f652cca4 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -10,358 +10,12 @@
10 * 10 *
11 */ 11 */
12 12
13#include <linux/module.h>
14#include <linux/dma-mapping.h>
15#include <linux/clk/at91_pmc.h>
16#include <linux/platform_device.h>
17
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/system_misc.h> 13#include <asm/system_misc.h>
22#include <mach/at91sam9g45.h>
23#include <mach/cpu.h> 14#include <mach/cpu.h>
24#include <mach/hardware.h> 15#include <mach/hardware.h>
25 16
26#include "at91_aic.h"
27#include "soc.h" 17#include "soc.h"
28#include "generic.h" 18#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32#if defined(CONFIG_OLD_CLK_AT91)
33#include "clock.h"
34/* --------------------------------------------------------------------
35 * Clocks
36 * -------------------------------------------------------------------- */
37
38/*
39 * The peripheral clocks.
40 */
41static struct clk pioA_clk = {
42 .name = "pioA_clk",
43 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioB_clk = {
47 .name = "pioB_clk",
48 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk pioC_clk = {
52 .name = "pioC_clk",
53 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk pioDE_clk = {
57 .name = "pioDE_clk",
58 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk trng_clk = {
62 .name = "trng_clk",
63 .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk usart0_clk = {
67 .name = "usart0_clk",
68 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk usart1_clk = {
72 .name = "usart1_clk",
73 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk usart2_clk = {
77 .name = "usart2_clk",
78 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk usart3_clk = {
82 .name = "usart3_clk",
83 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk mmc0_clk = {
87 .name = "mci0_clk",
88 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk twi0_clk = {
92 .name = "twi0_clk",
93 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk twi1_clk = {
97 .name = "twi1_clk",
98 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk spi0_clk = {
102 .name = "spi0_clk",
103 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk spi1_clk = {
107 .name = "spi1_clk",
108 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk ssc0_clk = {
112 .name = "ssc0_clk",
113 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk ssc1_clk = {
117 .name = "ssc1_clk",
118 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk tcb0_clk = {
122 .name = "tcb0_clk",
123 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk pwm_clk = {
127 .name = "pwm_clk",
128 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk tsc_clk = {
132 .name = "tsc_clk",
133 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk dma_clk = {
137 .name = "dma_clk",
138 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk uhphs_clk = {
142 .name = "uhphs_clk",
143 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk lcdc_clk = {
147 .name = "lcdc_clk",
148 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151static struct clk ac97_clk = {
152 .name = "ac97_clk",
153 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
154 .type = CLK_TYPE_PERIPHERAL,
155};
156static struct clk macb_clk = {
157 .name = "pclk",
158 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
159 .type = CLK_TYPE_PERIPHERAL,
160};
161static struct clk isi_clk = {
162 .name = "isi_clk",
163 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
164 .type = CLK_TYPE_PERIPHERAL,
165};
166static struct clk udphs_clk = {
167 .name = "udphs_clk",
168 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
169 .type = CLK_TYPE_PERIPHERAL,
170};
171static struct clk mmc1_clk = {
172 .name = "mci1_clk",
173 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
174 .type = CLK_TYPE_PERIPHERAL,
175};
176
177/* Video decoder clock - Only for sam9m10/sam9m11 */
178static struct clk vdec_clk = {
179 .name = "vdec_clk",
180 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
181 .type = CLK_TYPE_PERIPHERAL,
182};
183
184static struct clk adc_op_clk = {
185 .name = "adc_op_clk",
186 .type = CLK_TYPE_PERIPHERAL,
187 .rate_hz = 300000,
188};
189
190/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
191static struct clk aestdessha_clk = {
192 .name = "aestdessha_clk",
193 .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
194 .type = CLK_TYPE_PERIPHERAL,
195};
196
197static struct clk *periph_clocks[] __initdata = {
198 &pioA_clk,
199 &pioB_clk,
200 &pioC_clk,
201 &pioDE_clk,
202 &trng_clk,
203 &usart0_clk,
204 &usart1_clk,
205 &usart2_clk,
206 &usart3_clk,
207 &mmc0_clk,
208 &twi0_clk,
209 &twi1_clk,
210 &spi0_clk,
211 &spi1_clk,
212 &ssc0_clk,
213 &ssc1_clk,
214 &tcb0_clk,
215 &pwm_clk,
216 &tsc_clk,
217 &dma_clk,
218 &uhphs_clk,
219 &lcdc_clk,
220 &ac97_clk,
221 &macb_clk,
222 &isi_clk,
223 &udphs_clk,
224 &mmc1_clk,
225 &adc_op_clk,
226 &aestdessha_clk,
227 // irq0
228};
229
230static struct clk_lookup periph_clocks_lookups[] = {
231 /* One additional fake clock for macb_hclk */
232 CLKDEV_CON_ID("hclk", &macb_clk),
233 /* One additional fake clock for ohci */
234 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
235 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
236 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
237 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
238 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
239 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
240 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
241 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
242 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
243 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
244 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
245 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
246 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
247 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
248 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
249 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
250 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
251 CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
252 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
253 CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
254 CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
255 CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
256 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
257 CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k),
258 /* more usart lookup table for DT entries */
259 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
260 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
261 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
262 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
263 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
264 /* more tc lookup table for DT entries */
265 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
266 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
267 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
268 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
269 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
270 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
271 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
272 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
273 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
274 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
275 CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
276 CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
277 /* fake hclk clock */
278 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
279 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
280 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
281 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
282 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
283 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
284 CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k),
285
286 CLKDEV_CON_ID("pioA", &pioA_clk),
287 CLKDEV_CON_ID("pioB", &pioB_clk),
288 CLKDEV_CON_ID("pioC", &pioC_clk),
289 CLKDEV_CON_ID("pioD", &pioDE_clk),
290 CLKDEV_CON_ID("pioE", &pioDE_clk),
291 /* Fake adc clock */
292 CLKDEV_CON_ID("adc_clk", &tsc_clk),
293 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
294};
295
296static struct clk_lookup usart_clocks_lookups[] = {
297 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
298 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
299 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
300 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
301 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
302};
303
304/*
305 * The two programmable clocks.
306 * You must configure pin multiplexing to bring these signals out.
307 */
308static struct clk pck0 = {
309 .name = "pck0",
310 .pmc_mask = AT91_PMC_PCK0,
311 .type = CLK_TYPE_PROGRAMMABLE,
312 .id = 0,
313};
314static struct clk pck1 = {
315 .name = "pck1",
316 .pmc_mask = AT91_PMC_PCK1,
317 .type = CLK_TYPE_PROGRAMMABLE,
318 .id = 1,
319};
320
321static void __init at91sam9g45_register_clocks(void)
322{
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
326 clk_register(periph_clocks[i]);
327
328 clkdev_add_table(periph_clocks_lookups,
329 ARRAY_SIZE(periph_clocks_lookups));
330 clkdev_add_table(usart_clocks_lookups,
331 ARRAY_SIZE(usart_clocks_lookups));
332
333 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
334 clk_register(&vdec_clk);
335
336 clk_register(&pck0);
337 clk_register(&pck1);
338}
339#else
340#define at91sam9g45_register_clocks NULL
341#endif
342
343/* --------------------------------------------------------------------
344 * GPIO
345 * -------------------------------------------------------------------- */
346
347static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
348 {
349 .id = AT91SAM9G45_ID_PIOA,
350 .regbase = AT91SAM9G45_BASE_PIOA,
351 }, {
352 .id = AT91SAM9G45_ID_PIOB,
353 .regbase = AT91SAM9G45_BASE_PIOB,
354 }, {
355 .id = AT91SAM9G45_ID_PIOC,
356 .regbase = AT91SAM9G45_BASE_PIOC,
357 }, {
358 .id = AT91SAM9G45_ID_PIODE,
359 .regbase = AT91SAM9G45_BASE_PIOD,
360 }, {
361 .id = AT91SAM9G45_ID_PIODE,
362 .regbase = AT91SAM9G45_BASE_PIOE,
363 }
364};
365 19
366/* -------------------------------------------------------------------- 20/* --------------------------------------------------------------------
367 * AT91SAM9G45 processor initialization 21 * AT91SAM9G45 processor initialization
@@ -372,113 +26,14 @@ static void __init at91sam9g45_map_io(void)
372 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE); 26 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
373} 27}
374 28
375static void __init at91sam9g45_ioremap_registers(void)
376{
377 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
378 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
379 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
380 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
381 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
382 at91_pm_set_standby(at91_ddr_standby);
383}
384
385static void __init at91sam9g45_initialize(void) 29static void __init at91sam9g45_initialize(void)
386{ 30{
387 arm_pm_idle = at91sam9_idle; 31 arm_pm_idle = at91sam9_idle;
388 32
389 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC); 33 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
390 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT); 34 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
391
392 /* Register GPIO subsystem */
393 at91_gpio_init(at91sam9g45_gpio, 5);
394}
395
396static struct resource rstc_resources[] = {
397 [0] = {
398 .start = AT91SAM9G45_BASE_RSTC,
399 .end = AT91SAM9G45_BASE_RSTC + SZ_16 - 1,
400 .flags = IORESOURCE_MEM,
401 },
402 [1] = {
403 .start = AT91SAM9G45_BASE_DDRSDRC1,
404 .end = AT91SAM9G45_BASE_DDRSDRC1 + SZ_512 - 1,
405 .flags = IORESOURCE_MEM,
406 },
407 [2] = {
408 .start = AT91SAM9G45_BASE_DDRSDRC0,
409 .end = AT91SAM9G45_BASE_DDRSDRC0 + SZ_512 - 1,
410 .flags = IORESOURCE_MEM,
411 },
412};
413
414static struct platform_device rstc_device = {
415 .name = "at91-sam9g45-reset",
416 .resource = rstc_resources,
417 .num_resources = ARRAY_SIZE(rstc_resources),
418};
419
420static struct resource shdwc_resources[] = {
421 [0] = {
422 .start = AT91SAM9G45_BASE_SHDWC,
423 .end = AT91SAM9G45_BASE_SHDWC + SZ_16 - 1,
424 .flags = IORESOURCE_MEM,
425 },
426};
427
428static struct platform_device shdwc_device = {
429 .name = "at91-poweroff",
430 .resource = shdwc_resources,
431 .num_resources = ARRAY_SIZE(shdwc_resources),
432};
433
434static void __init at91sam9g45_register_devices(void)
435{
436 platform_device_register(&rstc_device);
437 platform_device_register(&shdwc_device);
438} 35}
439 36
440/* --------------------------------------------------------------------
441 * Interrupt initialization
442 * -------------------------------------------------------------------- */
443
444/*
445 * The default interrupt priority levels (0 = lowest, 7 = highest).
446 */
447static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
448 7, /* Advanced Interrupt Controller (FIQ) */
449 7, /* System Peripherals */
450 1, /* Parallel IO Controller A */
451 1, /* Parallel IO Controller B */
452 1, /* Parallel IO Controller C */
453 1, /* Parallel IO Controller D and E */
454 0,
455 5, /* USART 0 */
456 5, /* USART 1 */
457 5, /* USART 2 */
458 5, /* USART 3 */
459 0, /* Multimedia Card Interface 0 */
460 6, /* Two-Wire Interface 0 */
461 6, /* Two-Wire Interface 1 */
462 5, /* Serial Peripheral Interface 0 */
463 5, /* Serial Peripheral Interface 1 */
464 4, /* Serial Synchronous Controller 0 */
465 4, /* Serial Synchronous Controller 1 */
466 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
467 0, /* Pulse Width Modulation Controller */
468 0, /* Touch Screen Controller */
469 0, /* DMA Controller */
470 2, /* USB Host High Speed port */
471 3, /* LDC Controller */
472 5, /* AC97 Controller */
473 3, /* Ethernet */
474 0, /* Image Sensor Interface */
475 2, /* USB Device High speed port */
476 0, /* AESTDESSHA Crypto HW Accelerators */
477 0, /* Multimedia Card Interface 1 */
478 0,
479 0, /* Advanced Interrupt Controller (IRQ0) */
480};
481
482static void __init at91sam9g45_init_time(void) 37static void __init at91sam9g45_init_time(void)
483{ 38{
484 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS); 39 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
@@ -486,11 +41,6 @@ static void __init at91sam9g45_init_time(void)
486 41
487AT91_SOC_START(at91sam9g45) 42AT91_SOC_START(at91sam9g45)
488 .map_io = at91sam9g45_map_io, 43 .map_io = at91sam9g45_map_io,
489 .default_irq_priority = at91sam9g45_default_irq_priority,
490 .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
491 .ioremap_registers = at91sam9g45_ioremap_registers,
492 .register_clocks = at91sam9g45_register_clocks,
493 .register_devices = at91sam9g45_register_devices,
494 .init = at91sam9g45_initialize, 44 .init = at91sam9g45_initialize,
495 .init_time = at91sam9g45_init_time, 45 .init_time = at91sam9g45_init_time,
496AT91_SOC_END 46AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
deleted file mode 100644
index 21ab782cc8e9..000000000000
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ /dev/null
@@ -1,1915 +0,0 @@
1/*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
19#include <linux/i2c-gpio.h>
20#include <linux/atmel-mci.h>
21#include <linux/platform_data/crypto-atmel.h>
22
23#include <linux/platform_data/at91_adc.h>
24
25#include <linux/fb.h>
26#include <video/atmel_lcdc.h>
27
28#include <mach/at91sam9g45.h>
29#include <mach/at91sam9g45_matrix.h>
30#include <mach/at91_matrix.h>
31#include <mach/at91sam9_smc.h>
32#include <linux/platform_data/dma-atmel.h>
33#include <mach/atmel-mci.h>
34#include <mach/hardware.h>
35
36#include <media/atmel-isi.h>
37
38#include "board.h"
39#include "generic.h"
40#include "clock.h"
41#include "gpio.h"
42
43
44/* --------------------------------------------------------------------
45 * HDMAC - AHB DMA Controller
46 * -------------------------------------------------------------------- */
47
48#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
49static u64 hdmac_dmamask = DMA_BIT_MASK(32);
50
51static struct resource hdmac_resources[] = {
52 [0] = {
53 .start = AT91SAM9G45_BASE_DMA,
54 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
59 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
60 .flags = IORESOURCE_IRQ,
61 },
62};
63
64static struct platform_device at_hdmac_device = {
65 .name = "at91sam9g45_dma",
66 .id = -1,
67 .dev = {
68 .dma_mask = &hdmac_dmamask,
69 .coherent_dma_mask = DMA_BIT_MASK(32),
70 },
71 .resource = hdmac_resources,
72 .num_resources = ARRAY_SIZE(hdmac_resources),
73};
74
75void __init at91_add_device_hdmac(void)
76{
77 platform_device_register(&at_hdmac_device);
78}
79#else
80void __init at91_add_device_hdmac(void) {}
81#endif
82
83
84/* --------------------------------------------------------------------
85 * USB Host (OHCI)
86 * -------------------------------------------------------------------- */
87
88#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
89static u64 ohci_dmamask = DMA_BIT_MASK(32);
90static struct at91_usbh_data usbh_ohci_data;
91
92static struct resource usbh_ohci_resources[] = {
93 [0] = {
94 .start = AT91SAM9G45_OHCI_BASE,
95 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
100 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
101 .flags = IORESOURCE_IRQ,
102 },
103};
104
105static struct platform_device at91_usbh_ohci_device = {
106 .name = "at91_ohci",
107 .id = -1,
108 .dev = {
109 .dma_mask = &ohci_dmamask,
110 .coherent_dma_mask = DMA_BIT_MASK(32),
111 .platform_data = &usbh_ohci_data,
112 },
113 .resource = usbh_ohci_resources,
114 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
115};
116
117void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
118{
119 int i;
120
121 if (!data)
122 return;
123
124 /* Enable VBus control for UHP ports */
125 for (i = 0; i < data->ports; i++) {
126 if (gpio_is_valid(data->vbus_pin[i]))
127 at91_set_gpio_output(data->vbus_pin[i],
128 data->vbus_pin_active_low[i]);
129 }
130
131 /* Enable overcurrent notification */
132 for (i = 0; i < data->ports; i++) {
133 if (gpio_is_valid(data->overcurrent_pin[i]))
134 at91_set_gpio_input(data->overcurrent_pin[i], 1);
135 }
136
137 usbh_ohci_data = *data;
138 platform_device_register(&at91_usbh_ohci_device);
139}
140#else
141void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
142#endif
143
144
145/* --------------------------------------------------------------------
146 * USB Host HS (EHCI)
147 * Needs an OHCI host for low and full speed management
148 * -------------------------------------------------------------------- */
149
150#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
151static u64 ehci_dmamask = DMA_BIT_MASK(32);
152static struct at91_usbh_data usbh_ehci_data;
153
154static struct resource usbh_ehci_resources[] = {
155 [0] = {
156 .start = AT91SAM9G45_EHCI_BASE,
157 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
162 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
163 .flags = IORESOURCE_IRQ,
164 },
165};
166
167static struct platform_device at91_usbh_ehci_device = {
168 .name = "atmel-ehci",
169 .id = -1,
170 .dev = {
171 .dma_mask = &ehci_dmamask,
172 .coherent_dma_mask = DMA_BIT_MASK(32),
173 .platform_data = &usbh_ehci_data,
174 },
175 .resource = usbh_ehci_resources,
176 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
177};
178
179void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
180{
181 int i;
182
183 if (!data)
184 return;
185
186 /* Enable VBus control for UHP ports */
187 for (i = 0; i < data->ports; i++) {
188 if (gpio_is_valid(data->vbus_pin[i]))
189 at91_set_gpio_output(data->vbus_pin[i],
190 data->vbus_pin_active_low[i]);
191 }
192
193 usbh_ehci_data = *data;
194 platform_device_register(&at91_usbh_ehci_device);
195}
196#else
197void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
198#endif
199
200
201/* --------------------------------------------------------------------
202 * USB HS Device (Gadget)
203 * -------------------------------------------------------------------- */
204
205#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
206static struct resource usba_udc_resources[] = {
207 [0] = {
208 .start = AT91SAM9G45_UDPHS_FIFO,
209 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = AT91SAM9G45_BASE_UDPHS,
214 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 [2] = {
218 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
219 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
225 [idx] = { \
226 .name = nam, \
227 .index = idx, \
228 .fifo_size = maxpkt, \
229 .nr_banks = maxbk, \
230 .can_dma = dma, \
231 .can_isoc = isoc, \
232 }
233
234static struct usba_ep_data usba_udc_ep[] __initdata = {
235 EP("ep0", 0, 64, 1, 0, 0),
236 EP("ep1", 1, 1024, 2, 1, 1),
237 EP("ep2", 2, 1024, 2, 1, 1),
238 EP("ep3", 3, 1024, 3, 1, 0),
239 EP("ep4", 4, 1024, 3, 1, 0),
240 EP("ep5", 5, 1024, 3, 1, 1),
241 EP("ep6", 6, 1024, 3, 1, 1),
242};
243
244#undef EP
245
246/*
247 * pdata doesn't have room for any endpoints, so we need to
248 * append room for the ones we need right after it.
249 */
250static struct {
251 struct usba_platform_data pdata;
252 struct usba_ep_data ep[7];
253} usba_udc_data;
254
255static struct platform_device at91_usba_udc_device = {
256 .name = "atmel_usba_udc",
257 .id = -1,
258 .dev = {
259 .platform_data = &usba_udc_data.pdata,
260 },
261 .resource = usba_udc_resources,
262 .num_resources = ARRAY_SIZE(usba_udc_resources),
263};
264
265void __init at91_add_device_usba(struct usba_platform_data *data)
266{
267 usba_udc_data.pdata.vbus_pin = -EINVAL;
268 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
269 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
270
271 if (data && gpio_is_valid(data->vbus_pin)) {
272 at91_set_gpio_input(data->vbus_pin, 0);
273 at91_set_deglitch(data->vbus_pin, 1);
274 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
275 }
276
277 /* Pullup pin is handled internally by USB device peripheral */
278
279 platform_device_register(&at91_usba_udc_device);
280}
281#else
282void __init at91_add_device_usba(struct usba_platform_data *data) {}
283#endif
284
285
286/* --------------------------------------------------------------------
287 * Ethernet
288 * -------------------------------------------------------------------- */
289
290#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
291static u64 eth_dmamask = DMA_BIT_MASK(32);
292static struct macb_platform_data eth_data;
293
294static struct resource eth_resources[] = {
295 [0] = {
296 .start = AT91SAM9G45_BASE_EMAC,
297 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
302 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
303 .flags = IORESOURCE_IRQ,
304 },
305};
306
307static struct platform_device at91sam9g45_eth_device = {
308 .name = "macb",
309 .id = -1,
310 .dev = {
311 .dma_mask = &eth_dmamask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
313 .platform_data = &eth_data,
314 },
315 .resource = eth_resources,
316 .num_resources = ARRAY_SIZE(eth_resources),
317};
318
319void __init at91_add_device_eth(struct macb_platform_data *data)
320{
321 if (!data)
322 return;
323
324 if (gpio_is_valid(data->phy_irq_pin)) {
325 at91_set_gpio_input(data->phy_irq_pin, 0);
326 at91_set_deglitch(data->phy_irq_pin, 1);
327 }
328
329 /* Pins used for MII and RMII */
330 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
331 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
332 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
333 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
334 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
335 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
336 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
337 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
338 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
339 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
340
341 if (!data->is_rmii) {
342 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
343 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
344 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
345 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
346 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
347 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
348 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
349 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
350 }
351
352 eth_data = *data;
353 platform_device_register(&at91sam9g45_eth_device);
354}
355#else
356void __init at91_add_device_eth(struct macb_platform_data *data) {}
357#endif
358
359
360/* --------------------------------------------------------------------
361 * MMC / SD
362 * -------------------------------------------------------------------- */
363
364#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
365static u64 mmc_dmamask = DMA_BIT_MASK(32);
366static struct mci_platform_data mmc0_data, mmc1_data;
367
368static struct resource mmc0_resources[] = {
369 [0] = {
370 .start = AT91SAM9G45_BASE_MCI0,
371 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
372 .flags = IORESOURCE_MEM,
373 },
374 [1] = {
375 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
376 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
377 .flags = IORESOURCE_IRQ,
378 },
379};
380
381static struct platform_device at91sam9g45_mmc0_device = {
382 .name = "atmel_mci",
383 .id = 0,
384 .dev = {
385 .dma_mask = &mmc_dmamask,
386 .coherent_dma_mask = DMA_BIT_MASK(32),
387 .platform_data = &mmc0_data,
388 },
389 .resource = mmc0_resources,
390 .num_resources = ARRAY_SIZE(mmc0_resources),
391};
392
393static struct resource mmc1_resources[] = {
394 [0] = {
395 .start = AT91SAM9G45_BASE_MCI1,
396 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
397 .flags = IORESOURCE_MEM,
398 },
399 [1] = {
400 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
401 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
402 .flags = IORESOURCE_IRQ,
403 },
404};
405
406static struct platform_device at91sam9g45_mmc1_device = {
407 .name = "atmel_mci",
408 .id = 1,
409 .dev = {
410 .dma_mask = &mmc_dmamask,
411 .coherent_dma_mask = DMA_BIT_MASK(32),
412 .platform_data = &mmc1_data,
413 },
414 .resource = mmc1_resources,
415 .num_resources = ARRAY_SIZE(mmc1_resources),
416};
417
418/* Consider only one slot : slot 0 */
419void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
420{
421
422 if (!data)
423 return;
424
425 /* Must have at least one usable slot */
426 if (!data->slot[0].bus_width)
427 return;
428
429#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
430 {
431 struct at_dma_slave *atslave;
432 struct mci_dma_data *alt_atslave;
433
434 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
435 atslave = &alt_atslave->sdata;
436
437 /* DMA slave channel configuration */
438 atslave->dma_dev = &at_hdmac_device.dev;
439 atslave->cfg = ATC_FIFOCFG_HALFFIFO
440 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
441 if (mmc_id == 0) /* MCI0 */
442 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
443 | ATC_DST_PER(AT_DMA_ID_MCI0);
444
445 else /* MCI1 */
446 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
447 | ATC_DST_PER(AT_DMA_ID_MCI1);
448
449 data->dma_slave = alt_atslave;
450 }
451#endif
452
453
454 /* input/irq */
455 if (gpio_is_valid(data->slot[0].detect_pin)) {
456 at91_set_gpio_input(data->slot[0].detect_pin, 1);
457 at91_set_deglitch(data->slot[0].detect_pin, 1);
458 }
459 if (gpio_is_valid(data->slot[0].wp_pin))
460 at91_set_gpio_input(data->slot[0].wp_pin, 1);
461
462 if (mmc_id == 0) { /* MCI0 */
463
464 /* CLK */
465 at91_set_A_periph(AT91_PIN_PA0, 0);
466
467 /* CMD */
468 at91_set_A_periph(AT91_PIN_PA1, 1);
469
470 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
471 at91_set_A_periph(AT91_PIN_PA2, 1);
472 if (data->slot[0].bus_width == 4) {
473 at91_set_A_periph(AT91_PIN_PA3, 1);
474 at91_set_A_periph(AT91_PIN_PA4, 1);
475 at91_set_A_periph(AT91_PIN_PA5, 1);
476 if (data->slot[0].bus_width == 8) {
477 at91_set_A_periph(AT91_PIN_PA6, 1);
478 at91_set_A_periph(AT91_PIN_PA7, 1);
479 at91_set_A_periph(AT91_PIN_PA8, 1);
480 at91_set_A_periph(AT91_PIN_PA9, 1);
481 }
482 }
483
484 mmc0_data = *data;
485 platform_device_register(&at91sam9g45_mmc0_device);
486
487 } else { /* MCI1 */
488
489 /* CLK */
490 at91_set_A_periph(AT91_PIN_PA31, 0);
491
492 /* CMD */
493 at91_set_A_periph(AT91_PIN_PA22, 1);
494
495 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
496 at91_set_A_periph(AT91_PIN_PA23, 1);
497 if (data->slot[0].bus_width == 4) {
498 at91_set_A_periph(AT91_PIN_PA24, 1);
499 at91_set_A_periph(AT91_PIN_PA25, 1);
500 at91_set_A_periph(AT91_PIN_PA26, 1);
501 if (data->slot[0].bus_width == 8) {
502 at91_set_A_periph(AT91_PIN_PA27, 1);
503 at91_set_A_periph(AT91_PIN_PA28, 1);
504 at91_set_A_periph(AT91_PIN_PA29, 1);
505 at91_set_A_periph(AT91_PIN_PA30, 1);
506 }
507 }
508
509 mmc1_data = *data;
510 platform_device_register(&at91sam9g45_mmc1_device);
511
512 }
513}
514#else
515void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
516#endif
517
518
519/* --------------------------------------------------------------------
520 * NAND / SmartMedia
521 * -------------------------------------------------------------------- */
522
523#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
524static struct atmel_nand_data nand_data;
525
526#define NAND_BASE AT91_CHIPSELECT_3
527
528static struct resource nand_resources[] = {
529 [0] = {
530 .start = NAND_BASE,
531 .end = NAND_BASE + SZ_256M - 1,
532 .flags = IORESOURCE_MEM,
533 },
534 [1] = {
535 .start = AT91SAM9G45_BASE_ECC,
536 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
537 .flags = IORESOURCE_MEM,
538 }
539};
540
541static struct platform_device at91sam9g45_nand_device = {
542 .name = "atmel_nand",
543 .id = -1,
544 .dev = {
545 .platform_data = &nand_data,
546 },
547 .resource = nand_resources,
548 .num_resources = ARRAY_SIZE(nand_resources),
549};
550
551void __init at91_add_device_nand(struct atmel_nand_data *data)
552{
553 unsigned long csa;
554
555 if (!data)
556 return;
557
558 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
559 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
560
561 /* enable pin */
562 if (gpio_is_valid(data->enable_pin))
563 at91_set_gpio_output(data->enable_pin, 1);
564
565 /* ready/busy pin */
566 if (gpio_is_valid(data->rdy_pin))
567 at91_set_gpio_input(data->rdy_pin, 1);
568
569 /* card detect pin */
570 if (gpio_is_valid(data->det_pin))
571 at91_set_gpio_input(data->det_pin, 1);
572
573 nand_data = *data;
574 platform_device_register(&at91sam9g45_nand_device);
575}
576#else
577void __init at91_add_device_nand(struct atmel_nand_data *data) {}
578#endif
579
580
581/* --------------------------------------------------------------------
582 * TWI (i2c)
583 * -------------------------------------------------------------------- */
584
585/*
586 * Prefer the GPIO code since the TWI controller isn't robust
587 * (gets overruns and underruns under load) and can only issue
588 * repeated STARTs in one scenario (the driver doesn't yet handle them).
589 */
590#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
591static struct i2c_gpio_platform_data pdata_i2c0 = {
592 .sda_pin = AT91_PIN_PA20,
593 .sda_is_open_drain = 1,
594 .scl_pin = AT91_PIN_PA21,
595 .scl_is_open_drain = 1,
596 .udelay = 5, /* ~100 kHz */
597};
598
599static struct platform_device at91sam9g45_twi0_device = {
600 .name = "i2c-gpio",
601 .id = 0,
602 .dev.platform_data = &pdata_i2c0,
603};
604
605static struct i2c_gpio_platform_data pdata_i2c1 = {
606 .sda_pin = AT91_PIN_PB10,
607 .sda_is_open_drain = 1,
608 .scl_pin = AT91_PIN_PB11,
609 .scl_is_open_drain = 1,
610 .udelay = 5, /* ~100 kHz */
611};
612
613static struct platform_device at91sam9g45_twi1_device = {
614 .name = "i2c-gpio",
615 .id = 1,
616 .dev.platform_data = &pdata_i2c1,
617};
618
619void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
620{
621 i2c_register_board_info(i2c_id, devices, nr_devices);
622
623 if (i2c_id == 0) {
624 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
625 at91_set_multi_drive(AT91_PIN_PA20, 1);
626
627 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
628 at91_set_multi_drive(AT91_PIN_PA21, 1);
629
630 platform_device_register(&at91sam9g45_twi0_device);
631 } else {
632 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
633 at91_set_multi_drive(AT91_PIN_PB10, 1);
634
635 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
636 at91_set_multi_drive(AT91_PIN_PB11, 1);
637
638 platform_device_register(&at91sam9g45_twi1_device);
639 }
640}
641
642#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
643static struct resource twi0_resources[] = {
644 [0] = {
645 .start = AT91SAM9G45_BASE_TWI0,
646 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 [1] = {
650 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
651 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
652 .flags = IORESOURCE_IRQ,
653 },
654};
655
656static struct platform_device at91sam9g45_twi0_device = {
657 .name = "i2c-at91sam9g10",
658 .id = 0,
659 .resource = twi0_resources,
660 .num_resources = ARRAY_SIZE(twi0_resources),
661};
662
663static struct resource twi1_resources[] = {
664 [0] = {
665 .start = AT91SAM9G45_BASE_TWI1,
666 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
667 .flags = IORESOURCE_MEM,
668 },
669 [1] = {
670 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
671 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
672 .flags = IORESOURCE_IRQ,
673 },
674};
675
676static struct platform_device at91sam9g45_twi1_device = {
677 .name = "i2c-at91sam9g10",
678 .id = 1,
679 .resource = twi1_resources,
680 .num_resources = ARRAY_SIZE(twi1_resources),
681};
682
683void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
684{
685 i2c_register_board_info(i2c_id, devices, nr_devices);
686
687 /* pins used for TWI interface */
688 if (i2c_id == 0) {
689 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
690 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
691
692 platform_device_register(&at91sam9g45_twi0_device);
693 } else {
694 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
695 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
696
697 platform_device_register(&at91sam9g45_twi1_device);
698 }
699}
700#else
701void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
702#endif
703
704
705/* --------------------------------------------------------------------
706 * SPI
707 * -------------------------------------------------------------------- */
708
709#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
710static u64 spi_dmamask = DMA_BIT_MASK(32);
711
712static struct resource spi0_resources[] = {
713 [0] = {
714 .start = AT91SAM9G45_BASE_SPI0,
715 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
716 .flags = IORESOURCE_MEM,
717 },
718 [1] = {
719 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
720 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
721 .flags = IORESOURCE_IRQ,
722 },
723};
724
725static struct platform_device at91sam9g45_spi0_device = {
726 .name = "atmel_spi",
727 .id = 0,
728 .dev = {
729 .dma_mask = &spi_dmamask,
730 .coherent_dma_mask = DMA_BIT_MASK(32),
731 },
732 .resource = spi0_resources,
733 .num_resources = ARRAY_SIZE(spi0_resources),
734};
735
736static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
737
738static struct resource spi1_resources[] = {
739 [0] = {
740 .start = AT91SAM9G45_BASE_SPI1,
741 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
742 .flags = IORESOURCE_MEM,
743 },
744 [1] = {
745 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
746 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
747 .flags = IORESOURCE_IRQ,
748 },
749};
750
751static struct platform_device at91sam9g45_spi1_device = {
752 .name = "atmel_spi",
753 .id = 1,
754 .dev = {
755 .dma_mask = &spi_dmamask,
756 .coherent_dma_mask = DMA_BIT_MASK(32),
757 },
758 .resource = spi1_resources,
759 .num_resources = ARRAY_SIZE(spi1_resources),
760};
761
762static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
763
764void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
765{
766 int i;
767 unsigned long cs_pin;
768 short enable_spi0 = 0;
769 short enable_spi1 = 0;
770
771 /* Choose SPI chip-selects */
772 for (i = 0; i < nr_devices; i++) {
773 if (devices[i].controller_data)
774 cs_pin = (unsigned long) devices[i].controller_data;
775 else if (devices[i].bus_num == 0)
776 cs_pin = spi0_standard_cs[devices[i].chip_select];
777 else
778 cs_pin = spi1_standard_cs[devices[i].chip_select];
779
780 if (!gpio_is_valid(cs_pin))
781 continue;
782
783 if (devices[i].bus_num == 0)
784 enable_spi0 = 1;
785 else
786 enable_spi1 = 1;
787
788 /* enable chip-select pin */
789 at91_set_gpio_output(cs_pin, 1);
790
791 /* pass chip-select pin to driver */
792 devices[i].controller_data = (void *) cs_pin;
793 }
794
795 spi_register_board_info(devices, nr_devices);
796
797 /* Configure SPI bus(es) */
798 if (enable_spi0) {
799 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
800 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
801 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
802
803 platform_device_register(&at91sam9g45_spi0_device);
804 }
805 if (enable_spi1) {
806 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
807 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
808 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
809
810 platform_device_register(&at91sam9g45_spi1_device);
811 }
812}
813#else
814void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
815#endif
816
817
818/* --------------------------------------------------------------------
819 * AC97
820 * -------------------------------------------------------------------- */
821
822#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
823static u64 ac97_dmamask = DMA_BIT_MASK(32);
824static struct ac97c_platform_data ac97_data;
825
826static struct resource ac97_resources[] = {
827 [0] = {
828 .start = AT91SAM9G45_BASE_AC97C,
829 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
830 .flags = IORESOURCE_MEM,
831 },
832 [1] = {
833 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
834 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
835 .flags = IORESOURCE_IRQ,
836 },
837};
838
839static struct platform_device at91sam9g45_ac97_device = {
840 .name = "atmel_ac97c",
841 .id = 0,
842 .dev = {
843 .dma_mask = &ac97_dmamask,
844 .coherent_dma_mask = DMA_BIT_MASK(32),
845 .platform_data = &ac97_data,
846 },
847 .resource = ac97_resources,
848 .num_resources = ARRAY_SIZE(ac97_resources),
849};
850
851void __init at91_add_device_ac97(struct ac97c_platform_data *data)
852{
853 if (!data)
854 return;
855
856 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
857 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
858 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
859 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
860
861 /* reset */
862 if (gpio_is_valid(data->reset_pin))
863 at91_set_gpio_output(data->reset_pin, 0);
864
865 ac97_data = *data;
866 platform_device_register(&at91sam9g45_ac97_device);
867}
868#else
869void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
870#endif
871
872/* --------------------------------------------------------------------
873 * Image Sensor Interface
874 * -------------------------------------------------------------------- */
875#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
876static u64 isi_dmamask = DMA_BIT_MASK(32);
877static struct isi_platform_data isi_data;
878
879struct resource isi_resources[] = {
880 [0] = {
881 .start = AT91SAM9G45_BASE_ISI,
882 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
883 .flags = IORESOURCE_MEM,
884 },
885 [1] = {
886 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
887 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
888 .flags = IORESOURCE_IRQ,
889 },
890};
891
892static struct platform_device at91sam9g45_isi_device = {
893 .name = "atmel_isi",
894 .id = 0,
895 .dev = {
896 .dma_mask = &isi_dmamask,
897 .coherent_dma_mask = DMA_BIT_MASK(32),
898 .platform_data = &isi_data,
899 },
900 .resource = isi_resources,
901 .num_resources = ARRAY_SIZE(isi_resources),
902};
903
904static struct clk_lookup isi_mck_lookups[] = {
905 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
906};
907
908void __init at91_add_device_isi(struct isi_platform_data *data,
909 bool use_pck_as_mck)
910{
911 struct clk *pck;
912 struct clk *parent;
913
914 if (!data)
915 return;
916 isi_data = *data;
917
918 at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
919 at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
920 at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
921 at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
922 at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
923 at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
924 at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
925 at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
926 at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
927 at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
928 at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
929 at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
930 at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
931 at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
932 at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
933
934 platform_device_register(&at91sam9g45_isi_device);
935
936 if (use_pck_as_mck) {
937 at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
938
939 pck = clk_get(NULL, "pck1");
940 parent = clk_get(NULL, "plla");
941
942 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
943
944 if (clk_set_parent(pck, parent)) {
945 pr_err("Failed to set PCK's parent\n");
946 } else {
947 /* Register PCK as ISI_MCK */
948 isi_mck_lookups[0].clk = pck;
949 clkdev_add_table(isi_mck_lookups,
950 ARRAY_SIZE(isi_mck_lookups));
951 }
952
953 clk_put(pck);
954 clk_put(parent);
955 }
956}
957#else
958void __init at91_add_device_isi(struct isi_platform_data *data,
959 bool use_pck_as_mck) {}
960#endif
961
962
963/* --------------------------------------------------------------------
964 * LCD Controller
965 * -------------------------------------------------------------------- */
966
967#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
968static u64 lcdc_dmamask = DMA_BIT_MASK(32);
969static struct atmel_lcdfb_pdata lcdc_data;
970
971static struct resource lcdc_resources[] = {
972 [0] = {
973 .start = AT91SAM9G45_LCDC_BASE,
974 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
975 .flags = IORESOURCE_MEM,
976 },
977 [1] = {
978 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
979 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
980 .flags = IORESOURCE_IRQ,
981 },
982};
983
984static struct platform_device at91_lcdc_device = {
985 .id = 0,
986 .dev = {
987 .dma_mask = &lcdc_dmamask,
988 .coherent_dma_mask = DMA_BIT_MASK(32),
989 .platform_data = &lcdc_data,
990 },
991 .resource = lcdc_resources,
992 .num_resources = ARRAY_SIZE(lcdc_resources),
993};
994
995void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
996{
997 if (!data)
998 return;
999
1000 if (cpu_is_at91sam9g45es())
1001 at91_lcdc_device.name = "at91sam9g45es-lcdfb";
1002 else
1003 at91_lcdc_device.name = "at91sam9g45-lcdfb";
1004
1005 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
1006
1007 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
1008 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
1009 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
1010 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
1011 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
1012 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
1013 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
1014 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
1015 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
1016 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
1017 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
1018 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
1019 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
1020 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
1021 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
1022 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
1023 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
1024 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
1025 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
1026 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
1027 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
1028 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
1029 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
1030 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
1031 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
1032 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
1033 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
1034 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
1035 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
1036
1037 lcdc_data = *data;
1038 platform_device_register(&at91_lcdc_device);
1039}
1040#else
1041void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
1042#endif
1043
1044
1045/* --------------------------------------------------------------------
1046 * Timer/Counter block
1047 * -------------------------------------------------------------------- */
1048
1049#ifdef CONFIG_ATMEL_TCLIB
1050static struct resource tcb0_resources[] = {
1051 [0] = {
1052 .start = AT91SAM9G45_BASE_TCB0,
1053 .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1054 .flags = IORESOURCE_MEM,
1055 },
1056 [1] = {
1057 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1058 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1059 .flags = IORESOURCE_IRQ,
1060 },
1061};
1062
1063static struct platform_device at91sam9g45_tcb0_device = {
1064 .name = "atmel_tcb",
1065 .id = 0,
1066 .resource = tcb0_resources,
1067 .num_resources = ARRAY_SIZE(tcb0_resources),
1068};
1069
1070/* TCB1 begins with TC3 */
1071static struct resource tcb1_resources[] = {
1072 [0] = {
1073 .start = AT91SAM9G45_BASE_TCB1,
1074 .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1075 .flags = IORESOURCE_MEM,
1076 },
1077 [1] = {
1078 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1079 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1080 .flags = IORESOURCE_IRQ,
1081 },
1082};
1083
1084static struct platform_device at91sam9g45_tcb1_device = {
1085 .name = "atmel_tcb",
1086 .id = 1,
1087 .resource = tcb1_resources,
1088 .num_resources = ARRAY_SIZE(tcb1_resources),
1089};
1090
1091static void __init at91_add_device_tc(void)
1092{
1093 platform_device_register(&at91sam9g45_tcb0_device);
1094 platform_device_register(&at91sam9g45_tcb1_device);
1095}
1096#else
1097static void __init at91_add_device_tc(void) { }
1098#endif
1099
1100
1101/* --------------------------------------------------------------------
1102 * RTC
1103 * -------------------------------------------------------------------- */
1104
1105#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1106static struct resource rtc_resources[] = {
1107 [0] = {
1108 .start = AT91SAM9G45_BASE_RTC,
1109 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1110 .flags = IORESOURCE_MEM,
1111 },
1112 [1] = {
1113 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1114 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1115 .flags = IORESOURCE_IRQ,
1116 },
1117};
1118
1119static struct platform_device at91sam9g45_rtc_device = {
1120 .name = "at91_rtc",
1121 .id = -1,
1122 .resource = rtc_resources,
1123 .num_resources = ARRAY_SIZE(rtc_resources),
1124};
1125
1126static void __init at91_add_device_rtc(void)
1127{
1128 platform_device_register(&at91sam9g45_rtc_device);
1129}
1130#else
1131static void __init at91_add_device_rtc(void) {}
1132#endif
1133
1134
1135/* --------------------------------------------------------------------
1136 * ADC and touchscreen
1137 * -------------------------------------------------------------------- */
1138
1139#if IS_ENABLED(CONFIG_AT91_ADC)
1140static struct at91_adc_data adc_data;
1141
1142static struct resource adc_resources[] = {
1143 [0] = {
1144 .start = AT91SAM9G45_BASE_TSC,
1145 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1146 .flags = IORESOURCE_MEM,
1147 },
1148 [1] = {
1149 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1150 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1151 .flags = IORESOURCE_IRQ,
1152 }
1153};
1154
1155static struct platform_device at91_adc_device = {
1156 .name = "at91sam9g45-adc",
1157 .id = -1,
1158 .dev = {
1159 .platform_data = &adc_data,
1160 },
1161 .resource = adc_resources,
1162 .num_resources = ARRAY_SIZE(adc_resources),
1163};
1164
1165static struct at91_adc_trigger at91_adc_triggers[] = {
1166 [0] = {
1167 .name = "external-rising",
1168 .value = 1,
1169 .is_external = true,
1170 },
1171 [1] = {
1172 .name = "external-falling",
1173 .value = 2,
1174 .is_external = true,
1175 },
1176 [2] = {
1177 .name = "external-any",
1178 .value = 3,
1179 .is_external = true,
1180 },
1181 [3] = {
1182 .name = "continuous",
1183 .value = 6,
1184 .is_external = false,
1185 },
1186};
1187
1188void __init at91_add_device_adc(struct at91_adc_data *data)
1189{
1190 if (!data)
1191 return;
1192
1193 if (test_bit(0, &data->channels_used))
1194 at91_set_gpio_input(AT91_PIN_PD20, 0);
1195 if (test_bit(1, &data->channels_used))
1196 at91_set_gpio_input(AT91_PIN_PD21, 0);
1197 if (test_bit(2, &data->channels_used))
1198 at91_set_gpio_input(AT91_PIN_PD22, 0);
1199 if (test_bit(3, &data->channels_used))
1200 at91_set_gpio_input(AT91_PIN_PD23, 0);
1201 if (test_bit(4, &data->channels_used))
1202 at91_set_gpio_input(AT91_PIN_PD24, 0);
1203 if (test_bit(5, &data->channels_used))
1204 at91_set_gpio_input(AT91_PIN_PD25, 0);
1205 if (test_bit(6, &data->channels_used))
1206 at91_set_gpio_input(AT91_PIN_PD26, 0);
1207 if (test_bit(7, &data->channels_used))
1208 at91_set_gpio_input(AT91_PIN_PD27, 0);
1209
1210 if (data->use_external_triggers)
1211 at91_set_A_periph(AT91_PIN_PD28, 0);
1212
1213 data->startup_time = 40;
1214 data->trigger_number = 4;
1215 data->trigger_list = at91_adc_triggers;
1216
1217 adc_data = *data;
1218 platform_device_register(&at91_adc_device);
1219}
1220#else
1221void __init at91_add_device_adc(struct at91_adc_data *data) {}
1222#endif
1223
1224/* --------------------------------------------------------------------
1225 * RTT
1226 * -------------------------------------------------------------------- */
1227
1228static struct resource rtt_resources[] = {
1229 {
1230 .start = AT91SAM9G45_BASE_RTT,
1231 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1232 .flags = IORESOURCE_MEM,
1233 }, {
1234 .flags = IORESOURCE_MEM,
1235 }, {
1236 .flags = IORESOURCE_IRQ,
1237 }
1238};
1239
1240static struct platform_device at91sam9g45_rtt_device = {
1241 .name = "at91_rtt",
1242 .id = 0,
1243 .resource = rtt_resources,
1244};
1245
1246#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1247static void __init at91_add_device_rtt_rtc(void)
1248{
1249 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1250 /*
1251 * The second resource is needed:
1252 * GPBR will serve as the storage for RTC time offset
1253 */
1254 at91sam9g45_rtt_device.num_resources = 3;
1255 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1256 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1257 rtt_resources[1].end = rtt_resources[1].start + 3;
1258 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1259 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1260}
1261#else
1262static void __init at91_add_device_rtt_rtc(void)
1263{
1264 /* Only one resource is needed: RTT not used as RTC */
1265 at91sam9g45_rtt_device.num_resources = 1;
1266}
1267#endif
1268
1269static void __init at91_add_device_rtt(void)
1270{
1271 at91_add_device_rtt_rtc();
1272 platform_device_register(&at91sam9g45_rtt_device);
1273}
1274
1275
1276/* --------------------------------------------------------------------
1277 * TRNG
1278 * -------------------------------------------------------------------- */
1279
1280#if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1281static struct resource trng_resources[] = {
1282 {
1283 .start = AT91SAM9G45_BASE_TRNG,
1284 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1285 .flags = IORESOURCE_MEM,
1286 },
1287};
1288
1289static struct platform_device at91sam9g45_trng_device = {
1290 .name = "atmel-trng",
1291 .id = -1,
1292 .resource = trng_resources,
1293 .num_resources = ARRAY_SIZE(trng_resources),
1294};
1295
1296static void __init at91_add_device_trng(void)
1297{
1298 platform_device_register(&at91sam9g45_trng_device);
1299}
1300#else
1301static void __init at91_add_device_trng(void) {}
1302#endif
1303
1304/* --------------------------------------------------------------------
1305 * Watchdog
1306 * -------------------------------------------------------------------- */
1307
1308#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1309static struct resource wdt_resources[] = {
1310 {
1311 .start = AT91SAM9G45_BASE_WDT,
1312 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1313 .flags = IORESOURCE_MEM,
1314 }
1315};
1316
1317static struct platform_device at91sam9g45_wdt_device = {
1318 .name = "at91_wdt",
1319 .id = -1,
1320 .resource = wdt_resources,
1321 .num_resources = ARRAY_SIZE(wdt_resources),
1322};
1323
1324static void __init at91_add_device_watchdog(void)
1325{
1326 platform_device_register(&at91sam9g45_wdt_device);
1327}
1328#else
1329static void __init at91_add_device_watchdog(void) {}
1330#endif
1331
1332
1333/* --------------------------------------------------------------------
1334 * PWM
1335 * --------------------------------------------------------------------*/
1336
1337#if IS_ENABLED(CONFIG_PWM_ATMEL)
1338static struct resource pwm_resources[] = {
1339 [0] = {
1340 .start = AT91SAM9G45_BASE_PWMC,
1341 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1342 .flags = IORESOURCE_MEM,
1343 },
1344 [1] = {
1345 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1346 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1347 .flags = IORESOURCE_IRQ,
1348 },
1349};
1350
1351static struct platform_device at91sam9g45_pwm0_device = {
1352 .name = "at91sam9rl-pwm",
1353 .id = -1,
1354 .resource = pwm_resources,
1355 .num_resources = ARRAY_SIZE(pwm_resources),
1356};
1357
1358void __init at91_add_device_pwm(u32 mask)
1359{
1360 if (mask & (1 << AT91_PWM0))
1361 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1362
1363 if (mask & (1 << AT91_PWM1))
1364 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1365
1366 if (mask & (1 << AT91_PWM2))
1367 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1368
1369 if (mask & (1 << AT91_PWM3))
1370 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1371
1372 platform_device_register(&at91sam9g45_pwm0_device);
1373}
1374#else
1375void __init at91_add_device_pwm(u32 mask) {}
1376#endif
1377
1378
1379/* --------------------------------------------------------------------
1380 * SSC -- Synchronous Serial Controller
1381 * -------------------------------------------------------------------- */
1382
1383#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1384static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1385
1386static struct resource ssc0_resources[] = {
1387 [0] = {
1388 .start = AT91SAM9G45_BASE_SSC0,
1389 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1390 .flags = IORESOURCE_MEM,
1391 },
1392 [1] = {
1393 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1394 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1395 .flags = IORESOURCE_IRQ,
1396 },
1397};
1398
1399static struct platform_device at91sam9g45_ssc0_device = {
1400 .name = "at91sam9g45_ssc",
1401 .id = 0,
1402 .dev = {
1403 .dma_mask = &ssc0_dmamask,
1404 .coherent_dma_mask = DMA_BIT_MASK(32),
1405 },
1406 .resource = ssc0_resources,
1407 .num_resources = ARRAY_SIZE(ssc0_resources),
1408};
1409
1410static inline void configure_ssc0_pins(unsigned pins)
1411{
1412 if (pins & ATMEL_SSC_TF)
1413 at91_set_A_periph(AT91_PIN_PD1, 1);
1414 if (pins & ATMEL_SSC_TK)
1415 at91_set_A_periph(AT91_PIN_PD0, 1);
1416 if (pins & ATMEL_SSC_TD)
1417 at91_set_A_periph(AT91_PIN_PD2, 1);
1418 if (pins & ATMEL_SSC_RD)
1419 at91_set_A_periph(AT91_PIN_PD3, 1);
1420 if (pins & ATMEL_SSC_RK)
1421 at91_set_A_periph(AT91_PIN_PD4, 1);
1422 if (pins & ATMEL_SSC_RF)
1423 at91_set_A_periph(AT91_PIN_PD5, 1);
1424}
1425
1426static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1427
1428static struct resource ssc1_resources[] = {
1429 [0] = {
1430 .start = AT91SAM9G45_BASE_SSC1,
1431 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1432 .flags = IORESOURCE_MEM,
1433 },
1434 [1] = {
1435 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1436 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1437 .flags = IORESOURCE_IRQ,
1438 },
1439};
1440
1441static struct platform_device at91sam9g45_ssc1_device = {
1442 .name = "at91sam9g45_ssc",
1443 .id = 1,
1444 .dev = {
1445 .dma_mask = &ssc1_dmamask,
1446 .coherent_dma_mask = DMA_BIT_MASK(32),
1447 },
1448 .resource = ssc1_resources,
1449 .num_resources = ARRAY_SIZE(ssc1_resources),
1450};
1451
1452static inline void configure_ssc1_pins(unsigned pins)
1453{
1454 if (pins & ATMEL_SSC_TF)
1455 at91_set_A_periph(AT91_PIN_PD14, 1);
1456 if (pins & ATMEL_SSC_TK)
1457 at91_set_A_periph(AT91_PIN_PD12, 1);
1458 if (pins & ATMEL_SSC_TD)
1459 at91_set_A_periph(AT91_PIN_PD10, 1);
1460 if (pins & ATMEL_SSC_RD)
1461 at91_set_A_periph(AT91_PIN_PD11, 1);
1462 if (pins & ATMEL_SSC_RK)
1463 at91_set_A_periph(AT91_PIN_PD13, 1);
1464 if (pins & ATMEL_SSC_RF)
1465 at91_set_A_periph(AT91_PIN_PD15, 1);
1466}
1467
1468/*
1469 * SSC controllers are accessed through library code, instead of any
1470 * kind of all-singing/all-dancing driver. For example one could be
1471 * used by a particular I2S audio codec's driver, while another one
1472 * on the same system might be used by a custom data capture driver.
1473 */
1474void __init at91_add_device_ssc(unsigned id, unsigned pins)
1475{
1476 struct platform_device *pdev;
1477
1478 /*
1479 * NOTE: caller is responsible for passing information matching
1480 * "pins" to whatever will be using each particular controller.
1481 */
1482 switch (id) {
1483 case AT91SAM9G45_ID_SSC0:
1484 pdev = &at91sam9g45_ssc0_device;
1485 configure_ssc0_pins(pins);
1486 break;
1487 case AT91SAM9G45_ID_SSC1:
1488 pdev = &at91sam9g45_ssc1_device;
1489 configure_ssc1_pins(pins);
1490 break;
1491 default:
1492 return;
1493 }
1494
1495 platform_device_register(pdev);
1496}
1497
1498#else
1499void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1500#endif
1501
1502
1503/* --------------------------------------------------------------------
1504 * UART
1505 * -------------------------------------------------------------------- */
1506
1507#if defined(CONFIG_SERIAL_ATMEL)
1508static struct resource dbgu_resources[] = {
1509 [0] = {
1510 .start = AT91SAM9G45_BASE_DBGU,
1511 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1512 .flags = IORESOURCE_MEM,
1513 },
1514 [1] = {
1515 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1516 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1517 .flags = IORESOURCE_IRQ,
1518 },
1519};
1520
1521static struct atmel_uart_data dbgu_data = {
1522 .use_dma_tx = 0,
1523 .use_dma_rx = 0,
1524};
1525
1526static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1527
1528static struct platform_device at91sam9g45_dbgu_device = {
1529 .name = "atmel_usart",
1530 .id = 0,
1531 .dev = {
1532 .dma_mask = &dbgu_dmamask,
1533 .coherent_dma_mask = DMA_BIT_MASK(32),
1534 .platform_data = &dbgu_data,
1535 },
1536 .resource = dbgu_resources,
1537 .num_resources = ARRAY_SIZE(dbgu_resources),
1538};
1539
1540static inline void configure_dbgu_pins(void)
1541{
1542 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1543 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1544}
1545
1546static struct resource uart0_resources[] = {
1547 [0] = {
1548 .start = AT91SAM9G45_BASE_US0,
1549 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1550 .flags = IORESOURCE_MEM,
1551 },
1552 [1] = {
1553 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1554 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1555 .flags = IORESOURCE_IRQ,
1556 },
1557};
1558
1559static struct atmel_uart_data uart0_data = {
1560 .use_dma_tx = 1,
1561 .use_dma_rx = 1,
1562};
1563
1564static u64 uart0_dmamask = DMA_BIT_MASK(32);
1565
1566static struct platform_device at91sam9g45_uart0_device = {
1567 .name = "atmel_usart",
1568 .id = 1,
1569 .dev = {
1570 .dma_mask = &uart0_dmamask,
1571 .coherent_dma_mask = DMA_BIT_MASK(32),
1572 .platform_data = &uart0_data,
1573 },
1574 .resource = uart0_resources,
1575 .num_resources = ARRAY_SIZE(uart0_resources),
1576};
1577
1578static inline void configure_usart0_pins(unsigned pins)
1579{
1580 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1581 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1582
1583 if (pins & ATMEL_UART_RTS)
1584 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1585 if (pins & ATMEL_UART_CTS)
1586 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1587}
1588
1589static struct resource uart1_resources[] = {
1590 [0] = {
1591 .start = AT91SAM9G45_BASE_US1,
1592 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1593 .flags = IORESOURCE_MEM,
1594 },
1595 [1] = {
1596 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1597 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1598 .flags = IORESOURCE_IRQ,
1599 },
1600};
1601
1602static struct atmel_uart_data uart1_data = {
1603 .use_dma_tx = 1,
1604 .use_dma_rx = 1,
1605};
1606
1607static u64 uart1_dmamask = DMA_BIT_MASK(32);
1608
1609static struct platform_device at91sam9g45_uart1_device = {
1610 .name = "atmel_usart",
1611 .id = 2,
1612 .dev = {
1613 .dma_mask = &uart1_dmamask,
1614 .coherent_dma_mask = DMA_BIT_MASK(32),
1615 .platform_data = &uart1_data,
1616 },
1617 .resource = uart1_resources,
1618 .num_resources = ARRAY_SIZE(uart1_resources),
1619};
1620
1621static inline void configure_usart1_pins(unsigned pins)
1622{
1623 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1624 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1625
1626 if (pins & ATMEL_UART_RTS)
1627 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1628 if (pins & ATMEL_UART_CTS)
1629 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1630}
1631
1632static struct resource uart2_resources[] = {
1633 [0] = {
1634 .start = AT91SAM9G45_BASE_US2,
1635 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1636 .flags = IORESOURCE_MEM,
1637 },
1638 [1] = {
1639 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1640 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1641 .flags = IORESOURCE_IRQ,
1642 },
1643};
1644
1645static struct atmel_uart_data uart2_data = {
1646 .use_dma_tx = 1,
1647 .use_dma_rx = 1,
1648};
1649
1650static u64 uart2_dmamask = DMA_BIT_MASK(32);
1651
1652static struct platform_device at91sam9g45_uart2_device = {
1653 .name = "atmel_usart",
1654 .id = 3,
1655 .dev = {
1656 .dma_mask = &uart2_dmamask,
1657 .coherent_dma_mask = DMA_BIT_MASK(32),
1658 .platform_data = &uart2_data,
1659 },
1660 .resource = uart2_resources,
1661 .num_resources = ARRAY_SIZE(uart2_resources),
1662};
1663
1664static inline void configure_usart2_pins(unsigned pins)
1665{
1666 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1667 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1668
1669 if (pins & ATMEL_UART_RTS)
1670 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1671 if (pins & ATMEL_UART_CTS)
1672 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1673}
1674
1675static struct resource uart3_resources[] = {
1676 [0] = {
1677 .start = AT91SAM9G45_BASE_US3,
1678 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1679 .flags = IORESOURCE_MEM,
1680 },
1681 [1] = {
1682 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1683 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1684 .flags = IORESOURCE_IRQ,
1685 },
1686};
1687
1688static struct atmel_uart_data uart3_data = {
1689 .use_dma_tx = 1,
1690 .use_dma_rx = 1,
1691};
1692
1693static u64 uart3_dmamask = DMA_BIT_MASK(32);
1694
1695static struct platform_device at91sam9g45_uart3_device = {
1696 .name = "atmel_usart",
1697 .id = 4,
1698 .dev = {
1699 .dma_mask = &uart3_dmamask,
1700 .coherent_dma_mask = DMA_BIT_MASK(32),
1701 .platform_data = &uart3_data,
1702 },
1703 .resource = uart3_resources,
1704 .num_resources = ARRAY_SIZE(uart3_resources),
1705};
1706
1707static inline void configure_usart3_pins(unsigned pins)
1708{
1709 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1710 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1711
1712 if (pins & ATMEL_UART_RTS)
1713 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1714 if (pins & ATMEL_UART_CTS)
1715 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1716}
1717
1718static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1719
1720void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1721{
1722 struct platform_device *pdev;
1723 struct atmel_uart_data *pdata;
1724
1725 switch (id) {
1726 case 0: /* DBGU */
1727 pdev = &at91sam9g45_dbgu_device;
1728 configure_dbgu_pins();
1729 break;
1730 case AT91SAM9G45_ID_US0:
1731 pdev = &at91sam9g45_uart0_device;
1732 configure_usart0_pins(pins);
1733 break;
1734 case AT91SAM9G45_ID_US1:
1735 pdev = &at91sam9g45_uart1_device;
1736 configure_usart1_pins(pins);
1737 break;
1738 case AT91SAM9G45_ID_US2:
1739 pdev = &at91sam9g45_uart2_device;
1740 configure_usart2_pins(pins);
1741 break;
1742 case AT91SAM9G45_ID_US3:
1743 pdev = &at91sam9g45_uart3_device;
1744 configure_usart3_pins(pins);
1745 break;
1746 default:
1747 return;
1748 }
1749 pdata = pdev->dev.platform_data;
1750 pdata->num = portnr; /* update to mapped ID */
1751
1752 if (portnr < ATMEL_MAX_UART)
1753 at91_uarts[portnr] = pdev;
1754}
1755
1756void __init at91_add_device_serial(void)
1757{
1758 int i;
1759
1760 for (i = 0; i < ATMEL_MAX_UART; i++) {
1761 if (at91_uarts[i])
1762 platform_device_register(at91_uarts[i]);
1763 }
1764}
1765#else
1766void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1767void __init at91_add_device_serial(void) {}
1768#endif
1769
1770/* --------------------------------------------------------------------
1771 * SHA1/SHA256
1772 * -------------------------------------------------------------------- */
1773
1774#if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
1775static struct resource sha_resources[] = {
1776 {
1777 .start = AT91SAM9G45_BASE_SHA,
1778 .end = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
1779 .flags = IORESOURCE_MEM,
1780 },
1781 [1] = {
1782 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1783 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1784 .flags = IORESOURCE_IRQ,
1785 },
1786};
1787
1788static struct platform_device at91sam9g45_sha_device = {
1789 .name = "atmel_sha",
1790 .id = -1,
1791 .resource = sha_resources,
1792 .num_resources = ARRAY_SIZE(sha_resources),
1793};
1794
1795static void __init at91_add_device_sha(void)
1796{
1797 platform_device_register(&at91sam9g45_sha_device);
1798}
1799#else
1800static void __init at91_add_device_sha(void) {}
1801#endif
1802
1803/* --------------------------------------------------------------------
1804 * DES/TDES
1805 * -------------------------------------------------------------------- */
1806
1807#if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
1808static struct resource tdes_resources[] = {
1809 [0] = {
1810 .start = AT91SAM9G45_BASE_TDES,
1811 .end = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
1812 .flags = IORESOURCE_MEM,
1813 },
1814 [1] = {
1815 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1816 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1817 .flags = IORESOURCE_IRQ,
1818 },
1819};
1820
1821static struct platform_device at91sam9g45_tdes_device = {
1822 .name = "atmel_tdes",
1823 .id = -1,
1824 .resource = tdes_resources,
1825 .num_resources = ARRAY_SIZE(tdes_resources),
1826};
1827
1828static void __init at91_add_device_tdes(void)
1829{
1830 platform_device_register(&at91sam9g45_tdes_device);
1831}
1832#else
1833static void __init at91_add_device_tdes(void) {}
1834#endif
1835
1836/* --------------------------------------------------------------------
1837 * AES
1838 * -------------------------------------------------------------------- */
1839
1840#if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
1841static struct crypto_platform_data aes_data;
1842static struct crypto_dma_data alt_atslave;
1843static u64 aes_dmamask = DMA_BIT_MASK(32);
1844
1845static struct resource aes_resources[] = {
1846 [0] = {
1847 .start = AT91SAM9G45_BASE_AES,
1848 .end = AT91SAM9G45_BASE_AES + SZ_16K - 1,
1849 .flags = IORESOURCE_MEM,
1850 },
1851 [1] = {
1852 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1853 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1854 .flags = IORESOURCE_IRQ,
1855 },
1856};
1857
1858static struct platform_device at91sam9g45_aes_device = {
1859 .name = "atmel_aes",
1860 .id = -1,
1861 .dev = {
1862 .dma_mask = &aes_dmamask,
1863 .coherent_dma_mask = DMA_BIT_MASK(32),
1864 .platform_data = &aes_data,
1865 },
1866 .resource = aes_resources,
1867 .num_resources = ARRAY_SIZE(aes_resources),
1868};
1869
1870static void __init at91_add_device_aes(void)
1871{
1872 struct at_dma_slave *atslave;
1873
1874 /* DMA TX slave channel configuration */
1875 atslave = &alt_atslave.txdata;
1876 atslave->dma_dev = &at_hdmac_device.dev;
1877 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_SRC_H2SEL_HW |
1878 ATC_SRC_PER(AT_DMA_ID_AES_RX);
1879
1880 /* DMA RX slave channel configuration */
1881 atslave = &alt_atslave.rxdata;
1882 atslave->dma_dev = &at_hdmac_device.dev;
1883 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_DST_H2SEL_HW |
1884 ATC_DST_PER(AT_DMA_ID_AES_TX);
1885
1886 aes_data.dma_slave = &alt_atslave;
1887 platform_device_register(&at91sam9g45_aes_device);
1888}
1889#else
1890static void __init at91_add_device_aes(void) {}
1891#endif
1892
1893/* -------------------------------------------------------------------- */
1894/*
1895 * These devices are always present and don't need any board-specific
1896 * setup.
1897 */
1898static int __init at91_add_standard_devices(void)
1899{
1900 if (of_have_populated_dt())
1901 return 0;
1902
1903 at91_add_device_hdmac();
1904 at91_add_device_rtc();
1905 at91_add_device_rtt();
1906 at91_add_device_trng();
1907 at91_add_device_watchdog();
1908 at91_add_device_tc();
1909 at91_add_device_sha();
1910 at91_add_device_tdes();
1911 at91_add_device_aes();
1912 return 0;
1913}
1914
1915arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 40c815c62742..6ca7fc5ca812 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -9,286 +9,13 @@
9 * more details. 9 * more details.
10 */ 10 */
11 11
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/clk/at91_pmc.h>
15
16#include <asm/proc-fns.h>
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/system_misc.h> 12#include <asm/system_misc.h>
21#include <mach/cpu.h> 13#include <mach/cpu.h>
22#include <mach/at91_dbgu.h> 14#include <mach/at91_dbgu.h>
23#include <mach/at91sam9rl.h>
24#include <mach/hardware.h> 15#include <mach/hardware.h>
25 16
26#include "at91_aic.h"
27#include "soc.h" 17#include "soc.h"
28#include "generic.h" 18#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32/* --------------------------------------------------------------------
33 * Clocks
34 * -------------------------------------------------------------------- */
35#if defined(CONFIG_OLD_CLK_AT91)
36#include "clock.h"
37
38/*
39 * The peripheral clocks.
40 */
41static struct clk pioA_clk = {
42 .name = "pioA_clk",
43 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioB_clk = {
47 .name = "pioB_clk",
48 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk pioC_clk = {
52 .name = "pioC_clk",
53 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk pioD_clk = {
57 .name = "pioD_clk",
58 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk usart0_clk = {
62 .name = "usart0_clk",
63 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk usart1_clk = {
67 .name = "usart1_clk",
68 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk usart2_clk = {
72 .name = "usart2_clk",
73 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk usart3_clk = {
77 .name = "usart3_clk",
78 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk mmc_clk = {
82 .name = "mci_clk",
83 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk twi0_clk = {
87 .name = "twi0_clk",
88 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk twi1_clk = {
92 .name = "twi1_clk",
93 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk spi_clk = {
97 .name = "spi_clk",
98 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk ssc0_clk = {
102 .name = "ssc0_clk",
103 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk ssc1_clk = {
107 .name = "ssc1_clk",
108 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk tc0_clk = {
112 .name = "tc0_clk",
113 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk tc1_clk = {
117 .name = "tc1_clk",
118 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk tc2_clk = {
122 .name = "tc2_clk",
123 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk pwm_clk = {
127 .name = "pwm_clk",
128 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk tsc_clk = {
132 .name = "tsc_clk",
133 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk dma_clk = {
137 .name = "dma_clk",
138 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk udphs_clk = {
142 .name = "udphs_clk",
143 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk lcdc_clk = {
147 .name = "lcdc_clk",
148 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151static struct clk ac97_clk = {
152 .name = "ac97_clk",
153 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
154 .type = CLK_TYPE_PERIPHERAL,
155};
156static struct clk adc_op_clk = {
157 .name = "adc_op_clk",
158 .type = CLK_TYPE_PERIPHERAL,
159 .rate_hz = 1000000,
160};
161
162static struct clk *periph_clocks[] __initdata = {
163 &pioA_clk,
164 &pioB_clk,
165 &pioC_clk,
166 &pioD_clk,
167 &usart0_clk,
168 &usart1_clk,
169 &usart2_clk,
170 &usart3_clk,
171 &mmc_clk,
172 &twi0_clk,
173 &twi1_clk,
174 &spi_clk,
175 &ssc0_clk,
176 &ssc1_clk,
177 &tc0_clk,
178 &tc1_clk,
179 &tc2_clk,
180 &pwm_clk,
181 &tsc_clk,
182 &dma_clk,
183 &udphs_clk,
184 &lcdc_clk,
185 &ac97_clk,
186 &adc_op_clk,
187 // irq0
188};
189
190static struct clk_lookup periph_clocks_lookups[] = {
191 CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
192 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
193 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
194 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
195 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
196 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
197 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
198 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
199 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
200 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
201 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
202 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
203 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
204 CLKDEV_CON_ID("pioA", &pioA_clk),
205 CLKDEV_CON_ID("pioB", &pioB_clk),
206 CLKDEV_CON_ID("pioC", &pioC_clk),
207 CLKDEV_CON_ID("pioD", &pioD_clk),
208 CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k),
209 /* more lookup table for DT entries */
210 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
211 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
212 CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
213 CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
214 CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
215 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
216 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
217 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
218 CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
220 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
222 CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
226 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
227 CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k),
228 CLKDEV_CON_ID("adc_clk", &tsc_clk),
229};
230
231static struct clk_lookup usart_clocks_lookups[] = {
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
236 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
237};
238
239/*
240 * The two programmable clocks.
241 * You must configure pin multiplexing to bring these signals out.
242 */
243static struct clk pck0 = {
244 .name = "pck0",
245 .pmc_mask = AT91_PMC_PCK0,
246 .type = CLK_TYPE_PROGRAMMABLE,
247 .id = 0,
248};
249static struct clk pck1 = {
250 .name = "pck1",
251 .pmc_mask = AT91_PMC_PCK1,
252 .type = CLK_TYPE_PROGRAMMABLE,
253 .id = 1,
254};
255
256static void __init at91sam9rl_register_clocks(void)
257{
258 int i;
259
260 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
261 clk_register(periph_clocks[i]);
262
263 clkdev_add_table(periph_clocks_lookups,
264 ARRAY_SIZE(periph_clocks_lookups));
265 clkdev_add_table(usart_clocks_lookups,
266 ARRAY_SIZE(usart_clocks_lookups));
267
268 clk_register(&pck0);
269 clk_register(&pck1);
270}
271#endif
272
273/* --------------------------------------------------------------------
274 * GPIO
275 * -------------------------------------------------------------------- */
276
277static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
278 {
279 .id = AT91SAM9RL_ID_PIOA,
280 .regbase = AT91SAM9RL_BASE_PIOA,
281 }, {
282 .id = AT91SAM9RL_ID_PIOB,
283 .regbase = AT91SAM9RL_BASE_PIOB,
284 }, {
285 .id = AT91SAM9RL_ID_PIOC,
286 .regbase = AT91SAM9RL_BASE_PIOC,
287 }, {
288 .id = AT91SAM9RL_ID_PIOD,
289 .regbase = AT91SAM9RL_BASE_PIOD,
290 }
291};
292 19
293/* -------------------------------------------------------------------- 20/* --------------------------------------------------------------------
294 * AT91SAM9RL processor initialization 21 * AT91SAM9RL processor initialization
@@ -311,107 +38,14 @@ static void __init at91sam9rl_map_io(void)
311 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size); 38 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
312} 39}
313 40
314static void __init at91sam9rl_ioremap_registers(void)
315{
316 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
317 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
318 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
319 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
320 at91_pm_set_standby(at91sam9_sdram_standby);
321}
322
323static void __init at91sam9rl_initialize(void) 41static void __init at91sam9rl_initialize(void)
324{ 42{
325 arm_pm_idle = at91sam9_idle; 43 arm_pm_idle = at91sam9_idle;
326 44
327 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC); 45 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
328 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT); 46 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
329
330 /* Register GPIO subsystem */
331 at91_gpio_init(at91sam9rl_gpio, 4);
332}
333
334static struct resource rstc_resources[] = {
335 [0] = {
336 .start = AT91SAM9RL_BASE_RSTC,
337 .end = AT91SAM9RL_BASE_RSTC + SZ_16 - 1,
338 .flags = IORESOURCE_MEM,
339 },
340 [1] = {
341 .start = AT91SAM9RL_BASE_SDRAMC,
342 .end = AT91SAM9RL_BASE_SDRAMC + SZ_512 - 1,
343 .flags = IORESOURCE_MEM,
344 },
345};
346
347static struct platform_device rstc_device = {
348 .name = "at91-sam9260-reset",
349 .resource = rstc_resources,
350 .num_resources = ARRAY_SIZE(rstc_resources),
351};
352
353static struct resource shdwc_resources[] = {
354 [0] = {
355 .start = AT91SAM9RL_BASE_SHDWC,
356 .end = AT91SAM9RL_BASE_SHDWC + SZ_16 - 1,
357 .flags = IORESOURCE_MEM,
358 },
359};
360
361static struct platform_device shdwc_device = {
362 .name = "at91-poweroff",
363 .resource = shdwc_resources,
364 .num_resources = ARRAY_SIZE(shdwc_resources),
365};
366
367static void __init at91sam9rl_register_devices(void)
368{
369 platform_device_register(&rstc_device);
370 platform_device_register(&shdwc_device);
371} 47}
372 48
373/* --------------------------------------------------------------------
374 * Interrupt initialization
375 * -------------------------------------------------------------------- */
376
377/*
378 * The default interrupt priority levels (0 = lowest, 7 = highest).
379 */
380static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
381 7, /* Advanced Interrupt Controller */
382 7, /* System Peripherals */
383 1, /* Parallel IO Controller A */
384 1, /* Parallel IO Controller B */
385 1, /* Parallel IO Controller C */
386 1, /* Parallel IO Controller D */
387 5, /* USART 0 */
388 5, /* USART 1 */
389 5, /* USART 2 */
390 5, /* USART 3 */
391 0, /* Multimedia Card Interface */
392 6, /* Two-Wire Interface 0 */
393 6, /* Two-Wire Interface 1 */
394 5, /* Serial Peripheral Interface */
395 4, /* Serial Synchronous Controller 0 */
396 4, /* Serial Synchronous Controller 1 */
397 0, /* Timer Counter 0 */
398 0, /* Timer Counter 1 */
399 0, /* Timer Counter 2 */
400 0,
401 0, /* Touch Screen Controller */
402 0, /* DMA Controller */
403 2, /* USB Device High speed port */
404 2, /* LCD Controller */
405 6, /* AC97 Controller */
406 0,
407 0,
408 0,
409 0,
410 0,
411 0,
412 0, /* Advanced Interrupt Controller */
413};
414
415static void __init at91sam9rl_init_time(void) 49static void __init at91sam9rl_init_time(void)
416{ 50{
417 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS); 51 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
@@ -419,13 +53,6 @@ static void __init at91sam9rl_init_time(void)
419 53
420AT91_SOC_START(at91sam9rl) 54AT91_SOC_START(at91sam9rl)
421 .map_io = at91sam9rl_map_io, 55 .map_io = at91sam9rl_map_io,
422 .default_irq_priority = at91sam9rl_default_irq_priority,
423 .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
424 .ioremap_registers = at91sam9rl_ioremap_registers,
425#if defined(CONFIG_OLD_CLK_AT91)
426 .register_clocks = at91sam9rl_register_clocks,
427#endif
428 .register_devices = at91sam9rl_register_devices,
429 .init = at91sam9rl_initialize, 56 .init = at91sam9rl_initialize,
430 .init_time = at91sam9rl_init_time, 57 .init_time = at91sam9rl_init_time,
431AT91_SOC_END 58AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
deleted file mode 100644
index 37d1c9ed4562..000000000000
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ /dev/null
@@ -1,1260 +0,0 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14#include <linux/platform_device.h>
15#include <linux/i2c-gpio.h>
16
17#include <linux/fb.h>
18#include <video/atmel_lcdc.h>
19
20#include <mach/at91sam9rl.h>
21#include <mach/at91sam9rl_matrix.h>
22#include <mach/at91_matrix.h>
23#include <mach/at91sam9_smc.h>
24#include <mach/hardware.h>
25#include <linux/platform_data/dma-atmel.h>
26#include <linux/platform_data/at91_adc.h>
27
28#include "board.h"
29#include "generic.h"
30#include "gpio.h"
31
32
33/* --------------------------------------------------------------------
34 * HDMAC - AHB DMA Controller
35 * -------------------------------------------------------------------- */
36
37#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
38static u64 hdmac_dmamask = DMA_BIT_MASK(32);
39
40static struct resource hdmac_resources[] = {
41 [0] = {
42 .start = AT91SAM9RL_BASE_DMA,
43 .end = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [2] = {
47 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
48 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at_hdmac_device = {
54 .name = "at91sam9rl_dma",
55 .id = -1,
56 .dev = {
57 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 },
60 .resource = hdmac_resources,
61 .num_resources = ARRAY_SIZE(hdmac_resources),
62};
63
64void __init at91_add_device_hdmac(void)
65{
66 platform_device_register(&at_hdmac_device);
67}
68#else
69void __init at91_add_device_hdmac(void) {}
70#endif
71
72/* --------------------------------------------------------------------
73 * USB HS Device (Gadget)
74 * -------------------------------------------------------------------- */
75
76#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
77
78static struct resource usba_udc_resources[] = {
79 [0] = {
80 .start = AT91SAM9RL_UDPHS_FIFO,
81 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
82 .flags = IORESOURCE_MEM,
83 },
84 [1] = {
85 .start = AT91SAM9RL_BASE_UDPHS,
86 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 [2] = {
90 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
91 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
97 [idx] = { \
98 .name = nam, \
99 .index = idx, \
100 .fifo_size = maxpkt, \
101 .nr_banks = maxbk, \
102 .can_dma = dma, \
103 .can_isoc = isoc, \
104 }
105
106static struct usba_ep_data usba_udc_ep[] __initdata = {
107 EP("ep0", 0, 64, 1, 0, 0),
108 EP("ep1", 1, 1024, 2, 1, 1),
109 EP("ep2", 2, 1024, 2, 1, 1),
110 EP("ep3", 3, 1024, 3, 1, 0),
111 EP("ep4", 4, 1024, 3, 1, 0),
112 EP("ep5", 5, 1024, 3, 1, 1),
113 EP("ep6", 6, 1024, 3, 1, 1),
114};
115
116#undef EP
117
118/*
119 * pdata doesn't have room for any endpoints, so we need to
120 * append room for the ones we need right after it.
121 */
122static struct {
123 struct usba_platform_data pdata;
124 struct usba_ep_data ep[7];
125} usba_udc_data;
126
127static struct platform_device at91_usba_udc_device = {
128 .name = "atmel_usba_udc",
129 .id = -1,
130 .dev = {
131 .platform_data = &usba_udc_data.pdata,
132 },
133 .resource = usba_udc_resources,
134 .num_resources = ARRAY_SIZE(usba_udc_resources),
135};
136
137void __init at91_add_device_usba(struct usba_platform_data *data)
138{
139 /*
140 * Invalid pins are 0 on AT91, but the usba driver is shared
141 * with AVR32, which use negative values instead. Once/if
142 * gpio_is_valid() is ported to AT91, revisit this code.
143 */
144 usba_udc_data.pdata.vbus_pin = -EINVAL;
145 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
146 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
147
148 if (data && gpio_is_valid(data->vbus_pin)) {
149 at91_set_gpio_input(data->vbus_pin, 0);
150 at91_set_deglitch(data->vbus_pin, 1);
151 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
152 }
153
154 /* Pullup pin is handled internally by USB device peripheral */
155
156 platform_device_register(&at91_usba_udc_device);
157}
158#else
159void __init at91_add_device_usba(struct usba_platform_data *data) {}
160#endif
161
162
163/* --------------------------------------------------------------------
164 * MMC / SD
165 * -------------------------------------------------------------------- */
166
167#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
168static u64 mmc_dmamask = DMA_BIT_MASK(32);
169static struct mci_platform_data mmc_data;
170
171static struct resource mmc_resources[] = {
172 [0] = {
173 .start = AT91SAM9RL_BASE_MCI,
174 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
175 .flags = IORESOURCE_MEM,
176 },
177 [1] = {
178 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
179 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct platform_device at91sam9rl_mmc_device = {
185 .name = "atmel_mci",
186 .id = -1,
187 .dev = {
188 .dma_mask = &mmc_dmamask,
189 .coherent_dma_mask = DMA_BIT_MASK(32),
190 .platform_data = &mmc_data,
191 },
192 .resource = mmc_resources,
193 .num_resources = ARRAY_SIZE(mmc_resources),
194};
195
196void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
197{
198 if (!data)
199 return;
200
201 if (data->slot[0].bus_width) {
202 /* input/irq */
203 if (gpio_is_valid(data->slot[0].detect_pin)) {
204 at91_set_gpio_input(data->slot[0].detect_pin, 1);
205 at91_set_deglitch(data->slot[0].detect_pin, 1);
206 }
207 if (gpio_is_valid(data->slot[0].wp_pin))
208 at91_set_gpio_input(data->slot[0].wp_pin, 1);
209
210 /* CLK */
211 at91_set_A_periph(AT91_PIN_PA2, 0);
212
213 /* CMD */
214 at91_set_A_periph(AT91_PIN_PA1, 1);
215
216 /* DAT0, maybe DAT1..DAT3 */
217 at91_set_A_periph(AT91_PIN_PA0, 1);
218 if (data->slot[0].bus_width == 4) {
219 at91_set_A_periph(AT91_PIN_PA3, 1);
220 at91_set_A_periph(AT91_PIN_PA4, 1);
221 at91_set_A_periph(AT91_PIN_PA5, 1);
222 }
223
224 mmc_data = *data;
225 platform_device_register(&at91sam9rl_mmc_device);
226 }
227}
228#else
229void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
230#endif
231
232
233/* --------------------------------------------------------------------
234 * NAND / SmartMedia
235 * -------------------------------------------------------------------- */
236
237#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
238static struct atmel_nand_data nand_data;
239
240#define NAND_BASE AT91_CHIPSELECT_3
241
242static struct resource nand_resources[] = {
243 [0] = {
244 .start = NAND_BASE,
245 .end = NAND_BASE + SZ_256M - 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = AT91SAM9RL_BASE_ECC,
250 .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
251 .flags = IORESOURCE_MEM,
252 }
253};
254
255static struct platform_device atmel_nand_device = {
256 .name = "atmel_nand",
257 .id = -1,
258 .dev = {
259 .platform_data = &nand_data,
260 },
261 .resource = nand_resources,
262 .num_resources = ARRAY_SIZE(nand_resources),
263};
264
265void __init at91_add_device_nand(struct atmel_nand_data *data)
266{
267 unsigned long csa;
268
269 if (!data)
270 return;
271
272 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
273 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
274
275 /* enable pin */
276 if (gpio_is_valid(data->enable_pin))
277 at91_set_gpio_output(data->enable_pin, 1);
278
279 /* ready/busy pin */
280 if (gpio_is_valid(data->rdy_pin))
281 at91_set_gpio_input(data->rdy_pin, 1);
282
283 /* card detect pin */
284 if (gpio_is_valid(data->det_pin))
285 at91_set_gpio_input(data->det_pin, 1);
286
287 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
288 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
289
290 nand_data = *data;
291 platform_device_register(&atmel_nand_device);
292}
293
294#else
295void __init at91_add_device_nand(struct atmel_nand_data *data) {}
296#endif
297
298
299/* --------------------------------------------------------------------
300 * TWI (i2c)
301 * -------------------------------------------------------------------- */
302
303/*
304 * Prefer the GPIO code since the TWI controller isn't robust
305 * (gets overruns and underruns under load) and can only issue
306 * repeated STARTs in one scenario (the driver doesn't yet handle them).
307 */
308#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
309
310static struct i2c_gpio_platform_data pdata = {
311 .sda_pin = AT91_PIN_PA23,
312 .sda_is_open_drain = 1,
313 .scl_pin = AT91_PIN_PA24,
314 .scl_is_open_drain = 1,
315 .udelay = 2, /* ~100 kHz */
316};
317
318static struct platform_device at91sam9rl_twi_device = {
319 .name = "i2c-gpio",
320 .id = 0,
321 .dev.platform_data = &pdata,
322};
323
324void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
325{
326 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
327 at91_set_multi_drive(AT91_PIN_PA23, 1);
328
329 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
330 at91_set_multi_drive(AT91_PIN_PA24, 1);
331
332 i2c_register_board_info(0, devices, nr_devices);
333 platform_device_register(&at91sam9rl_twi_device);
334}
335
336#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
337
338static struct resource twi_resources[] = {
339 [0] = {
340 .start = AT91SAM9RL_BASE_TWI0,
341 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
345 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
346 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
347 .flags = IORESOURCE_IRQ,
348 },
349};
350
351static struct platform_device at91sam9rl_twi_device = {
352 .name = "i2c-at91sam9g20",
353 .id = 0,
354 .resource = twi_resources,
355 .num_resources = ARRAY_SIZE(twi_resources),
356};
357
358void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
359{
360 /* pins used for TWI interface */
361 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
362 at91_set_multi_drive(AT91_PIN_PA23, 1);
363
364 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
365 at91_set_multi_drive(AT91_PIN_PA24, 1);
366
367 i2c_register_board_info(0, devices, nr_devices);
368 platform_device_register(&at91sam9rl_twi_device);
369}
370#else
371void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
372#endif
373
374
375/* --------------------------------------------------------------------
376 * SPI
377 * -------------------------------------------------------------------- */
378
379#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
380static u64 spi_dmamask = DMA_BIT_MASK(32);
381
382static struct resource spi_resources[] = {
383 [0] = {
384 .start = AT91SAM9RL_BASE_SPI,
385 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
390 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
391 .flags = IORESOURCE_IRQ,
392 },
393};
394
395static struct platform_device at91sam9rl_spi_device = {
396 .name = "atmel_spi",
397 .id = 0,
398 .dev = {
399 .dma_mask = &spi_dmamask,
400 .coherent_dma_mask = DMA_BIT_MASK(32),
401 },
402 .resource = spi_resources,
403 .num_resources = ARRAY_SIZE(spi_resources),
404};
405
406static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
407
408
409void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
410{
411 int i;
412 unsigned long cs_pin;
413
414 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
415 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
416 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
417
418 /* Enable SPI chip-selects */
419 for (i = 0; i < nr_devices; i++) {
420 if (devices[i].controller_data)
421 cs_pin = (unsigned long) devices[i].controller_data;
422 else
423 cs_pin = spi_standard_cs[devices[i].chip_select];
424
425 if (!gpio_is_valid(cs_pin))
426 continue;
427
428 /* enable chip-select pin */
429 at91_set_gpio_output(cs_pin, 1);
430
431 /* pass chip-select pin to driver */
432 devices[i].controller_data = (void *) cs_pin;
433 }
434
435 spi_register_board_info(devices, nr_devices);
436 platform_device_register(&at91sam9rl_spi_device);
437}
438#else
439void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
440#endif
441
442
443/* --------------------------------------------------------------------
444 * AC97
445 * -------------------------------------------------------------------- */
446
447#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
448static u64 ac97_dmamask = DMA_BIT_MASK(32);
449static struct ac97c_platform_data ac97_data;
450
451static struct resource ac97_resources[] = {
452 [0] = {
453 .start = AT91SAM9RL_BASE_AC97C,
454 .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 [1] = {
458 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
459 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
460 .flags = IORESOURCE_IRQ,
461 },
462};
463
464static struct platform_device at91sam9rl_ac97_device = {
465 .name = "atmel_ac97c",
466 .id = 0,
467 .dev = {
468 .dma_mask = &ac97_dmamask,
469 .coherent_dma_mask = DMA_BIT_MASK(32),
470 .platform_data = &ac97_data,
471 },
472 .resource = ac97_resources,
473 .num_resources = ARRAY_SIZE(ac97_resources),
474};
475
476void __init at91_add_device_ac97(struct ac97c_platform_data *data)
477{
478 if (!data)
479 return;
480
481 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */
482 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */
483 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */
484 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
485
486 /* reset */
487 if (gpio_is_valid(data->reset_pin))
488 at91_set_gpio_output(data->reset_pin, 0);
489
490 ac97_data = *data;
491 platform_device_register(&at91sam9rl_ac97_device);
492}
493#else
494void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
495#endif
496
497
498/* --------------------------------------------------------------------
499 * LCD Controller
500 * -------------------------------------------------------------------- */
501
502#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
503static u64 lcdc_dmamask = DMA_BIT_MASK(32);
504static struct atmel_lcdfb_pdata lcdc_data;
505
506static struct resource lcdc_resources[] = {
507 [0] = {
508 .start = AT91SAM9RL_LCDC_BASE,
509 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
510 .flags = IORESOURCE_MEM,
511 },
512 [1] = {
513 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
514 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
515 .flags = IORESOURCE_IRQ,
516 },
517};
518
519static struct platform_device at91_lcdc_device = {
520 .name = "at91sam9rl-lcdfb",
521 .id = 0,
522 .dev = {
523 .dma_mask = &lcdc_dmamask,
524 .coherent_dma_mask = DMA_BIT_MASK(32),
525 .platform_data = &lcdc_data,
526 },
527 .resource = lcdc_resources,
528 .num_resources = ARRAY_SIZE(lcdc_resources),
529};
530
531void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
532{
533 if (!data) {
534 return;
535 }
536
537 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
538 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
539 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
540 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
541 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
542 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
543 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
544 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
545 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
546 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
547 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
548 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
549 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
550 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
551 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
552 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
553 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
554 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
555 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
556 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
557 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
558
559 lcdc_data = *data;
560 platform_device_register(&at91_lcdc_device);
561}
562#else
563void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
564#endif
565
566
567/* --------------------------------------------------------------------
568 * Timer/Counter block
569 * -------------------------------------------------------------------- */
570
571#ifdef CONFIG_ATMEL_TCLIB
572
573static struct resource tcb_resources[] = {
574 [0] = {
575 .start = AT91SAM9RL_BASE_TCB0,
576 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
581 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
582 .flags = IORESOURCE_IRQ,
583 },
584 [2] = {
585 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
586 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
587 .flags = IORESOURCE_IRQ,
588 },
589 [3] = {
590 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
591 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device at91sam9rl_tcb_device = {
597 .name = "atmel_tcb",
598 .id = 0,
599 .resource = tcb_resources,
600 .num_resources = ARRAY_SIZE(tcb_resources),
601};
602
603static void __init at91_add_device_tc(void)
604{
605 platform_device_register(&at91sam9rl_tcb_device);
606}
607#else
608static void __init at91_add_device_tc(void) { }
609#endif
610
611
612/* --------------------------------------------------------------------
613 * ADC and Touchscreen
614 * -------------------------------------------------------------------- */
615
616#if IS_ENABLED(CONFIG_AT91_ADC)
617static struct at91_adc_data adc_data;
618
619static struct resource adc_resources[] = {
620 [0] = {
621 .start = AT91SAM9RL_BASE_TSC,
622 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
623 .flags = IORESOURCE_MEM,
624 },
625 [1] = {
626 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
627 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
628 .flags = IORESOURCE_IRQ,
629 }
630};
631
632static struct platform_device at91_adc_device = {
633 .name = "at91sam9rl-adc",
634 .id = -1,
635 .dev = {
636 .platform_data = &adc_data,
637 },
638 .resource = adc_resources,
639 .num_resources = ARRAY_SIZE(adc_resources),
640};
641
642static struct at91_adc_trigger at91_adc_triggers[] = {
643 [0] = {
644 .name = "external-rising",
645 .value = 1,
646 .is_external = true,
647 },
648 [1] = {
649 .name = "external-falling",
650 .value = 2,
651 .is_external = true,
652 },
653 [2] = {
654 .name = "external-any",
655 .value = 3,
656 .is_external = true,
657 },
658 [3] = {
659 .name = "continuous",
660 .value = 6,
661 .is_external = false,
662 },
663};
664
665void __init at91_add_device_adc(struct at91_adc_data *data)
666{
667 if (!data)
668 return;
669
670 if (test_bit(0, &data->channels_used))
671 at91_set_A_periph(AT91_PIN_PA17, 0);
672 if (test_bit(1, &data->channels_used))
673 at91_set_A_periph(AT91_PIN_PA18, 0);
674 if (test_bit(2, &data->channels_used))
675 at91_set_A_periph(AT91_PIN_PA19, 0);
676 if (test_bit(3, &data->channels_used))
677 at91_set_A_periph(AT91_PIN_PA20, 0);
678 if (test_bit(4, &data->channels_used))
679 at91_set_A_periph(AT91_PIN_PD6, 0);
680 if (test_bit(5, &data->channels_used))
681 at91_set_A_periph(AT91_PIN_PD7, 0);
682
683 if (data->use_external_triggers)
684 at91_set_A_periph(AT91_PIN_PB15, 0);
685
686 data->startup_time = 40;
687 data->trigger_number = 4;
688 data->trigger_list = at91_adc_triggers;
689
690 adc_data = *data;
691 platform_device_register(&at91_adc_device);
692}
693#else
694void __init at91_add_device_adc(struct at91_adc_data *data) {}
695#endif
696
697/* --------------------------------------------------------------------
698 * RTC
699 * -------------------------------------------------------------------- */
700
701#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
702static struct platform_device at91sam9rl_rtc_device = {
703 .name = "at91_rtc",
704 .id = -1,
705 .num_resources = 0,
706};
707
708static void __init at91_add_device_rtc(void)
709{
710 platform_device_register(&at91sam9rl_rtc_device);
711}
712#else
713static void __init at91_add_device_rtc(void) {}
714#endif
715
716
717/* --------------------------------------------------------------------
718 * RTT
719 * -------------------------------------------------------------------- */
720
721static struct resource rtt_resources[] = {
722 {
723 .start = AT91SAM9RL_BASE_RTT,
724 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
725 .flags = IORESOURCE_MEM,
726 }, {
727 .flags = IORESOURCE_MEM,
728 }, {
729 .flags = IORESOURCE_IRQ,
730 }
731};
732
733static struct platform_device at91sam9rl_rtt_device = {
734 .name = "at91_rtt",
735 .id = 0,
736 .resource = rtt_resources,
737};
738
739#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
740static void __init at91_add_device_rtt_rtc(void)
741{
742 at91sam9rl_rtt_device.name = "rtc-at91sam9";
743 /*
744 * The second resource is needed:
745 * GPBR will serve as the storage for RTC time offset
746 */
747 at91sam9rl_rtt_device.num_resources = 3;
748 rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
749 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
750 rtt_resources[1].end = rtt_resources[1].start + 3;
751 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
752 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
753}
754#else
755static void __init at91_add_device_rtt_rtc(void)
756{
757 /* Only one resource is needed: RTT not used as RTC */
758 at91sam9rl_rtt_device.num_resources = 1;
759}
760#endif
761
762static void __init at91_add_device_rtt(void)
763{
764 at91_add_device_rtt_rtc();
765 platform_device_register(&at91sam9rl_rtt_device);
766}
767
768
769/* --------------------------------------------------------------------
770 * Watchdog
771 * -------------------------------------------------------------------- */
772
773#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
774static struct resource wdt_resources[] = {
775 {
776 .start = AT91SAM9RL_BASE_WDT,
777 .end = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
778 .flags = IORESOURCE_MEM,
779 }
780};
781
782static struct platform_device at91sam9rl_wdt_device = {
783 .name = "at91_wdt",
784 .id = -1,
785 .resource = wdt_resources,
786 .num_resources = ARRAY_SIZE(wdt_resources),
787};
788
789static void __init at91_add_device_watchdog(void)
790{
791 platform_device_register(&at91sam9rl_wdt_device);
792}
793#else
794static void __init at91_add_device_watchdog(void) {}
795#endif
796
797
798/* --------------------------------------------------------------------
799 * PWM
800 * --------------------------------------------------------------------*/
801
802#if IS_ENABLED(CONFIG_PWM_ATMEL)
803static struct resource pwm_resources[] = {
804 [0] = {
805 .start = AT91SAM9RL_BASE_PWMC,
806 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
807 .flags = IORESOURCE_MEM,
808 },
809 [1] = {
810 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
811 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
812 .flags = IORESOURCE_IRQ,
813 },
814};
815
816static struct platform_device at91sam9rl_pwm0_device = {
817 .name = "at91sam9rl-pwm",
818 .id = -1,
819 .resource = pwm_resources,
820 .num_resources = ARRAY_SIZE(pwm_resources),
821};
822
823void __init at91_add_device_pwm(u32 mask)
824{
825 if (mask & (1 << AT91_PWM0))
826 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
827
828 if (mask & (1 << AT91_PWM1))
829 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
830
831 if (mask & (1 << AT91_PWM2))
832 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
833
834 if (mask & (1 << AT91_PWM3))
835 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
836
837 platform_device_register(&at91sam9rl_pwm0_device);
838}
839#else
840void __init at91_add_device_pwm(u32 mask) {}
841#endif
842
843
844/* --------------------------------------------------------------------
845 * SSC -- Synchronous Serial Controller
846 * -------------------------------------------------------------------- */
847
848#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
849static u64 ssc0_dmamask = DMA_BIT_MASK(32);
850
851static struct resource ssc0_resources[] = {
852 [0] = {
853 .start = AT91SAM9RL_BASE_SSC0,
854 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
855 .flags = IORESOURCE_MEM,
856 },
857 [1] = {
858 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
859 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
860 .flags = IORESOURCE_IRQ,
861 },
862};
863
864static struct platform_device at91sam9rl_ssc0_device = {
865 .name = "at91rm9200_ssc",
866 .id = 0,
867 .dev = {
868 .dma_mask = &ssc0_dmamask,
869 .coherent_dma_mask = DMA_BIT_MASK(32),
870 },
871 .resource = ssc0_resources,
872 .num_resources = ARRAY_SIZE(ssc0_resources),
873};
874
875static inline void configure_ssc0_pins(unsigned pins)
876{
877 if (pins & ATMEL_SSC_TF)
878 at91_set_A_periph(AT91_PIN_PC0, 1);
879 if (pins & ATMEL_SSC_TK)
880 at91_set_A_periph(AT91_PIN_PC1, 1);
881 if (pins & ATMEL_SSC_TD)
882 at91_set_A_periph(AT91_PIN_PA15, 1);
883 if (pins & ATMEL_SSC_RD)
884 at91_set_A_periph(AT91_PIN_PA16, 1);
885 if (pins & ATMEL_SSC_RK)
886 at91_set_B_periph(AT91_PIN_PA10, 1);
887 if (pins & ATMEL_SSC_RF)
888 at91_set_B_periph(AT91_PIN_PA22, 1);
889}
890
891static u64 ssc1_dmamask = DMA_BIT_MASK(32);
892
893static struct resource ssc1_resources[] = {
894 [0] = {
895 .start = AT91SAM9RL_BASE_SSC1,
896 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
897 .flags = IORESOURCE_MEM,
898 },
899 [1] = {
900 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
901 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
902 .flags = IORESOURCE_IRQ,
903 },
904};
905
906static struct platform_device at91sam9rl_ssc1_device = {
907 .name = "at91rm9200_ssc",
908 .id = 1,
909 .dev = {
910 .dma_mask = &ssc1_dmamask,
911 .coherent_dma_mask = DMA_BIT_MASK(32),
912 },
913 .resource = ssc1_resources,
914 .num_resources = ARRAY_SIZE(ssc1_resources),
915};
916
917static inline void configure_ssc1_pins(unsigned pins)
918{
919 if (pins & ATMEL_SSC_TF)
920 at91_set_B_periph(AT91_PIN_PA29, 1);
921 if (pins & ATMEL_SSC_TK)
922 at91_set_B_periph(AT91_PIN_PA30, 1);
923 if (pins & ATMEL_SSC_TD)
924 at91_set_B_periph(AT91_PIN_PA13, 1);
925 if (pins & ATMEL_SSC_RD)
926 at91_set_B_periph(AT91_PIN_PA14, 1);
927 if (pins & ATMEL_SSC_RK)
928 at91_set_B_periph(AT91_PIN_PA9, 1);
929 if (pins & ATMEL_SSC_RF)
930 at91_set_B_periph(AT91_PIN_PA8, 1);
931}
932
933/*
934 * SSC controllers are accessed through library code, instead of any
935 * kind of all-singing/all-dancing driver. For example one could be
936 * used by a particular I2S audio codec's driver, while another one
937 * on the same system might be used by a custom data capture driver.
938 */
939void __init at91_add_device_ssc(unsigned id, unsigned pins)
940{
941 struct platform_device *pdev;
942
943 /*
944 * NOTE: caller is responsible for passing information matching
945 * "pins" to whatever will be using each particular controller.
946 */
947 switch (id) {
948 case AT91SAM9RL_ID_SSC0:
949 pdev = &at91sam9rl_ssc0_device;
950 configure_ssc0_pins(pins);
951 break;
952 case AT91SAM9RL_ID_SSC1:
953 pdev = &at91sam9rl_ssc1_device;
954 configure_ssc1_pins(pins);
955 break;
956 default:
957 return;
958 }
959
960 platform_device_register(pdev);
961}
962
963#else
964void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
965#endif
966
967
968/* --------------------------------------------------------------------
969 * UART
970 * -------------------------------------------------------------------- */
971
972#if defined(CONFIG_SERIAL_ATMEL)
973static struct resource dbgu_resources[] = {
974 [0] = {
975 .start = AT91SAM9RL_BASE_DBGU,
976 .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
977 .flags = IORESOURCE_MEM,
978 },
979 [1] = {
980 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
981 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
982 .flags = IORESOURCE_IRQ,
983 },
984};
985
986static struct atmel_uart_data dbgu_data = {
987 .use_dma_tx = 0,
988 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
989};
990
991static u64 dbgu_dmamask = DMA_BIT_MASK(32);
992
993static struct platform_device at91sam9rl_dbgu_device = {
994 .name = "atmel_usart",
995 .id = 0,
996 .dev = {
997 .dma_mask = &dbgu_dmamask,
998 .coherent_dma_mask = DMA_BIT_MASK(32),
999 .platform_data = &dbgu_data,
1000 },
1001 .resource = dbgu_resources,
1002 .num_resources = ARRAY_SIZE(dbgu_resources),
1003};
1004
1005static inline void configure_dbgu_pins(void)
1006{
1007 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
1008 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
1009}
1010
1011static struct resource uart0_resources[] = {
1012 [0] = {
1013 .start = AT91SAM9RL_BASE_US0,
1014 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
1015 .flags = IORESOURCE_MEM,
1016 },
1017 [1] = {
1018 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
1019 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
1020 .flags = IORESOURCE_IRQ,
1021 },
1022};
1023
1024static struct atmel_uart_data uart0_data = {
1025 .use_dma_tx = 1,
1026 .use_dma_rx = 1,
1027};
1028
1029static u64 uart0_dmamask = DMA_BIT_MASK(32);
1030
1031static struct platform_device at91sam9rl_uart0_device = {
1032 .name = "atmel_usart",
1033 .id = 1,
1034 .dev = {
1035 .dma_mask = &uart0_dmamask,
1036 .coherent_dma_mask = DMA_BIT_MASK(32),
1037 .platform_data = &uart0_data,
1038 },
1039 .resource = uart0_resources,
1040 .num_resources = ARRAY_SIZE(uart0_resources),
1041};
1042
1043static inline void configure_usart0_pins(unsigned pins)
1044{
1045 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
1046 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
1047
1048 if (pins & ATMEL_UART_RTS)
1049 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
1050 if (pins & ATMEL_UART_CTS)
1051 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
1052 if (pins & ATMEL_UART_DSR)
1053 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
1054 if (pins & ATMEL_UART_DTR)
1055 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
1056 if (pins & ATMEL_UART_DCD)
1057 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
1058 if (pins & ATMEL_UART_RI)
1059 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
1060}
1061
1062static struct resource uart1_resources[] = {
1063 [0] = {
1064 .start = AT91SAM9RL_BASE_US1,
1065 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1066 .flags = IORESOURCE_MEM,
1067 },
1068 [1] = {
1069 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
1070 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
1071 .flags = IORESOURCE_IRQ,
1072 },
1073};
1074
1075static struct atmel_uart_data uart1_data = {
1076 .use_dma_tx = 1,
1077 .use_dma_rx = 1,
1078};
1079
1080static u64 uart1_dmamask = DMA_BIT_MASK(32);
1081
1082static struct platform_device at91sam9rl_uart1_device = {
1083 .name = "atmel_usart",
1084 .id = 2,
1085 .dev = {
1086 .dma_mask = &uart1_dmamask,
1087 .coherent_dma_mask = DMA_BIT_MASK(32),
1088 .platform_data = &uart1_data,
1089 },
1090 .resource = uart1_resources,
1091 .num_resources = ARRAY_SIZE(uart1_resources),
1092};
1093
1094static inline void configure_usart1_pins(unsigned pins)
1095{
1096 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
1097 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
1098
1099 if (pins & ATMEL_UART_RTS)
1100 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
1101 if (pins & ATMEL_UART_CTS)
1102 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
1103}
1104
1105static struct resource uart2_resources[] = {
1106 [0] = {
1107 .start = AT91SAM9RL_BASE_US2,
1108 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
1109 .flags = IORESOURCE_MEM,
1110 },
1111 [1] = {
1112 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
1113 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
1114 .flags = IORESOURCE_IRQ,
1115 },
1116};
1117
1118static struct atmel_uart_data uart2_data = {
1119 .use_dma_tx = 1,
1120 .use_dma_rx = 1,
1121};
1122
1123static u64 uart2_dmamask = DMA_BIT_MASK(32);
1124
1125static struct platform_device at91sam9rl_uart2_device = {
1126 .name = "atmel_usart",
1127 .id = 3,
1128 .dev = {
1129 .dma_mask = &uart2_dmamask,
1130 .coherent_dma_mask = DMA_BIT_MASK(32),
1131 .platform_data = &uart2_data,
1132 },
1133 .resource = uart2_resources,
1134 .num_resources = ARRAY_SIZE(uart2_resources),
1135};
1136
1137static inline void configure_usart2_pins(unsigned pins)
1138{
1139 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1140 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
1141
1142 if (pins & ATMEL_UART_RTS)
1143 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1144 if (pins & ATMEL_UART_CTS)
1145 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
1146}
1147
1148static struct resource uart3_resources[] = {
1149 [0] = {
1150 .start = AT91SAM9RL_BASE_US3,
1151 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1152 .flags = IORESOURCE_MEM,
1153 },
1154 [1] = {
1155 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
1156 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
1157 .flags = IORESOURCE_IRQ,
1158 },
1159};
1160
1161static struct atmel_uart_data uart3_data = {
1162 .use_dma_tx = 1,
1163 .use_dma_rx = 1,
1164};
1165
1166static u64 uart3_dmamask = DMA_BIT_MASK(32);
1167
1168static struct platform_device at91sam9rl_uart3_device = {
1169 .name = "atmel_usart",
1170 .id = 4,
1171 .dev = {
1172 .dma_mask = &uart3_dmamask,
1173 .coherent_dma_mask = DMA_BIT_MASK(32),
1174 .platform_data = &uart3_data,
1175 },
1176 .resource = uart3_resources,
1177 .num_resources = ARRAY_SIZE(uart3_resources),
1178};
1179
1180static inline void configure_usart3_pins(unsigned pins)
1181{
1182 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1183 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
1184
1185 if (pins & ATMEL_UART_RTS)
1186 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1187 if (pins & ATMEL_UART_CTS)
1188 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1189}
1190
1191static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1192
1193void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1194{
1195 struct platform_device *pdev;
1196 struct atmel_uart_data *pdata;
1197
1198 switch (id) {
1199 case 0: /* DBGU */
1200 pdev = &at91sam9rl_dbgu_device;
1201 configure_dbgu_pins();
1202 break;
1203 case AT91SAM9RL_ID_US0:
1204 pdev = &at91sam9rl_uart0_device;
1205 configure_usart0_pins(pins);
1206 break;
1207 case AT91SAM9RL_ID_US1:
1208 pdev = &at91sam9rl_uart1_device;
1209 configure_usart1_pins(pins);
1210 break;
1211 case AT91SAM9RL_ID_US2:
1212 pdev = &at91sam9rl_uart2_device;
1213 configure_usart2_pins(pins);
1214 break;
1215 case AT91SAM9RL_ID_US3:
1216 pdev = &at91sam9rl_uart3_device;
1217 configure_usart3_pins(pins);
1218 break;
1219 default:
1220 return;
1221 }
1222 pdata = pdev->dev.platform_data;
1223 pdata->num = portnr; /* update to mapped ID */
1224
1225 if (portnr < ATMEL_MAX_UART)
1226 at91_uarts[portnr] = pdev;
1227}
1228
1229void __init at91_add_device_serial(void)
1230{
1231 int i;
1232
1233 for (i = 0; i < ATMEL_MAX_UART; i++) {
1234 if (at91_uarts[i])
1235 platform_device_register(at91_uarts[i]);
1236 }
1237}
1238#else
1239void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1240void __init at91_add_device_serial(void) {}
1241#endif
1242
1243
1244/* -------------------------------------------------------------------- */
1245
1246/*
1247 * These devices are always present and don't need any board-specific
1248 * setup.
1249 */
1250static int __init at91_add_standard_devices(void)
1251{
1252 at91_add_device_hdmac();
1253 at91_add_device_rtc();
1254 at91_add_device_rtt();
1255 at91_add_device_watchdog();
1256 at91_add_device_tc();
1257 return 0;
1258}
1259
1260arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
deleted file mode 100644
index 7523f1cdfe1d..000000000000
--- a/arch/arm/mach-at91/at91x40.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91x40.c
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 * Copyright (C) 2005 SAN People
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/proc-fns.h>
18#include <asm/system_misc.h>
19#include <asm/mach/arch.h>
20#include <mach/at91x40.h>
21#include <mach/at91_st.h>
22#include <mach/hardware.h>
23
24#include "at91_aic.h"
25#include "generic.h"
26
27/*
28 * Export the clock functions for the AT91X40. Some external code common
29 * to all AT91 family parts relys on this, like the gpio and serial support.
30 */
31int clk_enable(struct clk *clk)
32{
33 return 0;
34}
35
36void clk_disable(struct clk *clk)
37{
38}
39
40unsigned long clk_get_rate(struct clk *clk)
41{
42 return AT91X40_MASTER_CLOCK;
43}
44
45static void at91x40_idle(void)
46{
47 /*
48 * Disable the processor clock. The processor will be automatically
49 * re-enabled by an interrupt or by a reset.
50 */
51 __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
52 cpu_do_idle();
53}
54
55void __init at91x40_initialize(unsigned long main_clock)
56{
57 arm_pm_idle = at91x40_idle;
58}
59
60/*
61 * The default interrupt priority levels (0 = lowest, 7 = highest).
62 */
63static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
64 7, /* Advanced Interrupt Controller (FIQ) */
65 0, /* System Peripherals */
66 0, /* USART 0 */
67 0, /* USART 1 */
68 2, /* Timer Counter 0 */
69 2, /* Timer Counter 1 */
70 2, /* Timer Counter 2 */
71 0, /* Watchdog timer */
72 0, /* Parallel IO Controller A */
73 0, /* Reserved */
74 0, /* Reserved */
75 0, /* Reserved */
76 0, /* Reserved */
77 0, /* Reserved */
78 0, /* Reserved */
79 0, /* Reserved */
80 0, /* External IRQ0 */
81 0, /* External IRQ1 */
82 0, /* External IRQ2 */
83};
84
85void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
86{
87 u32 extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
88 | (1 << AT91X40_ID_IRQ2);
89 if (!priority)
90 priority = at91x40_default_irq_priority;
91
92 at91_aic_init(priority, extern_irq);
93}
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
deleted file mode 100644
index 07d0bf2ac2da..000000000000
--- a/arch/arm/mach-at91/at91x40_time.c
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91x40_time.c
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/time.h>
26#include <linux/io.h>
27#include <mach/hardware.h>
28#include <mach/at91x40.h>
29#include <asm/mach/time.h>
30
31#include "at91_tc.h"
32
33#define at91_tc_read(field) \
34 __raw_readl(AT91_IO_P2V(AT91_TC) + field)
35
36#define at91_tc_write(field, value) \
37 __raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
38
39/*
40 * 3 counter/timer units present.
41 */
42#define AT91_TC_CLK0BASE 0
43#define AT91_TC_CLK1BASE 0x40
44#define AT91_TC_CLK2BASE 0x80
45
46static u32 at91x40_gettimeoffset(void)
47{
48 return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 /
49 (AT91X40_MASTER_CLOCK / 128)) * 1000;
50}
51
52static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
53{
54 at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
55 timer_tick();
56 return IRQ_HANDLED;
57}
58
59static struct irqaction at91x40_timer_irq = {
60 .name = "at91_tick",
61 .flags = IRQF_TIMER,
62 .handler = at91x40_timer_interrupt
63};
64
65void __init at91x40_timer_init(void)
66{
67 unsigned int v;
68
69 arch_gettimeoffset = at91x40_gettimeoffset;
70
71 at91_tc_write(AT91_TC_BCR, 0);
72 v = at91_tc_read(AT91_TC_BMR);
73 v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
74 at91_tc_write(AT91_TC_BMR, v);
75
76 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
77 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
78 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
79 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
80 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
81
82 setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
83
84 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
85}
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
deleted file mode 100644
index becf0a6a289e..000000000000
--- a/arch/arm/mach-at91/board-eb01.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * arch/arm/mach-at91/board-eb01.c
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/irq.h>
26#include <asm/mach-types.h>
27#include <mach/hardware.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30
31#include "at91_aic.h"
32#include "board.h"
33#include "generic.h"
34
35static void __init at91eb01_init_irq(void)
36{
37 at91x40_init_interrupts(NULL);
38}
39
40static void __init at91eb01_init_early(void)
41{
42 at91x40_initialize(40000000);
43}
44
45MACHINE_START(AT91EB01, "Atmel AT91 EB01")
46 /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
47 .init_time = at91x40_timer_init,
48 .handle_irq = at91_aic_handle_irq,
49 .init_early = at91eb01_init_early,
50 .init_irq = at91eb01_init_irq,
51MACHINE_END
52
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
deleted file mode 100644
index a517c7f7af92..000000000000
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ /dev/null
@@ -1,527 +0,0 @@
1/*
2 * Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
3 *
4 * Covers: * AT91SAM9G45-EKES board
5 * * AT91SAM9M10G45-EK board
6 *
7 * Copyright (C) 2009 Atmel Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/types.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23#include <linux/fb.h>
24#include <linux/gpio_keys.h>
25#include <linux/input.h>
26#include <linux/leds.h>
27#include <linux/atmel-mci.h>
28#include <linux/delay.h>
29#include <linux/pwm.h>
30#include <linux/leds_pwm.h>
31
32#include <linux/platform_data/at91_adc.h>
33
34#include <mach/hardware.h>
35#include <video/atmel_lcdc.h>
36#include <media/soc_camera.h>
37#include <media/atmel-isi.h>
38
39#include <asm/setup.h>
40#include <asm/mach-types.h>
41#include <asm/irq.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46
47#include <mach/at91sam9_smc.h>
48#include <mach/system_rev.h>
49
50#include "at91_aic.h"
51#include "board.h"
52#include "sam9_smc.h"
53#include "generic.h"
54#include "gpio.h"
55
56
57static void __init ek_init_early(void)
58{
59 /* Initialize processor: 12.000 MHz crystal */
60 at91_initialize(12000000);
61}
62
63/*
64 * USB HS Host port (common to OHCI & EHCI)
65 */
66static struct at91_usbh_data __initdata ek_usbh_hs_data = {
67 .ports = 2,
68 .vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3},
69 .vbus_pin_active_low = {1, 1},
70 .overcurrent_pin= {-EINVAL, -EINVAL},
71};
72
73
74/*
75 * USB HS Device port
76 */
77static struct usba_platform_data __initdata ek_usba_udc_data = {
78 .vbus_pin = AT91_PIN_PB19,
79};
80
81
82/*
83 * SPI devices.
84 */
85static struct spi_board_info ek_spi_devices[] = {
86 { /* DataFlash chip */
87 .modalias = "mtd_dataflash",
88 .chip_select = 0,
89 .max_speed_hz = 15 * 1000 * 1000,
90 .bus_num = 0,
91 },
92};
93
94
95/*
96 * MCI (SD/MMC)
97 */
98static struct mci_platform_data __initdata mci0_data = {
99 .slot[0] = {
100 .bus_width = 4,
101 .detect_pin = AT91_PIN_PD10,
102 .wp_pin = -EINVAL,
103 },
104};
105
106static struct mci_platform_data __initdata mci1_data = {
107 .slot[0] = {
108 .bus_width = 4,
109 .detect_pin = AT91_PIN_PD11,
110 .wp_pin = AT91_PIN_PD29,
111 },
112};
113
114
115/*
116 * MACB Ethernet device
117 */
118static struct macb_platform_data __initdata ek_macb_data = {
119 .phy_irq_pin = AT91_PIN_PD5,
120 .is_rmii = 1,
121};
122
123
124/*
125 * NAND flash
126 */
127static struct mtd_partition __initdata ek_nand_partition[] = {
128 {
129 .name = "Partition 1",
130 .offset = 0,
131 .size = SZ_64M,
132 },
133 {
134 .name = "Partition 2",
135 .offset = MTDPART_OFS_NXTBLK,
136 .size = MTDPART_SIZ_FULL,
137 },
138};
139
140/* det_pin is not connected */
141static struct atmel_nand_data __initdata ek_nand_data = {
142 .ale = 21,
143 .cle = 22,
144 .rdy_pin = AT91_PIN_PC8,
145 .enable_pin = AT91_PIN_PC14,
146 .det_pin = -EINVAL,
147 .ecc_mode = NAND_ECC_SOFT,
148 .on_flash_bbt = 1,
149 .parts = ek_nand_partition,
150 .num_parts = ARRAY_SIZE(ek_nand_partition),
151};
152
153static struct sam9_smc_config __initdata ek_nand_smc_config = {
154 .ncs_read_setup = 0,
155 .nrd_setup = 2,
156 .ncs_write_setup = 0,
157 .nwe_setup = 2,
158
159 .ncs_read_pulse = 4,
160 .nrd_pulse = 4,
161 .ncs_write_pulse = 4,
162 .nwe_pulse = 4,
163
164 .read_cycle = 7,
165 .write_cycle = 7,
166
167 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
168 .tdf_cycles = 3,
169};
170
171static void __init ek_add_device_nand(void)
172{
173 ek_nand_data.bus_width_16 = board_have_nand_16bit();
174 /* setup bus-width (8 or 16) */
175 if (ek_nand_data.bus_width_16)
176 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
177 else
178 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
179
180 /* configure chip-select 3 (NAND) */
181 sam9_smc_configure(0, 3, &ek_nand_smc_config);
182
183 at91_add_device_nand(&ek_nand_data);
184}
185
186
187/*
188 * ISI
189 */
190static struct isi_platform_data __initdata isi_data = {
191 .frate = ISI_CFG1_FRATE_CAPTURE_ALL,
192 /* to use codec and preview path simultaneously */
193 .full_mode = 1,
194 .data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
195 /* ISI_MCK is provided by programmable clock or external clock */
196 .mck_hz = 25000000,
197};
198
199
200/*
201 * soc-camera OV2640
202 */
203#if defined(CONFIG_SOC_CAMERA_OV2640) || \
204 defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
205static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
206{
207 /* ISI board for ek using default 8-bits connection */
208 return SOCAM_DATAWIDTH_8;
209}
210
211static int i2c_camera_power(struct device *dev, int on)
212{
213 /* enable or disable the camera */
214 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
215 at91_set_gpio_output(AT91_PIN_PD13, !on);
216
217 if (!on)
218 goto out;
219
220 /* If enabled, give a reset impulse */
221 at91_set_gpio_output(AT91_PIN_PD12, 0);
222 msleep(20);
223 at91_set_gpio_output(AT91_PIN_PD12, 1);
224 msleep(100);
225
226out:
227 return 0;
228}
229
230static struct i2c_board_info i2c_camera = {
231 I2C_BOARD_INFO("ov2640", 0x30),
232};
233
234static struct soc_camera_link iclink_ov2640 = {
235 .bus_id = 0,
236 .board_info = &i2c_camera,
237 .i2c_adapter_id = 0,
238 .power = i2c_camera_power,
239 .query_bus_param = isi_camera_query_bus_param,
240};
241
242static struct platform_device isi_ov2640 = {
243 .name = "soc-camera-pdrv",
244 .id = 0,
245 .dev = {
246 .platform_data = &iclink_ov2640,
247 },
248};
249#endif
250
251
252/*
253 * LCD Controller
254 */
255#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
256static struct fb_videomode at91_tft_vga_modes[] = {
257 {
258 .name = "LG",
259 .refresh = 60,
260 .xres = 480, .yres = 272,
261 .pixclock = KHZ2PICOS(9000),
262
263 .left_margin = 1, .right_margin = 1,
264 .upper_margin = 40, .lower_margin = 1,
265 .hsync_len = 45, .vsync_len = 1,
266
267 .sync = 0,
268 .vmode = FB_VMODE_NONINTERLACED,
269 },
270};
271
272static struct fb_monspecs at91fb_default_monspecs = {
273 .manufacturer = "LG",
274 .monitor = "LB043WQ1",
275
276 .modedb = at91_tft_vga_modes,
277 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
278 .hfmin = 15000,
279 .hfmax = 17640,
280 .vfmin = 57,
281 .vfmax = 67,
282};
283
284#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
285 | ATMEL_LCDC_DISTYPE_TFT \
286 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
287
288/* Driver datas */
289static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
290 .lcdcon_is_backlight = true,
291 .default_bpp = 32,
292 .default_dmacon = ATMEL_LCDC_DMAEN,
293 .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2,
294 .default_monspecs = &at91fb_default_monspecs,
295 .guard_time = 9,
296 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
297};
298
299#else
300static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
301#endif
302
303
304/*
305 * ADCs and touchscreen
306 */
307static struct at91_adc_data ek_adc_data = {
308 .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7),
309 .use_external_triggers = true,
310 .vref = 3300,
311 .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
312};
313
314/*
315 * GPIO Buttons
316 */
317#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
318static struct gpio_keys_button ek_buttons[] = {
319 { /* BP1, "leftclic" */
320 .code = BTN_LEFT,
321 .gpio = AT91_PIN_PB6,
322 .active_low = 1,
323 .desc = "left_click",
324 .wakeup = 1,
325 },
326 { /* BP2, "rightclic" */
327 .code = BTN_RIGHT,
328 .gpio = AT91_PIN_PB7,
329 .active_low = 1,
330 .desc = "right_click",
331 .wakeup = 1,
332 },
333 /* BP3, "joystick" */
334 {
335 .code = KEY_LEFT,
336 .gpio = AT91_PIN_PB14,
337 .active_low = 1,
338 .desc = "Joystick Left",
339 },
340 {
341 .code = KEY_RIGHT,
342 .gpio = AT91_PIN_PB15,
343 .active_low = 1,
344 .desc = "Joystick Right",
345 },
346 {
347 .code = KEY_UP,
348 .gpio = AT91_PIN_PB16,
349 .active_low = 1,
350 .desc = "Joystick Up",
351 },
352 {
353 .code = KEY_DOWN,
354 .gpio = AT91_PIN_PB17,
355 .active_low = 1,
356 .desc = "Joystick Down",
357 },
358 {
359 .code = KEY_ENTER,
360 .gpio = AT91_PIN_PB18,
361 .active_low = 1,
362 .desc = "Joystick Press",
363 },
364};
365
366static struct gpio_keys_platform_data ek_button_data = {
367 .buttons = ek_buttons,
368 .nbuttons = ARRAY_SIZE(ek_buttons),
369};
370
371static struct platform_device ek_button_device = {
372 .name = "gpio-keys",
373 .id = -1,
374 .num_resources = 0,
375 .dev = {
376 .platform_data = &ek_button_data,
377 }
378};
379
380static void __init ek_add_device_buttons(void)
381{
382 int i;
383
384 for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
385 at91_set_GPIO_periph(ek_buttons[i].gpio, 1);
386 at91_set_deglitch(ek_buttons[i].gpio, 1);
387 }
388
389 platform_device_register(&ek_button_device);
390}
391#else
392static void __init ek_add_device_buttons(void) {}
393#endif
394
395
396/*
397 * AC97
398 * reset_pin is not connected: NRST
399 */
400static struct ac97c_platform_data ek_ac97_data = {
401 .reset_pin = -EINVAL,
402};
403
404
405/*
406 * LEDs ... these could all be PWM-driven, for variable brightness
407 */
408static struct gpio_led ek_leds[] = {
409 { /* "top" led, red, powerled */
410 .name = "d8",
411 .gpio = AT91_PIN_PD30,
412 .default_trigger = "heartbeat",
413 },
414 { /* "left" led, green, userled2, pwm3 */
415 .name = "d6",
416 .gpio = AT91_PIN_PD0,
417 .active_low = 1,
418 .default_trigger = "nand-disk",
419 },
420#if !IS_ENABLED(CONFIG_LEDS_PWM)
421 { /* "right" led, green, userled1, pwm1 */
422 .name = "d7",
423 .gpio = AT91_PIN_PD31,
424 .active_low = 1,
425 .default_trigger = "mmc0",
426 },
427#endif
428};
429
430
431/*
432 * PWM Leds
433 */
434static struct pwm_lookup pwm_lookup[] = {
435 PWM_LOOKUP("at91sam9rl-pwm", 1, "leds_pwm", "d7",
436 5000, PWM_POLARITY_INVERSED),
437};
438
439#if IS_ENABLED(CONFIG_LEDS_PWM)
440static struct led_pwm pwm_leds[] = {
441 { /* "right" led, green, userled1, pwm1 */
442 .name = "d7",
443 .max_brightness = 255,
444 },
445};
446
447static struct led_pwm_platform_data pwm_data = {
448 .num_leds = ARRAY_SIZE(pwm_leds),
449 .leds = pwm_leds,
450};
451
452static struct platform_device leds_pwm = {
453 .name = "leds_pwm",
454 .id = -1,
455 .dev = {
456 .platform_data = &pwm_data,
457 },
458};
459#endif
460
461static struct platform_device *devices[] __initdata = {
462#if defined(CONFIG_SOC_CAMERA_OV2640) || \
463 defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
464 &isi_ov2640,
465#endif
466#if IS_ENABLED(CONFIG_LEDS_PWM)
467 &leds_pwm,
468#endif
469};
470
471static void __init ek_board_init(void)
472{
473 at91_register_devices();
474
475 /* Serial */
476 /* DGBU on ttyS0. (Rx & Tx only) */
477 at91_register_uart(0, 0, 0);
478
479 /* USART0 not connected on the -EK board */
480 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
481 at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
482 at91_add_device_serial();
483 /* USB HS Host */
484 at91_add_device_usbh_ohci(&ek_usbh_hs_data);
485 at91_add_device_usbh_ehci(&ek_usbh_hs_data);
486 /* USB HS Device */
487 at91_add_device_usba(&ek_usba_udc_data);
488 /* SPI */
489 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
490 /* MMC */
491 at91_add_device_mci(0, &mci0_data);
492 at91_add_device_mci(1, &mci1_data);
493 /* Ethernet */
494 at91_add_device_eth(&ek_macb_data);
495 /* NAND */
496 ek_add_device_nand();
497 /* I2C */
498 at91_add_device_i2c(0, NULL, 0);
499 /* ISI, using programmable clock as ISI_MCK */
500 at91_add_device_isi(&isi_data, true);
501 /* LCD Controller */
502 at91_add_device_lcdc(&ek_lcdc_data);
503 /* ADC and touchscreen */
504 at91_add_device_adc(&ek_adc_data);
505 /* Push Buttons */
506 ek_add_device_buttons();
507 /* AC97 */
508 at91_add_device_ac97(&ek_ac97_data);
509 /* LEDs */
510 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
511 pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
512#if IS_ENABLED(CONFIG_LEDS_PWM)
513 at91_add_device_pwm(1 << AT91_PWM1);
514#endif
515 /* Other platform devices */
516 platform_add_devices(devices, ARRAY_SIZE(devices));
517}
518
519MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
520 /* Maintainer: Atmel */
521 .init_time = at91_init_time,
522 .map_io = at91_map_io,
523 .handle_irq = at91_aic_handle_irq,
524 .init_early = ek_init_early,
525 .init_irq = at91_init_irq_default,
526 .init_machine = ek_board_init,
527MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
deleted file mode 100644
index 8bca329b0293..000000000000
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ /dev/null
@@ -1,333 +0,0 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2007 Atmel Corporation
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
7 * more details.
8 */
9
10#include <linux/types.h>
11#include <linux/gpio.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/fb.h>
18#include <linux/clk.h>
19#include <linux/input.h>
20#include <linux/gpio_keys.h>
21#include <linux/platform_data/at91_adc.h>
22
23#include <video/atmel_lcdc.h>
24
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27#include <asm/irq.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/irq.h>
32
33#include <mach/hardware.h>
34#include <mach/at91sam9_smc.h>
35
36
37#include "at91_aic.h"
38#include "board.h"
39#include "sam9_smc.h"
40#include "generic.h"
41#include "gpio.h"
42
43
44static void __init ek_init_early(void)
45{
46 /* Initialize processor: 12.000 MHz crystal */
47 at91_initialize(12000000);
48}
49
50/*
51 * USB HS Device port
52 */
53static struct usba_platform_data __initdata ek_usba_udc_data = {
54 .vbus_pin = AT91_PIN_PA8,
55};
56
57
58/*
59 * MCI (SD/MMC)
60 */
61static struct mci_platform_data __initdata mci0_data = {
62 .slot[0] = {
63 .bus_width = 4,
64 .detect_pin = AT91_PIN_PA15,
65 .wp_pin = -EINVAL,
66 },
67};
68
69
70/*
71 * NAND flash
72 */
73static struct mtd_partition __initdata ek_nand_partition[] = {
74 {
75 .name = "Partition 1",
76 .offset = 0,
77 .size = SZ_256K,
78 },
79 {
80 .name = "Partition 2",
81 .offset = MTDPART_OFS_NXTBLK,
82 .size = MTDPART_SIZ_FULL,
83 },
84};
85
86static struct atmel_nand_data __initdata ek_nand_data = {
87 .ale = 21,
88 .cle = 22,
89 .det_pin = -EINVAL,
90 .rdy_pin = AT91_PIN_PD17,
91 .enable_pin = AT91_PIN_PB6,
92 .ecc_mode = NAND_ECC_SOFT,
93 .on_flash_bbt = 1,
94 .parts = ek_nand_partition,
95 .num_parts = ARRAY_SIZE(ek_nand_partition),
96};
97
98static struct sam9_smc_config __initdata ek_nand_smc_config = {
99 .ncs_read_setup = 0,
100 .nrd_setup = 1,
101 .ncs_write_setup = 0,
102 .nwe_setup = 1,
103
104 .ncs_read_pulse = 3,
105 .nrd_pulse = 3,
106 .ncs_write_pulse = 3,
107 .nwe_pulse = 3,
108
109 .read_cycle = 5,
110 .write_cycle = 5,
111
112 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
113 .tdf_cycles = 2,
114};
115
116static void __init ek_add_device_nand(void)
117{
118 /* configure chip-select 3 (NAND) */
119 sam9_smc_configure(0, 3, &ek_nand_smc_config);
120
121 at91_add_device_nand(&ek_nand_data);
122}
123
124
125/*
126 * SPI devices
127 */
128static struct spi_board_info ek_spi_devices[] = {
129 { /* DataFlash chip */
130 .modalias = "mtd_dataflash",
131 .chip_select = 0,
132 .max_speed_hz = 15 * 1000 * 1000,
133 .bus_num = 0,
134 },
135};
136
137
138/*
139 * LCD Controller
140 */
141#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
142static struct fb_videomode at91_tft_vga_modes[] = {
143 {
144 .name = "TX09D50VM1CCA @ 60",
145 .refresh = 60,
146 .xres = 240, .yres = 320,
147 .pixclock = KHZ2PICOS(4965),
148
149 .left_margin = 1, .right_margin = 33,
150 .upper_margin = 1, .lower_margin = 0,
151 .hsync_len = 5, .vsync_len = 1,
152
153 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
154 .vmode = FB_VMODE_NONINTERLACED,
155 },
156};
157
158static struct fb_monspecs at91fb_default_monspecs = {
159 .manufacturer = "HIT",
160 .monitor = "TX09D50VM1CCA",
161
162 .modedb = at91_tft_vga_modes,
163 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
164 .hfmin = 15000,
165 .hfmax = 64000,
166 .vfmin = 50,
167 .vfmax = 150,
168};
169
170#define AT91SAM9RL_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
171 | ATMEL_LCDC_DISTYPE_TFT \
172 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
173
174static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on)
175{
176 if (on)
177 at91_set_gpio_value(AT91_PIN_PC1, 0); /* power up */
178 else
179 at91_set_gpio_value(AT91_PIN_PC1, 1); /* power down */
180}
181
182/* Driver datas */
183static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
184 .lcdcon_is_backlight = true,
185 .default_bpp = 16,
186 .default_dmacon = ATMEL_LCDC_DMAEN,
187 .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2,
188 .default_monspecs = &at91fb_default_monspecs,
189 .atmel_lcdfb_power_control = at91_lcdc_power_control,
190 .guard_time = 1,
191 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
192};
193
194#else
195static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
196#endif
197
198
199/*
200 * AC97
201 * reset_pin is not connected: NRST
202 */
203static struct ac97c_platform_data ek_ac97_data = {
204 .reset_pin = -EINVAL,
205};
206
207
208/*
209 * LEDs
210 */
211static struct gpio_led ek_leds[] = {
212 { /* "bottom" led, green, userled1 to be defined */
213 .name = "ds1",
214 .gpio = AT91_PIN_PD15,
215 .active_low = 1,
216 .default_trigger = "none",
217 },
218 { /* "bottom" led, green, userled2 to be defined */
219 .name = "ds2",
220 .gpio = AT91_PIN_PD16,
221 .active_low = 1,
222 .default_trigger = "none",
223 },
224 { /* "power" led, yellow */
225 .name = "ds3",
226 .gpio = AT91_PIN_PD14,
227 .default_trigger = "heartbeat",
228 }
229};
230
231
232/*
233 * ADC + Touchscreen
234 */
235static struct at91_adc_data ek_adc_data = {
236 .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
237 .use_external_triggers = true,
238 .vref = 3300,
239 .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
240};
241
242
243/*
244 * GPIO Buttons
245 */
246#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
247static struct gpio_keys_button ek_buttons[] = {
248 {
249 .gpio = AT91_PIN_PB0,
250 .code = BTN_2,
251 .desc = "Right Click",
252 .active_low = 1,
253 .wakeup = 1,
254 },
255 {
256 .gpio = AT91_PIN_PB1,
257 .code = BTN_1,
258 .desc = "Left Click",
259 .active_low = 1,
260 .wakeup = 1,
261 }
262};
263
264static struct gpio_keys_platform_data ek_button_data = {
265 .buttons = ek_buttons,
266 .nbuttons = ARRAY_SIZE(ek_buttons),
267};
268
269static struct platform_device ek_button_device = {
270 .name = "gpio-keys",
271 .id = -1,
272 .num_resources = 0,
273 .dev = {
274 .platform_data = &ek_button_data,
275 }
276};
277
278static void __init ek_add_device_buttons(void)
279{
280 at91_set_gpio_input(AT91_PIN_PB1, 1); /* btn1 */
281 at91_set_deglitch(AT91_PIN_PB1, 1);
282 at91_set_gpio_input(AT91_PIN_PB0, 1); /* btn2 */
283 at91_set_deglitch(AT91_PIN_PB0, 1);
284
285 platform_device_register(&ek_button_device);
286}
287#else
288static void __init ek_add_device_buttons(void) {}
289#endif
290
291
292static void __init ek_board_init(void)
293{
294 at91_register_devices();
295
296 /* Serial */
297 /* DBGU on ttyS0. (Rx & Tx only) */
298 at91_register_uart(0, 0, 0);
299
300 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
301 at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
302 at91_add_device_serial();
303 /* USB HS */
304 at91_add_device_usba(&ek_usba_udc_data);
305 /* I2C */
306 at91_add_device_i2c(NULL, 0);
307 /* NAND */
308 ek_add_device_nand();
309 /* SPI */
310 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
311 /* MMC */
312 at91_add_device_mci(0, &mci0_data);
313 /* LCD Controller */
314 at91_add_device_lcdc(&ek_lcdc_data);
315 /* AC97 */
316 at91_add_device_ac97(&ek_ac97_data);
317 /* Touch Screen Controller + ADC */
318 at91_add_device_adc(&ek_adc_data);
319 /* LEDs */
320 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
321 /* Push Buttons */
322 ek_add_device_buttons();
323}
324
325MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
326 /* Maintainer: Atmel */
327 .init_time = at91_init_time,
328 .map_io = at91_map_io,
329 .handle_irq = at91_aic_handle_irq,
330 .init_early = ek_init_early,
331 .init_irq = at91_init_irq_default,
332 .init_machine = ek_board_init,
333MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 81959cf4a137..464b08e9830a 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -24,14 +24,12 @@ extern void __init at91_init_sram(int bank, unsigned long base,
24 /* Processors */ 24 /* Processors */
25extern void __init at91rm9200_set_type(int type); 25extern void __init at91rm9200_set_type(int type);
26extern void __init at91_initialize(unsigned long main_clock); 26extern void __init at91_initialize(unsigned long main_clock);
27extern void __init at91x40_initialize(unsigned long main_clock);
28extern void __init at91rm9200_dt_initialize(void); 27extern void __init at91rm9200_dt_initialize(void);
29extern void __init at91_dt_initialize(void); 28extern void __init at91_dt_initialize(void);
30 29
31 /* Interrupts */ 30 /* Interrupts */
32extern void __init at91_init_irq_default(void); 31extern void __init at91_init_irq_default(void);
33extern void __init at91_init_interrupts(unsigned int priority[]); 32extern void __init at91_init_interrupts(unsigned int priority[]);
34extern void __init at91x40_init_interrupts(unsigned int priority[]);
35extern void __init at91_aic_init(unsigned int priority[], 33extern void __init at91_aic_init(unsigned int priority[],
36 unsigned int ext_irq_mask); 34 unsigned int ext_irq_mask);
37extern int __init at91_aic_of_init(struct device_node *node, 35extern int __init at91_aic_of_init(struct device_node *node,
@@ -50,7 +48,6 @@ extern void at91rm9200_ioremap_st(u32 addr);
50extern void at91rm9200_timer_init(void); 48extern void at91rm9200_timer_init(void);
51extern void at91sam926x_ioremap_pit(u32 addr); 49extern void at91sam926x_ioremap_pit(u32 addr);
52extern void at91sam926x_pit_init(int irq); 50extern void at91sam926x_pit_init(int irq);
53extern void at91x40_timer_init(void);
54 51
55 /* Clocks */ 52 /* Clocks */
56#ifdef CONFIG_OLD_CLK_AT91 53#ifdef CONFIG_OLD_CLK_AT91
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 3b5948566e52..42925e8f78e4 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -16,7 +16,6 @@
16#ifndef AT91_DBGU_H 16#ifndef AT91_DBGU_H
17#define AT91_DBGU_H 17#define AT91_DBGU_H
18 18
19#if !defined(CONFIG_ARCH_AT91X40)
20#define AT91_DBGU_CR (0x00) /* Control Register */ 19#define AT91_DBGU_CR (0x00) /* Control Register */
21#define AT91_DBGU_MR (0x04) /* Mode Register */ 20#define AT91_DBGU_MR (0x04) /* Mode Register */
22#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ 21#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
@@ -34,8 +33,6 @@
34#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ 33#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
35#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ 34#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
36 35
37#endif /* AT91_DBGU */
38
39/* 36/*
40 * Some AT91 parts that don't have full DEBUG units still support the ID 37 * Some AT91 parts that don't have full DEBUG units still support the ID
41 * and extensions register. 38 * and extensions register.
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
deleted file mode 100644
index 38dca2bb027f..000000000000
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91x40.h
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef AT91X40_H
13#define AT91X40_H
14
15/*
16 * IRQ list.
17 */
18#define AT91X40_ID_USART0 2 /* USART port 0 */
19#define AT91X40_ID_USART1 3 /* USART port 1 */
20#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */
21#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/
22#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/
23#define AT91X40_ID_WD 7 /* Watchdog? */
24#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */
25
26#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */
27#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */
28#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
29
30/*
31 * System Peripherals
32 */
33#define AT91_BASE_SYS 0xffc00000
34
35#define AT91_EBI 0xffe00000 /* External Bus Interface */
36#define AT91_SF 0xfff00000 /* Special Function */
37#define AT91_USART1 0xfffcc000 /* USART 1 */
38#define AT91_USART0 0xfffd0000 /* USART 0 */
39#define AT91_TC 0xfffe0000 /* Timer Counter */
40#define AT91_PIOA 0xffff0000 /* PIO Controller A */
41#define AT91_PS 0xffff4000 /* Power Save */
42#define AT91_WD 0xffff8000 /* Watchdog Timer */
43
44/*
45 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
46 * But it does have a chip identify register and extension ID, so define at
47 * least these here.
48 */
49#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
50#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
51
52/*
53 * Support defines for the simple Power Controller module.
54 */
55#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
56#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
57
58#define AT91X40_MASTER_CLOCK 40000000
59
60#endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index b27e9ca65653..61914fb35f5d 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -62,7 +62,6 @@
62#define ARCH_EXID_SAMA5D43 0x00000003 62#define ARCH_EXID_SAMA5D43 0x00000003
63#define ARCH_EXID_SAMA5D44 0x00000004 63#define ARCH_EXID_SAMA5D44 0x00000004
64 64
65#define ARCH_FAMILY_AT91X92 0x09200000
66#define ARCH_FAMILY_AT91SAM9 0x01900000 65#define ARCH_FAMILY_AT91SAM9 0x01900000
67#define ARCH_FAMILY_AT91SAM9XE 0x02900000 66#define ARCH_FAMILY_AT91SAM9XE 0x02900000
68 67
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index c13797352688..a57c1c52a574 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -24,9 +24,6 @@
24/* sama5d4 */ 24/* sama5d4 */
25#define AT91_BASE_DBGU2 0xfc069000 25#define AT91_BASE_DBGU2 0xfc069000
26 26
27#if defined(CONFIG_ARCH_AT91X40)
28#include <mach/at91x40.h>
29#else
30#include <mach/at91rm9200.h> 27#include <mach/at91rm9200.h>
31#include <mach/at91sam9260.h> 28#include <mach/at91sam9260.h>
32#include <mach/at91sam9261.h> 29#include <mach/at91sam9261.h>
@@ -51,8 +48,6 @@
51 */ 48 */
52#define AT91_BASE_SYS 0xffffc000 49#define AT91_BASE_SYS 0xffffc000
53 50
54#endif
55
56/* 51/*
57 * On sama5d4 there is no system controller, we map some needed peripherals 52 * On sama5d4 there is no system controller, we map some needed peripherals
58 */ 53 */
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index acb2d890ad7e..4ebb609369e3 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -31,7 +31,6 @@
31 31
32void __iomem *at91_uart; 32void __iomem *at91_uart;
33 33
34#if !defined(CONFIG_ARCH_AT91X40)
35static const u32 uarts_rm9200[] = { 34static const u32 uarts_rm9200[] = {
36 AT91_BASE_DBGU0, 35 AT91_BASE_DBGU0,
37 AT91RM9200_BASE_US0, 36 AT91RM9200_BASE_US0,
@@ -188,12 +187,6 @@ static inline void arch_decomp_setup(void)
188 187
189 at91_uart = NULL; 188 at91_uart = NULL;
190} 189}
191#else
192static inline void arch_decomp_setup(void)
193{
194 at91_uart = NULL;
195}
196#endif
197 190
198/* 191/*
199 * The following code assumes the serial port has already been 192 * The following code assumes the serial port has already been
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 961079250b83..a78fbb7b13c9 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -418,7 +418,7 @@ void __init at91_ioremap_matrix(u32 base_addr)
418 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n")); 418 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
419} 419}
420 420
421#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40) 421#if defined(CONFIG_OF)
422static struct of_device_id ramc_ids[] = { 422static struct of_device_id ramc_ids[] = {
423 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, 423 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
424 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, 424 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 77eb13cabe6d..eb4669cd9597 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1110,7 +1110,7 @@ config RTC_DRV_AT91RM9200
1110 1110
1111config RTC_DRV_AT91SAM9 1111config RTC_DRV_AT91SAM9
1112 tristate "AT91SAM9 RTT as RTC" 1112 tristate "AT91SAM9 RTT as RTC"
1113 depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40) 1113 depends on ARCH_AT91 && !ARCH_AT91RM9200
1114 select MFD_SYSCON 1114 select MFD_SYSCON
1115 help 1115 help
1116 Some AT91SAM9 SoCs provide an RTT (Real Time Timer) block which 1116 Some AT91SAM9 SoCs provide an RTT (Real Time Timer) block which
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-03 11:05:33 -0400