diff options
| -rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 25 |
1 files changed, 4 insertions, 21 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 9902904de2ce..4c822e19d960 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
| @@ -113,23 +113,6 @@ static u32 intel_infoframe_enable(struct dip_infoframe *frame) | |||
| 113 | return flags; | 113 | return flags; |
| 114 | } | 114 | } |
| 115 | 115 | ||
| 116 | static u32 intel_infoframe_frequency(struct dip_infoframe *frame) | ||
| 117 | { | ||
| 118 | u32 flags = 0; | ||
| 119 | |||
| 120 | switch (frame->type) { | ||
| 121 | case DIP_TYPE_AVI: | ||
| 122 | case DIP_TYPE_SPD: | ||
| 123 | flags |= VIDEO_DIP_FREQ_VSYNC; | ||
| 124 | break; | ||
| 125 | default: | ||
| 126 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | ||
| 127 | break; | ||
| 128 | } | ||
| 129 | |||
| 130 | return flags; | ||
| 131 | } | ||
| 132 | |||
| 133 | static void i9xx_write_infoframe(struct drm_encoder *encoder, | 116 | static void i9xx_write_infoframe(struct drm_encoder *encoder, |
| 134 | struct dip_infoframe *frame) | 117 | struct dip_infoframe *frame) |
| 135 | { | 118 | { |
| @@ -165,7 +148,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, | |||
| 165 | 148 | ||
| 166 | val |= intel_infoframe_enable(frame); | 149 | val |= intel_infoframe_enable(frame); |
| 167 | val &= ~VIDEO_DIP_FREQ_MASK; | 150 | val &= ~VIDEO_DIP_FREQ_MASK; |
| 168 | val |= intel_infoframe_frequency(frame); | 151 | val |= VIDEO_DIP_FREQ_VSYNC; |
| 169 | 152 | ||
| 170 | I915_WRITE(VIDEO_DIP_CTL, val); | 153 | I915_WRITE(VIDEO_DIP_CTL, val); |
| 171 | } | 154 | } |
| @@ -215,7 +198,7 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, | |||
| 215 | 198 | ||
| 216 | val |= intel_infoframe_enable(frame); | 199 | val |= intel_infoframe_enable(frame); |
| 217 | val &= ~VIDEO_DIP_FREQ_MASK; | 200 | val &= ~VIDEO_DIP_FREQ_MASK; |
| 218 | val |= intel_infoframe_frequency(frame); | 201 | val |= VIDEO_DIP_FREQ_VSYNC; |
| 219 | 202 | ||
| 220 | I915_WRITE(reg, val); | 203 | I915_WRITE(reg, val); |
| 221 | } | 204 | } |
| @@ -255,7 +238,7 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, | |||
| 255 | 238 | ||
| 256 | val |= intel_infoframe_enable(frame); | 239 | val |= intel_infoframe_enable(frame); |
| 257 | val &= ~VIDEO_DIP_FREQ_MASK; | 240 | val &= ~VIDEO_DIP_FREQ_MASK; |
| 258 | val |= intel_infoframe_frequency(frame); | 241 | val |= VIDEO_DIP_FREQ_VSYNC; |
| 259 | 242 | ||
| 260 | I915_WRITE(reg, val); | 243 | I915_WRITE(reg, val); |
| 261 | } | 244 | } |
| @@ -289,7 +272,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, | |||
| 289 | 272 | ||
| 290 | val |= intel_infoframe_enable(frame); | 273 | val |= intel_infoframe_enable(frame); |
| 291 | val &= ~VIDEO_DIP_FREQ_MASK; | 274 | val &= ~VIDEO_DIP_FREQ_MASK; |
| 292 | val |= intel_infoframe_frequency(frame); | 275 | val |= VIDEO_DIP_FREQ_VSYNC; |
| 293 | 276 | ||
| 294 | I915_WRITE(reg, val); | 277 | I915_WRITE(reg, val); |
| 295 | } | 278 | } |
