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-rw-r--r--drivers/staging/dwc2/hw.h19
1 files changed, 4 insertions, 15 deletions
diff --git a/drivers/staging/dwc2/hw.h b/drivers/staging/dwc2/hw.h
index cf0dc97d5520..0777d8a23e51 100644
--- a/drivers/staging/dwc2/hw.h
+++ b/drivers/staging/dwc2/hw.h
@@ -190,14 +190,7 @@
190#define GRXFSIZ HSOTG_REG(0x024) 190#define GRXFSIZ HSOTG_REG(0x024)
191 191
192#define GNPTXFSIZ HSOTG_REG(0x028) 192#define GNPTXFSIZ HSOTG_REG(0x028)
193#define GNPTXFSIZ_NP_TXF_DEP_MASK (0xffff << 16) 193/* Use FIFOSIZE_* constants to access this register */
194#define GNPTXFSIZ_NP_TXF_DEP_SHIFT 16
195#define GNPTXFSIZ_NP_TXF_DEP_LIMIT 0xffff
196#define GNPTXFSIZ_NP_TXF_DEP(_x) ((_x) << 16)
197#define GNPTXFSIZ_NP_TXF_ST_ADDR_MASK (0xffff << 0)
198#define GNPTXFSIZ_NP_TXF_ST_ADDR_SHIFT 0
199#define GNPTXFSIZ_NP_TXF_ST_ADDR_LIMIT 0xffff
200#define GNPTXFSIZ_NP_TXF_ST_ADDR(_x) ((_x) << 0)
201 194
202#define GNPTXSTS HSOTG_REG(0x02C) 195#define GNPTXSTS HSOTG_REG(0x02C)
203#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24) 196#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
@@ -395,16 +388,12 @@
395#define ADPCTL_PRB_DSCHRG_SHIFT 0 388#define ADPCTL_PRB_DSCHRG_SHIFT 0
396 389
397#define HPTXFSIZ HSOTG_REG(0x100) 390#define HPTXFSIZ HSOTG_REG(0x100)
391/* Use FIFOSIZE_* constants to access this register */
398 392
399#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) 393#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
400#define DPTXFSIZN_DP_TXF_SIZE_MASK (0xffff << 16) 394/* Use FIFOSIZE_* constants to access this register */
401#define DPTXFSIZN_DP_TXF_SIZE_SHIFT 16
402#define DPTXFSIZN_DP_TXF_SIZE_GET(_v) (((_v) >> 16) & 0xffff)
403#define DPTXFSIZN_DP_TXF_SIZE_LIMIT 0xffff
404#define DPTXFSIZN_DP_TXF_SIZE(_x) ((_x) << 16)
405#define DPTXFSIZN_DP_TXF_ST_ADDR_MASK (0xffff << 0)
406#define DPTXFSIZN_DP_TXF_ST_ADDR_SHIFT 0
407 395
396/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
408#define FIFOSIZE_DEPTH_MASK (0xffff << 16) 397#define FIFOSIZE_DEPTH_MASK (0xffff << 16)
409#define FIFOSIZE_DEPTH_SHIFT 16 398#define FIFOSIZE_DEPTH_SHIFT 16
410#define FIFOSIZE_STARTADDR_MASK (0xffff << 0) 399#define FIFOSIZE_STARTADDR_MASK (0xffff << 0)