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-rw-r--r--sound/pci/hda/patch_ca0132.c51
1 files changed, 43 insertions, 8 deletions
diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c
index da655359da02..846826d2b738 100644
--- a/sound/pci/hda/patch_ca0132.c
+++ b/sound/pci/hda/patch_ca0132.c
@@ -27,6 +27,7 @@
27#include <linux/pci.h> 27#include <linux/pci.h>
28#include <linux/mutex.h> 28#include <linux/mutex.h>
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/firmware.h>
30#include <sound/core.h> 31#include <sound/core.h>
31#include "hda_codec.h" 32#include "hda_codec.h"
32#include "hda_local.h" 33#include "hda_local.h"
@@ -34,12 +35,33 @@
34 35
35#include "ca0132_regs.h" 36#include "ca0132_regs.h"
36 37
38#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
39#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
40
41#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
42#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
43#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
44
45#define MASTERCONTROL 0x80
46#define MASTERCONTROL_ALLOC_DMA_CHAN 9
47
37#define WIDGET_CHIP_CTRL 0x15 48#define WIDGET_CHIP_CTRL 0x15
38#define WIDGET_DSP_CTRL 0x16 49#define WIDGET_DSP_CTRL 0x16
39 50
40#define WUH_MEM_CONNID 10 51#define WUH_MEM_CONNID 10
41#define DSP_MEM_CONNID 16 52#define DSP_MEM_CONNID 16
42 53
54#define MEM_CONNID_MICIN1 3
55#define MEM_CONNID_MICIN2 5
56#define MEM_CONNID_MICOUT1 12
57#define MEM_CONNID_MICOUT2 14
58#define MEM_CONNID_WUH 10
59#define MEM_CONNID_DSP 16
60#define MEM_CONNID_DMIC 100
61
62#define SCP_SET 0
63#define SCP_GET 1
64
43enum hda_cmd_vendor_io { 65enum hda_cmd_vendor_io {
44 /* for DspIO node */ 66 /* for DspIO node */
45 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 67 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
@@ -64,7 +86,11 @@ enum hda_cmd_vendor_io {
64 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 86 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
65 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 87 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
66 88
89 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
90 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
91
67 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 92 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
93 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
68 94
69 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 95 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
70 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 96 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
@@ -72,18 +98,27 @@ enum hda_cmd_vendor_io {
72 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 98 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
73 VENDOR_CHIPIO_FLAG_SET = 0x70F, 99 VENDOR_CHIPIO_FLAG_SET = 0x70F,
74 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 100 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
75 VENDOR_CHIPIO_PARAMETER_SET = 0x710, 101 VENDOR_CHIPIO_PARAM_SET = 0x710,
76 VENDOR_CHIPIO_PARAMETER_GET = 0xF10, 102 VENDOR_CHIPIO_PARAM_GET = 0xF10,
77 103
78 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 104 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
79 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 105 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
80 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 106 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
81 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 107 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
82 108
83 VENDOR_CHIPIO_PARAMETER_EX_ID_GET = 0xF17, 109 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
84 VENDOR_CHIPIO_PARAMETER_EX_ID_SET = 0x717, 110 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
85 VENDOR_CHIPIO_PARAMETER_EX_VALUE_GET = 0xF18, 111 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
86 VENDOR_CHIPIO_PARAMETER_EX_VALUE_SET = 0x718 112 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
113
114 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
115 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
116 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
117 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
118 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
119 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
120
121 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
87}; 122};
88 123
89/* 124/*
@@ -133,7 +168,7 @@ enum control_flag_id {
133 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 168 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
134 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 169 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
135 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 170 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
136 CONTROL_FLAG_PORT_D_10K0HM_LOAD = 21, 171 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
137 /* ASI rate is 48kHz/96kHz */ 172 /* ASI rate is 48kHz/96kHz */
138 CONTROL_FLAG_ASI_96KHZ = 22, 173 CONTROL_FLAG_ASI_96KHZ = 22,
139 /* DAC power settings able to control attached ports no/yes */ 174 /* DAC power settings able to control attached ports no/yes */
@@ -147,7 +182,7 @@ enum control_flag_id {
147/* 182/*
148 * Control parameter IDs 183 * Control parameter IDs
149 */ 184 */
150enum control_parameter_id { 185enum control_param_id {
151 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 186 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
152 CONTROL_PARAM_SPDIF1_SOURCE = 2, 187 CONTROL_PARAM_SPDIF1_SOURCE = 2,
153 188