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-rw-r--r--drivers/mmc/host/Kconfig6
-rw-r--r--drivers/mmc/host/Makefile1
-rw-r--r--drivers/mmc/host/tmio_mmc.c691
-rw-r--r--drivers/mmc/host/tmio_mmc.h194
4 files changed, 892 insertions, 0 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index dc6f2579f85c..6fef078a2049 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -174,3 +174,9 @@ config MMC_SDRICOH_CS
174 To compile this driver as a module, choose M here: the 174 To compile this driver as a module, choose M here: the
175 module will be called sdricoh_cs. 175 module will be called sdricoh_cs.
176 176
177config MMC_TMIO
178 tristate "Toshiba Mobile IO Controller (TMIO) MMC/SD function support"
179 depends on MFD_CORE
180 help
181 This provides support for the SD/MMC cell found in TC6393XB,
182 T7L66XB and also ipaq ASIC3
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index db52eebfb50e..c794cc5ce442 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -21,4 +21,5 @@ obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
21obj-$(CONFIG_MMC_SPI) += mmc_spi.o 21obj-$(CONFIG_MMC_SPI) += mmc_spi.o
22obj-$(CONFIG_MMC_S3C) += s3cmci.o 22obj-$(CONFIG_MMC_S3C) += s3cmci.o
23obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o 23obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o
24obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o
24 25
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
new file mode 100644
index 000000000000..95430b81ec11
--- /dev/null
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -0,0 +1,691 @@
1/*
2 * linux/drivers/mmc/tmio_mmc.c
3 *
4 * Copyright (C) 2004 Ian Molton
5 * Copyright (C) 2007 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Driver for the MMC / SD / SDIO cell found in:
12 *
13 * TC6393XB TC6391XB TC6387XB T7L66XB
14 *
15 * This driver draws mainly on scattered spec sheets, Reverse engineering
16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
17 * support). (Further 4 bit support from a later datasheet).
18 *
19 * TODO:
20 * Investigate using a workqueue for PIO transfers
21 * Eliminate FIXMEs
22 * SDIO support
23 * Better Power management
24 * Handle MMC errors better
25 * double buffer support
26 *
27 */
28#include <linux/module.h>
29#include <linux/irq.h>
30#include <linux/device.h>
31#include <linux/delay.h>
32#include <linux/mmc/host.h>
33#include <linux/mfd/core.h>
34#include <linux/mfd/tmio.h>
35
36#include "tmio_mmc.h"
37
38/*
39 * Fixme - documentation conflicts on what the clock values are for the
40 * various dividers.
41 * One document I have says that its a divisor of a 24MHz clock, another 33.
42 * This probably depends on HCLK for a given platform, so we may need to
43 * require HCLK be passed to us from the MFD core.
44 *
45 */
46
47static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
48{
49 void __iomem *cnf = host->cnf;
50 void __iomem *ctl = host->ctl;
51 u32 clk = 0, clock;
52
53 if (new_clock) {
54 for (clock = 46875, clk = 0x100; new_clock >= (clock<<1); ) {
55 clock <<= 1;
56 clk >>= 1;
57 }
58 if (clk & 0x1)
59 clk = 0x20000;
60
61 clk >>= 2;
62 tmio_iowrite8((clk & 0x8000) ? 0 : 1, cnf + CNF_SD_CLK_MODE);
63 clk |= 0x100;
64 }
65
66 tmio_iowrite16(clk, ctl + CTL_SD_CARD_CLK_CTL);
67}
68
69static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
70{
71 void __iomem *ctl = host->ctl;
72
73 tmio_iowrite16(0x0000, ctl + CTL_CLK_AND_WAIT_CTL);
74 msleep(10);
75 tmio_iowrite16(tmio_ioread16(ctl + CTL_SD_CARD_CLK_CTL) & ~0x0100,
76 ctl + CTL_SD_CARD_CLK_CTL);
77 msleep(10);
78}
79
80static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
81{
82 void __iomem *ctl = host->ctl;
83
84 tmio_iowrite16(tmio_ioread16(ctl + CTL_SD_CARD_CLK_CTL) | 0x0100,
85 ctl + CTL_SD_CARD_CLK_CTL);
86 msleep(10);
87 tmio_iowrite16(0x0100, ctl + CTL_CLK_AND_WAIT_CTL);
88 msleep(10);
89}
90
91static void reset(struct tmio_mmc_host *host)
92{
93 void __iomem *ctl = host->ctl;
94
95 /* FIXME - should we set stop clock reg here */
96 tmio_iowrite16(0x0000, ctl + CTL_RESET_SD);
97 tmio_iowrite16(0x0000, ctl + CTL_RESET_SDIO);
98 msleep(10);
99 tmio_iowrite16(0x0001, ctl + CTL_RESET_SD);
100 tmio_iowrite16(0x0001, ctl + CTL_RESET_SDIO);
101 msleep(10);
102}
103
104static void
105tmio_mmc_finish_request(struct tmio_mmc_host *host)
106{
107 struct mmc_request *mrq = host->mrq;
108
109 host->mrq = NULL;
110 host->cmd = NULL;
111 host->data = NULL;
112
113 mmc_request_done(host->mmc, mrq);
114}
115
116/* These are the bitmasks the tmio chip requires to implement the MMC response
117 * types. Note that R1 and R6 are the same in this scheme. */
118#define APP_CMD 0x0040
119#define RESP_NONE 0x0300
120#define RESP_R1 0x0400
121#define RESP_R1B 0x0500
122#define RESP_R2 0x0600
123#define RESP_R3 0x0700
124#define DATA_PRESENT 0x0800
125#define TRANSFER_READ 0x1000
126#define TRANSFER_MULTI 0x2000
127#define SECURITY_CMD 0x4000
128
129static int
130tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
131{
132 void __iomem *ctl = host->ctl;
133 struct mmc_data *data = host->data;
134 int c = cmd->opcode;
135
136 /* Command 12 is handled by hardware */
137 if (cmd->opcode == 12 && !cmd->arg) {
138 tmio_iowrite16(0x001, ctl + CTL_STOP_INTERNAL_ACTION);
139 return 0;
140 }
141
142 switch (mmc_resp_type(cmd)) {
143 case MMC_RSP_NONE: c |= RESP_NONE; break;
144 case MMC_RSP_R1: c |= RESP_R1; break;
145 case MMC_RSP_R1B: c |= RESP_R1B; break;
146 case MMC_RSP_R2: c |= RESP_R2; break;
147 case MMC_RSP_R3: c |= RESP_R3; break;
148 default:
149 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
150 return -EINVAL;
151 }
152
153 host->cmd = cmd;
154
155/* FIXME - this seems to be ok comented out but the spec suggest this bit should
156 * be set when issuing app commands.
157 * if(cmd->flags & MMC_FLAG_ACMD)
158 * c |= APP_CMD;
159 */
160 if (data) {
161 c |= DATA_PRESENT;
162 if (data->blocks > 1) {
163 tmio_iowrite16(0x100, ctl + CTL_STOP_INTERNAL_ACTION);
164 c |= TRANSFER_MULTI;
165 }
166 if (data->flags & MMC_DATA_READ)
167 c |= TRANSFER_READ;
168 }
169
170 enable_mmc_irqs(ctl, TMIO_MASK_CMD);
171
172 /* Fire off the command */
173 tmio_iowrite32(cmd->arg, ctl + CTL_ARG_REG);
174 tmio_iowrite16(c, ctl + CTL_SD_CMD);
175
176 return 0;
177}
178
179/* This chip always returns (at least?) as much data as you ask for.
180 * I'm unsure what happens if you ask for less than a block. This should be
181 * looked into to ensure that a funny length read doesnt hose the controller.
182 *
183 */
184static inline void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
185{
186 void __iomem *ctl = host->ctl;
187 struct mmc_data *data = host->data;
188 unsigned short *buf;
189 unsigned int count;
190 unsigned long flags;
191
192 if (!data) {
193 pr_debug("Spurious PIO IRQ\n");
194 return;
195 }
196
197 buf = (unsigned short *)(tmio_mmc_kmap_atomic(host, &flags) +
198 host->sg_off);
199
200 count = host->sg_ptr->length - host->sg_off;
201 if (count > data->blksz)
202 count = data->blksz;
203
204 pr_debug("count: %08x offset: %08x flags %08x\n",
205 count, host->sg_off, data->flags);
206
207 /* Transfer the data */
208 if (data->flags & MMC_DATA_READ)
209 tmio_ioread16_rep(ctl + CTL_SD_DATA_PORT, buf, count >> 1);
210 else
211 tmio_iowrite16_rep(ctl + CTL_SD_DATA_PORT, buf, count >> 1);
212
213 host->sg_off += count;
214
215 tmio_mmc_kunmap_atomic(host, &flags);
216
217 if (host->sg_off == host->sg_ptr->length)
218 tmio_mmc_next_sg(host);
219
220 return;
221}
222
223static inline void tmio_mmc_data_irq(struct tmio_mmc_host *host)
224{
225 void __iomem *ctl = host->ctl;
226 struct mmc_data *data = host->data;
227 struct mmc_command *stop = data->stop;
228
229 host->data = NULL;
230
231 if (!data) {
232 pr_debug("Spurious data end IRQ\n");
233 return;
234 }
235
236 /* FIXME - return correct transfer count on errors */
237 if (!data->error)
238 data->bytes_xfered = data->blocks * data->blksz;
239 else
240 data->bytes_xfered = 0;
241
242 pr_debug("Completed data request\n");
243
244 /*FIXME - other drivers allow an optional stop command of any given type
245 * which we dont do, as the chip can auto generate them.
246 * Perhaps we can be smarter about when to use auto CMD12 and
247 * only issue the auto request when we know this is the desired
248 * stop command, allowing fallback to the stop command the
249 * upper layers expect. For now, we do what works.
250 */
251
252 if (data->flags & MMC_DATA_READ)
253 disable_mmc_irqs(ctl, TMIO_MASK_READOP);
254 else
255 disable_mmc_irqs(ctl, TMIO_MASK_WRITEOP);
256
257 if (stop) {
258 if (stop->opcode == 12 && !stop->arg)
259 tmio_iowrite16(0x000, ctl + CTL_STOP_INTERNAL_ACTION);
260 else
261 BUG();
262 }
263
264 tmio_mmc_finish_request(host);
265}
266
267static inline void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
268 unsigned int stat)
269{
270 void __iomem *ctl = host->ctl, *addr;
271 struct mmc_command *cmd = host->cmd;
272 int i;
273
274 if (!host->cmd) {
275 pr_debug("Spurious CMD irq\n");
276 return;
277 }
278
279 host->cmd = NULL;
280
281 /* This controller is sicker than the PXA one. Not only do we need to
282 * drop the top 8 bits of the first response word, we also need to
283 * modify the order of the response for short response command types.
284 */
285
286 for (i = 3, addr = ctl + CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
287 cmd->resp[i] = tmio_ioread32(addr);
288
289 if (cmd->flags & MMC_RSP_136) {
290 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
291 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
292 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
293 cmd->resp[3] <<= 8;
294 } else if (cmd->flags & MMC_RSP_R3) {
295 cmd->resp[0] = cmd->resp[3];
296 }
297
298 if (stat & TMIO_STAT_CMDTIMEOUT)
299 cmd->error = -ETIMEDOUT;
300 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
301 cmd->error = -EILSEQ;
302
303 /* If there is data to handle we enable data IRQs here, and
304 * we will ultimatley finish the request in the data_end handler.
305 * If theres no data or we encountered an error, finish now.
306 */
307 if (host->data && !cmd->error) {
308 if (host->data->flags & MMC_DATA_READ)
309 enable_mmc_irqs(ctl, TMIO_MASK_READOP);
310 else
311 enable_mmc_irqs(ctl, TMIO_MASK_WRITEOP);
312 } else {
313 tmio_mmc_finish_request(host);
314 }
315
316 return;
317}
318
319
320static irqreturn_t tmio_mmc_irq(int irq, void *devid)
321{
322 struct tmio_mmc_host *host = devid;
323 void __iomem *ctl = host->ctl;
324 unsigned int ireg, irq_mask, status;
325
326 pr_debug("MMC IRQ begin\n");
327
328 status = tmio_ioread32(ctl + CTL_STATUS);
329 irq_mask = tmio_ioread32(ctl + CTL_IRQ_MASK);
330 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
331
332 pr_debug_status(status);
333 pr_debug_status(ireg);
334
335 if (!ireg) {
336 disable_mmc_irqs(ctl, status & ~irq_mask);
337
338 pr_debug("tmio_mmc: Spurious irq, disabling! "
339 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
340 pr_debug_status(status);
341
342 goto out;
343 }
344
345 while (ireg) {
346 /* Card insert / remove attempts */
347 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
348 ack_mmc_irqs(ctl, TMIO_STAT_CARD_INSERT |
349 TMIO_STAT_CARD_REMOVE);
350 mmc_detect_change(host->mmc, 0);
351 }
352
353 /* CRC and other errors */
354/* if (ireg & TMIO_STAT_ERR_IRQ)
355 * handled |= tmio_error_irq(host, irq, stat);
356 */
357
358 /* Command completion */
359 if (ireg & TMIO_MASK_CMD) {
360 ack_mmc_irqs(ctl, TMIO_MASK_CMD);
361 tmio_mmc_cmd_irq(host, status);
362 }
363
364 /* Data transfer */
365 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
366 ack_mmc_irqs(ctl, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
367 tmio_mmc_pio_irq(host);
368 }
369
370 /* Data transfer completion */
371 if (ireg & TMIO_STAT_DATAEND) {
372 ack_mmc_irqs(ctl, TMIO_STAT_DATAEND);
373 tmio_mmc_data_irq(host);
374 }
375
376 /* Check status - keep going until we've handled it all */
377 status = tmio_ioread32(ctl + CTL_STATUS);
378 irq_mask = tmio_ioread32(ctl + CTL_IRQ_MASK);
379 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
380
381 pr_debug("Status at end of loop: %08x\n", status);
382 pr_debug_status(status);
383 }
384 pr_debug("MMC IRQ end\n");
385
386out:
387 return IRQ_HANDLED;
388}
389
390static int tmio_mmc_start_data(struct tmio_mmc_host *host,
391 struct mmc_data *data)
392{
393 void __iomem *ctl = host->ctl;
394
395 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
396 data->blksz, data->blocks);
397
398 /* Hardware cannot perform 1 and 2 byte requests in 4 bit mode */
399 if (data->blksz < 4 && host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
400 printk(KERN_ERR "%s: %d byte block unsupported in 4 bit mode\n",
401 mmc_hostname(host->mmc), data->blksz);
402 return -EINVAL;
403 }
404
405 tmio_mmc_init_sg(host, data);
406 host->data = data;
407
408 /* Set transfer length / blocksize */
409 tmio_iowrite16(data->blksz, ctl + CTL_SD_XFER_LEN);
410 tmio_iowrite16(data->blocks, ctl + CTL_XFER_BLK_COUNT);
411
412 return 0;
413}
414
415/* Process requests from the MMC layer */
416static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
417{
418 struct tmio_mmc_host *host = mmc_priv(mmc);
419 int ret;
420
421 if (host->mrq)
422 pr_debug("request not null\n");
423
424 host->mrq = mrq;
425
426 if (mrq->data) {
427 ret = tmio_mmc_start_data(host, mrq->data);
428 if (ret)
429 goto fail;
430 }
431
432 ret = tmio_mmc_start_command(host, mrq->cmd);
433
434 if (!ret)
435 return;
436
437fail:
438 mrq->cmd->error = ret;
439 mmc_request_done(mmc, mrq);
440}
441
442/* Set MMC clock / power.
443 * Note: This controller uses a simple divider scheme therefore it cannot
444 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
445 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
446 * slowest setting.
447 */
448static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
449{
450 struct tmio_mmc_host *host = mmc_priv(mmc);
451 void __iomem *cnf = host->cnf;
452 void __iomem *ctl = host->ctl;
453
454 if (ios->clock)
455 tmio_mmc_set_clock(host, ios->clock);
456
457 /* Power sequence - OFF -> ON -> UP */
458 switch (ios->power_mode) {
459 case MMC_POWER_OFF: /* power down SD bus */
460 tmio_iowrite8(0x00, cnf + CNF_PWR_CTL_2);
461 tmio_mmc_clk_stop(host);
462 break;
463 case MMC_POWER_ON: /* power up SD bus */
464
465 tmio_iowrite8(0x02, cnf + CNF_PWR_CTL_2);
466 break;
467 case MMC_POWER_UP: /* start bus clock */
468 tmio_mmc_clk_start(host);
469 break;
470 }
471
472 switch (ios->bus_width) {
473 case MMC_BUS_WIDTH_1:
474 tmio_iowrite16(0x80e0, ctl + CTL_SD_MEM_CARD_OPT);
475 break;
476 case MMC_BUS_WIDTH_4:
477 tmio_iowrite16(0x00e0, ctl + CTL_SD_MEM_CARD_OPT);
478 break;
479 }
480
481 /* Let things settle. delay taken from winCE driver */
482 udelay(140);
483}
484
485static int tmio_mmc_get_ro(struct mmc_host *mmc)
486{
487 struct tmio_mmc_host *host = mmc_priv(mmc);
488 void __iomem *ctl = host->ctl;
489
490 return (tmio_ioread16(ctl + CTL_STATUS) & TMIO_STAT_WRPROTECT) ? 0 : 1;
491}
492
493static struct mmc_host_ops tmio_mmc_ops = {
494 .request = tmio_mmc_request,
495 .set_ios = tmio_mmc_set_ios,
496 .get_ro = tmio_mmc_get_ro,
497};
498
499#ifdef CONFIG_PM
500static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state)
501{
502 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
503 struct mmc_host *mmc = platform_get_drvdata(dev);
504 int ret;
505
506 ret = mmc_suspend_host(mmc, state);
507
508 /* Tell MFD core it can disable us now.*/
509 if (!ret && cell->disable)
510 cell->disable(dev);
511
512 return ret;
513}
514
515static int tmio_mmc_resume(struct platform_device *dev)
516{
517 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
518 struct mmc_host *mmc = platform_get_drvdata(dev);
519 struct tmio_mmc_host *host = mmc_priv(mmc);
520 void __iomem *cnf = host->cnf;
521 int ret = 0;
522
523 /* Enable the MMC/SD Control registers */
524 tmio_iowrite16(SDCREN, cnf + CNF_CMD);
525 tmio_iowrite32(dev->resource[0].start & 0xfffe, cnf + CNF_CTL_BASE);
526
527 /* Tell the MFD core we are ready to be enabled */
528 if (cell->enable) {
529 ret = cell->enable(dev);
530 if (ret)
531 goto out;
532 }
533
534 mmc_resume_host(mmc);
535
536out:
537 return ret;
538}
539#else
540#define tmio_mmc_suspend NULL
541#define tmio_mmc_resume NULL
542#endif
543
544static int __devinit tmio_mmc_probe(struct platform_device *dev)
545{
546 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
547 struct resource *res_ctl, *res_cnf;
548 struct tmio_mmc_host *host;
549 struct mmc_host *mmc;
550 int ret = -ENOMEM;
551
552 if (dev->num_resources != 3)
553 goto out;
554
555 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
556 res_cnf = platform_get_resource(dev, IORESOURCE_MEM, 1);
557 if (!res_ctl || !res_cnf) {
558 ret = -EINVAL;
559 goto out;
560 }
561
562 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
563 if (!mmc)
564 goto out;
565
566 host = mmc_priv(mmc);
567 host->mmc = mmc;
568 platform_set_drvdata(dev, mmc);
569
570 host->ctl = ioremap(res_ctl->start, res_ctl->end - res_ctl->start);
571 if (!host->ctl)
572 goto host_free;
573
574 host->cnf = ioremap(res_cnf->start, res_cnf->end - res_cnf->start);
575 if (!host->cnf)
576 goto unmap_ctl;
577
578 mmc->ops = &tmio_mmc_ops;
579 mmc->caps = MMC_CAP_4_BIT_DATA;
580 mmc->f_min = 46875; /* 24000000 / 512 */
581 mmc->f_max = 24000000;
582 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
583
584 /* Enable the MMC/SD Control registers */
585 tmio_iowrite16(SDCREN, host->cnf + CNF_CMD);
586 tmio_iowrite32(dev->resource[0].start & 0xfffe,
587 host->cnf + CNF_CTL_BASE);
588
589 /* Tell the MFD core we are ready to be enabled */
590 if (cell->enable) {
591 ret = cell->enable(dev);
592 if (ret)
593 goto unmap_cnf;
594 }
595
596 /* Disable SD power during suspend */
597 tmio_iowrite8(0x01, host->cnf + CNF_PWR_CTL_3);
598
599 /* The below is required but why? FIXME */
600 tmio_iowrite8(0x1f, host->cnf + CNF_STOP_CLK_CTL);
601
602 /* Power down SD bus*/
603 tmio_iowrite8(0x0, host->cnf + CNF_PWR_CTL_2);
604
605 tmio_mmc_clk_stop(host);
606 reset(host);
607
608 ret = platform_get_irq(dev, 0);
609 if (ret >= 0)
610 host->irq = ret;
611 else
612 goto unmap_cnf;
613
614 disable_mmc_irqs(host->ctl, TMIO_MASK_ALL);
615
616 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED, "tmio-mmc",
617 host);
618 if (ret)
619 goto unmap_cnf;
620
621 set_irq_type(host->irq, IRQ_TYPE_EDGE_FALLING);
622
623 mmc_add_host(mmc);
624
625 printk(KERN_INFO "%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
626 (unsigned long)host->ctl, host->irq);
627
628 /* Unmask the IRQs we want to know about */
629 enable_mmc_irqs(host->ctl, TMIO_MASK_IRQ);
630
631 return 0;
632
633unmap_cnf:
634 iounmap(host->cnf);
635unmap_ctl:
636 iounmap(host->ctl);
637host_free:
638 mmc_free_host(mmc);
639out:
640 return ret;
641}
642
643static int __devexit tmio_mmc_remove(struct platform_device *dev)
644{
645 struct mmc_host *mmc = platform_get_drvdata(dev);
646
647 platform_set_drvdata(dev, NULL);
648
649 if (mmc) {
650 struct tmio_mmc_host *host = mmc_priv(mmc);
651 mmc_remove_host(mmc);
652 mmc_free_host(mmc);
653 free_irq(host->irq, host);
654 iounmap(host->ctl);
655 iounmap(host->cnf);
656 }
657
658 return 0;
659}
660
661/* ------------------- device registration ----------------------- */
662
663static struct platform_driver tmio_mmc_driver = {
664 .driver = {
665 .name = "tmio-mmc",
666 .owner = THIS_MODULE,
667 },
668 .probe = tmio_mmc_probe,
669 .remove = __devexit_p(tmio_mmc_remove),
670 .suspend = tmio_mmc_suspend,
671 .resume = tmio_mmc_resume,
672};
673
674
675static int __init tmio_mmc_init(void)
676{
677 return platform_driver_register(&tmio_mmc_driver);
678}
679
680static void __exit tmio_mmc_exit(void)
681{
682 platform_driver_unregister(&tmio_mmc_driver);
683}
684
685module_init(tmio_mmc_init);
686module_exit(tmio_mmc_exit);
687
688MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver");
689MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
690MODULE_LICENSE("GPL v2");
691MODULE_ALIAS("platform:tmio-mmc");
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
new file mode 100644
index 000000000000..9e647a06054f
--- /dev/null
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -0,0 +1,194 @@
1/* Definitons for use with the tmio_mmc.c
2 *
3 * (c) 2004 Ian Molton <spyro@f2s.com>
4 * (c) 2007 Ian Molton <spyro@f2s.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#define CNF_CMD 0x04
12#define CNF_CTL_BASE 0x10
13#define CNF_INT_PIN 0x3d
14#define CNF_STOP_CLK_CTL 0x40
15#define CNF_GCLK_CTL 0x41
16#define CNF_SD_CLK_MODE 0x42
17#define CNF_PIN_STATUS 0x44
18#define CNF_PWR_CTL_1 0x48
19#define CNF_PWR_CTL_2 0x49
20#define CNF_PWR_CTL_3 0x4a
21#define CNF_CARD_DETECT_MODE 0x4c
22#define CNF_SD_SLOT 0x50
23#define CNF_EXT_GCLK_CTL_1 0xf0
24#define CNF_EXT_GCLK_CTL_2 0xf1
25#define CNF_EXT_GCLK_CTL_3 0xf9
26#define CNF_SD_LED_EN_1 0xfa
27#define CNF_SD_LED_EN_2 0xfe
28
29#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
30
31#define CTL_SD_CMD 0x00
32#define CTL_ARG_REG 0x04
33#define CTL_STOP_INTERNAL_ACTION 0x08
34#define CTL_XFER_BLK_COUNT 0xa
35#define CTL_RESPONSE 0x0c
36#define CTL_STATUS 0x1c
37#define CTL_IRQ_MASK 0x20
38#define CTL_SD_CARD_CLK_CTL 0x24
39#define CTL_SD_XFER_LEN 0x26
40#define CTL_SD_MEM_CARD_OPT 0x28
41#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
42#define CTL_SD_DATA_PORT 0x30
43#define CTL_TRANSACTION_CTL 0x34
44#define CTL_RESET_SD 0xe0
45#define CTL_SDIO_REGS 0x100
46#define CTL_CLK_AND_WAIT_CTL 0x138
47#define CTL_RESET_SDIO 0x1e0
48
49/* Definitions for values the CTRL_STATUS register can take. */
50#define TMIO_STAT_CMDRESPEND 0x00000001
51#define TMIO_STAT_DATAEND 0x00000004
52#define TMIO_STAT_CARD_REMOVE 0x00000008
53#define TMIO_STAT_CARD_INSERT 0x00000010
54#define TMIO_STAT_SIGSTATE 0x00000020
55#define TMIO_STAT_WRPROTECT 0x00000080
56#define TMIO_STAT_CARD_REMOVE_A 0x00000100
57#define TMIO_STAT_CARD_INSERT_A 0x00000200
58#define TMIO_STAT_SIGSTATE_A 0x00000400
59#define TMIO_STAT_CMD_IDX_ERR 0x00010000
60#define TMIO_STAT_CRCFAIL 0x00020000
61#define TMIO_STAT_STOPBIT_ERR 0x00040000
62#define TMIO_STAT_DATATIMEOUT 0x00080000
63#define TMIO_STAT_RXOVERFLOW 0x00100000
64#define TMIO_STAT_TXUNDERRUN 0x00200000
65#define TMIO_STAT_CMDTIMEOUT 0x00400000
66#define TMIO_STAT_RXRDY 0x01000000
67#define TMIO_STAT_TXRQ 0x02000000
68#define TMIO_STAT_ILL_FUNC 0x20000000
69#define TMIO_STAT_CMD_BUSY 0x40000000
70#define TMIO_STAT_ILL_ACCESS 0x80000000
71
72/* Define some IRQ masks */
73/* This is the mask used at reset by the chip */
74#define TMIO_MASK_ALL 0x837f031d
75#define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND | \
76 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
77#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND | \
78 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
79#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
80 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
81#define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
82
83#define enable_mmc_irqs(ctl, i) \
84 do { \
85 u32 mask;\
86 mask = tmio_ioread32((ctl) + CTL_IRQ_MASK); \
87 mask &= ~((i) & TMIO_MASK_IRQ); \
88 tmio_iowrite32(mask, (ctl) + CTL_IRQ_MASK); \
89 } while (0)
90
91#define disable_mmc_irqs(ctl, i) \
92 do { \
93 u32 mask;\
94 mask = tmio_ioread32((ctl) + CTL_IRQ_MASK); \
95 mask |= ((i) & TMIO_MASK_IRQ); \
96 tmio_iowrite32(mask, (ctl) + CTL_IRQ_MASK); \
97 } while (0)
98
99#define ack_mmc_irqs(ctl, i) \
100 do { \
101 u32 mask;\
102 mask = tmio_ioread32((ctl) + CTL_STATUS); \
103 mask &= ~((i) & TMIO_MASK_IRQ); \
104 tmio_iowrite32(mask, (ctl) + CTL_STATUS); \
105 } while (0)
106
107
108struct tmio_mmc_host {
109 void __iomem *cnf;
110 void __iomem *ctl;
111 struct mmc_command *cmd;
112 struct mmc_request *mrq;
113 struct mmc_data *data;
114 struct mmc_host *mmc;
115 int irq;
116
117 /* pio related stuff */
118 struct scatterlist *sg_ptr;
119 unsigned int sg_len;
120 unsigned int sg_off;
121};
122
123#include <linux/scatterlist.h>
124#include <linux/blkdev.h>
125
126static inline void tmio_mmc_init_sg(struct tmio_mmc_host *host,
127 struct mmc_data *data)
128{
129 host->sg_len = data->sg_len;
130 host->sg_ptr = data->sg;
131 host->sg_off = 0;
132}
133
134static inline int tmio_mmc_next_sg(struct tmio_mmc_host *host)
135{
136 host->sg_ptr = sg_next(host->sg_ptr);
137 host->sg_off = 0;
138 return --host->sg_len;
139}
140
141static inline char *tmio_mmc_kmap_atomic(struct tmio_mmc_host *host,
142 unsigned long *flags)
143{
144 struct scatterlist *sg = host->sg_ptr;
145
146 local_irq_save(*flags);
147 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
148}
149
150static inline void tmio_mmc_kunmap_atomic(struct tmio_mmc_host *host,
151 unsigned long *flags)
152{
153 kunmap_atomic(sg_page(host->sg_ptr), KM_BIO_SRC_IRQ);
154 local_irq_restore(*flags);
155}
156
157#ifdef CONFIG_MMC_DEBUG
158
159#define STATUS_TO_TEXT(a) \
160 do { \
161 if (status & TMIO_STAT_##a) \
162 printf(#a); \
163 } while (0)
164
165void debug_status(u32 status)
166{
167 printk(KERN_DEBUG "status: %08x = ", status);
168 STATUS_TO_TEXT(CARD_REMOVE);
169 STATUS_TO_TEXT(CARD_INSERT);
170 STATUS_TO_TEXT(SIGSTATE);
171 STATUS_TO_TEXT(WRPROTECT);
172 STATUS_TO_TEXT(CARD_REMOVE_A);
173 STATUS_TO_TEXT(CARD_INSERT_A);
174 STATUS_TO_TEXT(SIGSTATE_A);
175 STATUS_TO_TEXT(CMD_IDX_ERR);
176 STATUS_TO_TEXT(STOPBIT_ERR);
177 STATUS_TO_TEXT(ILL_FUNC);
178 STATUS_TO_TEXT(CMD_BUSY);
179 STATUS_TO_TEXT(CMDRESPEND);
180 STATUS_TO_TEXT(DATAEND);
181 STATUS_TO_TEXT(CRCFAIL);
182 STATUS_TO_TEXT(DATATIMEOUT);
183 STATUS_TO_TEXT(CMDTIMEOUT);
184 STATUS_TO_TEXT(RXOVERFLOW);
185 STATUS_TO_TEXT(TXUNDERRUN);
186 STATUS_TO_TEXT(RXRDY);
187 STATUS_TO_TEXT(TXRQ);
188 STATUS_TO_TEXT(ILL_ACCESS);
189 printk("\n");
190}
191
192#else
193#define pr_debug_status(s) do { } while (0)
194#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 08:01:36 -0500