1 files changed, 24 insertions, 0 deletions

diff --git a/arch/sh/include/cpu-sh4/cpu/sh7785.h b/arch/sh/include/cpu-sh4/cpu/sh7785.h
index e4006afb735e..89afaa6dc2d8 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7785.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7785.h
@@ -1,6 +1,30 @@
 #ifndef __ASM_SH7785_H__
 #define __ASM_SH7785_H__
 
+/* Boot Mode Pins, more information in sh7785 manual Rev.1.00, page 1628 */
+enum {
+        MODE_PIN_MODE0,  /* CPG - Initial Pck/Bck Frequency [FRQMR1] */
+        MODE_PIN_MODE1,  /* CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1] */
+        MODE_PIN_MODE2,  /* CPG - Reserved (L: Normal operation) */
+        MODE_PIN_MODE3,  /* CPG - Reserved (L: Normal operation) */
+        MODE_PIN_MODE4,  /* CPG - Initial PLL setting (72x/36x) */
+        MODE_PIN_MODE5,  /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.8] */
+        MODE_PIN_MODE6,  /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.9] */
+        MODE_PIN_MODE7,  /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.3] */
+        MODE_PIN_MODE8,  /* LBSC - Endian Mode (L: Big, H: Little) [BCR.31] */
+        MODE_PIN_MODE9,  /* LBSC - Master/Slave Mode (L: Slave) [BCR.30] */
+        MODE_PIN_MODE10, /* CPG - Clock Input (L: Ext Clk, H: Crystal) */
+        MODE_PIN_MODE11, /* PCI - Pin Mode (LL: PCI host, LH: PCI slave) */
+        MODE_PIN_MODE12, /* PCI - Pin Mode (HL: Local bus, HH: DU) */
+        MODE_PIN_MODE13, /* Boot Address Mode (L: 29-bit, H: 32-bit) */
+        MODE_PIN_MODE14, /* Reserved (H: Normal operation) */
+        MODE_PIN_MPMD,   /* Emulation Mode (L: Emulation mode, H: LSI mode) */
+};
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
+ */
 enum {
         /* PA */
         GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,