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-rw-r--r--Documentation/fb/sh7760fb.txt131
-rw-r--r--drivers/video/Kconfig13
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/sh7760fb.c658
-rw-r--r--include/asm-sh/sh7760fb.h197
5 files changed, 1000 insertions, 0 deletions
diff --git a/Documentation/fb/sh7760fb.txt b/Documentation/fb/sh7760fb.txt
new file mode 100644
index 000000000000..c87bfe5c630a
--- /dev/null
+++ b/Documentation/fb/sh7760fb.txt
@@ -0,0 +1,131 @@
1SH7760/SH7763 integrated LCDC Framebuffer driver
2================================================
3
40. Overwiew
5-----------
6The SH7760/SH7763 have an integrated LCD Display controller (LCDC) which
7supports (in theory) resolutions ranging from 1x1 to 1024x1024,
8with color depths ranging from 1 to 16 bits, on STN, DSTN and TFT Panels.
9
10Caveats:
11* Framebuffer memory must be a large chunk allocated at the top
12 of Area3 (HW requirement). Because of this requirement you should NOT
13 make the driver a module since at runtime it may become impossible to
14 get a large enough contiguous chunk of memory.
15
16* The driver does not support changing resolution while loaded
17 (displays aren't hotpluggable anyway)
18
19* Heavy flickering may be observed
20 a) if you're using 15/16bit color modes at >= 640x480 px resolutions,
21 b) during PCMCIA (or any other slow bus) activity.
22
23* Rotation works only 90degress clockwise, and only if horizontal
24 resolution is <= 320 pixels.
25
26files: drivers/video/sh7760fb.c
27 include/asm-sh/sh7760fb.h
28 Documentation/fb/sh7760fb.txt
29
301. Platform setup
31-----------------
32SH7760:
33 Video data is fetched via the DMABRG DMA engine, so you have to
34 configure the SH DMAC for DMABRG mode (write 0x94808080 to the
35 DMARSRA register somewhere at boot).
36
37 PFC registers PCCR and PCDR must be set to peripheral mode.
38 (write zeros to both).
39
40The driver does NOT do the above for you since board setup is, well, job
41of the board setup code.
42
432. Panel definitions
44--------------------
45The LCDC must explicitly be told about the type of LCD panel
46attached. Data must be wrapped in a "struct sh7760fb_platdata" and
47passed to the driver as platform_data.
48
49Suggest you take a closer look at the SH7760 Manual, Section 30.
50(http://documentation.renesas.com/eng/products/mpumcu/e602291_sh7760.pdf)
51
52The following code illustrates what needs to be done to
53get the framebuffer working on a 640x480 TFT:
54
55====================== cut here ======================================
56
57#include <linux/fb.h>
58#include <asm/sh7760fb.h>
59
60/*
61 * NEC NL6440bc26-01 640x480 TFT
62 * dotclock 25175 kHz
63 * Xres 640 Yres 480
64 * Htotal 800 Vtotal 525
65 * HsynStart 656 VsynStart 490
66 * HsynLenn 30 VsynLenn 2
67 *
68 * The linux framebuffer layer does not use the syncstart/synclen
69 * values but right/left/upper/lower margin values. The comments
70 * for the x_margin explain how to calculate those from given
71 * panel sync timings.
72 */
73static struct fb_videomode nl6448bc26 = {
74 .name = "NL6448BC26",
75 .refresh = 60,
76 .xres = 640,
77 .yres = 480,
78 .pixclock = 39683, /* in picoseconds! */
79 .hsync_len = 30,
80 .vsync_len = 2,
81 .left_margin = 114, /* HTOT - (HSYNSLEN + HSYNSTART) */
82 .right_margin = 16, /* HSYNSTART - XRES */
83 .upper_margin = 33, /* VTOT - (VSYNLEN + VSYNSTART) */
84 .lower_margin = 10, /* VSYNSTART - YRES */
85 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
86 .vmode = FB_VMODE_NONINTERLACED,
87 .flag = 0,
88};
89
90static struct sh7760fb_platdata sh7760fb_nl6448 = {
91 .def_mode = &nl6448bc26,
92 .ldmtr = LDMTR_TFT_COLOR_16, /* 16bit TFT panel */
93 .lddfr = LDDFR_8BPP, /* we want 8bit output */
94 .ldpmmr = 0x0070,
95 .ldpspr = 0x0500,
96 .ldaclnr = 0,
97 .ldickr = LDICKR_CLKSRC(LCDC_CLKSRC_EXTERNAL) |
98 LDICKR_CLKDIV(1),
99 .rotate = 0,
100 .novsync = 1,
101 .blank = NULL,
102};
103
104/* SH7760:
105 * 0xFE300800: 256 * 4byte xRGB palette ram
106 * 0xFE300C00: 42 bytes ctrl registers
107 */
108static struct resource sh7760_lcdc_res[] = {
109 [0] = {
110 .start = 0xFE300800,
111 .end = 0xFE300CFF,
112 .flags = IORESOURCE_MEM,
113 },
114 [1] = {
115 .start = 65,
116 .end = 65,
117 .flags = IORESOURCE_IRQ,
118 },
119};
120
121static struct platform_device sh7760_lcdc_dev = {
122 .dev = {
123 .platform_data = &sh7760fb_nl6448,
124 },
125 .name = "sh7760-lcdc",
126 .id = -1,
127 .resource = sh7760_lcdc_res,
128 .num_resources = ARRAY_SIZE(sh7760_lcdc_res),
129};
130
131====================== cut here ======================================
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index c1b7db843411..70d135e0cc47 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1991,6 +1991,19 @@ config FB_COBALT
1991 tristate "Cobalt server LCD frame buffer support" 1991 tristate "Cobalt server LCD frame buffer support"
1992 depends on FB && MIPS_COBALT 1992 depends on FB && MIPS_COBALT
1993 1993
1994config FB_SH7760
1995 bool "SH7760/SH7763 LCDC support"
1996 depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763)
1997 select FB_CFB_FILLRECT
1998 select FB_CFB_COPYAREA
1999 select FB_CFB_IMAGEBLIT
2000 help
2001 Support for the SH7760/SH7763 integrated (D)STN/TFT LCD Controller.
2002 Supports display resolutions up to 1024x1024 pixel, grayscale and
2003 color operation, with depths ranging from 1 bpp to 8 bpp monochrome
2004 and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
2005 panels <= 320 pixel horizontal resolution.
2006
1994config FB_VIRTUAL 2007config FB_VIRTUAL
1995 tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)" 2008 tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
1996 depends on FB 2009 depends on FB
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 358032597757..0ebc1bfd2514 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
106obj-$(CONFIG_FB_MAXINE) += maxinefb.o 106obj-$(CONFIG_FB_MAXINE) += maxinefb.o
107obj-$(CONFIG_FB_METRONOME) += metronomefb.o 107obj-$(CONFIG_FB_METRONOME) += metronomefb.o
108obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o 108obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
109obj-$(CONFIG_FB_SH7760) += sh7760fb.o
109obj-$(CONFIG_FB_IMX) += imxfb.o 110obj-$(CONFIG_FB_IMX) += imxfb.o
110obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o 111obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
111obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o 112obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o
diff --git a/drivers/video/sh7760fb.c b/drivers/video/sh7760fb.c
new file mode 100644
index 000000000000..4d0e28c5790b
--- /dev/null
+++ b/drivers/video/sh7760fb.c
@@ -0,0 +1,658 @@
1/*
2 * SH7760/SH7763 LCDC Framebuffer driver.
3 *
4 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
5 * Manuel Lauss <mano@roarinelk.homelinux.net>
6 * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
11 *
12 * PLEASE HAVE A LOOK AT Documentation/fb/sh7760fb.txt!
13 *
14 * Thanks to Siegfried Schaefer <s.schaefer at schaefer-edv.de>
15 * for his original source and testing!
16 */
17
18#include <linux/completion.h>
19#include <linux/delay.h>
20#include <linux/dma-mapping.h>
21#include <linux/fb.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27
28#include <asm/sh7760fb.h>
29
30struct sh7760fb_par {
31 void __iomem *base;
32 int irq;
33
34 struct sh7760fb_platdata *pd; /* display information */
35
36 dma_addr_t fbdma; /* physical address */
37
38 int rot; /* rotation enabled? */
39
40 u32 pseudo_palette[16];
41
42 struct platform_device *dev;
43 struct resource *ioarea;
44 struct completion vsync; /* vsync irq event */
45};
46
47static irqreturn_t sh7760fb_irq(int irq, void *data)
48{
49 struct completion *c = data;
50
51 complete(c);
52
53 return IRQ_HANDLED;
54}
55
56static void sh7760fb_wait_vsync(struct fb_info *info)
57{
58 struct sh7760fb_par *par = info->par;
59
60 if (par->pd->novsync)
61 return;
62
63 iowrite16(ioread16(par->base + LDINTR) & ~VINT_CHECK,
64 par->base + LDINTR);
65
66 if (par->irq < 0) {
67 /* poll for vert. retrace: status bit is sticky */
68 while (!(ioread16(par->base + LDINTR) & VINT_CHECK))
69 cpu_relax();
70 } else {
71 /* a "wait_for_irq_event(par->irq)" would be extremely nice */
72 init_completion(&par->vsync);
73 enable_irq(par->irq);
74 wait_for_completion(&par->vsync);
75 disable_irq_nosync(par->irq);
76 }
77}
78
79/* wait_for_lps - wait until power supply has reached a certain state. */
80static int wait_for_lps(struct sh7760fb_par *par, int val)
81{
82 int i = 100;
83 while (--i && ((ioread16(par->base + LDPMMR) & 3) != val))
84 msleep(1);
85
86 if (i <= 0)
87 return -ETIMEDOUT;
88
89 return 0;
90}
91
92/* en/disable the LCDC */
93static int sh7760fb_blank(int blank, struct fb_info *info)
94{
95 struct sh7760fb_par *par = info->par;
96 struct sh7760fb_platdata *pd = par->pd;
97 unsigned short cntr = ioread16(par->base + LDCNTR);
98 unsigned short intr = ioread16(par->base + LDINTR);
99 int lps;
100
101 if (blank == FB_BLANK_UNBLANK) {
102 intr |= VINT_START;
103 cntr = LDCNTR_DON2 | LDCNTR_DON;
104 lps = 3;
105 } else {
106 intr &= ~VINT_START;
107 cntr = LDCNTR_DON2;
108 lps = 0;
109 }
110
111 if (pd->blank)
112 pd->blank(blank);
113
114 iowrite16(intr, par->base + LDINTR);
115 iowrite16(cntr, par->base + LDCNTR);
116
117 return wait_for_lps(par, lps);
118}
119
120/* set color registers */
121static int sh7760fb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
122{
123 struct sh7760fb_par *par = info->par;
124 u32 s = cmap->start;
125 u32 l = cmap->len;
126 u16 *r = cmap->red;
127 u16 *g = cmap->green;
128 u16 *b = cmap->blue;
129 u32 col, tmo;
130 int ret;
131
132 ret = 0;
133
134 sh7760fb_wait_vsync(info);
135
136 /* request palette access */
137 iowrite16(LDPALCR_PALEN, par->base + LDPALCR);
138
139 /* poll for access grant */
140 tmo = 100;
141 while (!(ioread16(par->base + LDPALCR) & LDPALCR_PALS) && (--tmo))
142 cpu_relax();
143
144 if (!tmo) {
145 ret = 1;
146 dev_dbg(info->dev, "no palette access!\n");
147 goto out;
148 }
149
150 while (l && (s < 256)) {
151 col = ((*r) & 0xff) << 16;
152 col |= ((*g) & 0xff) << 8;
153 col |= ((*b) & 0xff);
154 col &= SH7760FB_PALETTE_MASK;
155
156 if (s < 16)
157 ((u32 *) (info->pseudo_palette))[s] = s;
158
159 s++;
160 l--;
161 r++;
162 g++;
163 b++;
164 }
165out:
166 iowrite16(0, par->base + LDPALCR);
167 return ret;
168}
169
170static void encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info,
171 unsigned long stride)
172{
173 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
174 strcpy(fix->id, "sh7760-lcdc");
175
176 fix->smem_start = (unsigned long)info->screen_base;
177 fix->smem_len = info->screen_size;
178
179 fix->line_length = stride;
180}
181
182static int sh7760fb_get_color_info(struct device *dev,
183 u16 lddfr, int *bpp, int *gray)
184{
185 int lbpp, lgray;
186
187 lgray = lbpp = 0;
188
189 switch (lddfr & LDDFR_COLOR_MASK) {
190 case LDDFR_1BPP_MONO:
191 lgray = 1;
192 lbpp = 1;
193 break;
194 case LDDFR_2BPP_MONO:
195 lgray = 1;
196 lbpp = 2;
197 break;
198 case LDDFR_4BPP_MONO:
199 lgray = 1;
200 case LDDFR_4BPP:
201 lbpp = 4;
202 break;
203 case LDDFR_6BPP_MONO:
204 lgray = 1;
205 case LDDFR_8BPP:
206 lbpp = 8;
207 break;
208 case LDDFR_16BPP_RGB555:
209 case LDDFR_16BPP_RGB565:
210 lbpp = 16;
211 lgray = 0;
212 break;
213 default:
214 dev_dbg(dev, "unsupported LDDFR bit depth.\n");
215 return -EINVAL;
216 }
217
218 if (bpp)
219 *bpp = lbpp;
220 if (gray)
221 *gray = lgray;
222
223 return 0;
224}
225
226static int sh7760fb_check_var(struct fb_var_screeninfo *var,
227 struct fb_info *info)
228{
229 struct fb_fix_screeninfo *fix = &info->fix;
230 struct sh7760fb_par *par = info->par;
231 int ret, bpp;
232
233 /* get color info from register value */
234 ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, NULL);
235 if (ret)
236 return ret;
237
238 var->bits_per_pixel = bpp;
239
240 if ((var->grayscale) && (var->bits_per_pixel == 1))
241 fix->visual = FB_VISUAL_MONO10;
242 else if (var->bits_per_pixel >= 15)
243 fix->visual = FB_VISUAL_TRUECOLOR;
244 else
245 fix->visual = FB_VISUAL_PSEUDOCOLOR;
246
247 /* TODO: add some more validation here */
248 return 0;
249}
250
251/*
252 * sh7760fb_set_par - set videomode.
253 *
254 * NOTE: The rotation, grayscale and DSTN codepaths are
255 * totally untested!
256 */
257static int sh7760fb_set_par(struct fb_info *info)
258{
259 struct sh7760fb_par *par = info->par;
260 struct fb_videomode *vm = par->pd->def_mode;
261 unsigned long sbase, dstn_off, ldsarl, stride;
262 unsigned short hsynp, hsynw, htcn, hdcn;
263 unsigned short vsynp, vsynw, vtln, vdln;
264 unsigned short lddfr, ldmtr;
265 int ret, bpp, gray;
266
267 par->rot = par->pd->rotate;
268
269 /* rotate only works with xres <= 320 */
270 if (par->rot && (vm->xres > 320)) {
271 dev_dbg(info->dev, "rotation disabled due to display size\n");
272 par->rot = 0;
273 }
274
275 /* calculate LCDC reg vals from display parameters */
276 hsynp = vm->right_margin + vm->xres;
277 hsynw = vm->hsync_len;
278 htcn = vm->left_margin + hsynp + hsynw;
279 hdcn = vm->xres;
280 vsynp = vm->lower_margin + vm->yres;
281 vsynw = vm->vsync_len;
282 vtln = vm->upper_margin + vsynp + vsynw;
283 vdln = vm->yres;
284
285 /* get color info from register value */
286 ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, &gray);
287 if (ret)
288 return ret;
289
290 dev_dbg(info->dev, "%dx%d %dbpp %s (orientation %s)\n", hdcn,
291 vdln, bpp, gray ? "grayscale" : "color",
292 par->rot ? "rotated" : "normal");
293
294#ifdef CONFIG_CPU_LITTLE_ENDIAN
295 lddfr = par->pd->lddfr | (1 << 8);
296#else
297 lddfr = par->pd->lddfr & ~(1 << 8);
298#endif
299
300 ldmtr = par->pd->ldmtr;
301
302 if (!(vm->sync & FB_SYNC_HOR_HIGH_ACT))
303 ldmtr |= LDMTR_CL1POL;
304 if (!(vm->sync & FB_SYNC_VERT_HIGH_ACT))
305 ldmtr |= LDMTR_FLMPOL;
306
307 /* shut down LCDC before changing display parameters */
308 sh7760fb_blank(FB_BLANK_POWERDOWN, info);
309
310 iowrite16(par->pd->ldickr, par->base + LDICKR); /* pixclock */
311 iowrite16(ldmtr, par->base + LDMTR); /* polarities */
312 iowrite16(lddfr, par->base + LDDFR); /* color/depth */
313 iowrite16((par->rot ? 1 << 13 : 0), par->base + LDSMR); /* rotate */
314 iowrite16(par->pd->ldpmmr, par->base + LDPMMR); /* Power Management */
315 iowrite16(par->pd->ldpspr, par->base + LDPSPR); /* Power Supply Ctrl */
316
317 /* display resolution */
318 iowrite16(((htcn >> 3) - 1) | (((hdcn >> 3) - 1) << 8),
319 par->base + LDHCNR);
320 iowrite16(vdln - 1, par->base + LDVDLNR);
321 iowrite16(vtln - 1, par->base + LDVTLNR);
322 /* h/v sync signals */
323 iowrite16((vsynp - 1) | ((vsynw - 1) << 12), par->base + LDVSYNR);
324 iowrite16(((hsynp >> 3) - 1) | (((hsynw >> 3) - 1) << 12),
325 par->base + LDHSYNR);
326 /* AC modulation sig */
327 iowrite16(par->pd->ldaclnr, par->base + LDACLNR);
328
329 stride = (par->rot) ? vtln : hdcn;
330 if (!gray)
331 stride *= (bpp + 7) >> 3;
332 else {
333 if (bpp == 1)
334 stride >>= 3;
335 else if (bpp == 2)
336 stride >>= 2;
337 else if (bpp == 4)
338 stride >>= 1;
339 /* 6 bpp == 8 bpp */
340 }
341
342 /* if rotated, stride must be power of 2 */
343 if (par->rot) {
344 unsigned long bit = 1 << 31;
345 while (bit) {
346 if (stride & bit)
347 break;
348 bit >>= 1;
349 }
350 if (stride & ~bit)
351 stride = bit << 1; /* not P-o-2, round up */
352 }
353 iowrite16(stride, par->base + LDLAOR);
354
355 /* set display mem start address */
356 sbase = (unsigned long)par->fbdma;
357 if (par->rot)
358 sbase += (hdcn - 1) * stride;
359
360 iowrite32(sbase, par->base + LDSARU);
361
362 /*
363 * for DSTN need to set address for lower half.
364 * I (mlau) don't know which address to set it to,
365 * so I guessed at (stride * yres/2).
366 */
367 if (((ldmtr & 0x003f) >= LDMTR_DSTN_MONO_8) &&
368 ((ldmtr & 0x003f) <= LDMTR_DSTN_COLOR_16)) {
369
370 dev_dbg(info->dev, " ***** DSTN untested! *****\n");
371
372 dstn_off = stride;
373 if (par->rot)
374 dstn_off *= hdcn >> 1;
375 else
376 dstn_off *= vdln >> 1;
377
378 ldsarl = sbase + dstn_off;
379 } else
380 ldsarl = 0;
381
382 iowrite32(ldsarl, par->base + LDSARL); /* mem for lower half of DSTN */
383
384 encode_fix(&info->fix, info, stride);
385 sh7760fb_check_var(&info->var, info);
386
387 sh7760fb_blank(FB_BLANK_UNBLANK, info); /* panel on! */
388
389 dev_dbg(info->dev, "hdcn : %6d htcn : %6d\n", hdcn, htcn);
390 dev_dbg(info->dev, "hsynw : %6d hsynp : %6d\n", hsynw, hsynp);
391 dev_dbg(info->dev, "vdln : %6d vtln : %6d\n", vdln, vtln);
392 dev_dbg(info->dev, "vsynw : %6d vsynp : %6d\n", vsynw, vsynp);
393 dev_dbg(info->dev, "clksrc: %6d clkdiv: %6d\n",
394 (par->pd->ldickr >> 12) & 3, par->pd->ldickr & 0x1f);
395 dev_dbg(info->dev, "ldpmmr: 0x%04x ldpspr: 0x%04x\n", par->pd->ldpmmr,
396 par->pd->ldpspr);
397 dev_dbg(info->dev, "ldmtr : 0x%04x lddfr : 0x%04x\n", ldmtr, lddfr);
398 dev_dbg(info->dev, "ldlaor: %ld\n", stride);
399 dev_dbg(info->dev, "ldsaru: 0x%08lx ldsarl: 0x%08lx\n", sbase, ldsarl);
400
401 return 0;
402}
403
404static struct fb_ops sh7760fb_ops = {
405 .owner = THIS_MODULE,
406 .fb_blank = sh7760fb_blank,
407 .fb_check_var = sh7760fb_check_var,
408 .fb_setcmap = sh7760fb_setcmap,
409 .fb_set_par = sh7760fb_set_par,
410 .fb_fillrect = cfb_fillrect,
411 .fb_copyarea = cfb_copyarea,
412 .fb_imageblit = cfb_imageblit,
413};
414
415static void sh7760fb_free_mem(struct fb_info *info)
416{
417 struct sh7760fb_par *par = info->par;
418
419 if (!info->screen_base)
420 return;
421
422 dma_free_coherent(info->dev, info->screen_size,
423 info->screen_base, par->fbdma);
424
425 par->fbdma = 0;
426 info->screen_base = NULL;
427 info->screen_size = 0;
428}
429
430/* allocate the framebuffer memory. This memory must be in Area3,
431 * (dictated by the DMA engine) and contiguous, at a 512 byte boundary.
432 */
433static int sh7760fb_alloc_mem(struct fb_info *info)
434{
435 struct sh7760fb_par *par = info->par;
436 void *fbmem;
437 unsigned long vram;
438 int ret, bpp;
439
440 if (info->screen_base)
441 return 0;
442
443 /* get color info from register value */
444 ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, NULL);
445 if (ret) {
446 printk(KERN_ERR "colinfo\n");
447 return ret;
448 }
449
450 /* min VRAM: xres_min = 16, yres_min = 1, bpp = 1: 2byte -> 1 page
451 max VRAM: xres_max = 1024, yres_max = 1024, bpp = 16: 2MB */
452
453 vram = info->var.xres * info->var.yres;
454 if (info->var.grayscale) {
455 if (bpp == 1)
456 vram >>= 3;
457 else if (bpp == 2)
458 vram >>= 2;
459 else if (bpp == 4)
460 vram >>= 1;
461 } else if (bpp > 8)
462 vram *= 2;
463 if ((vram < 1) || (vram > 1024 * 2048)) {
464 dev_dbg(info->dev, "too much VRAM required. Check settings\n");
465 return -ENODEV;
466 }
467
468 if (vram < PAGE_SIZE)
469 vram = PAGE_SIZE;
470
471 fbmem = dma_alloc_coherent(info->dev, vram, &par->fbdma, GFP_KERNEL);
472
473 if (!fbmem)
474 return -ENOMEM;
475
476 if ((par->fbdma & SH7760FB_DMA_MASK) != SH7760FB_DMA_MASK) {
477 sh7760fb_free_mem(info);
478 dev_err(info->dev, "kernel gave me memory at 0x%08lx, which is"
479 "unusable for the LCDC\n", (unsigned long)par->fbdma);
480 return -ENOMEM;
481 }
482
483 info->screen_base = fbmem;
484 info->screen_size = vram;
485
486 return 0;
487}
488
489static int __devinit sh7760fb_probe(struct platform_device *pdev)
490{
491 struct fb_info *info;
492 struct resource *res;
493 struct sh7760fb_par *par;
494 int ret;
495
496 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
497 if (unlikely(res == NULL)) {
498 dev_err(&pdev->dev, "invalid resource\n");
499 return -EINVAL;
500 }
501
502 info = framebuffer_alloc(sizeof(struct sh7760fb_par), &pdev->dev);
503 if (!info)
504 return -ENOMEM;
505
506 par = info->par;
507 par->dev = pdev;
508
509 par->pd = pdev->dev.platform_data;
510 if (!par->pd) {
511 dev_dbg(info->dev, "no display setup data!\n");
512 ret = -ENODEV;
513 goto out_fb;
514 }
515
516 par->ioarea = request_mem_region(res->start,
517 (res->end - res->start), pdev->name);
518 if (!par->ioarea) {
519 dev_err(&pdev->dev, "mmio area busy\n");
520 ret = -EBUSY;
521 goto out_fb;
522 }
523
524 par->base = ioremap_nocache(res->start, res->end - res->start + 1);
525 if (!par->base) {
526 dev_err(&pdev->dev, "cannot remap\n");
527 ret = -ENODEV;
528 goto out_res;
529 }
530
531 iowrite16(0, par->base + LDINTR); /* disable vsync irq */
532 par->irq = platform_get_irq(pdev, 0);
533 if (par->irq >= 0) {
534 ret = request_irq(par->irq, sh7760fb_irq, 0,
535 "sh7760-lcdc", &par->vsync);
536 if (ret) {
537 dev_err(&pdev->dev, "cannot grab IRQ\n");
538 par->irq = -ENXIO;
539 } else
540 disable_irq_nosync(par->irq);
541 }
542
543 fb_videomode_to_var(&info->var, par->pd->def_mode);
544
545 ret = sh7760fb_alloc_mem(info);
546 if (ret) {
547 dev_dbg(info->dev, "framebuffer memory allocation failed!\n");
548 goto out_unmap;
549 }
550
551 info->pseudo_palette = par->pseudo_palette;
552
553 /* fixup color register bitpositions. These are fixed by hardware */
554 info->var.red.offset = 11;
555 info->var.red.length = 5;
556 info->var.red.msb_right = 0;
557
558 info->var.green.offset = 5;
559 info->var.green.length = 6;
560 info->var.green.msb_right = 0;
561
562 info->var.blue.offset = 0;
563 info->var.blue.length = 5;
564 info->var.blue.msb_right = 0;
565
566 info->var.transp.offset = 0;
567 info->var.transp.length = 0;
568 info->var.transp.msb_right = 0;
569
570 /* set the DON2 bit now, before cmap allocation, as it will randomize
571 * palette memory.
572 */
573 iowrite16(LDCNTR_DON2, par->base + LDCNTR);
574 info->fbops = &sh7760fb_ops;
575
576 ret = fb_alloc_cmap(&info->cmap, 256, 0);
577 if (ret) {
578 dev_dbg(info->dev, "Unable to allocate cmap memory\n");
579 goto out_mem;
580 }
581
582 ret = register_framebuffer(info);
583 if (ret < 0) {
584 dev_dbg(info->dev, "cannot register fb!\n");
585 goto out_cmap;
586 }
587 platform_set_drvdata(pdev, info);
588
589 printk(KERN_INFO "%s: memory at phys 0x%08lx-0x%08lx, size %ld KiB\n",
590 pdev->name,
591 (unsigned long)par->fbdma,
592 (unsigned long)(par->fbdma + info->screen_size - 1),
593 info->screen_size >> 10);
594
595 return 0;
596
597out_cmap:
598 sh7760fb_blank(FB_BLANK_POWERDOWN, info);
599 fb_dealloc_cmap(&info->cmap);
600out_mem:
601 sh7760fb_free_mem(info);
602out_unmap:
603 if (par->irq >= 0)
604 free_irq(par->irq, &par->vsync);
605 iounmap(par->base);
606out_res:
607 release_resource(par->ioarea);
608 kfree(par->ioarea);
609out_fb:
610 framebuffer_release(info);
611 return ret;
612}
613
614static int __devexit sh7760fb_remove(struct platform_device *dev)
615{
616 struct fb_info *info = platform_get_drvdata(dev);
617 struct sh7760fb_par *par = info->par;
618
619 sh7760fb_blank(FB_BLANK_POWERDOWN, info);
620 unregister_framebuffer(info);
621 fb_dealloc_cmap(&info->cmap);
622 sh7760fb_free_mem(info);
623 if (par->irq >= 0)
624 free_irq(par->irq, par);
625 iounmap(par->base);
626 release_resource(par->ioarea);
627 kfree(par->ioarea);
628 framebuffer_release(info);
629 platform_set_drvdata(dev, NULL);
630
631 return 0;
632}
633
634static struct platform_driver sh7760_lcdc_driver = {
635 .driver = {
636 .name = "sh7760-lcdc",
637 .owner = THIS_MODULE,
638 },
639 .probe = sh7760fb_probe,
640 .remove = __devexit_p(sh7760fb_remove),
641};
642
643static int __init sh7760fb_init(void)
644{
645 return platform_driver_register(&sh7760_lcdc_driver);
646}
647
648static void __exit sh7760fb_exit(void)
649{
650 platform_driver_unregister(&sh7760_lcdc_driver);
651}
652
653module_init(sh7760fb_init);
654module_exit(sh7760fb_exit);
655
656MODULE_AUTHOR("Nobuhiro Iwamatsu, Manuel Lauss");
657MODULE_DESCRIPTION("FBdev for SH7760/63 integrated LCD Controller");
658MODULE_LICENSE("GPL");
diff --git a/include/asm-sh/sh7760fb.h b/include/asm-sh/sh7760fb.h
new file mode 100644
index 000000000000..8767f61aceca
--- /dev/null
+++ b/include/asm-sh/sh7760fb.h
@@ -0,0 +1,197 @@
1/*
2 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
3 *
4 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
5 * Manuel Lauss <mano@roarinelk.homelinux.net>
6 * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7 */
8
9#ifndef _ASM_SH_SH7760FB_H
10#define _ASM_SH_SH7760FB_H
11
12/*
13 * some bits of the colormap registers should be written as zero.
14 * create a mask for that.
15 */
16#define SH7760FB_PALETTE_MASK 0x00f8fcf8
17
18/* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
19#define SH7760FB_DMA_MASK 0x0C000000
20
21/* palette */
22#define LDPR(x) (((x) << 2))
23
24/* framebuffer registers and bits */
25#define LDICKR 0x400
26#define LDMTR 0x402
27/* see sh7760fb.h for LDMTR bits */
28#define LDDFR 0x404
29#define LDDFR_PABD (1 << 8)
30#define LDDFR_COLOR_MASK 0x7F
31#define LDSMR 0x406
32#define LDSMR_ROT (1 << 13)
33#define LDSARU 0x408
34#define LDSARL 0x40c
35#define LDLAOR 0x410
36#define LDPALCR 0x412
37#define LDPALCR_PALS (1 << 4)
38#define LDPALCR_PALEN (1 << 0)
39#define LDHCNR 0x414
40#define LDHSYNR 0x416
41#define LDVDLNR 0x418
42#define LDVTLNR 0x41a
43#define LDVSYNR 0x41c
44#define LDACLNR 0x41e
45#define LDINTR 0x420
46#define LDPMMR 0x424
47#define LDPSPR 0x426
48#define LDCNTR 0x428
49#define LDCNTR_DON (1 << 0)
50#define LDCNTR_DON2 (1 << 4)
51
52#ifdef CONFIG_CPU_SUBTYPE_SH7763
53# define LDLIRNR 0x440
54/* LDINTR bit */
55# define LDINTR_MINTEN (1 << 15)
56# define LDINTR_FINTEN (1 << 14)
57# define LDINTR_VSINTEN (1 << 13)
58# define LDINTR_VEINTEN (1 << 12)
59# define LDINTR_MINTS (1 << 11)
60# define LDINTR_FINTS (1 << 10)
61# define LDINTR_VSINTS (1 << 9)
62# define LDINTR_VEINTS (1 << 8)
63# define VINT_START (LDINTR_VSINTEN)
64# define VINT_CHECK (LDINTR_VSINTS)
65#else
66/* LDINTR bit */
67# define LDINTR_VINTSEL (1 << 12)
68# define LDINTR_VINTE (1 << 8)
69# define LDINTR_VINTS (1 << 0)
70# define VINT_START (LDINTR_VINTSEL)
71# define VINT_CHECK (LDINTR_VINTS)
72#endif
73
74/* HSYNC polarity inversion */
75#define LDMTR_FLMPOL (1 << 15)
76
77/* VSYNC polarity inversion */
78#define LDMTR_CL1POL (1 << 14)
79
80/* DISPLAY-ENABLE polarity inversion */
81#define LDMTR_DISPEN_LOWACT (1 << 13)
82
83/* DISPLAY DATA BUS polarity inversion */
84#define LDMTR_DPOL_LOWACT (1 << 12)
85
86/* AC modulation signal enable */
87#define LDMTR_MCNT (1 << 10)
88
89/* Disable output of HSYNC during VSYNC period */
90#define LDMTR_CL1CNT (1 << 9)
91
92/* Disable output of VSYNC during VSYNC period */
93#define LDMTR_CL2CNT (1 << 8)
94
95/* Display types supported by the LCDC */
96#define LDMTR_STN_MONO_4 0x00
97#define LDMTR_STN_MONO_8 0x01
98#define LDMTR_STN_COLOR_4 0x08
99#define LDMTR_STN_COLOR_8 0x09
100#define LDMTR_STN_COLOR_12 0x0A
101#define LDMTR_STN_COLOR_16 0x0B
102#define LDMTR_DSTN_MONO_8 0x11
103#define LDMTR_DSTN_MONO_16 0x13
104#define LDMTR_DSTN_COLOR_8 0x19
105#define LDMTR_DSTN_COLOR_12 0x1A
106#define LDMTR_DSTN_COLOR_16 0x1B
107#define LDMTR_TFT_COLOR_16 0x2B
108
109/* framebuffer color layout */
110#define LDDFR_1BPP_MONO 0x00
111#define LDDFR_2BPP_MONO 0x01
112#define LDDFR_4BPP_MONO 0x02
113#define LDDFR_6BPP_MONO 0x04
114#define LDDFR_4BPP 0x0A
115#define LDDFR_8BPP 0x0C
116#define LDDFR_16BPP_RGB555 0x1D
117#define LDDFR_16BPP_RGB565 0x2D
118
119/* LCDC Pixclock sources */
120#define LCDC_CLKSRC_BUSCLOCK 0
121#define LCDC_CLKSRC_PERIPHERAL 1
122#define LCDC_CLKSRC_EXTERNAL 2
123
124#define LDICKR_CLKSRC(x) \
125 (((x) & 3) << 12)
126
127/* LCDC pixclock input divider. Set to 1 at a minimum! */
128#define LDICKR_CLKDIV(x) \
129 ((x) & 0x1f)
130
131struct sh7760fb_platdata {
132
133 /* Set this member to a valid fb_videmode for the display you
134 * wish to use. The following members must be initialized:
135 * xres, yres, hsync_len, vsync_len, sync,
136 * {left,right,upper,lower}_margin.
137 * The driver uses the above members to calculate register values
138 * and memory requirements. Other members are ignored but may
139 * be used by other framebuffer layer components.
140 */
141 struct fb_videomode *def_mode;
142
143 /* LDMTR includes display type and signal polarity. The
144 * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo
145 * data above; however the polarities of the following signals
146 * must be encoded in the ldmtr member:
147 * Display Enable signal (default high-active) DISPEN_LOWACT
148 * Display Data signals (default high-active) DPOL_LOWACT
149 * AC Modulation signal (default off) MCNT
150 * Hsync-During-Vsync suppression (default off) CL1CNT
151 * Vsync-during-vsync suppression (default off) CL2CNT
152 * NOTE: also set a display type!
153 * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16})
154 */
155 u16 ldmtr;
156
157 /* LDDFR controls framebuffer image format (depth, organization)
158 * Use ONE of the LDDFR_?BPP_* macros!
159 */
160 u16 lddfr;
161
162 /* LDPMMR and LDPSPR control the timing of the power signals
163 * for the display. Please read the SH7760 Hardware Manual,
164 * Chapters 30.3.17, 30.3.18 and 30.4.6!
165 */
166 u16 ldpmmr;
167 u16 ldpspr;
168
169 /* LDACLNR contains the line numbers after which the AC modulation
170 * signal is to toggle. Set to ZERO for TFTs or displays which
171 * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual).
172 */
173 u16 ldaclnr;
174
175 /* LDICKR contains information on pixelclock source and config.
176 * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros.
177 * minimal value for CLKDIV() must be 1!.
178 */
179 u16 ldickr;
180
181 /* set this member to 1 if you wish to use the LCDC's hardware
182 * rotation function. This is limited to displays <= 320x200
183 * pixels resolution!
184 */
185 int rotate; /* set to 1 to rotate 90 CCW */
186
187 /* set this to 1 to suppress vsync irq use. */
188 int novsync;
189
190 /* blanking hook for platform. Set this if your platform can do
191 * more than the LCDC in terms of blanking (e.g. disable clock
192 * generator / backlight power supply / etc.
193 */
194 void (*blank) (int);
195};
196
197#endif /* _ASM_SH_SH7760FB_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 03:11:50 -0500