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-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts4
-rw-r--r--arch/arm/boot/dts/am335x-igep0033.dtsi4
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi7
-rw-r--r--arch/arm/boot/dts/am4372.dtsi1
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts4
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts405
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts111
-rw-r--r--arch/arm/boot/dts/dra7.dtsi167
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts296
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi22
-rw-r--r--arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi41
-rw-r--r--arch/arm/boot/dts/omap-zoom-common.dtsi62
-rw-r--r--arch/arm/boot/dts/omap2420-n8x0-common.dtsi4
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi1
-rw-r--r--arch/arm/boot/dts/omap2430-sdp.dts28
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3517.dts11
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3530.dts11
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3730.dts24
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x.dtsi39
-rw-r--r--arch/arm/boot/dts/omap3-devkit8000.dts4
-rw-r--r--arch/arm/boot/dts/omap3-evm-37xx.dts5
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dtsi86
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi103
-rw-r--r--arch/arm/boot/dts/omap3-igep0020-common.dtsi246
-rw-r--r--arch/arm/boot/dts/omap3-igep0020-rev-f.dts45
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts285
-rw-r--r--arch/arm/boot/dts/omap3-igep0030-common.dtsi60
-rw-r--r--arch/arm/boot/dts/omap3-igep0030-rev-g.dts67
-rw-r--r--arch/arm/boot/dts/omap3-igep0030.dts123
-rw-r--r--arch/arm/boot/dts/omap3-ldp.dts3
-rw-r--r--arch/arm/boot/dts/omap3-lilly-a83x.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts35
-rw-r--r--arch/arm/boot/dts/omap3-n950-n9.dtsi4
-rw-r--r--arch/arm/boot/dts/omap3-sb-t35.dtsi90
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3517.dts14
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3530.dts14
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3730.dts14
-rw-r--r--arch/arm/boot/dts/omap3-tao3530.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts8
-rw-r--r--arch/arm/boot/dts/omap4.dtsi1
-rw-r--r--arch/arm/boot/dts/omap5.dtsi1
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c36
45 files changed, 1980 insertions, 515 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5a8b065e3d7b..2b57568af583 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -309,7 +309,9 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
309 omap3-ha.dtb \ 309 omap3-ha.dtb \
310 omap3-ha-lcd.dtb \ 310 omap3-ha-lcd.dtb \
311 omap3-igep0020.dtb \ 311 omap3-igep0020.dtb \
312 omap3-igep0020-rev-f.dtb \
312 omap3-igep0030.dtb \ 313 omap3-igep0030.dtb \
314 omap3-igep0030-rev-g.dtb \
313 omap3-ldp.dtb \ 315 omap3-ldp.dtb \
314 omap3-lilly-dbb056.dtb \ 316 omap3-lilly-dbb056.dtb \
315 omap3-n900.dtb \ 317 omap3-n900.dtb \
@@ -354,6 +356,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
354 omap5-sbc-t54.dtb \ 356 omap5-sbc-t54.dtb \
355 omap5-uevm.dtb 357 omap5-uevm.dtb
356dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ 358dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
359 am57xx-beagle-x15.dtb \
357 dra72-evm.dtb 360 dra72-evm.dtb
358dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ 361dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
359 orion5x-lacie-ethernet-disk-mini-v2.dtb \ 362 orion5x-lacie-ethernet-disk-mini-v2.dtb \
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index e2156a583de7..43a536c08c9f 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -437,9 +437,9 @@
437 status = "okay"; 437 status = "okay";
438 pinctrl-names = "default"; 438 pinctrl-names = "default";
439 pinctrl-0 = <&nandflash_pins_s0>; 439 pinctrl-0 = <&nandflash_pins_s0>;
440 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 440 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
441 nand@0,0 { 441 nand@0,0 {
442 reg = <0 0 0>; /* CS0, offset 0 */ 442 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
443 ti,nand-ecc-opt = "bch8"; 443 ti,nand-ecc-opt = "bch8";
444 ti,elm-id = <&elm>; 444 ti,elm-id = <&elm>;
445 nand-bus-width = <8>; 445 nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index a1a0cc5eb35c..c0e1135256cc 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -126,10 +126,10 @@
126 pinctrl-names = "default"; 126 pinctrl-names = "default";
127 pinctrl-0 = <&nandflash_pins>; 127 pinctrl-0 = <&nandflash_pins>;
128 128
129 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 129 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
130 130
131 nand@0,0 { 131 nand@0,0 {
132 reg = <0 0 0>; /* CS0, offset 0 */ 132 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
133 nand-bus-width = <8>; 133 nand-bus-width = <8>;
134 ti,nand-ecc-opt = "bch8"; 134 ti,nand-ecc-opt = "bch8";
135 gpmc,device-width = <1>; 135 gpmc,device-width = <1>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 831810583823..62bf053d2cb8 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -204,6 +204,8 @@
204 reg = <0x44e09000 0x2000>; 204 reg = <0x44e09000 0x2000>;
205 interrupts = <72>; 205 interrupts = <72>;
206 status = "disabled"; 206 status = "disabled";
207 dmas = <&edma 26>, <&edma 27>;
208 dma-names = "tx", "rx";
207 }; 209 };
208 210
209 uart1: serial@48022000 { 211 uart1: serial@48022000 {
@@ -213,6 +215,8 @@
213 reg = <0x48022000 0x2000>; 215 reg = <0x48022000 0x2000>;
214 interrupts = <73>; 216 interrupts = <73>;
215 status = "disabled"; 217 status = "disabled";
218 dmas = <&edma 28>, <&edma 29>;
219 dma-names = "tx", "rx";
216 }; 220 };
217 221
218 uart2: serial@48024000 { 222 uart2: serial@48024000 {
@@ -222,6 +226,8 @@
222 reg = <0x48024000 0x2000>; 226 reg = <0x48024000 0x2000>;
223 interrupts = <74>; 227 interrupts = <74>;
224 status = "disabled"; 228 status = "disabled";
229 dmas = <&edma 30>, <&edma 31>;
230 dma-names = "tx", "rx";
225 }; 231 };
226 232
227 uart3: serial@481a6000 { 233 uart3: serial@481a6000 {
@@ -356,6 +362,7 @@
356 reg = <0x480C8000 0x200>; 362 reg = <0x480C8000 0x200>;
357 interrupts = <77>; 363 interrupts = <77>;
358 ti,hwmods = "mailbox"; 364 ti,hwmods = "mailbox";
365 #mbox-cells = <1>;
359 ti,mbox-num-users = <4>; 366 ti,mbox-num-users = <4>;
360 ti,mbox-num-fifos = <8>; 367 ti,mbox-num-fifos = <8>;
361 mbox_wkupm3: wkup_m3 { 368 mbox_wkupm3: wkup_m3 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 46660ffd2b65..4367f7550183 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -168,6 +168,7 @@
168 reg = <0x480C8000 0x200>; 168 reg = <0x480C8000 0x200>;
169 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 169 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
170 ti,hwmods = "mailbox"; 170 ti,hwmods = "mailbox";
171 #mbox-cells = <1>;
171 ti,mbox-num-users = <4>; 172 ti,mbox-num-users = <4>;
172 ti,mbox-num-fifos = <8>; 173 ti,mbox-num-fifos = <8>;
173 mbox_wkupm3: wkup_m3 { 174 mbox_wkupm3: wkup_m3 {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index ac3e4859935f..bb4cb8554b4a 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -438,9 +438,9 @@
438 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 438 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
439 pinctrl-names = "default"; 439 pinctrl-names = "default";
440 pinctrl-0 = <&nand_flash_x8>; 440 pinctrl-0 = <&nand_flash_x8>;
441 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 441 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
442 nand@0,0 { 442 nand@0,0 {
443 reg = <0 0 0>; /* CS0, offset 0 */ 443 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
444 ti,nand-ecc-opt = "bch16"; 444 ti,nand-ecc-opt = "bch16";
445 ti,elm-id = <&elm>; 445 ti,elm-id = <&elm>;
446 nand-bus-width = <8>; 446 nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
new file mode 100644
index 000000000000..49edbda68cd5
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -0,0 +1,405 @@
1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra74x.dtsi"
11#include <dt-bindings/clk/ti-dra7-atl.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15/ {
16 model = "TI AM5728 BeagleBoard-X15";
17 compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
18
19 aliases {
20 rtc0 = &mcp_rtc;
21 rtc1 = &tps659038_rtc;
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x80000000>;
27 };
28
29 vdd_3v3: fixedregulator-vdd_3v3 {
30 compatible = "regulator-fixed";
31 regulator-name = "vdd_3v3";
32 vin-supply = <&regen1>;
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 };
36
37 vtt_fixed: fixedregulator-vtt {
38 /* TPS51200 */
39 compatible = "regulator-fixed";
40 regulator-name = "vtt_fixed";
41 vin-supply = <&smps3_reg>;
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 regulator-always-on;
45 regulator-boot-on;
46 enable-active-high;
47 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
48 };
49
50 leds {
51 compatible = "gpio-leds";
52 pinctrl-names = "default";
53 pinctrl-0 = <&leds_pins_default>;
54
55 led@0 {
56 label = "beagle-x15:usr0";
57 gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
58 linux,default-trigger = "heartbeat";
59 default-state = "off";
60 };
61
62 led@1 {
63 label = "beagle-x15:usr1";
64 gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "cpu0";
66 default-state = "off";
67 };
68
69 led@2 {
70 label = "beagle-x15:usr2";
71 gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
72 linux,default-trigger = "mmc0";
73 default-state = "off";
74 };
75
76 led@3 {
77 label = "beagle-x15:usr3";
78 gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
79 linux,default-trigger = "ide-disk";
80 default-state = "off";
81 };
82 };
83};
84
85&dra7_pmx_core {
86 leds_pins_default: leds_pins_default {
87 pinctrl-single,pins = <
88 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
89 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
90 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
91 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
92 >;
93 };
94
95 i2c1_pins_default: i2c1_pins_default {
96 pinctrl-single,pins = <
97 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
98 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
99 >;
100 };
101
102 i2c3_pins_default: i2c3_pins_default {
103 pinctrl-single,pins = <
104 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
105 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
106 >;
107 };
108
109 uart3_pins_default: uart3_pins_default {
110 pinctrl-single,pins = <
111 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
112 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
113 >;
114 };
115
116 mmc1_pins_default: mmc1_pins_default {
117 pinctrl-single,pins = <
118 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
119 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
120 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
121 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
122 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
123 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
124 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
125 >;
126 };
127
128 mmc2_pins_default: mmc2_pins_default {
129 pinctrl-single,pins = <
130 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
131 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
132 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
133 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
134 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
135 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
136 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
137 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
138 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
139 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
140 >;
141 };
142
143 tps659038_pins_default: tps659038_pins_default {
144 pinctrl-single,pins = <
145 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
146 >;
147 };
148
149 tmp102_pins_default: tmp102_pins_default {
150 pinctrl-single,pins = <
151 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
152 >;
153 };
154
155 mcp79410_pins_default: mcp79410_pins_default {
156 pinctrl-single,pins = <
157 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
158 >;
159 };
160
161 usb1_pins: pinmux_usb1_pins {
162 pinctrl-single,pins = <
163 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
164 >;
165 };
166
167};
168
169&i2c1 {
170 status = "okay";
171 pinctrl-names = "default";
172 pinctrl-0 = <&i2c1_pins_default>;
173 clock-frequency = <400000>;
174
175 tps659038: tps659038@58 {
176 compatible = "ti,tps659038";
177 reg = <0x58>;
178 interrupt-parent = <&gpio1>;
179 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
180
181 pinctrl-names = "default";
182 pinctrl-0 = <&tps659038_pins_default>;
183
184 #interrupt-cells = <2>;
185 interrupt-controller;
186
187 ti,system-power-controller;
188
189 tps659038_pmic {
190 compatible = "ti,tps659038-pmic";
191
192 regulators {
193 smps12_reg: smps12 {
194 /* VDD_MPU */
195 regulator-name = "smps12";
196 regulator-min-microvolt = < 850000>;
197 regulator-max-microvolt = <1250000>;
198 regulator-always-on;
199 regulator-boot-on;
200 };
201
202 smps3_reg: smps3 {
203 /* VDD_DDR */
204 regulator-name = "smps3";
205 regulator-min-microvolt = <1350000>;
206 regulator-max-microvolt = <1350000>;
207 regulator-always-on;
208 regulator-boot-on;
209 };
210
211 smps45_reg: smps45 {
212 /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
213 regulator-name = "smps45";
214 regulator-min-microvolt = < 850000>;
215 regulator-max-microvolt = <1150000>;
216 regulator-always-on;
217 regulator-boot-on;
218 };
219
220 smps6_reg: smps6 {
221 /* VDD_CORE */
222 regulator-name = "smps6";
223 regulator-min-microvolt = <850000>;
224 regulator-max-microvolt = <1030000>;
225 regulator-always-on;
226 regulator-boot-on;
227 };
228
229 /* SMPS7 unused */
230
231 smps8_reg: smps8 {
232 /* VDD_1V8 */
233 regulator-name = "smps8";
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <1800000>;
236 regulator-always-on;
237 regulator-boot-on;
238 };
239
240 /* SMPS9 unused */
241
242 ldo1_reg: ldo1 {
243 /* VDD_SD */
244 regulator-name = "ldo1";
245 regulator-min-microvolt = <1800000>;
246 regulator-max-microvolt = <3300000>;
247 regulator-boot-on;
248 };
249
250 ldo2_reg: ldo2 {
251 /* VDD_SHV5 */
252 regulator-name = "ldo2";
253 regulator-min-microvolt = <3300000>;
254 regulator-max-microvolt = <3300000>;
255 regulator-always-on;
256 regulator-boot-on;
257 };
258
259 ldo3_reg: ldo3 {
260 /* VDDA_1V8_PHY */
261 regulator-name = "ldo3";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264 regulator-always-on;
265 regulator-boot-on;
266 };
267
268 ldo9_reg: ldo9 {
269 /* VDD_RTC */
270 regulator-name = "ldo9";
271 regulator-min-microvolt = <1050000>;
272 regulator-max-microvolt = <1050000>;
273 regulator-always-on;
274 regulator-boot-on;
275 };
276
277 ldoln_reg: ldoln {
278 /* VDDA_1V8_PLL */
279 regulator-name = "ldoln";
280 regulator-min-microvolt = <1800000>;
281 regulator-max-microvolt = <1800000>;
282 regulator-always-on;
283 regulator-boot-on;
284 };
285
286 ldousb_reg: ldousb {
287 /* VDDA_3V_USB: VDDA_USBHS33 */
288 regulator-name = "ldousb";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
291 regulator-boot-on;
292 };
293
294 regen1: regen1 {
295 /* VDD_3V3_ON */
296 regulator-name = "regen1";
297 regulator-boot-on;
298 regulator-always-on;
299 };
300 };
301 };
302
303 tps659038_rtc: tps659038_rtc {
304 compatible = "ti,palmas-rtc";
305 interrupt-parent = <&tps659038>;
306 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
307 wakeup-source;
308 };
309
310 tps659038_pwr_button: tps659038_pwr_button {
311 compatible = "ti,palmas-pwrbutton";
312 interrupt-parent = <&tps659038>;
313 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
314 wakeup-source;
315 ti,palmas-long-press-seconds = <12>;
316 };
317 };
318
319 tmp102: tmp102@48 {
320 compatible = "ti,tmp102";
321 reg = <0x48>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&tmp102_pins_default>;
324 interrupt-parent = <&gpio7>;
325 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
326 };
327};
328
329&i2c3 {
330 status = "okay";
331 pinctrl-names = "default";
332 pinctrl-0 = <&i2c3_pins_default>;
333 clock-frequency = <400000>;
334
335 mcp_rtc: rtc@6f {
336 compatible = "microchip,mcp7941x";
337 reg = <0x6f>;
338 interrupt-parent = <&gic>;
339 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
340
341 pinctrl-names = "default";
342 pinctrl-0 = <&mcp79410_pins_default>;
343
344 vcc-supply = <&vdd_3v3>;
345 wakeup-source;
346 };
347};
348
349&gpio7 {
350 ti,no-reset-on-init;
351 ti,no-idle-on-init;
352};
353
354&cpu0 {
355 cpu0-supply = <&smps12_reg>;
356 voltage-tolerance = <1>;
357};
358
359&uart3 {
360 status = "okay";
361 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
362 <&dra7_pmx_core 0x248>;
363
364 pinctrl-names = "default";
365 pinctrl-0 = <&uart3_pins_default>;
366};
367
368&mmc1 {
369 status = "okay";
370
371 pinctrl-names = "default";
372 pinctrl-0 = <&mmc1_pins_default>;
373
374 vmmc-supply = <&ldo1_reg>;
375 vmmc_aux-supply = <&vdd_3v3>;
376 pbias-supply = <&pbias_mmc_reg>;
377 bus-width = <4>;
378 cd-gpios = <&gpio6 27 0>; /* gpio 219 */
379};
380
381&mmc2 {
382 status = "okay";
383
384 pinctrl-names = "default";
385 pinctrl-0 = <&mmc2_pins_default>;
386
387 vmmc-supply = <&vdd_3v3>;
388 bus-width = <8>;
389 ti,non-removable;
390 cap-mmc-dual-data-rate;
391};
392
393&sata {
394 status = "okay";
395};
396
397&usb2_phy1 {
398 phy-supply = <&ldousb_reg>;
399};
400
401&usb1 {
402 dr_mode = "host";
403 pinctrl-names = "default";
404 pinctrl-0 = <&usb1_pins>;
405};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index c6ce6258434f..0d8a3bd0f00d 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -171,6 +171,86 @@
171 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ 171 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
172 >; 172 >;
173 }; 173 };
174
175 cpsw_default: cpsw_default {
176 pinctrl-single,pins = <
177 /* Slave 1 */
178 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
179 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
180 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
181 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
182 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
183 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
184 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
185 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
186 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
187 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
188 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
189 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
190
191 /* Slave 2 */
192 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
193 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
194 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
195 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
196 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
197 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
198 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
199 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
200 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
201 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
202 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
203 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
204 >;
205
206 };
207
208 cpsw_sleep: cpsw_sleep {
209 pinctrl-single,pins = <
210 /* Slave 1 */
211 0x250 (MUX_MODE15)
212 0x254 (MUX_MODE15)
213 0x258 (MUX_MODE15)
214 0x25c (MUX_MODE15)
215 0x260 (MUX_MODE15)
216 0x264 (MUX_MODE15)
217 0x268 (MUX_MODE15)
218 0x26c (MUX_MODE15)
219 0x270 (MUX_MODE15)
220 0x274 (MUX_MODE15)
221 0x278 (MUX_MODE15)
222 0x27c (MUX_MODE15)
223
224 /* Slave 2 */
225 0x198 (MUX_MODE15)
226 0x19c (MUX_MODE15)
227 0x1a0 (MUX_MODE15)
228 0x1a4 (MUX_MODE15)
229 0x1a8 (MUX_MODE15)
230 0x1ac (MUX_MODE15)
231 0x1b0 (MUX_MODE15)
232 0x1b4 (MUX_MODE15)
233 0x1b8 (MUX_MODE15)
234 0x1bc (MUX_MODE15)
235 0x1c0 (MUX_MODE15)
236 0x1c4 (MUX_MODE15)
237 >;
238 };
239
240 davinci_mdio_default: davinci_mdio_default {
241 pinctrl-single,pins = <
242 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
243 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
244 >;
245 };
246
247 davinci_mdio_sleep: davinci_mdio_sleep {
248 pinctrl-single,pins = <
249 0x23c (MUX_MODE15)
250 0x240 (MUX_MODE15)
251 >;
252 };
253
174}; 254};
175 255
176&i2c1 { 256&i2c1 {
@@ -201,6 +281,7 @@
201 regulator-name = "smps45"; 281 regulator-name = "smps45";
202 regulator-min-microvolt = < 850000>; 282 regulator-min-microvolt = < 850000>;
203 regulator-max-microvolt = <1150000>; 283 regulator-max-microvolt = <1150000>;
284 regulator-always-on;
204 regulator-boot-on; 285 regulator-boot-on;
205 }; 286 };
206 287
@@ -209,6 +290,7 @@
209 regulator-name = "smps6"; 290 regulator-name = "smps6";
210 regulator-min-microvolt = <850000>; 291 regulator-min-microvolt = <850000>;
211 regulator-max-microvolt = <12500000>; 292 regulator-max-microvolt = <12500000>;
293 regulator-always-on;
212 regulator-boot-on; 294 regulator-boot-on;
213 }; 295 };
214 296
@@ -226,6 +308,7 @@
226 regulator-name = "smps8"; 308 regulator-name = "smps8";
227 regulator-min-microvolt = < 850000>; 309 regulator-min-microvolt = < 850000>;
228 regulator-max-microvolt = <1250000>; 310 regulator-max-microvolt = <1250000>;
311 regulator-always-on;
229 regulator-boot-on; 312 regulator-boot-on;
230 }; 313 };
231 314
@@ -252,6 +335,7 @@
252 regulator-name = "ldo2"; 335 regulator-name = "ldo2";
253 regulator-min-microvolt = <3300000>; 336 regulator-min-microvolt = <3300000>;
254 regulator-max-microvolt = <3300000>; 337 regulator-max-microvolt = <3300000>;
338 regulator-always-on;
255 regulator-boot-on; 339 regulator-boot-on;
256 }; 340 };
257 341
@@ -269,6 +353,7 @@
269 regulator-name = "ldo9"; 353 regulator-name = "ldo9";
270 regulator-min-microvolt = <1050000>; 354 regulator-min-microvolt = <1050000>;
271 regulator-max-microvolt = <1050000>; 355 regulator-max-microvolt = <1050000>;
356 regulator-always-on;
272 regulator-boot-on; 357 regulator-boot-on;
273 }; 358 };
274 359
@@ -528,3 +613,29 @@
528 ti,no-reset-on-init; 613 ti,no-reset-on-init;
529 ti,no-idle-on-init; 614 ti,no-idle-on-init;
530}; 615};
616
617&mac {
618 status = "okay";
619 pinctrl-names = "default", "sleep";
620 pinctrl-0 = <&cpsw_default>;
621 pinctrl-1 = <&cpsw_sleep>;
622 dual_emac;
623};
624
625&cpsw_emac0 {
626 phy_id = <&davinci_mdio>, <2>;
627 phy-mode = "rgmii";
628 dual_emac_res_vlan = <1>;
629};
630
631&cpsw_emac1 {
632 phy_id = <&davinci_mdio>, <3>;
633 phy-mode = "rgmii";
634 dual_emac_res_vlan = <2>;
635};
636
637&davinci_mdio {
638 pinctrl-names = "default", "sleep";
639 pinctrl-0 = <&davinci_mdio_default>;
640 pinctrl-1 = <&davinci_mdio_sleep>;
641};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9cc98436a982..9cd99b931302 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,12 @@
34 serial3 = &uart4; 34 serial3 = &uart4;
35 serial4 = &uart5; 35 serial4 = &uart5;
36 serial5 = &uart6; 36 serial5 = &uart6;
37 serial6 = &uart7;
38 serial7 = &uart8;
39 serial8 = &uart9;
40 serial9 = &uart10;
41 ethernet0 = &cpsw_emac0;
42 ethernet1 = &cpsw_emac1;
37 }; 43 };
38 44
39 timer { 45 timer {
@@ -335,6 +341,8 @@
335 ti,hwmods = "uart1"; 341 ti,hwmods = "uart1";
336 clock-frequency = <48000000>; 342 clock-frequency = <48000000>;
337 status = "disabled"; 343 status = "disabled";
344 dmas = <&sdma 49>, <&sdma 50>;
345 dma-names = "tx", "rx";
338 }; 346 };
339 347
340 uart2: serial@4806c000 { 348 uart2: serial@4806c000 {
@@ -344,6 +352,8 @@
344 ti,hwmods = "uart2"; 352 ti,hwmods = "uart2";
345 clock-frequency = <48000000>; 353 clock-frequency = <48000000>;
346 status = "disabled"; 354 status = "disabled";
355 dmas = <&sdma 51>, <&sdma 52>;
356 dma-names = "tx", "rx";
347 }; 357 };
348 358
349 uart3: serial@48020000 { 359 uart3: serial@48020000 {
@@ -353,6 +363,8 @@
353 ti,hwmods = "uart3"; 363 ti,hwmods = "uart3";
354 clock-frequency = <48000000>; 364 clock-frequency = <48000000>;
355 status = "disabled"; 365 status = "disabled";
366 dmas = <&sdma 53>, <&sdma 54>;
367 dma-names = "tx", "rx";
356 }; 368 };
357 369
358 uart4: serial@4806e000 { 370 uart4: serial@4806e000 {
@@ -362,6 +374,8 @@
362 ti,hwmods = "uart4"; 374 ti,hwmods = "uart4";
363 clock-frequency = <48000000>; 375 clock-frequency = <48000000>;
364 status = "disabled"; 376 status = "disabled";
377 dmas = <&sdma 55>, <&sdma 56>;
378 dma-names = "tx", "rx";
365 }; 379 };
366 380
367 uart5: serial@48066000 { 381 uart5: serial@48066000 {
@@ -371,6 +385,8 @@
371 ti,hwmods = "uart5"; 385 ti,hwmods = "uart5";
372 clock-frequency = <48000000>; 386 clock-frequency = <48000000>;
373 status = "disabled"; 387 status = "disabled";
388 dmas = <&sdma 63>, <&sdma 64>;
389 dma-names = "tx", "rx";
374 }; 390 };
375 391
376 uart6: serial@48068000 { 392 uart6: serial@48068000 {
@@ -380,6 +396,8 @@
380 ti,hwmods = "uart6"; 396 ti,hwmods = "uart6";
381 clock-frequency = <48000000>; 397 clock-frequency = <48000000>;
382 status = "disabled"; 398 status = "disabled";
399 dmas = <&sdma 79>, <&sdma 80>;
400 dma-names = "tx", "rx";
383 }; 401 };
384 402
385 uart7: serial@48420000 { 403 uart7: serial@48420000 {
@@ -421,7 +439,11 @@
421 mailbox1: mailbox@4a0f4000 { 439 mailbox1: mailbox@4a0f4000 {
422 compatible = "ti,omap4-mailbox"; 440 compatible = "ti,omap4-mailbox";
423 reg = <0x4a0f4000 0x200>; 441 reg = <0x4a0f4000 0x200>;
442 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
424 ti,hwmods = "mailbox1"; 445 ti,hwmods = "mailbox1";
446 #mbox-cells = <1>;
425 ti,mbox-num-users = <3>; 447 ti,mbox-num-users = <3>;
426 ti,mbox-num-fifos = <8>; 448 ti,mbox-num-fifos = <8>;
427 status = "disabled"; 449 status = "disabled";
@@ -430,7 +452,12 @@
430 mailbox2: mailbox@4883a000 { 452 mailbox2: mailbox@4883a000 {
431 compatible = "ti,omap4-mailbox"; 453 compatible = "ti,omap4-mailbox";
432 reg = <0x4883a000 0x200>; 454 reg = <0x4883a000 0x200>;
455 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
433 ti,hwmods = "mailbox2"; 459 ti,hwmods = "mailbox2";
460 #mbox-cells = <1>;
434 ti,mbox-num-users = <4>; 461 ti,mbox-num-users = <4>;
435 ti,mbox-num-fifos = <12>; 462 ti,mbox-num-fifos = <12>;
436 status = "disabled"; 463 status = "disabled";
@@ -439,7 +466,12 @@
439 mailbox3: mailbox@4883c000 { 466 mailbox3: mailbox@4883c000 {
440 compatible = "ti,omap4-mailbox"; 467 compatible = "ti,omap4-mailbox";
441 reg = <0x4883c000 0x200>; 468 reg = <0x4883c000 0x200>;
469 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
442 ti,hwmods = "mailbox3"; 473 ti,hwmods = "mailbox3";
474 #mbox-cells = <1>;
443 ti,mbox-num-users = <4>; 475 ti,mbox-num-users = <4>;
444 ti,mbox-num-fifos = <12>; 476 ti,mbox-num-fifos = <12>;
445 status = "disabled"; 477 status = "disabled";
@@ -448,7 +480,12 @@
448 mailbox4: mailbox@4883e000 { 480 mailbox4: mailbox@4883e000 {
449 compatible = "ti,omap4-mailbox"; 481 compatible = "ti,omap4-mailbox";
450 reg = <0x4883e000 0x200>; 482 reg = <0x4883e000 0x200>;
483 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
451 ti,hwmods = "mailbox4"; 487 ti,hwmods = "mailbox4";
488 #mbox-cells = <1>;
452 ti,mbox-num-users = <4>; 489 ti,mbox-num-users = <4>;
453 ti,mbox-num-fifos = <12>; 490 ti,mbox-num-fifos = <12>;
454 status = "disabled"; 491 status = "disabled";
@@ -457,7 +494,12 @@
457 mailbox5: mailbox@48840000 { 494 mailbox5: mailbox@48840000 {
458 compatible = "ti,omap4-mailbox"; 495 compatible = "ti,omap4-mailbox";
459 reg = <0x48840000 0x200>; 496 reg = <0x48840000 0x200>;
497 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
460 ti,hwmods = "mailbox5"; 501 ti,hwmods = "mailbox5";
502 #mbox-cells = <1>;
461 ti,mbox-num-users = <4>; 503 ti,mbox-num-users = <4>;
462 ti,mbox-num-fifos = <12>; 504 ti,mbox-num-fifos = <12>;
463 status = "disabled"; 505 status = "disabled";
@@ -466,7 +508,12 @@
466 mailbox6: mailbox@48842000 { 508 mailbox6: mailbox@48842000 {
467 compatible = "ti,omap4-mailbox"; 509 compatible = "ti,omap4-mailbox";
468 reg = <0x48842000 0x200>; 510 reg = <0x48842000 0x200>;
511 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "mailbox6"; 515 ti,hwmods = "mailbox6";
516 #mbox-cells = <1>;
470 ti,mbox-num-users = <4>; 517 ti,mbox-num-users = <4>;
471 ti,mbox-num-fifos = <12>; 518 ti,mbox-num-fifos = <12>;
472 status = "disabled"; 519 status = "disabled";
@@ -475,7 +522,12 @@
475 mailbox7: mailbox@48844000 { 522 mailbox7: mailbox@48844000 {
476 compatible = "ti,omap4-mailbox"; 523 compatible = "ti,omap4-mailbox";
477 reg = <0x48844000 0x200>; 524 reg = <0x48844000 0x200>;
525 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
478 ti,hwmods = "mailbox7"; 529 ti,hwmods = "mailbox7";
530 #mbox-cells = <1>;
479 ti,mbox-num-users = <4>; 531 ti,mbox-num-users = <4>;
480 ti,mbox-num-fifos = <12>; 532 ti,mbox-num-fifos = <12>;
481 status = "disabled"; 533 status = "disabled";
@@ -484,7 +536,12 @@
484 mailbox8: mailbox@48846000 { 536 mailbox8: mailbox@48846000 {
485 compatible = "ti,omap4-mailbox"; 537 compatible = "ti,omap4-mailbox";
486 reg = <0x48846000 0x200>; 538 reg = <0x48846000 0x200>;
539 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "mailbox8"; 543 ti,hwmods = "mailbox8";
544 #mbox-cells = <1>;
488 ti,mbox-num-users = <4>; 545 ti,mbox-num-users = <4>;
489 ti,mbox-num-fifos = <12>; 546 ti,mbox-num-fifos = <12>;
490 status = "disabled"; 547 status = "disabled";
@@ -493,7 +550,12 @@
493 mailbox9: mailbox@4885e000 { 550 mailbox9: mailbox@4885e000 {
494 compatible = "ti,omap4-mailbox"; 551 compatible = "ti,omap4-mailbox";
495 reg = <0x4885e000 0x200>; 552 reg = <0x4885e000 0x200>;
553 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
496 ti,hwmods = "mailbox9"; 557 ti,hwmods = "mailbox9";
558 #mbox-cells = <1>;
497 ti,mbox-num-users = <4>; 559 ti,mbox-num-users = <4>;
498 ti,mbox-num-fifos = <12>; 560 ti,mbox-num-fifos = <12>;
499 status = "disabled"; 561 status = "disabled";
@@ -502,7 +564,12 @@
502 mailbox10: mailbox@48860000 { 564 mailbox10: mailbox@48860000 {
503 compatible = "ti,omap4-mailbox"; 565 compatible = "ti,omap4-mailbox";
504 reg = <0x48860000 0x200>; 566 reg = <0x48860000 0x200>;
567 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "mailbox10"; 571 ti,hwmods = "mailbox10";
572 #mbox-cells = <1>;
506 ti,mbox-num-users = <4>; 573 ti,mbox-num-users = <4>;
507 ti,mbox-num-fifos = <12>; 574 ti,mbox-num-fifos = <12>;
508 status = "disabled"; 575 status = "disabled";
@@ -511,7 +578,12 @@
511 mailbox11: mailbox@48862000 { 578 mailbox11: mailbox@48862000 {
512 compatible = "ti,omap4-mailbox"; 579 compatible = "ti,omap4-mailbox";
513 reg = <0x48862000 0x200>; 580 reg = <0x48862000 0x200>;
581 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
514 ti,hwmods = "mailbox11"; 585 ti,hwmods = "mailbox11";
586 #mbox-cells = <1>;
515 ti,mbox-num-users = <4>; 587 ti,mbox-num-users = <4>;
516 ti,mbox-num-fifos = <12>; 588 ti,mbox-num-fifos = <12>;
517 status = "disabled"; 589 status = "disabled";
@@ -520,7 +592,12 @@
520 mailbox12: mailbox@48864000 { 592 mailbox12: mailbox@48864000 {
521 compatible = "ti,omap4-mailbox"; 593 compatible = "ti,omap4-mailbox";
522 reg = <0x48864000 0x200>; 594 reg = <0x48864000 0x200>;
595 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
523 ti,hwmods = "mailbox12"; 599 ti,hwmods = "mailbox12";
600 #mbox-cells = <1>;
524 ti,mbox-num-users = <4>; 601 ti,mbox-num-users = <4>;
525 ti,mbox-num-fifos = <12>; 602 ti,mbox-num-fifos = <12>;
526 status = "disabled"; 603 status = "disabled";
@@ -529,7 +606,12 @@
529 mailbox13: mailbox@48802000 { 606 mailbox13: mailbox@48802000 {
530 compatible = "ti,omap4-mailbox"; 607 compatible = "ti,omap4-mailbox";
531 reg = <0x48802000 0x200>; 608 reg = <0x48802000 0x200>;
609 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
532 ti,hwmods = "mailbox13"; 613 ti,hwmods = "mailbox13";
614 #mbox-cells = <1>;
533 ti,mbox-num-users = <4>; 615 ti,mbox-num-users = <4>;
534 ti,mbox-num-fifos = <12>; 616 ti,mbox-num-fifos = <12>;
535 status = "disabled"; 617 status = "disabled";
@@ -1141,7 +1223,7 @@
1141 }; 1223 };
1142 }; 1224 };
1143 1225
1144 omap_dwc3_1@48880000 { 1226 omap_dwc3_1: omap_dwc3_1@48880000 {
1145 compatible = "ti,dwc3"; 1227 compatible = "ti,dwc3";
1146 ti,hwmods = "usb_otg_ss1"; 1228 ti,hwmods = "usb_otg_ss1";
1147 reg = <0x48880000 0x10000>; 1229 reg = <0x48880000 0x10000>;
@@ -1162,7 +1244,7 @@
1162 }; 1244 };
1163 }; 1245 };
1164 1246
1165 omap_dwc3_2@488c0000 { 1247 omap_dwc3_2: omap_dwc3_2@488c0000 {
1166 compatible = "ti,dwc3"; 1248 compatible = "ti,dwc3";
1167 ti,hwmods = "usb_otg_ss2"; 1249 ti,hwmods = "usb_otg_ss2";
1168 reg = <0x488c0000 0x10000>; 1250 reg = <0x488c0000 0x10000>;
@@ -1184,7 +1266,7 @@
1184 }; 1266 };
1185 1267
1186 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1268 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1187 omap_dwc3_3@48900000 { 1269 omap_dwc3_3: omap_dwc3_3@48900000 {
1188 compatible = "ti,dwc3"; 1270 compatible = "ti,dwc3";
1189 ti,hwmods = "usb_otg_ss3"; 1271 ti,hwmods = "usb_otg_ss3";
1190 reg = <0x48900000 0x10000>; 1272 reg = <0x48900000 0x10000>;
@@ -1204,26 +1286,6 @@
1204 }; 1286 };
1205 }; 1287 };
1206 1288
1207 omap_dwc3_4@48940000 {
1208 compatible = "ti,dwc3";
1209 ti,hwmods = "usb_otg_ss4";
1210 reg = <0x48940000 0x10000>;
1211 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1212 #address-cells = <1>;
1213 #size-cells = <1>;
1214 utmi-mode = <2>;
1215 ranges;
1216 status = "disabled";
1217 usb4: usb@48950000 {
1218 compatible = "snps,dwc3";
1219 reg = <0x48950000 0x17000>;
1220 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1221 tx-fifo-resize;
1222 maximum-speed = "high-speed";
1223 dr_mode = "otg";
1224 };
1225 };
1226
1227 elm: elm@48078000 { 1289 elm: elm@48078000 {
1228 compatible = "ti,am3352-elm"; 1290 compatible = "ti,am3352-elm";
1229 reg = <0x48078000 0xfc0>; /* device IO registers */ 1291 reg = <0x48078000 0xfc0>; /* device IO registers */
@@ -1265,6 +1327,65 @@
1265 ti,irqs-skip = <10 133 139 140>; 1327 ti,irqs-skip = <10 133 139 140>;
1266 ti,irqs-safe-map = <0>; 1328 ti,irqs-safe-map = <0>;
1267 }; 1329 };
1330
1331 mac: ethernet@4a100000 {
1332 compatible = "ti,cpsw";
1333 ti,hwmods = "gmac";
1334 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1335 clock-names = "fck", "cpts";
1336 cpdma_channels = <8>;
1337 ale_entries = <1024>;
1338 bd_ram_size = <0x2000>;
1339 no_bd_ram = <0>;
1340 rx_descs = <64>;
1341 mac_control = <0x20>;
1342 slaves = <2>;
1343 active_slave = <0>;
1344 cpts_clock_mult = <0x80000000>;
1345 cpts_clock_shift = <29>;
1346 reg = <0x48484000 0x1000
1347 0x48485200 0x2E00>;
1348 #address-cells = <1>;
1349 #size-cells = <1>;
1350 /*
1351 * rx_thresh_pend
1352 * rx_pend
1353 * tx_pend
1354 * misc_pend
1355 */
1356 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1360 ranges;
1361 status = "disabled";
1362
1363 davinci_mdio: mdio@48485000 {
1364 compatible = "ti,davinci_mdio";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1367 ti,hwmods = "davinci_mdio";
1368 bus_freq = <1000000>;
1369 reg = <0x48485000 0x100>;
1370 };
1371
1372 cpsw_emac0: slave@48480200 {
1373 /* Filled in by U-Boot */
1374 mac-address = [ 00 00 00 00 00 00 ];
1375 };
1376
1377 cpsw_emac1: slave@48480300 {
1378 /* Filled in by U-Boot */
1379 mac-address = [ 00 00 00 00 00 00 ];
1380 };
1381
1382 phy_sel: cpsw-phy-sel@4a002554 {
1383 compatible = "ti,dra7xx-cpsw-phy-sel";
1384 reg= <0x4a002554 0x4>;
1385 reg-names = "gmii-sel";
1386 };
1387 };
1388
1268 }; 1389 };
1269}; 1390};
1270 1391
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 41074288adfa..abbaaa782f88 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -17,6 +17,13 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1024 MB */ 18 reg = <0x80000000 0x40000000>; /* 1024 MB */
19 }; 19 };
20
21 evm_3v3: fixedregulator-evm_3v3 {
22 compatible = "regulator-fixed";
23 regulator-name = "evm_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
20}; 27};
21 28
22&dra7_pmx_core { 29&dra7_pmx_core {
@@ -26,6 +33,78 @@
26 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ 33 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
27 >; 34 >;
28 }; 35 };
36
37 nand_default: nand_default {
38 pinctrl-single,pins = <
39 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
40 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
41 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
42 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
43 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
44 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
45 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
46 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
47 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
48 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
49 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
50 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
51 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
52 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
53 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
54 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
55 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
56 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
57 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
58 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
59 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
60 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
61 >;
62 };
63
64 usb1_pins: pinmux_usb1_pins {
65 pinctrl-single,pins = <
66 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
67 >;
68 };
69
70 usb2_pins: pinmux_usb2_pins {
71 pinctrl-single,pins = <
72 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
73 >;
74 };
75
76 tps65917_pins_default: tps65917_pins_default {
77 pinctrl-single,pins = <
78 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
79 >;
80 };
81
82 mmc1_pins_default: mmc1_pins_default {
83 pinctrl-single,pins = <
84 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
85 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
86 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
87 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
88 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
89 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
90 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
91 >;
92 };
93
94 mmc2_pins_default: mmc2_pins_default {
95 pinctrl-single,pins = <
96 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
97 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
98 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
99 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
100 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
101 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
102 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
103 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
104 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
105 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
106 >;
107 };
29}; 108};
30 109
31&i2c1 { 110&i2c1 {
@@ -38,6 +117,9 @@
38 compatible = "ti,tps65917"; 117 compatible = "ti,tps65917";
39 reg = <0x58>; 118 reg = <0x58>;
40 119
120 pinctrl-names = "default";
121 pinctrl-0 = <&tps65917_pins_default>;
122
41 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 123 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
42 interrupt-parent = <&gic>; 124 interrupt-parent = <&gic>;
43 interrupt-controller; 125 interrupt-controller;
@@ -136,9 +218,223 @@
136 }; 218 };
137 }; 219 };
138 }; 220 };
221
222 tps65917_power_button {
223 compatible = "ti,palmas-pwrbutton";
224 interrupt-parent = <&tps65917>;
225 interrupts = <1 IRQ_TYPE_NONE>;
226 wakeup-source;
227 ti,palmas-long-press-seconds = <6>;
228 };
139 }; 229 };
140}; 230};
141 231
142&uart1 { 232&uart1 {
143 status = "okay"; 233 status = "okay";
144}; 234};
235
236&elm {
237 status = "okay";
238};
239
240&gpmc {
241 status = "okay";
242 pinctrl-names = "default";
243 pinctrl-0 = <&nand_default>;
244 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
245 nand@0,0 {
246 /* To use NAND, DIP switch SW5 must be set like so:
247 * SW5.1 (NAND_SELn) = ON (LOW)
248 * SW5.9 (GPMC_WPN) = OFF (HIGH)
249 */
250 reg = <0 0 4>; /* device IO registers */
251 ti,nand-ecc-opt = "bch8";
252 ti,elm-id = <&elm>;
253 nand-bus-width = <16>;
254 gpmc,device-width = <2>;
255 gpmc,sync-clk-ps = <0>;
256 gpmc,cs-on-ns = <0>;
257 gpmc,cs-rd-off-ns = <80>;
258 gpmc,cs-wr-off-ns = <80>;
259 gpmc,adv-on-ns = <0>;
260 gpmc,adv-rd-off-ns = <60>;
261 gpmc,adv-wr-off-ns = <60>;
262 gpmc,we-on-ns = <10>;
263 gpmc,we-off-ns = <50>;
264 gpmc,oe-on-ns = <4>;
265 gpmc,oe-off-ns = <40>;
266 gpmc,access-ns = <40>;
267 gpmc,wr-access-ns = <80>;
268 gpmc,rd-cycle-ns = <80>;
269 gpmc,wr-cycle-ns = <80>;
270 gpmc,bus-turnaround-ns = <0>;
271 gpmc,cycle2cycle-delay-ns = <0>;
272 gpmc,clk-activation-ns = <0>;
273 gpmc,wait-monitoring-ns = <0>;
274 gpmc,wr-data-mux-bus-ns = <0>;
275 /* MTD partition table */
276 /* All SPL-* partitions are sized to minimal length
277 * which can be independently programmable. For
278 * NAND flash this is equal to size of erase-block */
279 #address-cells = <1>;
280 #size-cells = <1>;
281 partition@0 {
282 label = "NAND.SPL";
283 reg = <0x00000000 0x000020000>;
284 };
285 partition@1 {
286 label = "NAND.SPL.backup1";
287 reg = <0x00020000 0x00020000>;
288 };
289 partition@2 {
290 label = "NAND.SPL.backup2";
291 reg = <0x00040000 0x00020000>;
292 };
293 partition@3 {
294 label = "NAND.SPL.backup3";
295 reg = <0x00060000 0x00020000>;
296 };
297 partition@4 {
298 label = "NAND.u-boot-spl-os";
299 reg = <0x00080000 0x00040000>;
300 };
301 partition@5 {
302 label = "NAND.u-boot";
303 reg = <0x000c0000 0x00100000>;
304 };
305 partition@6 {
306 label = "NAND.u-boot-env";
307 reg = <0x001c0000 0x00020000>;
308 };
309 partition@7 {
310 label = "NAND.u-boot-env.backup1";
311 reg = <0x001e0000 0x00020000>;
312 };
313 partition@8 {
314 label = "NAND.kernel";
315 reg = <0x00200000 0x00800000>;
316 };
317 partition@9 {
318 label = "NAND.file-system";
319 reg = <0x00a00000 0x0f600000>;
320 };
321 };
322};
323
324&usb2_phy1 {
325 phy-supply = <&ldo4_reg>;
326};
327
328&usb2_phy2 {
329 phy-supply = <&ldo4_reg>;
330};
331
332&usb1 {
333 dr_mode = "peripheral";
334 pinctrl-names = "default";
335 pinctrl-0 = <&usb1_pins>;
336};
337
338&usb2 {
339 dr_mode = "host";
340 pinctrl-names = "default";
341 pinctrl-0 = <&usb2_pins>;
342};
343
344&mmc1 {
345 status = "okay";
346 pinctrl-names = "default";
347 pinctrl-0 = <&mmc1_pins_default>;
348
349 vmmc-supply = <&ldo1_reg>;
350 bus-width = <4>;
351 /*
352 * SDCD signal is not being used here - using the fact that GPIO mode
353 * is a viable alternative
354 */
355 cd-gpios = <&gpio6 27 0>;
356};
357
358&mmc2 {
359 /* SW5-3 in ON position */
360 status = "okay";
361 pinctrl-names = "default";
362 pinctrl-0 = <&mmc2_pins_default>;
363
364 vmmc-supply = <&evm_3v3>;
365 bus-width = <8>;
366 ti,non-removable;
367};
368
369&dra7_pmx_core {
370 cpsw_default: cpsw_default {
371 pinctrl-single,pins = <
372 /* Slave 2 */
373 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
374 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
375 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
376 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
377 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
378 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
379 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
380 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
381 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
382 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
383 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
384 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
385 >;
386
387 };
388
389 cpsw_sleep: cpsw_sleep {
390 pinctrl-single,pins = <
391 /* Slave 2 */
392 0x198 (MUX_MODE15)
393 0x19c (MUX_MODE15)
394 0x1a0 (MUX_MODE15)
395 0x1a4 (MUX_MODE15)
396 0x1a8 (MUX_MODE15)
397 0x1ac (MUX_MODE15)
398 0x1b0 (MUX_MODE15)
399 0x1b4 (MUX_MODE15)
400 0x1b8 (MUX_MODE15)
401 0x1bc (MUX_MODE15)
402 0x1c0 (MUX_MODE15)
403 0x1c4 (MUX_MODE15)
404 >;
405 };
406
407 davinci_mdio_default: davinci_mdio_default {
408 pinctrl-single,pins = <
409 /* MDIO */
410 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
411 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
412 >;
413 };
414
415 davinci_mdio_sleep: davinci_mdio_sleep {
416 pinctrl-single,pins = <
417 0x23c (MUX_MODE15)
418 0x240 (MUX_MODE15)
419 >;
420 };
421};
422
423&mac {
424 status = "okay";
425 pinctrl-names = "default", "sleep";
426 pinctrl-0 = <&cpsw_default>;
427 pinctrl-1 = <&cpsw_sleep>;
428};
429
430&cpsw_emac1 {
431 phy_id = <&davinci_mdio>, <3>;
432 phy-mode = "rgmii";
433};
434
435&davinci_mdio {
436 pinctrl-names = "default", "sleep";
437 pinctrl-0 = <&davinci_mdio_default>;
438 pinctrl-1 = <&davinci_mdio_sleep>;
439 active_slave = <1>;
440};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 3be544c4891f..10173fab1a15 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -44,4 +44,26 @@
44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>, 44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>; 45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
46 }; 46 };
47
48 ocp {
49 omap_dwc3_4: omap_dwc3_4@48940000 {
50 compatible = "ti,dwc3";
51 ti,hwmods = "usb_otg_ss4";
52 reg = <0x48940000 0x10000>;
53 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 utmi-mode = <2>;
57 ranges;
58 status = "disabled";
59 usb4: usb@48950000 {
60 compatible = "snps,dwc3";
61 reg = <0x48950000 0x17000>;
62 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
63 tx-fifo-resize;
64 maximum-speed = "high-speed";
65 dr_mode = "otg";
66 };
67 };
68 };
47}; 69};
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index 521c587acaee..445fafc73254 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -23,24 +23,29 @@
23 ethernet@gpmc { 23 ethernet@gpmc {
24 compatible = "smsc,lan9221", "smsc,lan9115"; 24 compatible = "smsc,lan9221", "smsc,lan9115";
25 bank-width = <2>; 25 bank-width = <2>;
26 gpmc,mux-add-data; 26 gpmc,device-width = <1>;
27 gpmc,cs-on-ns = <1>; 27 gpmc,cycle2cycle-samecsen = <1>;
28 gpmc,cs-rd-off-ns = <180>; 28 gpmc,cycle2cycle-diffcsen = <1>;
29 gpmc,cs-wr-off-ns = <180>; 29 gpmc,cs-on-ns = <5>;
30 gpmc,adv-rd-off-ns = <18>; 30 gpmc,cs-rd-off-ns = <150>;
31 gpmc,adv-wr-off-ns = <48>; 31 gpmc,cs-wr-off-ns = <150>;
32 gpmc,oe-on-ns = <54>; 32 gpmc,adv-on-ns = <0>;
33 gpmc,oe-off-ns = <168>; 33 gpmc,adv-rd-off-ns = <15>;
34 gpmc,we-on-ns = <54>; 34 gpmc,adv-wr-off-ns = <40>;
35 gpmc,we-off-ns = <168>; 35 gpmc,oe-on-ns = <45>;
36 gpmc,rd-cycle-ns = <186>; 36 gpmc,oe-off-ns = <140>;
37 gpmc,wr-cycle-ns = <186>; 37 gpmc,we-on-ns = <45>;
38 gpmc,access-ns = <144>; 38 gpmc,we-off-ns = <140>;
39 gpmc,page-burst-access-ns = <24>; 39 gpmc,rd-cycle-ns = <155>;
40 gpmc,bus-turnaround-ns = <90>; 40 gpmc,wr-cycle-ns = <155>;
41 gpmc,cycle2cycle-delay-ns = <90>; 41 gpmc,access-ns = <120>;
42 gpmc,cycle2cycle-samecsen; 42 gpmc,page-burst-access-ns = <20>;
43 gpmc,cycle2cycle-diffcsen; 43 gpmc,bus-turnaround-ns = <75>;
44 gpmc,cycle2cycle-delay-ns = <75>;
45 gpmc,wait-monitoring-ns = <0>;
46 gpmc,clk-activation-ns = <0>;
47 gpmc,wr-data-mux-bus-ns = <0>;
48 gpmc,wr-access-ns = <0>;
44 vddvario-supply = <&vddvario>; 49 vddvario-supply = <&vddvario>;
45 vdd33a-supply = <&vdd33a>; 50 vdd33a-supply = <&vdd33a>;
46 reg-io-width = <4>; 51 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi
index 68221fab978d..46ef3e443861 100644
--- a/arch/arm/boot/dts/omap-zoom-common.dtsi
+++ b/arch/arm/boot/dts/omap-zoom-common.dtsi
@@ -5,7 +5,7 @@
5#include "omap-gpmc-smsc911x.dtsi" 5#include "omap-gpmc-smsc911x.dtsi"
6 6
7&gpmc { 7&gpmc {
8 ranges = <3 0 0x10000000 0x00000400>, 8 ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */
9 <7 0 0x2c000000 0x01000000>; 9 <7 0 0x2c000000 0x01000000>;
10 10
11 /* 11 /*
@@ -15,7 +15,65 @@
15 */ 15 */
16 uart@3,0 { 16 uart@3,0 {
17 compatible = "ns16550a"; 17 compatible = "ns16550a";
18 reg = <3 0 0x100>; 18 reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
19 bank-width = <2>;
20 reg-shift = <1>;
21 reg-io-width = <1>;
22 interrupt-parent = <&gpio4>;
23 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
24 clock-frequency = <1843200>;
25 current-speed = <115200>;
26 gpmc,mux-add-data = <0>;
27 gpmc,device-width = <1>;
28 gpmc,wait-pin = <1>;
29 gpmc,cycle2cycle-samecsen = <1>;
30 gpmc,cycle2cycle-diffcsen = <1>;
31 gpmc,cs-on-ns = <5>;
32 gpmc,cs-rd-off-ns = <155>;
33 gpmc,cs-wr-off-ns = <155>;
34 gpmc,adv-on-ns = <15>;
35 gpmc,adv-rd-off-ns = <40>;
36 gpmc,adv-wr-off-ns = <40>;
37 gpmc,oe-on-ns = <45>;
38 gpmc,oe-off-ns = <145>;
39 gpmc,we-on-ns = <45>;
40 gpmc,we-off-ns = <145>;
41 gpmc,rd-cycle-ns = <155>;
42 gpmc,wr-cycle-ns = <155>;
43 gpmc,access-ns = <145>;
44 gpmc,page-burst-access-ns = <20>;
45 gpmc,bus-turnaround-ns = <20>;
46 gpmc,cycle2cycle-delay-ns = <20>;
47 gpmc,wait-monitoring-ns = <0>;
48 gpmc,clk-activation-ns = <0>;
49 gpmc,wr-data-mux-bus-ns = <45>;
50 gpmc,wr-access-ns = <145>;
51 };
52 uart@3,1 {
53 compatible = "ns16550a";
54 reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */
55 bank-width = <2>;
56 reg-shift = <1>;
57 reg-io-width = <1>;
58 interrupt-parent = <&gpio4>;
59 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
60 clock-frequency = <1843200>;
61 current-speed = <115200>;
62 };
63 uart@3,2 {
64 compatible = "ns16550a";
65 reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */
66 bank-width = <2>;
67 reg-shift = <1>;
68 reg-io-width = <1>;
69 interrupt-parent = <&gpio4>;
70 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
71 clock-frequency = <1843200>;
72 current-speed = <115200>;
73 };
74 uart@3,3 {
75 compatible = "ns16550a";
76 reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */
19 bank-width = <2>; 77 bank-width = <2>;
20 reg-shift = <1>; 78 reg-shift = <1>;
21 reg-io-width = <1>; 79 reg-io-width = <1>;
diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 24c50db2a478..c9f1e93a95ae 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -40,14 +40,14 @@
40}; 40};
41 41
42&gpmc { 42&gpmc {
43 ranges = <0 0 0x04000000 0x10000000>; 43 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
44 44
45 /* gpio-irq for dma: 26 */ 45 /* gpio-irq for dma: 26 */
46 46
47 onenand@0,0 { 47 onenand@0,0 {
48 #address-cells = <1>; 48 #address-cells = <1>;
49 #size-cells = <1>; 49 #size-cells = <1>;
50 reg = <0 0 0x10000000>; 50 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
51 51
52 gpmc,sync-read; 52 gpmc,sync-read;
53 gpmc,burst-length = <16>; 53 gpmc,burst-length = <16>;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index ae89aad01595..e2b2e93d7b61 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -157,6 +157,7 @@
157 interrupts = <26>, <34>; 157 interrupts = <26>, <34>;
158 interrupt-names = "dsp", "iva"; 158 interrupt-names = "dsp", "iva";
159 ti,hwmods = "mailbox"; 159 ti,hwmods = "mailbox";
160 #mbox-cells = <1>;
160 ti,mbox-num-users = <4>; 161 ti,mbox-num-users = <4>;
161 ti,mbox-num-fifos = <6>; 162 ti,mbox-num-fifos = <6>;
162 mbox_dsp: dsp { 163 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts
index 2c90d29b4cad..05eca2e4430f 100644
--- a/arch/arm/boot/dts/omap2430-sdp.dts
+++ b/arch/arm/boot/dts/omap2430-sdp.dts
@@ -43,7 +43,31 @@
43 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ 43 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
44 reg = <5 0x300 0xf>; 44 reg = <5 0x300 0xf>;
45 bank-width = <2>; 45 bank-width = <2>;
46 gpmc,mux-add-data; 46 gpmc,sync-clk-ps = <0>;
47 }; 47 gpmc,mux-add-data = <2>;
48 gpmc,device-width = <1>;
49 gpmc,cycle2cycle-samecsen = <1>;
50 gpmc,cycle2cycle-diffcsen = <1>;
51 gpmc,cs-on-ns = <7>;
52 gpmc,cs-rd-off-ns = <233>;
53 gpmc,cs-wr-off-ns = <233>;
54 gpmc,adv-on-ns = <22>;
55 gpmc,adv-rd-off-ns = <60>;
56 gpmc,adv-wr-off-ns = <60>;
57 gpmc,oe-on-ns = <67>;
58 gpmc,oe-off-ns = <210>;
59 gpmc,we-on-ns = <67>;
60 gpmc,we-off-ns = <210>;
61 gpmc,rd-cycle-ns = <233>;
62 gpmc,wr-cycle-ns = <233>;
63 gpmc,access-ns = <233>;
64 gpmc,page-burst-access-ns = <30>;
65 gpmc,bus-turnaround-ns = <30>;
66 gpmc,cycle2cycle-delay-ns = <30>;
67 gpmc,wait-monitoring-ns = <0>;
68 gpmc,clk-activation-ns = <0>;
69 gpmc,wr-data-mux-bus-ns = <0>;
70 gpmc,wr-access-ns = <0>;
71 };
48}; 72};
49 73
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index b56d71611026..0dc8de2782b1 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -247,6 +247,7 @@
247 reg = <0x48094000 0x200>; 247 reg = <0x48094000 0x200>;
248 interrupts = <26>; 248 interrupts = <26>;
249 ti,hwmods = "mailbox"; 249 ti,hwmods = "mailbox";
250 #mbox-cells = <1>;
250 ti,mbox-num-users = <4>; 251 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <6>; 252 ti,mbox-num-fifos = <6>;
252 mbox_dsp: dsp { 253 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index d00502f4fd9b..0ab748cf7749 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -134,3 +134,14 @@
134 bus-width = <4>; 134 bus-width = <4>;
135 cap-power-off-card; 135 cap-power-off-card;
136}; 136};
137
138&dss {
139 status = "ok";
140
141 pinctrl-names = "default";
142 pinctrl-0 = <
143 &dss_dpi_pins_common
144 &dss_dpi_pins_cm_t35x
145 >;
146};
147
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
index d1458496520e..8dd14fcf6825 100644
--- a/arch/arm/boot/dts/omap3-cm-t3530.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -46,3 +46,14 @@
46 bus-width = <4>; 46 bus-width = <4>;
47 cap-power-off-card; 47 cap-power-off-card;
48}; 48};
49
50&dss {
51 status = "ok";
52
53 pinctrl-names = "default";
54 pinctrl-0 = <
55 &dss_dpi_pins_common
56 &dss_dpi_pins_cm_t35x
57 >;
58};
59
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index b3f9a50b3bc8..46eadb21b5ef 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -31,6 +31,19 @@
31 }; 31 };
32}; 32};
33 33
34&omap3_pmx_wkup {
35 dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 {
36 pinctrl-single,pins = <
37 OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
38 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
39 OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
40 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
41 OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
42 OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
43 >;
44 };
45};
46
34&omap3_pmx_core { 47&omap3_pmx_core {
35 48
36 mmc2_pins: pinmux_mmc2_pins { 49 mmc2_pins: pinmux_mmc2_pins {
@@ -61,3 +74,14 @@
61 bus-width = <4>; 74 bus-width = <4>;
62 cap-power-off-card; 75 cap-power-off-card;
63}; 76};
77
78&dss {
79 status = "ok";
80
81 pinctrl-names = "default";
82 pinctrl-0 = <
83 &dss_dpi_pins_common
84 &dss_dpi_pins_cm_t3730
85 >;
86};
87
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index c671a2299ea8..b074673703bf 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -76,6 +76,45 @@
76 OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ 76 OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */
77 >; 77 >;
78 }; 78 };
79
80 dss_dpi_pins_common: pinmux_dss_dpi_pins_common {
81 pinctrl-single,pins = <
82 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
83 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
84 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
85 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
86
87 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
88 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
89 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
90 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
91 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
92 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
93 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
94 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
95 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
96 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
97 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
98 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
99 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
100 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
101 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
102 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
103 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
104 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
105 >;
106 };
107
108 dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x {
109 pinctrl-single,pins = <
110 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
111 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
112 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
113 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
114 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
115 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
116 >;
117 };
79}; 118};
80 119
81&uart3 { 120&uart3 {
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index da402f0fdab4..169037e5ff53 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -106,10 +106,10 @@
106}; 106};
107 107
108&gpmc { 108&gpmc {
109 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ 109 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
110 110
111 nand@0,0 { 111 nand@0,0 {
112 reg = <0 0 0>; /* CS0, offset 0 */ 112 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
113 nand-bus-width = <16>; 113 nand-bus-width = <16>;
114 114
115 gpmc,sync-clk-ps = <0>; 115 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index a8bd4349c7d2..16e8ce350dda 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -154,13 +154,14 @@
154}; 154};
155 155
156&gpmc { 156&gpmc {
157 ranges = <0 0 0x00000000 0x20000000>, 157 ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */
158 <5 0 0x2c000000 0x01000000>; 158 <5 0 0x2c000000 0x01000000>;
159 159
160 nand@0,0 { 160 nand@0,0 {
161 linux,mtd-name= "hynix,h8kds0un0mer-4em"; 161 linux,mtd-name= "hynix,h8kds0un0mer-4em";
162 reg = <0 0 0>; 162 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
163 nand-bus-width = <16>; 163 nand-bus-width = <16>;
164 gpmc,device-width = <2>;
164 ti,nand-ecc-opt = "bch8"; 165 ti,nand-ecc-opt = "bch8";
165 166
166 gpmc,sync-clk-ps = <0>; 167 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index fd34f913ace3..655d6e920a86 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -104,67 +104,67 @@
104 104
105 uart1_pins: pinmux_uart1_pins { 105 uart1_pins: pinmux_uart1_pins {
106 pinctrl-single,pins = < 106 pinctrl-single,pins = <
107 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 107 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
108 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ 108 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
109 >; 109 >;
110 }; 110 };
111 111
112 uart2_pins: pinmux_uart2_pins { 112 uart2_pins: pinmux_uart2_pins {
113 pinctrl-single,pins = < 113 pinctrl-single,pins = <
114 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 114 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
115 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 115 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
116 >; 116 >;
117 }; 117 };
118 118
119 uart3_pins: pinmux_uart3_pins { 119 uart3_pins: pinmux_uart3_pins {
120 pinctrl-single,pins = < 120 pinctrl-single,pins = <
121 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ 121 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
122 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ 122 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
123 >; 123 >;
124 }; 124 };
125 125
126 mmc1_pins: pinmux_mmc1_pins { 126 mmc1_pins: pinmux_mmc1_pins {
127 pinctrl-single,pins = < 127 pinctrl-single,pins = <
128 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 128 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
129 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 129 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
130 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 130 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
131 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 131 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
132 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 132 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
133 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 133 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
134 >; 134 >;
135 }; 135 };
136 136
137 dss_dpi_pins: pinmux_dss_dpi_pins { 137 dss_dpi_pins: pinmux_dss_dpi_pins {
138 pinctrl-single,pins = < 138 pinctrl-single,pins = <
139 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 139 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
140 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 140 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
141 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 141 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
142 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 142 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
143 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 143 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
144 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 144 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
145 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 145 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
146 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 146 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
147 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 147 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
148 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 148 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
149 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 149 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
150 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 150 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
151 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 151 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
152 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 152 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
153 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 153 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
154 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 154 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
155 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 155 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
156 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 156 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
157 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 157 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
158 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 158 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
159 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 159 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
160 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 160 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
161 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ 161 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
162 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ 162 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
163 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ 163 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
164 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ 164 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
165 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 165 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
166 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 166 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
167 >; 167 >;
168 }; 168 };
169}; 169};
170 170
@@ -397,10 +397,10 @@
397}; 397};
398 398
399&gpmc { 399&gpmc {
400 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ 400 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
401 401
402 nand@0,0 { 402 nand@0,0 {
403 reg = <0 0 0>; /* CS0, offset 0 */ 403 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
404 nand-bus-width = <16>; 404 nand-bus-width = <16>;
405 ti,nand-ecc-opt = "bch8"; 405 ti,nand-ecc-opt = "bch8";
406 406
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index e2d163bf0619..8a63ad2286aa 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -31,18 +31,6 @@
31 regulator-always-on; 31 regulator-always-on;
32 }; 32 };
33 33
34 lbee1usjyc_vmmc: lbee1usjyc_vmmc {
35 pinctrl-names = "default";
36 pinctrl-0 = <&lbee1usjyc_pins>;
37 compatible = "regulator-fixed";
38 regulator-name = "regulator-lbee1usjyc";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
42 startup-delay-us = <10000>;
43 enable-active-high;
44 vin-supply = <&vdd33>;
45 };
46}; 34};
47 35
48&omap3_pmx_core { 36&omap3_pmx_core {
@@ -53,13 +41,6 @@
53 >; 41 >;
54 }; 42 };
55 43
56 uart2_pins: pinmux_uart2_pins {
57 pinctrl-single,pins = <
58 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
59 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
60 >;
61 };
62
63 uart3_pins: pinmux_uart3_pins { 44 uart3_pins: pinmux_uart3_pins {
64 pinctrl-single,pins = < 45 pinctrl-single,pins = <
65 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ 46 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
@@ -67,15 +48,6 @@
67 >; 48 >;
68 }; 49 };
69 50
70 /* WiFi/BT combo */
71 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
72 pinctrl-single,pins = <
73 0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
74 0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
75 0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
76 >;
77 };
78
79 mcbsp2_pins: pinmux_mcbsp2_pins { 51 mcbsp2_pins: pinmux_mcbsp2_pins {
80 pinctrl-single,pins = < 52 pinctrl-single,pins = <
81 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ 53 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
@@ -120,13 +92,6 @@
120 >; 92 >;
121 }; 93 };
122 94
123 i2c2_pins: pinmux_i2c2_pins {
124 pinctrl-single,pins = <
125 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
126 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
127 >;
128 };
129
130 i2c3_pins: pinmux_i2c3_pins { 95 i2c3_pins: pinmux_i2c3_pins {
131 pinctrl-single,pins = < 96 pinctrl-single,pins = <
132 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ 97 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
@@ -135,6 +100,55 @@
135 }; 100 };
136}; 101};
137 102
103&gpmc {
104 nand@0,0 {
105 linux,mtd-name= "micron,mt29c4g96maz";
106 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
107 nand-bus-width = <16>;
108 gpmc,device-width = <2>;
109 ti,nand-ecc-opt = "bch8";
110
111 gpmc,sync-clk-ps = <0>;
112 gpmc,cs-on-ns = <0>;
113 gpmc,cs-rd-off-ns = <44>;
114 gpmc,cs-wr-off-ns = <44>;
115 gpmc,adv-on-ns = <6>;
116 gpmc,adv-rd-off-ns = <34>;
117 gpmc,adv-wr-off-ns = <44>;
118 gpmc,we-off-ns = <40>;
119 gpmc,oe-off-ns = <54>;
120 gpmc,access-ns = <64>;
121 gpmc,rd-cycle-ns = <82>;
122 gpmc,wr-cycle-ns = <82>;
123 gpmc,wr-access-ns = <40>;
124 gpmc,wr-data-mux-bus-ns = <0>;
125
126 #address-cells = <1>;
127 #size-cells = <1>;
128
129 partition@0 {
130 label = "SPL";
131 reg = <0 0x100000>;
132 };
133 partition@80000 {
134 label = "U-Boot";
135 reg = <0x100000 0x180000>;
136 };
137 partition@1c0000 {
138 label = "Environment";
139 reg = <0x280000 0x100000>;
140 };
141 partition@280000 {
142 label = "Kernel";
143 reg = <0x380000 0x300000>;
144 };
145 partition@780000 {
146 label = "Filesystem";
147 reg = <0x680000 0x1f980000>;
148 };
149 };
150};
151
138&i2c1 { 152&i2c1 {
139 pinctrl-names = "default"; 153 pinctrl-names = "default";
140 pinctrl-0 = <&i2c1_pins>; 154 pinctrl-0 = <&i2c1_pins>;
@@ -156,12 +170,6 @@
156#include "twl4030.dtsi" 170#include "twl4030.dtsi"
157#include "twl4030_omap3.dtsi" 171#include "twl4030_omap3.dtsi"
158 172
159&i2c2 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&i2c2_pins>;
162 clock-frequency = <400000>;
163};
164
165&i2c3 { 173&i2c3 {
166 pinctrl-names = "default"; 174 pinctrl-names = "default";
167 pinctrl-0 = <&i2c3_pins>; 175 pinctrl-0 = <&i2c3_pins>;
@@ -181,14 +189,6 @@
181 bus-width = <4>; 189 bus-width = <4>;
182}; 190};
183 191
184&mmc2 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&mmc2_pins>;
187 vmmc-supply = <&lbee1usjyc_vmmc>;
188 bus-width = <4>;
189 non-removable;
190};
191
192&mmc3 { 192&mmc3 {
193 status = "disabled"; 193 status = "disabled";
194}; 194};
@@ -198,11 +198,6 @@
198 pinctrl-0 = <&uart1_pins>; 198 pinctrl-0 = <&uart1_pins>;
199}; 199};
200 200
201&uart2 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&uart2_pins>;
204};
205
206&uart3 { 201&uart3 {
207 pinctrl-names = "default"; 202 pinctrl-names = "default";
208 pinctrl-0 = <&uart3_pins>; 203 pinctrl-0 = <&uart3_pins>;
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
new file mode 100644
index 000000000000..e458c2185e3c
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
@@ -0,0 +1,246 @@
1/*
2 * Common Device Tree Source for IGEPv2
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep.dtsi"
13#include "omap-gpmc-smsc9221.dtsi"
14
15/ {
16
17 leds {
18 pinctrl-names = "default";
19 pinctrl-0 = <&leds_pins>;
20 compatible = "gpio-leds";
21
22 boot {
23 label = "omap3:green:boot";
24 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
25 default-state = "on";
26 };
27
28 user0 {
29 label = "omap3:red:user0";
30 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
31 default-state = "off";
32 };
33
34 user1 {
35 label = "omap3:red:user1";
36 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
37 default-state = "off";
38 };
39
40 user2 {
41 label = "omap3:green:user1";
42 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
43 };
44 };
45
46 /* HS USB Port 1 Power */
47 hsusb1_power: hsusb1_power_reg {
48 compatible = "regulator-fixed";
49 regulator-name = "hsusb1_vbus";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
53 startup-delay-us = <70000>;
54 };
55
56 /* HS USB Host PHY on PORT 1 */
57 hsusb1_phy: hsusb1_phy {
58 compatible = "usb-nop-xceiv";
59 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
60 vcc-supply = <&hsusb1_power>;
61 };
62
63 tfp410: encoder@0 {
64 compatible = "ti,tfp410";
65 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
66
67 ports {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 port@0 {
72 reg = <0>;
73
74 tfp410_in: endpoint@0 {
75 remote-endpoint = <&dpi_out>;
76 };
77 };
78
79 port@1 {
80 reg = <1>;
81
82 tfp410_out: endpoint@0 {
83 remote-endpoint = <&dvi_connector_in>;
84 };
85 };
86 };
87 };
88
89 dvi0: connector@0 {
90 compatible = "dvi-connector";
91 label = "dvi";
92
93 digital;
94
95 ddc-i2c-bus = <&i2c3>;
96
97 port {
98 dvi_connector_in: endpoint {
99 remote-endpoint = <&tfp410_out>;
100 };
101 };
102 };
103};
104
105&omap3_pmx_core {
106 pinctrl-names = "default";
107 pinctrl-0 = <
108 &tfp410_pins
109 &dss_dpi_pins
110 >;
111
112 tfp410_pins: pinmux_tfp410_pins {
113 pinctrl-single,pins = <
114 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
115 >;
116 };
117
118 dss_dpi_pins: pinmux_dss_dpi_pins {
119 pinctrl-single,pins = <
120 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
121 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
122 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
123 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
124 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
125 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
126 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
127 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
128 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
129 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
130 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
131 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
132 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
133 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
134 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
135 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
136 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
137 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
138 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
139 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
140 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
141 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
142 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
143 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
144 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
145 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
146 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
147 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
148 >;
149 };
150
151 uart2_pins: pinmux_uart2_pins {
152 pinctrl-single,pins = <
153 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
154 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
155 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
156 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
157 >;
158 };
159};
160
161&omap3_pmx_core2 {
162 pinctrl-names = "default";
163 pinctrl-0 = <
164 &hsusbb1_pins
165 >;
166
167 hsusbb1_pins: pinmux_hsusbb1_pins {
168 pinctrl-single,pins = <
169 OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
170 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
171 OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
172 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
173 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
174 OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
175 OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
176 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
177 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
178 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
179 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
180 OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
181 >;
182 };
183
184 leds_pins: pinmux_leds_pins {
185 pinctrl-single,pins = <
186 OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
187 OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
188 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
189 >;
190 };
191};
192
193&i2c3 {
194 clock-frequency = <100000>;
195
196 /*
197 * Display monitor features are burnt in the EEPROM
198 * as EDID data.
199 */
200 eeprom@50 {
201 compatible = "ti,eeprom";
202 reg = <0x50>;
203 };
204};
205
206&gpmc {
207 ranges = <0 0 0x00000000 0x20000000>,
208 <5 0 0x2c000000 0x01000000>;
209
210 ethernet@gpmc {
211 pinctrl-names = "default";
212 pinctrl-0 = <&smsc9221_pins>;
213 reg = <5 0 0xff>;
214 interrupt-parent = <&gpio6>;
215 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
216 };
217};
218
219&uart2 {
220 pinctrl-names = "default";
221 pinctrl-0 = <&uart2_pins>;
222};
223
224&usbhshost {
225 port1-mode = "ehci-phy";
226};
227
228&usbhsehci {
229 phys = <&hsusb1_phy>;
230};
231
232&vpll2 {
233 /* Needed for DSS */
234 regulator-name = "vdds_dsi";
235};
236
237&dss {
238 status = "ok";
239
240 port {
241 dpi_out: endpoint {
242 remote-endpoint = <&tfp410_in>;
243 data-lines = <24>;
244 };
245 };
246};
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
new file mode 100644
index 000000000000..cc8bd0cd8cf8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -0,0 +1,45 @@
1/*
2 * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x)
3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep0020-common.dtsi"
13
14/ {
15 model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
17
18 /* Regulator to trigger the WL_EN signal of the Wifi module */
19 lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
20 compatible = "regulator-fixed";
21 regulator-name = "regulator-lbep5clwmc-wlen";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */
25 enable-active-high;
26 };
27};
28
29&omap3_pmx_core {
30 lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */
33 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */
34 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */
35 >;
36 };
37};
38
39&mmc2 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
42 vmmc-supply = <&lbep5clwmc_wlen>;
43 bus-width = <4>;
44 non-removable;
45};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index b22caaaf774b..fea7f7edb45d 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x) 2 * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,272 +9,59 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include "omap3-igep.dtsi" 12#include "omap3-igep0020-common.dtsi"
13#include "omap-gpmc-smsc9221.dtsi"
14 13
15/ { 14/ {
16 model = "IGEPv2 (TI OMAP AM/DM37x)"; 15 model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
17 compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; 16 compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
18 17
19 leds { 18 /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
20 pinctrl-names = "default"; 19 lbee1usjyc_pdn: lbee1usjyc_pdn {
21 pinctrl-0 = <&leds_pins>; 20 compatible = "regulator-fixed";
22 compatible = "gpio-leds"; 21 regulator-name = "regulator-lbee1usjyc-pdn";
23 22 regulator-min-microvolt = <3300000>;
24 boot { 23 regulator-max-microvolt = <3300000>;
25 label = "omap3:green:boot"; 24 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */
26 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 25 startup-delay-us = <10000>;
27 default-state = "on"; 26 enable-active-high;
28 };
29
30 user0 {
31 label = "omap3:red:user0";
32 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
33 default-state = "off";
34 };
35
36 user1 {
37 label = "omap3:red:user1";
38 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
39 default-state = "off";
40 };
41
42 user2 {
43 label = "omap3:green:user1";
44 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
45 };
46 }; 27 };
47 28
48 /* HS USB Port 1 Power */ 29 /* Regulator to trigger the RESET_N_W signal of the Wifi module */
49 hsusb1_power: hsusb1_power_reg { 30 lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
50 compatible = "regulator-fixed"; 31 compatible = "regulator-fixed";
51 regulator-name = "hsusb1_vbus"; 32 regulator-name = "regulator-lbee1usjyc-reset-n-w";
52 regulator-min-microvolt = <3300000>; 33 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>;
54 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ 35 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */
55 startup-delay-us = <70000>; 36 enable-active-high;
56 };
57
58 /* HS USB Host PHY on PORT 1 */
59 hsusb1_phy: hsusb1_phy {
60 compatible = "usb-nop-xceiv";
61 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
62 vcc-supply = <&hsusb1_power>;
63 };
64
65 tfp410: encoder@0 {
66 compatible = "ti,tfp410";
67 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
68
69 ports {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 port@0 {
74 reg = <0>;
75
76 tfp410_in: endpoint@0 {
77 remote-endpoint = <&dpi_out>;
78 };
79 };
80
81 port@1 {
82 reg = <1>;
83
84 tfp410_out: endpoint@0 {
85 remote-endpoint = <&dvi_connector_in>;
86 };
87 };
88 };
89 };
90
91 dvi0: connector@0 {
92 compatible = "dvi-connector";
93 label = "dvi";
94
95 digital;
96
97 ddc-i2c-bus = <&i2c3>;
98
99 port {
100 dvi_connector_in: endpoint {
101 remote-endpoint = <&tfp410_out>;
102 };
103 };
104 }; 37 };
105}; 38};
106 39
107&omap3_pmx_core { 40&omap3_pmx_core {
108 pinctrl-names = "default"; 41 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
109 pinctrl-0 = <
110 &tfp410_pins
111 &dss_dpi_pins
112 >;
113
114 tfp410_pins: pinmux_tfp410_pins {
115 pinctrl-single,pins = < 42 pinctrl-single,pins = <
116 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 43 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
44 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
45 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
117 >; 46 >;
118 }; 47 };
119 48
120 dss_dpi_pins: pinmux_dss_dpi_pins { 49 uart2_pins: pinmux_uart2_pins {
121 pinctrl-single,pins = < 50 pinctrl-single,pins = <
122 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 51 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
123 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 52 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
124 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 53 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
125 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 54 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
126 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
127 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
128 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
129 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
130 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
131 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
132 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
133 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
134 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
135 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
136 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
137 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
138 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
139 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
140 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
141 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
142 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
143 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
144 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
145 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
146 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
147 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
148 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
149 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
150 >; 55 >;
151 }; 56 };
152}; 57};
153 58
154&omap3_pmx_core2 { 59/* On board Wifi module */
60&mmc2 {
155 pinctrl-names = "default"; 61 pinctrl-names = "default";
156 pinctrl-0 = < 62 pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
157 &hsusbb1_pins 63 vmmc-supply = <&lbee1usjyc_pdn>;
158 >; 64 vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
159 65 bus-width = <4>;
160 hsusbb1_pins: pinmux_hsusbb1_pins { 66 non-removable;
161 pinctrl-single,pins = <
162 OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
163 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
164 OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
165 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
166 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
167 OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
168 OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
169 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
170 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
171 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
172 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
173 OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
174 >;
175 };
176
177 leds_pins: pinmux_leds_pins {
178 pinctrl-single,pins = <
179 OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
180 OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
181 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
182 >;
183 };
184};
185
186&i2c3 {
187 clock-frequency = <100000>;
188
189 /*
190 * Display monitor features are burnt in the EEPROM
191 * as EDID data.
192 */
193 eeprom@50 {
194 compatible = "ti,eeprom";
195 reg = <0x50>;
196 };
197};
198
199&gpmc {
200 ranges = <0 0 0x00000000 0x20000000>,
201 <5 0 0x2c000000 0x01000000>;
202
203 nand@0,0 {
204 linux,mtd-name= "micron,mt29c4g96maz";
205 reg = <0 0 0>;
206 nand-bus-width = <16>;
207 ti,nand-ecc-opt = "bch8";
208
209 gpmc,sync-clk-ps = <0>;
210 gpmc,cs-on-ns = <0>;
211 gpmc,cs-rd-off-ns = <44>;
212 gpmc,cs-wr-off-ns = <44>;
213 gpmc,adv-on-ns = <6>;
214 gpmc,adv-rd-off-ns = <34>;
215 gpmc,adv-wr-off-ns = <44>;
216 gpmc,we-off-ns = <40>;
217 gpmc,oe-off-ns = <54>;
218 gpmc,access-ns = <64>;
219 gpmc,rd-cycle-ns = <82>;
220 gpmc,wr-cycle-ns = <82>;
221 gpmc,wr-access-ns = <40>;
222 gpmc,wr-data-mux-bus-ns = <0>;
223
224 #address-cells = <1>;
225 #size-cells = <1>;
226
227 partition@0 {
228 label = "SPL";
229 reg = <0 0x100000>;
230 };
231 partition@80000 {
232 label = "U-Boot";
233 reg = <0x100000 0x180000>;
234 };
235 partition@1c0000 {
236 label = "Environment";
237 reg = <0x280000 0x100000>;
238 };
239 partition@280000 {
240 label = "Kernel";
241 reg = <0x380000 0x300000>;
242 };
243 partition@780000 {
244 label = "Filesystem";
245 reg = <0x680000 0x1f980000>;
246 };
247 };
248
249 ethernet@gpmc {
250 pinctrl-names = "default";
251 pinctrl-0 = <&smsc9221_pins>;
252 reg = <5 0 0xff>;
253 interrupt-parent = <&gpio6>;
254 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
255 };
256};
257
258&usbhshost {
259 port1-mode = "ehci-phy";
260};
261
262&usbhsehci {
263 phys = <&hsusb1_phy>;
264};
265
266&vpll2 {
267 /* Needed for DSS */
268 regulator-name = "vdds_dsi";
269};
270
271&dss {
272 status = "ok";
273
274 port {
275 dpi_out: endpoint {
276 remote-endpoint = <&tfp410_in>;
277 data-lines = <24>;
278 };
279 };
280}; 67};
diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
new file mode 100644
index 000000000000..0cb1527c39d4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
@@ -0,0 +1,60 @@
1/*
2 * Common Device Tree Source for IGEP COM MODULE
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep.dtsi"
13
14/ {
15 leds: gpio_leds {
16 compatible = "gpio-leds";
17
18 user0 {
19 label = "omap3:red:user0";
20 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
21 default-state = "off";
22 };
23
24 user1 {
25 label = "omap3:green:user1";
26 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
27 default-state = "off";
28 };
29
30 user2 {
31 label = "omap3:red:user1";
32 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */
33 default-state = "off";
34 };
35 };
36};
37
38&omap3_pmx_core {
39 uart2_pins: pinmux_uart2_pins {
40 pinctrl-single,pins = <
41 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
42 OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
43 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
44 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
45 >;
46 };
47};
48
49&omap3_pmx_core2 {
50 leds_core2_pins: pinmux_leds_core2_pins {
51 pinctrl-single,pins = <
52 OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
53 >;
54 };
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart2_pins>;
60};
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
new file mode 100644
index 000000000000..9326b282c94a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -0,0 +1,67 @@
1/*
2 * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep0030-common.dtsi"
13
14/ {
15 model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
17
18 /* Regulator to trigger the WL_EN signal of the Wifi module */
19 lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
20 compatible = "regulator-fixed";
21 regulator-name = "regulator-lbep5clwmc-wlen";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */
25 enable-active-high;
26 };
27};
28
29&omap3_pmx_core {
30 lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */
33 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */
34 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */
35 >;
36 };
37
38 leds_pins: pinmux_leds_pins {
39 pinctrl-single,pins = <
40 OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
41 >;
42 };
43
44};
45
46&i2c2 {
47 status = "disabled";
48};
49
50&leds {
51 pinctrl-names = "default";
52 pinctrl-0 = <&leds_pins &leds_core2_pins>;
53
54 boot {
55 label = "omap3:green:boot";
56 gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
57 default-state = "on";
58 };
59};
60
61&mmc2 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
64 vmmc-supply = <&lbep5clwmc_wlen>;
65 bus-width = <4>;
66 non-removable;
67};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 2793749eb1ba..8150f47ccdf5 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x) 2 * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,97 +9,62 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include "omap3-igep.dtsi" 12#include "omap3-igep0030-common.dtsi"
13 13
14/ { 14/ {
15 model = "IGEP COM MODULE (TI OMAP AM/DM37x)"; 15 model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3"; 16 compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
17 17
18 leds { 18 /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
19 pinctrl-names = "default"; 19 lbee1usjyc_pdn: lbee1usjyc_pdn {
20 pinctrl-0 = <&leds_pins>; 20 compatible = "regulator-fixed";
21 compatible = "gpio-leds"; 21 regulator-name = "regulator-lbee1usjyc-pdn";
22 22 regulator-min-microvolt = <3300000>;
23 boot { 23 regulator-max-microvolt = <3300000>;
24 label = "omap3:green:boot"; 24 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */
25 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; 25 startup-delay-us = <10000>;
26 default-state = "on"; 26 enable-active-high;
27 }; 27 };
28
29 user0 {
30 label = "omap3:red:user0";
31 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
32 default-state = "off";
33 };
34
35 user1 {
36 label = "omap3:green:user1";
37 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
38 default-state = "off";
39 };
40 28
41 user2 { 29 /* Regulator to trigger the RESET_N_W signal of the Wifi module */
42 label = "omap3:red:user1"; 30 lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
43 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 31 compatible = "regulator-fixed";
44 default-state = "off"; 32 regulator-name = "regulator-lbee1usjyc-reset-n-w";
45 }; 33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */
36 enable-active-high;
46 }; 37 };
47}; 38};
48 39
49&omap3_pmx_core2 { 40&omap3_pmx_core {
50 leds_pins: pinmux_leds_pins { 41 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
51 pinctrl-single,pins = < 42 pinctrl-single,pins = <
52 OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ 43 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
44 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
45 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
53 >; 46 >;
54 }; 47 };
55}; 48};
56 49
57&gpmc { 50&leds {
58 ranges = <0 0 0x00000000 0x20000000>; 51 pinctrl-names = "default";
59 52 pinctrl-0 = <&leds_core2_pins>;
60 nand@0,0 {
61 linux,mtd-name= "micron,mt29c4g96maz";
62 reg = <0 0 0>;
63 nand-bus-width = <16>;
64 ti,nand-ecc-opt = "bch8";
65 53
66 gpmc,sync-clk-ps = <0>; 54 boot {
67 gpmc,cs-on-ns = <0>; 55 label = "omap3:green:boot";
68 gpmc,cs-rd-off-ns = <44>; 56 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */
69 gpmc,cs-wr-off-ns = <44>; 57 default-state = "on";
70 gpmc,adv-on-ns = <6>;
71 gpmc,adv-rd-off-ns = <34>;
72 gpmc,adv-wr-off-ns = <44>;
73 gpmc,we-off-ns = <40>;
74 gpmc,oe-off-ns = <54>;
75 gpmc,access-ns = <64>;
76 gpmc,rd-cycle-ns = <82>;
77 gpmc,wr-cycle-ns = <82>;
78 gpmc,wr-access-ns = <40>;
79 gpmc,wr-data-mux-bus-ns = <0>;
80
81 #address-cells = <1>;
82 #size-cells = <1>;
83
84 partition@0 {
85 label = "SPL";
86 reg = <0 0x100000>;
87 };
88 partition@80000 {
89 label = "U-Boot";
90 reg = <0x100000 0x180000>;
91 };
92 partition@1c0000 {
93 label = "Environment";
94 reg = <0x280000 0x100000>;
95 };
96 partition@280000 {
97 label = "Kernel";
98 reg = <0x380000 0x300000>;
99 };
100 partition@780000 {
101 label = "Filesystem";
102 reg = <0x680000 0x1f980000>;
103 };
104 }; 58 };
105}; 59};
60
61/* On board Wifi module */
62&mmc2 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
65 vmmc-supply = <&lbee1usjyc_pdn>;
66 vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
67 bus-width = <4>;
68 non-removable;
69};
70
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 72dca0b7904d..202f95a5a383 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -101,8 +101,9 @@
101 101
102 nand@0,0 { 102 nand@0,0 {
103 linux,mtd-name= "micron,nand"; 103 linux,mtd-name= "micron,nand";
104 reg = <0 0 0>; 104 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
105 nand-bus-width = <16>; 105 nand-bus-width = <16>;
106 gpmc,device-width = <2>;
106 ti,nand-ecc-opt = "bch8"; 107 ti,nand-ecc-opt = "bch8";
107 108
108 gpmc,sync-clk-ps = <0>; 109 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index d97308896f0c..e81fb651d5d0 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -363,7 +363,7 @@
363 <7 0 0x15000000 0x01000000>; 363 <7 0 0x15000000 0x01000000>;
364 364
365 nand@0,0 { 365 nand@0,0 {
366 reg = <0 0 0x1000000>; 366 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
367 nand-bus-width = <16>; 367 nand-bus-width = <16>;
368 ti,nand-ecc-opt = "bch8"; 368 ti,nand-ecc-opt = "bch8";
369 /* no elm on omap3 */ 369 /* no elm on omap3 */
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index bc82a12d4c2c..08ef71fe5273 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -142,6 +142,33 @@
142 >; 142 >;
143 }; 143 };
144 144
145 gpmc_pins: pinmux_gpmc_pins {
146 pinctrl-single,pins = <
147
148 /* address lines */
149 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
150 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
151 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
152
153 /* data lines, gpmc_d0..d7 not muxable according to TRM */
154 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
155 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
156 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
157 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
158 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
159 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
160 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
161 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
162
163 /*
164 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
165 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
166 */
167 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
168 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
169 >;
170 };
171
145 i2c1_pins: pinmux_i2c1_pins { 172 i2c1_pins: pinmux_i2c1_pins {
146 pinctrl-single,pins = < 173 pinctrl-single,pins = <
147 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 174 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
@@ -585,16 +612,16 @@
585}; 612};
586 613
587&gpmc { 614&gpmc {
588 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
589 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ 615 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
590 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ 616 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
617 pinctrl-names = "default";
618 pinctrl-0 = <&gpmc_pins>;
591 619
592 /* gpio-irq for dma: 65 */ 620 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
593
594 onenand@0,0 { 621 onenand@0,0 {
595 #address-cells = <1>; 622 #address-cells = <1>;
596 #size-cells = <1>; 623 #size-cells = <1>;
597 reg = <0 0 0x10000000>; 624 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
598 625
599 gpmc,sync-read; 626 gpmc,sync-read;
600 gpmc,sync-write; 627 gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 70addcba37c5..1e49dfe7e212 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -115,12 +115,12 @@
115}; 115};
116 116
117&gpmc { 117&gpmc {
118 ranges = <0 0 0x04000000 0x20000000>; 118 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
119 119
120 onenand@0,0 { 120 onenand@0,0 {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 reg = <0 0 0x20000000>; 123 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
124 124
125 gpmc,sync-read; 125 gpmc,sync-read;
126 gpmc,sync-write; 126 gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index d59e3de1441e..b1cb5774f49a 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,6 +2,49 @@
2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
3 */ 3 */
4 4
5/ {
6 tfp410: encoder@0 {
7 compatible = "ti,tfp410";
8
9 powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */
10
11 pinctrl-names = "default";
12 pinctrl-0 = <&tfp410_pins>;
13
14 ports {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 port@0 {
19 reg = <0>;
20
21 tfp410_in: endpoint@0 {
22 remote-endpoint = <&dpi_out>;
23 };
24 };
25
26 port@1 {
27 reg = <1>;
28
29 tfp410_out: endpoint@0 {
30 remote-endpoint = <&dvi_connector_in>;
31 };
32 };
33 };
34 };
35
36 dvi0: connector@0 {
37 compatible = "dvi-connector";
38 label = "dvi";
39
40 port {
41 dvi_connector_in: endpoint {
42 remote-endpoint = <&tfp410_out>;
43 };
44 };
45 };
46};
47
5&omap3_pmx_core { 48&omap3_pmx_core {
6 smsc2_pins: pinmux_smsc2_pins { 49 smsc2_pins: pinmux_smsc2_pins {
7 pinctrl-single,pins = < 50 pinctrl-single,pins = <
@@ -9,6 +52,12 @@
9 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ 52 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
10 >; 53 >;
11 }; 54 };
55
56 tfp410_pins: pinmux_tfp410_pins {
57 pinctrl-single,pins = <
58 OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
59 >;
60 };
12}; 61};
13 62
14&gpmc { 63&gpmc {
@@ -22,24 +71,29 @@
22 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 71 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
23 reg = <4 0 0xff>; 72 reg = <4 0 0xff>;
24 bank-width = <2>; 73 bank-width = <2>;
25 gpmc,mux-add-data; 74 gpmc,device-width = <1>;
26 gpmc,cs-on-ns = <1>; 75 gpmc,cycle2cycle-samecsen = <1>;
27 gpmc,cs-rd-off-ns = <180>; 76 gpmc,cycle2cycle-diffcsen = <1>;
28 gpmc,cs-wr-off-ns = <180>; 77 gpmc,cs-on-ns = <5>;
29 gpmc,adv-rd-off-ns = <18>; 78 gpmc,cs-rd-off-ns = <150>;
30 gpmc,adv-wr-off-ns = <48>; 79 gpmc,cs-wr-off-ns = <150>;
31 gpmc,oe-on-ns = <54>; 80 gpmc,adv-on-ns = <0>;
32 gpmc,oe-off-ns = <168>; 81 gpmc,adv-rd-off-ns = <15>;
33 gpmc,we-on-ns = <54>; 82 gpmc,adv-wr-off-ns = <40>;
34 gpmc,we-off-ns = <168>; 83 gpmc,oe-on-ns = <45>;
35 gpmc,rd-cycle-ns = <186>; 84 gpmc,oe-off-ns = <140>;
36 gpmc,wr-cycle-ns = <186>; 85 gpmc,we-on-ns = <45>;
37 gpmc,access-ns = <144>; 86 gpmc,we-off-ns = <140>;
38 gpmc,page-burst-access-ns = <24>; 87 gpmc,rd-cycle-ns = <155>;
39 gpmc,bus-turnaround-ns = <90>; 88 gpmc,wr-cycle-ns = <155>;
40 gpmc,cycle2cycle-delay-ns = <90>; 89 gpmc,access-ns = <120>;
41 gpmc,cycle2cycle-samecsen; 90 gpmc,page-burst-access-ns = <20>;
42 gpmc,cycle2cycle-diffcsen; 91 gpmc,bus-turnaround-ns = <75>;
92 gpmc,cycle2cycle-delay-ns = <75>;
93 gpmc,wait-monitoring-ns = <0>;
94 gpmc,clk-activation-ns = <0>;
95 gpmc,wr-data-mux-bus-ns = <0>;
96 gpmc,wr-access-ns = <0>;
43 vddvario-supply = <&vddvario>; 97 vddvario-supply = <&vddvario>;
44 vdd33a-supply = <&vdd33a>; 98 vdd33a-supply = <&vdd33a>;
45 reg-io-width = <4>; 99 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 42189b65d393..4ec5d8684122 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -9,6 +9,10 @@
9 model = "CompuLab SBC-T3517 with CM-T3517"; 9 model = "CompuLab SBC-T3517 with CM-T3517";
10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
11 11
12 aliases {
13 display0 = &dvi0;
14 };
15
12 /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ 16 /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
13 vddvario: regulator-vddvario-sb-t35 { 17 vddvario: regulator-vddvario-sb-t35 {
14 compatible = "regulator-fixed"; 18 compatible = "regulator-fixed";
@@ -54,3 +58,13 @@
54 wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ 58 wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */
55 cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ 59 cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */
56}; 60};
61
62&dss {
63 port {
64 dpi_out: endpoint {
65 remote-endpoint = <&tfp410_in>;
66 data-lines = <24>;
67 };
68 };
69};
70
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index bbbeea6b1988..8dfc1df8cc17 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -8,6 +8,10 @@
8/ { 8/ {
9 model = "CompuLab SBC-T3530 with CM-T3530"; 9 model = "CompuLab SBC-T3530 with CM-T3530";
10 compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
11
12 aliases {
13 display0 = &dvi0;
14 };
11}; 15};
12 16
13&omap3_pmx_core { 17&omap3_pmx_core {
@@ -34,3 +38,13 @@
34&mmc1 { 38&mmc1 {
35 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; 39 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
36}; 40};
41
42&dss {
43 port {
44 dpi_out: endpoint {
45 remote-endpoint = <&tfp410_in>;
46 data-lines = <24>;
47 };
48 };
49};
50
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 08e4a7086f22..6b69864bd6ce 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -8,6 +8,10 @@
8/ { 8/ {
9 model = "CompuLab SBC-T3730 with CM-T3730"; 9 model = "CompuLab SBC-T3730 with CM-T3730";
10 compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
11
12 aliases {
13 display0 = &dvi0;
14 };
11}; 15};
12 16
13&omap3_pmx_core { 17&omap3_pmx_core {
@@ -25,3 +29,13 @@
25 ranges = <5 0 0x2c000000 0x01000000>, 29 ranges = <5 0 0x2c000000 0x01000000>,
26 <4 0 0x2d000000 0x01000000>; 30 <4 0 0x2d000000 0x01000000>;
27}; 31};
32
33&dss {
34 port {
35 dpi_out: endpoint {
36 remote-endpoint = <&tfp410_in>;
37 data-lines = <24>;
38 };
39 };
40};
41
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index b30f387d3a83..e89820a6776e 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -270,7 +270,7 @@
270 ranges = <0 0 0x00000000 0x01000000>; 270 ranges = <0 0 0x00000000 0x01000000>;
271 271
272 nand@0,0 { 272 nand@0,0 {
273 reg = <0 0 0>; /* CS0, offset 0 */ 273 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
274 nand-bus-width = <16>; 274 nand-bus-width = <16>;
275 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ 275 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
276 ti,nand-ecc-opt = "sw"; 276 ti,nand-ecc-opt = "sw";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d0e884d3a737..8db7def81c28 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -332,6 +332,7 @@
332 ti,hwmods = "mailbox"; 332 ti,hwmods = "mailbox";
333 reg = <0x48094000 0x200>; 333 reg = <0x48094000 0x200>;
334 interrupts = <26>; 334 interrupts = <26>;
335 #mbox-cells = <1>;
335 ti,mbox-num-users = <2>; 336 ti,mbox-num-users = <2>;
336 ti,mbox-num-fifos = <2>; 337 ti,mbox-num-fifos = <2>;
337 mbox_dsp: dsp { 338 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 9bad94efe1c8..16b0cdfbee9c 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -51,8 +51,8 @@
51 51
52&gpmc { 52&gpmc {
53 ranges = <0 0 0x10000000 0x08000000>, 53 ranges = <0 0 0x10000000 0x08000000>,
54 <1 0 0x28000000 0x08000000>, 54 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
55 <2 0 0x20000000 0x10000000>; 55 <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */
56 56
57 nor@0,0 { 57 nor@0,0 {
58 compatible = "cfi-flash"; 58 compatible = "cfi-flash";
@@ -106,7 +106,7 @@
106 linux,mtd-name= "micron,mt29f1g08abb"; 106 linux,mtd-name= "micron,mt29f1g08abb";
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <1>; 108 #size-cells = <1>;
109 reg = <1 0 0x08000000>; 109 reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
110 ti,nand-ecc-opt = "sw"; 110 ti,nand-ecc-opt = "sw";
111 nand-bus-width = <8>; 111 nand-bus-width = <8>;
112 gpmc,cs-on-ns = <0>; 112 gpmc,cs-on-ns = <0>;
@@ -150,7 +150,7 @@
150 linux,mtd-name= "samsung,kfm2g16q2m-deb8"; 150 linux,mtd-name= "samsung,kfm2g16q2m-deb8";
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <1>; 152 #size-cells = <1>;
153 reg = <2 0 0x10000000>; 153 reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */
154 154
155 gpmc,device-width = <2>; 155 gpmc,device-width = <2>;
156 gpmc,mux-add-data = <2>; 156 gpmc,mux-add-data = <2>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 878c979203d0..a46eab82d2da 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -661,6 +661,7 @@
661 reg = <0x4a0f4000 0x200>; 661 reg = <0x4a0f4000 0x200>;
662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
663 ti,hwmods = "mailbox"; 663 ti,hwmods = "mailbox";
664 #mbox-cells = <1>;
664 ti,mbox-num-users = <3>; 665 ti,mbox-num-users = <3>;
665 ti,mbox-num-fifos = <8>; 666 ti,mbox-num-fifos = <8>;
666 mbox_ipu: mbox_ipu { 667 mbox_ipu: mbox_ipu {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 256b7f69e45b..b321fdf42c9f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -651,6 +651,7 @@
651 reg = <0x4a0f4000 0x200>; 651 reg = <0x4a0f4000 0x200>;
652 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 652 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
653 ti,hwmods = "mailbox"; 653 ti,hwmods = "mailbox";
654 #mbox-cells = <1>;
654 ti,mbox-num-users = <3>; 655 ti,mbox-num-users = <3>;
655 ti,mbox-num-fifos = <8>; 656 ti,mbox-num-fifos = <8>;
656 mbox_ipu: mbox_ipu { 657 mbox_ipu: mbox_ipu {
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index cec9d6c6442c..2156f69fc282 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -13,6 +13,7 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16#include <linux/ti_wilink_st.h>
16#include <linux/wl12xx.h> 17#include <linux/wl12xx.h>
17 18
18#include <linux/platform_data/pinctrl-single.h> 19#include <linux/platform_data/pinctrl-single.h>
@@ -139,8 +140,38 @@ static void __init omap3_sbc_t3530_legacy_init(void)
139 omap_ads7846_init(1, 57, 0, NULL); 140 omap_ads7846_init(1, 57, 0, NULL);
140} 141}
141 142
142static void __init omap3_igep0020_legacy_init(void) 143struct ti_st_plat_data wilink_pdata = {
144 .nshutdown_gpio = 137,
145 .dev_name = "/dev/ttyO1",
146 .flow_cntrl = 1,
147 .baud_rate = 300000,
148};
149
150static struct platform_device wl18xx_device = {
151 .name = "kim",
152 .id = -1,
153 .dev = {
154 .platform_data = &wilink_pdata,
155 }
156};
157
158static struct platform_device btwilink_device = {
159 .name = "btwilink",
160 .id = -1,
161};
162
163static void __init omap3_igep0020_rev_f_legacy_init(void)
164{
165 legacy_init_wl12xx(0, 0, 177);
166 platform_device_register(&wl18xx_device);
167 platform_device_register(&btwilink_device);
168}
169
170static void __init omap3_igep0030_rev_g_legacy_init(void)
143{ 171{
172 legacy_init_wl12xx(0, 0, 136);
173 platform_device_register(&wl18xx_device);
174 platform_device_register(&btwilink_device);
144} 175}
145 176
146static void __init omap3_evm_legacy_init(void) 177static void __init omap3_evm_legacy_init(void)
@@ -390,7 +421,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
390 { "nokia,omap3-n900", nokia_n900_legacy_init, }, 421 { "nokia,omap3-n900", nokia_n900_legacy_init, },
391 { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, 422 { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
392 { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, 423 { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
393 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, 424 { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
425 { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
394 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, 426 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
395 { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, 427 { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
396 { "ti,am3517-evm", am3517_evm_legacy_init, }, 428 { "ti,am3517-evm", am3517_evm_legacy_init, },
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 08:21:17 -0400