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-rw-r--r--drivers/tty/serial/Kconfig18
-rw-r--r--drivers/tty/serial/Makefile1
-rw-r--r--drivers/tty/serial/sc26xx.c749
3 files changed, 0 insertions, 768 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index a3817ab8602f..7fbbbadea2dd 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1146,31 +1146,13 @@ config SERIAL_QE
1146 This driver supports the QE serial ports on Freescale embedded 1146 This driver supports the QE serial ports on Freescale embedded
1147 PowerPC that contain a QUICC Engine. 1147 PowerPC that contain a QUICC Engine.
1148 1148
1149config SERIAL_SC26XX
1150 tristate "SC2681/SC2692 serial port support"
1151 depends on SNI_RM
1152 select SERIAL_CORE
1153 help
1154 This is a driver for the onboard serial ports of
1155 older RM400 machines.
1156
1157config SERIAL_SC26XX_CONSOLE
1158 bool "Console on SC2681/SC2692 serial port"
1159 depends on SERIAL_SC26XX=y
1160 select SERIAL_CORE_CONSOLE
1161 help
1162 Support for Console on SC2681/SC2692 serial ports.
1163
1164config SERIAL_SCCNXP 1149config SERIAL_SCCNXP
1165 tristate "SCCNXP serial port support" 1150 tristate "SCCNXP serial port support"
1166 depends on !SERIAL_SC26XX
1167 select SERIAL_CORE 1151 select SERIAL_CORE
1168 default n
1169 help 1152 help
1170 This selects support for an advanced UART from NXP (Philips). 1153 This selects support for an advanced UART from NXP (Philips).
1171 Supported ICs are SCC2681, SCC2691, SCC2692, SC28L91, SC28L92, 1154 Supported ICs are SCC2681, SCC2691, SCC2692, SC28L91, SC28L92,
1172 SC28L202, SCC68681 and SCC68692. 1155 SC28L202, SCC68681 and SCC68692.
1173 Positioned as a replacement for the driver SC26XX.
1174 1156
1175config SERIAL_SCCNXP_CONSOLE 1157config SERIAL_SCCNXP_CONSOLE
1176 bool "Console on SCCNXP serial port" 1158 bool "Console on SCCNXP serial port"
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 3068c7722087..3680854fef41 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -47,7 +47,6 @@ obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o
47obj-$(CONFIG_SERIAL_MPSC) += mpsc.o 47obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
48obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o 48obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
49obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o 49obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
50obj-$(CONFIG_SERIAL_SC26XX) += sc26xx.o
51obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o 50obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o
52obj-$(CONFIG_SERIAL_JSM) += jsm/ 51obj-$(CONFIG_SERIAL_JSM) += jsm/
53obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o 52obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
diff --git a/drivers/tty/serial/sc26xx.c b/drivers/tty/serial/sc26xx.c
deleted file mode 100644
index 887b4f770749..000000000000
--- a/drivers/tty/serial/sc26xx.c
+++ /dev/null
@@ -1,749 +0,0 @@
1/*
2 * SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
3 *
4 * Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
5 */
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/errno.h>
10#include <linux/tty.h>
11#include <linux/tty_flip.h>
12#include <linux/major.h>
13#include <linux/circ_buf.h>
14#include <linux/serial.h>
15#include <linux/sysrq.h>
16#include <linux/console.h>
17#include <linux/spinlock.h>
18#include <linux/slab.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24
25#warning "Please try migrate to use new driver SCCNXP and report the status" \
26 "in the linux-serial mailing list."
27
28#if defined(CONFIG_MAGIC_SYSRQ)
29#define SUPPORT_SYSRQ
30#endif
31
32#include <linux/serial_core.h>
33
34#define SC26XX_MAJOR 204
35#define SC26XX_MINOR_START 205
36#define SC26XX_NR 2
37
38struct uart_sc26xx_port {
39 struct uart_port port[2];
40 u8 dsr_mask[2];
41 u8 cts_mask[2];
42 u8 dcd_mask[2];
43 u8 ri_mask[2];
44 u8 dtr_mask[2];
45 u8 rts_mask[2];
46 u8 imr;
47};
48
49/* register common to both ports */
50#define RD_ISR 0x14
51#define RD_IPR 0x34
52
53#define WR_ACR 0x10
54#define WR_IMR 0x14
55#define WR_OPCR 0x34
56#define WR_OPR_SET 0x38
57#define WR_OPR_CLR 0x3C
58
59/* access common register */
60#define READ_SC(p, r) readb((p)->membase + RD_##r)
61#define WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r)
62
63/* register per port */
64#define RD_PORT_MRx 0x00
65#define RD_PORT_SR 0x04
66#define RD_PORT_RHR 0x0c
67
68#define WR_PORT_MRx 0x00
69#define WR_PORT_CSR 0x04
70#define WR_PORT_CR 0x08
71#define WR_PORT_THR 0x0c
72
73/* SR bits */
74#define SR_BREAK (1 << 7)
75#define SR_FRAME (1 << 6)
76#define SR_PARITY (1 << 5)
77#define SR_OVERRUN (1 << 4)
78#define SR_TXRDY (1 << 2)
79#define SR_RXRDY (1 << 0)
80
81#define CR_RES_MR (1 << 4)
82#define CR_RES_RX (2 << 4)
83#define CR_RES_TX (3 << 4)
84#define CR_STRT_BRK (6 << 4)
85#define CR_STOP_BRK (7 << 4)
86#define CR_DIS_TX (1 << 3)
87#define CR_ENA_TX (1 << 2)
88#define CR_DIS_RX (1 << 1)
89#define CR_ENA_RX (1 << 0)
90
91/* ISR bits */
92#define ISR_RXRDYB (1 << 5)
93#define ISR_TXRDYB (1 << 4)
94#define ISR_RXRDYA (1 << 1)
95#define ISR_TXRDYA (1 << 0)
96
97/* IMR bits */
98#define IMR_RXRDY (1 << 1)
99#define IMR_TXRDY (1 << 0)
100
101/* access port register */
102static inline u8 read_sc_port(struct uart_port *p, u8 reg)
103{
104 return readb(p->membase + p->line * 0x20 + reg);
105}
106
107static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
108{
109 writeb(val, p->membase + p->line * 0x20 + reg);
110}
111
112#define READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r)
113#define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)
114
115static void sc26xx_enable_irq(struct uart_port *port, int mask)
116{
117 struct uart_sc26xx_port *up;
118 int line = port->line;
119
120 port -= line;
121 up = container_of(port, struct uart_sc26xx_port, port[0]);
122
123 up->imr |= mask << (line * 4);
124 WRITE_SC(port, IMR, up->imr);
125}
126
127static void sc26xx_disable_irq(struct uart_port *port, int mask)
128{
129 struct uart_sc26xx_port *up;
130 int line = port->line;
131
132 port -= line;
133 up = container_of(port, struct uart_sc26xx_port, port[0]);
134
135 up->imr &= ~(mask << (line * 4));
136 WRITE_SC(port, IMR, up->imr);
137}
138
139static bool receive_chars(struct uart_port *port)
140{
141 struct tty_port *tport = NULL;
142 int limit = 10000;
143 unsigned char ch;
144 char flag;
145 u8 status;
146
147 /* FIXME what is this trying to achieve? */
148 if (port->state != NULL) /* Unopened serial console */
149 tport = &port->state->port;