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-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv04.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv10.c16
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv20.c8
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv30.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv40.c32
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv50.c28
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nvc0.c18
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bus.h8
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c42
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h19
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c38
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c38
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c38
14 files changed, 133 insertions, 176 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
index 59dc340c6416..dbd2dde7b7e7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
@@ -51,7 +51,7 @@ nv04_identify(struct nouveau_device *device)
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
52 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass; 52 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass;
53 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 53 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
54 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 54 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
56 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; 56 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
57 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 57 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -69,7 +69,7 @@ nv04_identify(struct nouveau_device *device)
69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
70 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass; 70 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass;
71 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 71 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
72 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 72 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
74 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; 74 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
75 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 75 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
index a2f44b26fbfc..6e03dd6abeea 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
@@ -53,7 +53,7 @@ nv10_identify(struct nouveau_device *device)
53 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 53 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
54 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 54 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
55 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 55 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
56 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 56 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
57 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 57 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
58 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 58 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
59 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 59 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -70,7 +70,7 @@ nv10_identify(struct nouveau_device *device)
70 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 70 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
71 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
72 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 72 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
73 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 73 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
75 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 75 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
76 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 76 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -89,7 +89,7 @@ nv10_identify(struct nouveau_device *device)
89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
90 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 90 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
91 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 91 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
92 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 92 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
93 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 93 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
94 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 94 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
95 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 95 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -108,7 +108,7 @@ nv10_identify(struct nouveau_device *device)
108 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 108 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
109 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 109 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
110 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 110 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
111 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 111 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
113 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; 113 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
114 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 114 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -127,7 +127,7 @@ nv10_identify(struct nouveau_device *device)
127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
128 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 128 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
129 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 129 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
130 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 130 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
132 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 132 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
133 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -146,7 +146,7 @@ nv10_identify(struct nouveau_device *device)
146 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 146 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
147 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 147 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
148 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 148 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
149 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 149 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
151 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 151 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
152 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 152 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -165,7 +165,7 @@ nv10_identify(struct nouveau_device *device)
165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
166 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 166 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
167 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 167 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
168 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 168 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
170 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; 170 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
171 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 171 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -184,7 +184,7 @@ nv10_identify(struct nouveau_device *device)
184 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 184 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
185 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 185 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
186 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 186 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
187 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 187 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
189 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 189 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
190 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 190 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
index 4e02e0f87d06..dcde53b9f07f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
@@ -54,7 +54,7 @@ nv20_identify(struct nouveau_device *device)
54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
57 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
59 device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; 59 device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -73,7 +73,7 @@ nv20_identify(struct nouveau_device *device)
73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
74 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 74 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
76 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
78 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; 78 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -92,7 +92,7 @@ nv20_identify(struct nouveau_device *device)
92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
93 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
95 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
97 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; 97 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -111,7 +111,7 @@ nv20_identify(struct nouveau_device *device)
111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
112 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 112 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
113 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 113 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
114 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 114 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
115 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 115 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
116 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; 116 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
117 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 117 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
index 0be52b78139d..7b8662ef4f59 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
@@ -54,7 +54,7 @@ nv30_identify(struct nouveau_device *device)
54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
57 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
59 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; 59 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -73,7 +73,7 @@ nv30_identify(struct nouveau_device *device)
73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
74 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 74 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
76 device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass; 76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
78 device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; 78 device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -92,7 +92,7 @@ nv30_identify(struct nouveau_device *device)
92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
93 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
95 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
97 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; 97 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -112,7 +112,7 @@ nv30_identify(struct nouveau_device *device)
112 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 112 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
113 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 113 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
114 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 114 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
115 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 115 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
116 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 116 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
117 device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; 117 device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
118 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 118 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
@@ -132,7 +132,7 @@ nv30_identify(struct nouveau_device *device)
132 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 132 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
133 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 133 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
134 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 134 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
135 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 135 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
137 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 137 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
138 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; 138 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
index 0bf6066658b1..7bcc4c9ce13f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
@@ -57,7 +57,7 @@ nv40_identify(struct nouveau_device *device)
57 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 57 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
58 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 58 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
59 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 59 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
60 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 60 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
61 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 61 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
62 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; 62 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
63 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 63 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -78,7 +78,7 @@ nv40_identify(struct nouveau_device *device)
78 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 78 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
79 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 79 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
80 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 80 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
81 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 81 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
82 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 82 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
83 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; 83 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
84 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 84 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -99,7 +99,7 @@ nv40_identify(struct nouveau_device *device)
99 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 99 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
100 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 100 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
101 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 101 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
102 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 102 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
103 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 103 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
104 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; 104 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
105 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 105 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -120,7 +120,7 @@ nv40_identify(struct nouveau_device *device)
120 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 120 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
121 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 121 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
122 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 122 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
123 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 123 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
125 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; 125 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
126 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 126 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -141,7 +141,7 @@ nv40_identify(struct nouveau_device *device)
141 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 141 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
142 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 142 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
143 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 143 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
144 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 144 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
145 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 145 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
146 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; 146 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
147 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 147 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -162,7 +162,7 @@ nv40_identify(struct nouveau_device *device)
162 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 162 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
163 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 163 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
164 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 164 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
165 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 165 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
167 device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; 167 device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
168 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 168 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -183,7 +183,7 @@ nv40_identify(struct nouveau_device *device)
183 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 183 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
184 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 184 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
185 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 185 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
186 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 186 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
187 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 187 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
188 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; 188 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
189 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 189 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -204,7 +204,7 @@ nv40_identify(struct nouveau_device *device)
204 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 204 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
205 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 205 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
206 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 206 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
207 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 207 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
209 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; 209 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
210 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 210 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -225,7 +225,7 @@ nv40_identify(struct nouveau_device *device)
225 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 225 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
226 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 226 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
227 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 227 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
228 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 228 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
229 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 229 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
230 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; 230 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
231 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 231 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -246,7 +246,7 @@ nv40_identify(struct nouveau_device *device)
246 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 246 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
247 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 247 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
248 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 248 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
249 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 249 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
250 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 250 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
251 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 251 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
252 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 252 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -267,7 +267,7 @@ nv40_identify(struct nouveau_device *device)
267 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 267 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
268 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 268 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
269 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 269 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
270 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 270 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
271 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 271 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
272 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; 272 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
273 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 273 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -288,7 +288,7 @@ nv40_identify(struct nouveau_device *device)
288 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 288 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
289 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 289 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
290 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 290 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
291 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 291 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
292 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 292 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
293 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 293 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
294 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 294 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -309,7 +309,7 @@ nv40_identify(struct nouveau_device *device)
309 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 309 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
310 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 310 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
311 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 311 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
312 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 312 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
313 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 313 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
314 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; 314 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
315 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 315 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -330,7 +330,7 @@ nv40_identify(struct nouveau_device *device)
330 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 330 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
331 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 331 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
332 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 332 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
333 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 333 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
334 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 334 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
335 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 335 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
336 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 336 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -351,7 +351,7 @@ nv40_identify(struct nouveau_device *device)
351 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 351 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
352 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 352 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
353 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 353 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
354 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 354 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
355 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 355 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
356 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 356 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
357 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 357 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
@@ -372,7 +372,7 @@ nv40_identify(struct nouveau_device *device)
372 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 372 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
373 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 373 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
374 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 374 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
375 device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; 375 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
376 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 376 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
377 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 377 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
378 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; 378 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
index 536cacf9f5a6..cb6039c01a67 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
@@ -65,7 +65,7 @@ nv50_identify(struct nouveau_device *device)
65 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 65 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
66 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 66 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
67 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; 67 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
68 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 68 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
69 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 69 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
70 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; 70 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
71 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 71 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -88,7 +88,7 @@ nv50_identify(struct nouveau_device *device)
88 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 88 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
89 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 89 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
90 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; 90 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
91 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 91 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
92 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 92 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
93 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 93 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
94 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 94 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -114,7 +114,7 @@ nv50_identify(struct nouveau_device *device)
114 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 114 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
115 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 115 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
116 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; 116 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
117 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 117 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
118 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 118 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
119 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 119 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
120 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 120 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -140,7 +140,7 @@ nv50_identify(struct nouveau_device *device)
140 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 140 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
141 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 141 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
142 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; 142 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
143 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 143 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
144 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 144 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
145 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 145 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
146 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 146 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -166,7 +166,7 @@ nv50_identify(struct nouveau_device *device)
166 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 166 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
167 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 167 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
168 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; 168 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
169 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 169 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
170 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 170 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
171 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 171 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
172 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 172 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -192,7 +192,7 @@ nv50_identify(struct nouveau_device *device)
192 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 192 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
193 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 193 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
194 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; 194 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
195 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 195 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
196 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 196 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
197 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 197 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
198 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 198 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -218,7 +218,7 @@ nv50_identify(struct nouveau_device *device)
218 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 218 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
219 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 219 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
220 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 220 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
221 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 221 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
222 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 222 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
223 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 223 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
224 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 224 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -244,7 +244,7 @@ nv50_identify(struct nouveau_device *device)
244 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 244 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
245 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 245 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
246 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 246 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
247 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 247 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
248 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 248 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
249 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; 249 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
250 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 250 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -270,7 +270,7 @@ nv50_identify(struct nouveau_device *device)
270 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 270 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
271 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 271 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
272 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 272 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
273 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 273 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
274 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 274 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
275 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; 275 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
276 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 276 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -296,7 +296,7 @@ nv50_identify(struct nouveau_device *device)
296 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 296 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
297 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 297 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
298 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 298 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
299 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 299 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
300 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 300 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
301 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; 301 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
302 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 302 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -322,7 +322,7 @@ nv50_identify(struct nouveau_device *device)
322 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 322 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
323 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; 323 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
324 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 324 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
325 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 325 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
326 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 326 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
327 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; 327 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
328 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 328 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -350,7 +350,7 @@ nv50_identify(struct nouveau_device *device)
350 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 350 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
351 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; 351 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
352 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 352 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
353 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 353 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
354 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 354 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
355 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; 355 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
356 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 356 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -377,7 +377,7 @@ nv50_identify(struct nouveau_device *device)
377 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 377 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
378 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; 378 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
379 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 379 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
380 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 380 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
381 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 381 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
382 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; 382 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
383 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 383 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device)
404 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 404 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
405 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; 405 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
406 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 406 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
407 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass; 407 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
409 device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; 409 device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
410 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 410 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index e4947914f979..7db87cf231c7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -65,7 +65,7 @@ nvc0_identify(struct nouveau_device *device)
65 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 65 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
66 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 66 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
67 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; 67 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
68 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 68 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
69 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 69 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
70 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 70 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
71 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 71 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -95,7 +95,7 @@ nvc0_identify(struct nouveau_device *device)
95 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 95 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
96 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 96 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
97 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; 97 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
98 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 98 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
99 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 99 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
100 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 100 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
101 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 101 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -125,7 +125,7 @@ nvc0_identify(struct nouveau_device *device)
125 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 125 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
126 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 126 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
127 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 127 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
128 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 128 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
129 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 129 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
130 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 130 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
131 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 131 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -154,7 +154,7 @@ nvc0_identify(struct nouveau_device *device)
154 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 154 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
155 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 155 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
156 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 156 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
157 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 157 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
158 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 158 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
159 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 159 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
160 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 160 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device)
184 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 184 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
185 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 185 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
186 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 186 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
187 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 187 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
189 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 189 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
190 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 190 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device)
214 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 214 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
215 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 215 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
216 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 216 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
217 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 217 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
218 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 218 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
219 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 219 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
220 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 220 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -243,7 +243,7 @@ nvc0_identify(struct nouveau_device *device)
243 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 243 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
244 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 244 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
245 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 245 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
246 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 246 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
248 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 248 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
249 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 249 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -273,7 +273,7 @@ nvc0_identify(struct nouveau_device *device)
273 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 273 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
274 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 274 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
275 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 275 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
276 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 276 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
277 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 277 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
278 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 278 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
279 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 279 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -302,7 +302,7 @@ nvc0_identify(struct nouveau_device *device)
302 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 302 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
303 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 303 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
304 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 304 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
305 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 305 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
306 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 306 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
307 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 307 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
308 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 308 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index e6254a64e9fb..90b095c0875f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -65,7 +65,7 @@ nve0_identify(struct nouveau_device *device)
65 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 65 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
66 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 66 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
67 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 67 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
68 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 68 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
69 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 69 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
70 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 70 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
71 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 71 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -96,7 +96,7 @@ nve0_identify(struct nouveau_device *device)
96 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 96 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
97 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 97 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
98 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 98 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
99 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 99 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
100 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 100 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
101 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 101 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
102 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 102 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -127,7 +127,7 @@ nve0_identify(struct nouveau_device *device)
127 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 127 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
128 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 128 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
129 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 129 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
130 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 130 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
132 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 132 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
133 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 133 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device)
158 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 158 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
159 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 159 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
160 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 160 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
161 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 161 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
162 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 162 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
163 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 163 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
164 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 164 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
@@ -191,7 +191,7 @@ nve0_identify(struct nouveau_device *device)
191 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 191 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
192 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 192 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
193 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 193 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
194 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; 194 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
195 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 195 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
196 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; 196 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
197 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; 197 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h b/drivers/gpu/drm/nouveau/core/include/subdev/bus.h
index 7d88ec4a6d06..837401d41e7d 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bus.h
@@ -33,9 +33,9 @@ nouveau_bus(void *obj)
33#define _nouveau_bus_init _nouveau_subdev_init 33#define _nouveau_bus_init _nouveau_subdev_init
34#define _nouveau_bus_fini _nouveau_subdev_fini 34#define _nouveau_bus_fini _nouveau_subdev_fini
35 35
36extern struct nouveau_oclass nv04_bus_oclass; 36extern struct nouveau_oclass *nv04_bus_oclass;
37extern struct nouveau_oclass nv31_bus_oclass; 37extern struct nouveau_oclass *nv31_bus_oclass;
38extern struct nouveau_oclass nv50_bus_oclass; 38extern struct nouveau_oclass *nv50_bus_oclass;
39extern struct nouveau_oclass nvc0_bus_oclass; 39extern struct nouveau_oclass *nvc0_bus_oclass;
40 40
41#endif 41#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
index 8c7f8057a185..478209930dcd 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
@@ -23,11 +23,7 @@
23 * Ben Skeggs 23 * Ben Skeggs
24 */ 24 */
25 25
26#include <subdev/bus.h> 26#include "nv04.h"
27
28struct nv04_bus_priv {
29 struct nouveau_bus base;
30};
31 27
32static void 28static void
33nv04_bus_intr(struct nouveau_subdev *subdev) 29nv04_bus_intr(struct nouveau_subdev *subdev)
@@ -56,10 +52,22 @@ nv04_bus_intr(struct nouveau_subdev *subdev)
56} 52}
57 53
58static int 54static int
55nv04_bus_init(struct nouveau_object *object)
56{
57 struct nv04_bus_priv *priv = (void *)object;
58
59 nv_wr32(priv, 0x001100, 0xffffffff);
60 nv_wr32(priv, 0x001140, 0x00000111);
61
62 return nouveau_bus_init(&priv->base);
63}
64
65int
59nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 66nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
60 struct nouveau_oclass *oclass, void *data, u32 size, 67 struct nouveau_oclass *oclass, void *data, u32 size,
61 struct nouveau_object **pobject) 68 struct nouveau_object **pobject)
62{ 69{
70 struct nv04_bus_impl *impl = (void *)oclass;
63 struct nv04_bus_priv *priv; 71 struct nv04_bus_priv *priv;
64 int ret; 72 int ret;
65 73
@@ -68,28 +76,18 @@ nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
68 if (ret) 76 if (ret)
69 return ret; 77 return ret;
70 78
71 nv_subdev(priv)->intr = nv04_bus_intr; 79 nv_subdev(priv)->intr = impl->intr;
72 return 0; 80 return 0;
73} 81}
74 82
75static int 83struct nouveau_oclass *
76nv04_bus_init(struct nouveau_object *object) 84nv04_bus_oclass = &(struct nv04_bus_impl) {
77{ 85 .base.handle = NV_SUBDEV(BUS, 0x04),
78 struct nv04_bus_priv *priv = (void *)object; 86 .base.ofuncs = &(struct nouveau_ofuncs) {
79
80 nv_wr32(priv, 0x001100, 0xffffffff);
81 nv_wr32(priv, 0x001140, 0x00000111);
82
83 return nouveau_bus_init(&priv->base);
84}
85
86struct nouveau_oclass
87nv04_bus_oclass = {
88 .handle = NV_SUBDEV(BUS, 0x04),
89 .ofuncs = &(struct nouveau_ofuncs) {
90 .ctor = nv04_bus_ctor, 87 .ctor = nv04_bus_ctor,
91 .dtor = _nouveau_bus_dtor, 88 .dtor = _nouveau_bus_dtor,
92 .init = nv04_bus_init, 89 .init = nv04_bus_init,
93 .fini = _nouveau_bus_fini, 90 .fini = _nouveau_bus_fini,
94 }, 91 },
95}; 92 .intr = nv04_bus_intr,
93}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h
new file mode 100644
index 000000000000..0ac589d26a4c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h
@@ -0,0 +1,19 @@
1#ifndef __NVKM_BUS_NV04_H__
2#define __NVKM_BUS_NV04_H__
3
4#include <subdev/bus.h>
5
6struct nv04_bus_priv {
7 struct nouveau_bus base;
8};
9
10int nv04_bus_ctor(struct nouveau_object *, struct nouveau_object *,
11 struct nouveau_oclass *, void *, u32,
12 struct nouveau_object **);
13
14struct nv04_bus_impl {
15 struct nouveau_oclass base;
16 void (*intr)(struct nouveau_subdev *);
17};
18
19#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
index 34132aef34e1..94da46f61627 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
@@ -23,11 +23,7 @@
23 * Ben Skeggs 23 * Ben Skeggs
24 */ 24 */
25 25
26#include <subdev/bus.h> 26#include "nv04.h"
27
28struct nv31_bus_priv {
29 struct nouveau_bus base;
30};
31 27
32static void 28static void
33nv31_bus_intr(struct nouveau_subdev *subdev) 29nv31_bus_intr(struct nouveau_subdev *subdev)
@@ -71,7 +67,7 @@ nv31_bus_intr(struct nouveau_subdev *subdev)
71static int 67static int
72nv31_bus_init(struct nouveau_object *object) 68nv31_bus_init(struct nouveau_object *object)
73{ 69{
74 struct nv31_bus_priv *priv = (void *)object; 70 struct nv04_bus_priv *priv = (void *)object;
75 int ret; 71 int ret;
76 72
77 ret = nouveau_bus_init(&priv->base); 73 ret = nouveau_bus_init(&priv->base);
@@ -83,30 +79,14 @@ nv31_bus_init(struct nouveau_object *object)
83 return 0; 79 return 0;
84} 80}
85 81
86static int 82struct nouveau_oclass *
87nv31_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 83nv31_bus_oclass = &(struct nv04_bus_impl) {
88 struct nouveau_oclass *oclass, void *data, u32 size, 84 .base.handle = NV_SUBDEV(BUS, 0x31),
89 struct nouveau_object **pobject) 85 .base.ofuncs = &(struct nouveau_ofuncs) {
90{ 86 .ctor = nv04_bus_ctor,
91 struct nv31_bus_priv *priv;
92 int ret;
93
94 ret = nouveau_bus_create(parent, engine, oclass, &priv);
95 *pobject = nv_object(priv);
96 if (ret)
97 return ret;
98
99 nv_subdev(priv)->intr = nv31_bus_intr;
100 return 0;
101}
102
103struct nouveau_oclass
104nv31_bus_oclass = {
105 .handle = NV_SUBDEV(BUS, 0x31),
106 .ofuncs = &(struct nouveau_ofuncs) {
107 .ctor = nv31_bus_ctor,
108 .dtor = _nouveau_bus_dtor, 87 .dtor = _nouveau_bus_dtor,
109 .init = nv31_bus_init, 88 .init = nv31_bus_init,
110 .fini = _nouveau_bus_fini, 89 .fini = _nouveau_bus_fini,
111 }, 90 },
112}; 91 .intr = nv31_bus_intr,
92}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
index f5b2117fa8c6..cda534790d1d 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
@@ -23,11 +23,7 @@
23 * Ben Skeggs 23 * Ben Skeggs
24 */ 24 */
25 25
26#include <subdev/bus.h> 26#include "nv04.h"
27
28struct nv50_bus_priv {
29 struct nouveau_bus base;
30};
31 27
32static void 28static void
33nv50_bus_intr(struct nouveau_subdev *subdev) 29nv50_bus_intr(struct nouveau_subdev *subdev)
@@ -64,7 +60,7 @@ nv50_bus_intr(struct nouveau_subdev *subdev)
64static int 60static int
65nv50_bus_init(struct nouveau_object *object) 61nv50_bus_init(struct nouveau_object *object)
66{ 62{
67 struct nv50_bus_priv *priv = (void *)object; 63 struct nv04_bus_priv *priv = (void *)object;
68 int ret; 64 int ret;
69 65
70 ret = nouveau_bus_init(&priv->base); 66 ret = nouveau_bus_init(&priv->base);
@@ -76,30 +72,14 @@ nv50_bus_init(struct nouveau_object *object)
76 return 0; 72 return 0;
77} 73}
78 74
79static int 75struct nouveau_oclass *
80nv50_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 76nv50_bus_oclass = &(struct nv04_bus_impl) {
81 struct nouveau_oclass *oclass, void *data, u32 size, 77 .base.handle = NV_SUBDEV(BUS, 0x50),
82 struct nouveau_object **pobject) 78 .base.ofuncs = &(struct nouveau_ofuncs) {
83{ 79 .ctor = nv04_bus_ctor,
84 struct nv50_bus_priv *priv;
85 int ret;
86
87 ret = nouveau_bus_create(parent, engine, oclass, &priv);
88 *pobject = nv_object(priv);
89 if (ret)
90 return ret;
91
92 nv_subdev(priv)->intr = nv50_bus_intr;
93 return 0;
94}
95
96struct nouveau_oclass
97nv50_bus_oclass = {
98 .handle = NV_SUBDEV(BUS, 0x50),
99 .ofuncs = &(struct nouveau_ofuncs) {
100 .ctor = nv50_bus_ctor,
101 .dtor = _nouveau_bus_dtor, 80 .dtor = _nouveau_bus_dtor,
102 .init = nv50_bus_init, 81 .init = nv50_bus_init,
103 .fini = _nouveau_bus_fini, 82 .fini = _nouveau_bus_fini,
104 }, 83 },
105}; 84 .intr = nv50_bus_intr,
85}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
index b192d6246363..73839d7151a7 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
@@ -23,11 +23,7 @@
23 * Ben Skeggs 23 * Ben Skeggs
24 */ 24 */
25 25
26#include <subdev/bus.h> 26#include "nv04.h"
27
28struct nvc0_bus_priv {
29 struct nouveau_bus base;
30};
31 27
32static void 28static void
33nvc0_bus_intr(struct nouveau_subdev *subdev) 29nvc0_bus_intr(struct nouveau_subdev *subdev)
@@ -60,7 +56,7 @@ nvc0_bus_intr(struct nouveau_subdev *subdev)
60static int 56static int
61nvc0_bus_init(struct nouveau_object *object) 57nvc0_bus_init(struct nouveau_object *object)
62{ 58{
63 struct nvc0_bus_priv *priv = (void *)object; 59 struct nv04_bus_priv *priv = (void *)object;
64 int ret; 60 int ret;
65 61
66 ret = nouveau_bus_init(&priv->base); 62 ret = nouveau_bus_init(&priv->base);
@@ -72,30 +68,14 @@ nvc0_bus_init(struct nouveau_object *object)
72 return 0; 68 return 0;
73} 69}
74 70
75static int 71struct nouveau_oclass *
76nvc0_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 72nvc0_bus_oclass = &(struct nv04_bus_impl) {
77 struct nouveau_oclass *oclass, void *data, u32 size, 73 .base.handle = NV_SUBDEV(BUS, 0xc0),
78 struct nouveau_object **pobject) 74 .base.ofuncs = &(struct nouveau_ofuncs) {
79{ 75 .ctor = nv04_bus_ctor,
80 struct nvc0_bus_priv *priv;
81 int ret;
82
83 ret = nouveau_bus_create(parent, engine, oclass, &priv);
84 *pobject = nv_object(priv);
85 if (ret)
86 return ret;
87
88 nv_subdev(priv)->intr = nvc0_bus_intr;
89 return 0;
90}
91
92struct nouveau_oclass
93nvc0_bus_oclass = {
94 .handle = NV_SUBDEV(BUS, 0xc0),
95 .ofuncs = &(struct nouveau_ofuncs) {
96 .ctor = nvc0_bus_ctor,
97 .dtor = _nouveau_bus_dtor, 76 .dtor = _nouveau_bus_dtor,
98 .init = nvc0_bus_init, 77 .init = nvc0_bus_init,
99 .fini = _nouveau_bus_fini, 78 .fini = _nouveau_bus_fini,
100 }, 79 },
101}; 80 .intr = nvc0_bus_intr,
81}.base;
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 11:22:00 -0400