diff options
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-shx3.c | 66 |
1 files changed, 14 insertions, 52 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c index 1afdb93b8ccb..a9ba4f1851d1 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c | |||
@@ -101,6 +101,7 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
101 | }; | 101 | }; |
102 | 102 | ||
103 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 103 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
104 | #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } | ||
104 | 105 | ||
105 | static struct clk_lookup lookups[] = { | 106 | static struct clk_lookup lookups[] = { |
106 | /* main clocks */ | 107 | /* main clocks */ |
@@ -116,62 +117,23 @@ static struct clk_lookup lookups[] = { | |||
116 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | 117 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), |
117 | 118 | ||
118 | /* MSTP32 clocks */ | 119 | /* MSTP32 clocks */ |
119 | { | 120 | CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]), |
120 | /* SCIF3 */ | 121 | CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]), |
121 | .dev_id = "sh-sci.3", | 122 | CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]), |
122 | .con_id = "sci_fck", | 123 | CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]), |
123 | .clk = &mstp_clks[MSTP027], | 124 | |
124 | }, { | ||
125 | /* SCIF2 */ | ||
126 | .dev_id = "sh-sci.2", | ||
127 | .con_id = "sci_fck", | ||
128 | .clk = &mstp_clks[MSTP026], | ||
129 | }, { | ||
130 | /* SCIF1 */ | ||
131 | .dev_id = "sh-sci.1", | ||
132 | .con_id = "sci_fck", | ||
133 | .clk = &mstp_clks[MSTP025], | ||
134 | }, { | ||
135 | /* SCIF0 */ | ||
136 | .dev_id = "sh-sci.0", | ||
137 | .con_id = "sci_fck", | ||
138 | .clk = &mstp_clks[MSTP024], | ||
139 | }, | ||
140 | CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]), | 125 | CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]), |
141 | CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]), | 126 | CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]), |
142 | CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]), | 127 | CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]), |
143 | CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]), | 128 | CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]), |
144 | { | 129 | |
145 | /* TMU0 */ | 130 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP008]), |
146 | .dev_id = "sh_tmu.0", | 131 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP008]), |
147 | .con_id = "tmu_fck", | 132 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP008]), |
148 | .clk = &mstp_clks[MSTP008], | 133 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP009]), |
149 | }, { | 134 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP009]), |
150 | /* TMU1 */ | 135 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP009]), |
151 | .dev_id = "sh_tmu.1", | 136 | |
152 | .con_id = "tmu_fck", | ||
153 | .clk = &mstp_clks[MSTP008], | ||
154 | }, { | ||
155 | /* TMU2 */ | ||
156 | .dev_id = "sh_tmu.2", | ||
157 | .con_id = "tmu_fck", | ||
158 | .clk = &mstp_clks[MSTP008], | ||
159 | }, { | ||
160 | /* TMU3 */ | ||
161 | .dev_id = "sh_tmu.3", | ||
162 | .con_id = "tmu_fck", | ||
163 | .clk = &mstp_clks[MSTP009], | ||
164 | }, { | ||
165 | /* TMU4 */ | ||
166 | .dev_id = "sh_tmu.4", | ||
167 | .con_id = "tmu_fck", | ||
168 | .clk = &mstp_clks[MSTP009], | ||
169 | }, { | ||
170 | /* TMU5 */ | ||
171 | .dev_id = "sh_tmu.5", | ||
172 | .con_id = "tmu_fck", | ||
173 | .clk = &mstp_clks[MSTP009], | ||
174 | }, | ||
175 | CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), | 137 | CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), |
176 | CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), | 138 | CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), |
177 | CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), | 139 | CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), |