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-rw-r--r--drivers/gpu/drm/nouveau/Makefile2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_object.c132
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ramht.c160
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ramht.h31
4 files changed, 193 insertions, 132 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index e9b06e4ef2a2..d6cfbf259876 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -9,7 +9,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \ 9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \ 10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
11 nouveau_display.o nouveau_connector.o nouveau_fbcon.o \ 11 nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
12 nouveau_dp.o \ 12 nouveau_dp.o nouveau_ramht.o \
13 nv04_timer.o \ 13 nv04_timer.o \
14 nv04_mc.o nv40_mc.o nv50_mc.o \ 14 nv04_mc.o nv40_mc.o nv50_mc.o \
15 nv04_fb.o nv10_fb.o nv30_fb.o nv40_fb.o nv50_fb.o nvc0_fb.o \ 15 nv04_fb.o nv10_fb.o nv30_fb.o nv40_fb.o nv50_fb.o nvc0_fb.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index b6bcb254f4ab..e658aa2dbe67 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -34,6 +34,7 @@
34#include "drm.h" 34#include "drm.h"
35#include "nouveau_drv.h" 35#include "nouveau_drv.h"
36#include "nouveau_drm.h" 36#include "nouveau_drm.h"
37#include "nouveau_ramht.h"
37 38
38/* NVidia uses context objects to drive drawing operations. 39/* NVidia uses context objects to drive drawing operations.
39 40
@@ -65,137 +66,6 @@
65 The key into the hash table depends on the object handle and channel id and 66 The key into the hash table depends on the object handle and channel id and
66 is given as: 67 is given as:
67*/ 68*/
68static uint32_t
69nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)
70{
71 struct drm_nouveau_private *dev_priv = dev->dev_private;
72 uint32_t hash = 0;
73 int i;
74
75 NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle);
76
77 for (i = 32; i > 0; i -= dev_priv->ramht_bits) {
78 hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
79 handle >>= dev_priv->ramht_bits;
80 }
81
82 if (dev_priv->card_type < NV_50)
83 hash ^= channel << (dev_priv->ramht_bits - 4);
84 hash <<= 3;
85
86 NV_DEBUG(dev, "hash=0x%08x\n", hash);
87 return hash;
88}
89
90static int
91nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
92 uint32_t offset)
93{
94 struct drm_nouveau_private *dev_priv = dev->dev_private;
95 uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4);
96
97 if (dev_priv->card_type < NV_40)
98 return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
99 return (ctx != 0);
100}
101
102static int
103nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
104{
105 struct drm_nouveau_private *dev_priv = dev->dev_private;
106 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
107 struct nouveau_channel *chan = ref->channel;
108 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
109 uint32_t ctx, co, ho;
110
111 if (!ramht) {
112 NV_ERROR(dev, "No hash table!\n");
113 return -EINVAL;
114 }
115
116 if (dev_priv->card_type < NV_40) {
117 ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) |
118 (chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
119 (ref->gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
120 } else
121 if (dev_priv->card_type < NV_50) {
122 ctx = (ref->instance >> 4) |
123 (chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
124 (ref->gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
125 } else {
126 if (ref->gpuobj->engine == NVOBJ_ENGINE_DISPLAY) {
127 ctx = (ref->instance << 10) | 2;
128 } else {
129 ctx = (ref->instance >> 4) |
130 ((ref->gpuobj->engine <<
131 NV40_RAMHT_CONTEXT_ENGINE_SHIFT));
132 }
133 }
134
135 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
136 do {
137 if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
138 NV_DEBUG(dev,
139 "insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
140 chan->id, co, ref->handle, ctx);
141 nv_wo32(dev, ramht, (co + 0)/4, ref->handle);
142 nv_wo32(dev, ramht, (co + 4)/4, ctx);
143
144 list_add_tail(&ref->list, &chan->ramht_refs);
145 instmem->flush(dev);
146 return 0;
147 }
148 NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
149 chan->id, co, nv_ro32(dev, ramht, co/4));
150
151 co += 8;
152 if (co >= dev_priv->ramht_size)
153 co = 0;
154 } while (co != ho);
155
156 NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);
157 return -ENOMEM;
158}
159
160static void
161nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
162{
163 struct drm_nouveau_private *dev_priv = dev->dev_private;
164 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
165 struct nouveau_channel *chan = ref->channel;
166 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
167 uint32_t co, ho;
168
169 if (!ramht) {
170 NV_ERROR(dev, "No hash table!\n");
171 return;
172 }
173
174 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
175 do {
176 if (nouveau_ramht_entry_valid(dev, ramht, co) &&
177 (ref->handle == nv_ro32(dev, ramht, (co/4)))) {
178 NV_DEBUG(dev,
179 "remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
180 chan->id, co, ref->handle,
181 nv_ro32(dev, ramht, (co + 4)));
182 nv_wo32(dev, ramht, (co + 0)/4, 0x00000000);
183 nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);
184
185 list_del(&ref->list);
186 instmem->flush(dev);
187 return;
188 }
189
190 co += 8;
191 if (co >= dev_priv->ramht_size)
192 co = 0;
193 } while (co != ho);
194 list_del(&ref->list);
195
196 NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",
197 chan->id, ref->handle);
198}
199 69
200int 70int
201nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, 71nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
diff --git a/drivers/gpu/drm/nouveau/nouveau_ramht.c b/drivers/gpu/drm/nouveau/nouveau_ramht.c
new file mode 100644
index 000000000000..8b27ee5411b3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_ramht.c
@@ -0,0 +1,160 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_ramht.h"
29
30static uint32_t
31nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)
32{
33 struct drm_nouveau_private *dev_priv = dev->dev_private;
34 uint32_t hash = 0;
35 int i;
36
37 NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle);
38
39 for (i = 32; i > 0; i -= dev_priv->ramht_bits) {
40 hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
41 handle >>= dev_priv->ramht_bits;
42 }
43
44 if (dev_priv->card_type < NV_50)
45 hash ^= channel << (dev_priv->ramht_bits - 4);
46 hash <<= 3;
47
48 NV_DEBUG(dev, "hash=0x%08x\n", hash);
49 return hash;
50}
51
52static int
53nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
54 uint32_t offset)
55{
56 struct drm_nouveau_private *dev_priv = dev->dev_private;
57 uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4);
58
59 if (dev_priv->card_type < NV_40)
60 return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
61 return (ctx != 0);
62}
63
64int
65nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
66{
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
69 struct nouveau_channel *chan = ref->channel;
70 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
71 uint32_t ctx, co, ho;
72
73 if (!ramht) {
74 NV_ERROR(dev, "No hash table!\n");
75 return -EINVAL;
76 }
77
78 if (dev_priv->card_type < NV_40) {
79 ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) |
80 (chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
81 (ref->gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
82 } else
83 if (dev_priv->card_type < NV_50) {
84 ctx = (ref->instance >> 4) |
85 (chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
86 (ref->gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
87 } else {
88 if (ref->gpuobj->engine == NVOBJ_ENGINE_DISPLAY) {
89 ctx = (ref->instance << 10) | 2;
90 } else {
91 ctx = (ref->instance >> 4) |
92 ((ref->gpuobj->engine <<
93 NV40_RAMHT_CONTEXT_ENGINE_SHIFT));
94 }
95 }
96
97 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
98 do {
99 if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
100 NV_DEBUG(dev,
101 "insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
102 chan->id, co, ref->handle, ctx);
103 nv_wo32(dev, ramht, (co + 0)/4, ref->handle);
104 nv_wo32(dev, ramht, (co + 4)/4, ctx);
105
106 list_add_tail(&ref->list, &chan->ramht_refs);
107 instmem->flush(dev);
108 return 0;
109 }
110 NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
111 chan->id, co, nv_ro32(dev, ramht, co/4));
112
113 co += 8;
114 if (co >= dev_priv->ramht_size)
115 co = 0;
116 } while (co != ho);
117
118 NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);
119 return -ENOMEM;
120}
121
122void
123nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
124{
125 struct drm_nouveau_private *dev_priv = dev->dev_private;
126 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
127 struct nouveau_channel *chan = ref->channel;
128 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
129 uint32_t co, ho;
130
131 if (!ramht) {
132 NV_ERROR(dev, "No hash table!\n");
133 return;
134 }
135
136 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
137 do {
138 if (nouveau_ramht_entry_valid(dev, ramht, co) &&
139 (ref->handle == nv_ro32(dev, ramht, (co/4)))) {
140 NV_DEBUG(dev,
141 "remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
142 chan->id, co, ref->handle,
143 nv_ro32(dev, ramht, (co + 4)));
144 nv_wo32(dev, ramht, (co + 0)/4, 0x00000000);
145 nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);
146
147 list_del(&ref->list);
148 instmem->flush(dev);
149 return;
150 }
151
152 co += 8;
153 if (co >= dev_priv->ramht_size)
154 co = 0;
155 } while (co != ho);
156 list_del(&ref->list);
157
158 NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",
159 chan->id, ref->handle);
160}
diff --git a/drivers/gpu/drm/nouveau/nouveau_ramht.h b/drivers/gpu/drm/nouveau/nouveau_ramht.h
new file mode 100644
index 000000000000..e10455c6e7ff
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_ramht.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifndef __NOUVEAU_RAMHT_H__
26#define __NOUVEAU_RAMHT_H__
27
28extern int nouveau_ramht_insert(struct drm_device *, struct nouveau_gpuobj_ref *);
29extern void nouveau_ramht_remove(struct drm_device *, struct nouveau_gpuobj_ref *);
30
31#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 21:11:20 -0500