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-rw-r--r--Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt19
-rw-r--r--Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt21
-rw-r--r--Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt23
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Kconfig.debug38
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts84
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts59
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts65
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi147
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts9
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts54
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts149
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts136
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi167
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts6
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts6
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi84
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi179
-rw-r--r--arch/arm/include/debug/tegra.S223
-rw-r--r--arch/arm/mach-tegra/Kconfig51
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/apbio.c5
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c27
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c28
-rw-r--r--arch/arm/mach-tegra/clock.c2
-rw-r--r--arch/arm/mach-tegra/common.c28
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c3
-rw-r--r--arch/arm/mach-tegra/cpuidle.c2
-rw-r--r--arch/arm/mach-tegra/flowctrl.c3
-rw-r--r--arch/arm/mach-tegra/fuse.c52
-rw-r--r--arch/arm/mach-tegra/fuse.h16
-rw-r--r--arch/arm/mach-tegra/headsmp.S3
-rw-r--r--arch/arm/mach-tegra/include/mach/debug-macro.S100
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h54
-rw-r--r--arch/arm/mach-tegra/include/mach/irqs.h182
-rw-r--r--arch/arm/mach-tegra/include/mach/powergate.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/uncompress.h67
-rw-r--r--arch/arm/mach-tegra/io.c3
-rw-r--r--arch/arm/mach-tegra/iomap.h (renamed from arch/arm/mach-tegra/include/mach/iomap.h)16
-rw-r--r--arch/arm/mach-tegra/irammap.h (renamed from arch/arm/mach-tegra/include/mach/irammap.h)9
-rw-r--r--arch/arm/mach-tegra/irq.c3
-rw-r--r--arch/arm/mach-tegra/pcie.c5
-rw-r--r--arch/arm/mach-tegra/platsmp.c3
-rw-r--r--arch/arm/mach-tegra/pmc.c2
-rw-r--r--arch/arm/mach-tegra/powergate.c2
-rw-r--r--arch/arm/mach-tegra/reset.c5
-rw-r--r--arch/arm/mach-tegra/sleep-t20.S2
-rw-r--r--arch/arm/mach-tegra/sleep-t30.S2
-rw-r--r--arch/arm/mach-tegra/sleep.S2
-rw-r--r--arch/arm/mach-tegra/sleep.h2
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.c3
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c13
-rw-r--r--arch/arm/mach-tegra/tegra20_speedo.c109
-rw-r--r--arch/arm/mach-tegra/tegra2_emc.c2
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c109
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.h1
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c51
-rw-r--r--arch/arm/mach-tegra/tegra30_speedo.c292
-rw-r--r--arch/arm/mach-tegra/timer.c78
-rw-r--r--drivers/amba/tegra-ahb.c1
-rw-r--r--drivers/crypto/tegra-aes.c2
-rw-r--r--drivers/iommu/tegra-smmu.c4
-rw-r--r--drivers/staging/nvec/nvec.c1
-rw-r--r--drivers/usb/host/ehci-tegra.c5
-rw-r--r--drivers/usb/phy/tegra_usb_phy.c4
-rw-r--r--include/linux/tegra-ahb.h (renamed from arch/arm/mach-tegra/include/mach/tegra-ahb.h)6
-rw-r--r--sound/soc/tegra/tegra30_ahub.c1
-rw-r--r--sound/soc/tegra/tegra_pcm.h2
70 files changed, 1878 insertions, 966 deletions
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
new file mode 100644
index 000000000000..93f45e9dce7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
@@ -0,0 +1,19 @@
1NVIDIA Tegra20 real-time clock
2
3The Tegra RTC maintains seconds and milliseconds counters, and five alarm
4registers. The alarms and other interrupts may wake the system from low-power
5state.
6
7Required properties:
8
9- compatible : should be "nvidia,tegra20-rtc".
10- reg : Specifies base physical address and size of the registers.
11- interrupts : A single interrupt specifier.
12
13Example:
14
15timer {
16 compatible = "nvidia,tegra20-rtc";
17 reg = <0x7000e000 0x100>;
18 interrupts = <0 2 0x04>;
19};
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
new file mode 100644
index 000000000000..e019fdc38773
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
@@ -0,0 +1,21 @@
1NVIDIA Tegra20 timer
2
3The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
4running counter. The first two channels may also trigger a watchdog reset.
5
6Required properties:
7
8- compatible : should be "nvidia,tegra20-timer".
9- reg : Specifies base physical address and size of the registers.
10- interrupts : A list of 4 interrupts; one per timer channel.
11
12Example:
13
14timer {
15 compatible = "nvidia,tegra20-timer";
16 reg = <0x60005000 0x60>;
17 interrupts = <0 0 0x04
18 0 1 0x04
19 0 41 0x04
20 0 42 0x04>;
21};
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
new file mode 100644
index 000000000000..906109d4c593
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -0,0 +1,23 @@
1NVIDIA Tegra30 timer
2
3The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
4running counter, and 5 watchdog modules. The first two channels may also
5trigger a legacy watchdog reset.
6
7Required properties:
8
9- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
10- reg : Specifies base physical address and size of the registers.
11- interrupts : A list of 6 interrupts; one per each of timer channels 1
12 through 5, and one for the shared interrupt for the remaining channels.
13
14timer {
15 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
16 reg = <0x60005000 0x400>;
17 interrupts = <0 0 0x04
18 0 1 0x04
19 0 41 0x04
20 0 42 0x04
21 0 121 0x04
22 0 122 0x04>;
23};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 9de2b9ff9d6e..ac2c2c416a14 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -51,4 +51,5 @@ ti Texas Instruments
51via VIA Technologies, Inc. 51via VIA Technologies, Inc.
52wlf Wolfson Microelectronics 52wlf Wolfson Microelectronics
53wm Wondermedia Technologies, Inc. 53wm Wondermedia Technologies, Inc.
54winbond Winbond Electronics corp.
54xlnx Xilinx 55xlnx Xilinx
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 48982dc89ffc..9277f503481c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -644,6 +644,7 @@ config ARCH_TEGRA
644 select HAVE_CLK 644 select HAVE_CLK
645 select HAVE_SMP 645 select HAVE_SMP
646 select MIGHT_HAVE_CACHE_L2X0 646 select MIGHT_HAVE_CACHE_L2X0
647 select SPARSE_IRQ
647 select USE_OF 648 select USE_OF
648 help 649 help
649 This enables support for NVIDIA Tegra based systems (Tegra APX, 650 This enables support for NVIDIA Tegra based systems (Tegra APX,
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b0f3857b3a4c..96b9425219d9 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -345,6 +345,13 @@ choice
345 Say Y here if you want kernel low-level debugging support 345 Say Y here if you want kernel low-level debugging support
346 on SOCFPGA based platforms. 346 on SOCFPGA based platforms.
347 347
348 config DEBUG_TEGRA_UART
349 depends on ARCH_TEGRA
350 bool "Use Tegra UART for low-level debug"
351 help
352 Say Y here if you want kernel low-level debugging support
353 on Tegra based platforms.
354
348 config DEBUG_VEXPRESS_UART0_DETECT 355 config DEBUG_VEXPRESS_UART0_DETECT
349 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" 356 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
350 depends on ARCH_VEXPRESS && CPU_CP15_MMU 357 depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -409,6 +416,36 @@ choice
409 416
410endchoice 417endchoice
411 418
419choice
420 prompt "Low-level debug console UART"
421 depends on DEBUG_LL && DEBUG_TEGRA_UART
422
423 config TEGRA_DEBUG_UART_AUTO_ODMDATA
424 bool "Via ODMDATA"
425 help
426 Automatically determines which UART to use for low-level debug based
427 on the ODMDATA value. This value is part of the BCT, and is written
428 to the boot memory device using nvflash, or other flashing tool.
429 When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
430 0/1/2/3/4 are UART A/B/C/D/E.
431
432 config TEGRA_DEBUG_UARTA
433 bool "UART A"
434
435 config TEGRA_DEBUG_UARTB
436 bool "UART B"
437
438 config TEGRA_DEBUG_UARTC
439 bool "UART C"
440
441 config TEGRA_DEBUG_UARTD
442 bool "UART D"
443
444 config TEGRA_DEBUG_UARTE
445 bool "UART E"
446
447endchoice
448
412config DEBUG_LL_INCLUDE 449config DEBUG_LL_INCLUDE
413 string 450 string
414 default "debug/icedcc.S" if DEBUG_ICEDCC 451 default "debug/icedcc.S" if DEBUG_ICEDCC
@@ -418,6 +455,7 @@ config DEBUG_LL_INCLUDE
418 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART 455 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
419 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ 456 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
420 DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 457 DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
458 default "debug/tegra.S" if DEBUG_TEGRA_UART
421 default "mach/debug-macro.S" 459 default "mach/debug-macro.S"
422 460
423config EARLY_PRINTK 461config EARLY_PRINTK
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index c3ef1ad26b6a..43eb72af8948 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -262,9 +274,9 @@
262 }; 274 };
263 }; 275 };
264 276
265 i2c@7000c400 { 277 hdmi_ddc: i2c@7000c400 {
266 status = "okay"; 278 status = "okay";
267 clock-frequency = <400000>; 279 clock-frequency = <100000>;
268 }; 280 };
269 281
270 i2c@7000c500 { 282 i2c@7000c500 {
@@ -297,131 +309,98 @@
297 vinldo9-supply = <&sm2_reg>; 309 vinldo9-supply = <&sm2_reg>;
298 310
299 regulators { 311 regulators {
300 #address-cells = <1>; 312 sys_reg: sys {
301 #size-cells = <0>;
302
303 sys_reg: regulator@0 {
304 reg = <0>;
305 regulator-compatible = "sys";
306 regulator-name = "vdd_sys"; 313 regulator-name = "vdd_sys";
307 regulator-always-on; 314 regulator-always-on;
308 }; 315 };
309 316
310 regulator@1 { 317 sm0 {
311 reg = <1>;
312 regulator-compatible = "sm0";
313 regulator-name = "vdd_sm0,vdd_core"; 318 regulator-name = "vdd_sm0,vdd_core";
314 regulator-min-microvolt = <1200000>; 319 regulator-min-microvolt = <1200000>;
315 regulator-max-microvolt = <1200000>; 320 regulator-max-microvolt = <1200000>;
316 regulator-always-on; 321 regulator-always-on;
317 }; 322 };
318 323
319 regulator@2 { 324 sm1 {
320 reg = <2>;
321 regulator-compatible = "sm1";
322 regulator-name = "vdd_sm1,vdd_cpu"; 325 regulator-name = "vdd_sm1,vdd_cpu";
323 regulator-min-microvolt = <1000000>; 326 regulator-min-microvolt = <1000000>;
324 regulator-max-microvolt = <1000000>; 327 regulator-max-microvolt = <1000000>;
325 regulator-always-on; 328 regulator-always-on;
326 }; 329 };
327 330
328 sm2_reg: regulator@3 { 331 sm2_reg: sm2 {
329 reg = <3>;
330 regulator-compatible = "sm2";
331 regulator-name = "vdd_sm2,vin_ldo*"; 332 regulator-name = "vdd_sm2,vin_ldo*";
332 regulator-min-microvolt = <3700000>; 333 regulator-min-microvolt = <3700000>;
333 regulator-max-microvolt = <3700000>; 334 regulator-max-microvolt = <3700000>;
334 regulator-always-on; 335 regulator-always-on;
335 }; 336 };
336 337
337 regulator@4 { 338 ldo0 {
338 reg = <4>;
339 regulator-compatible = "ldo0";
340 regulator-name = "vdd_ldo0,vddio_pex_clk"; 339 regulator-name = "vdd_ldo0,vddio_pex_clk";
341 regulator-min-microvolt = <3300000>; 340 regulator-min-microvolt = <3300000>;
342 regulator-max-microvolt = <3300000>; 341 regulator-max-microvolt = <3300000>;
343 }; 342 };
344 343
345 regulator@5 { 344 ldo1 {
346 reg = <5>;
347 regulator-compatible = "ldo1";
348 regulator-name = "vdd_ldo1,avdd_pll*"; 345 regulator-name = "vdd_ldo1,avdd_pll*";
349 regulator-min-microvolt = <1100000>; 346 regulator-min-microvolt = <1100000>;
350 regulator-max-microvolt = <1100000>; 347 regulator-max-microvolt = <1100000>;
351 regulator-always-on; 348 regulator-always-on;
352 }; 349 };
353 350
354 regulator@6 { 351 ldo2 {
355 reg = <6>;
356 regulator-compatible = "ldo2";
357 regulator-name = "vdd_ldo2,vdd_rtc"; 352 regulator-name = "vdd_ldo2,vdd_rtc";
358 regulator-min-microvolt = <1200000>; 353 regulator-min-microvolt = <1200000>;
359 regulator-max-microvolt = <1200000>; 354 regulator-max-microvolt = <1200000>;
360 }; 355 };
361 356
362 regulator@7 { 357 ldo3 {
363 reg = <7>;
364 regulator-compatible = "ldo3";
365 regulator-name = "vdd_ldo3,avdd_usb*"; 358 regulator-name = "vdd_ldo3,avdd_usb*";
366 regulator-min-microvolt = <3300000>; 359 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>; 360 regulator-max-microvolt = <3300000>;
368 regulator-always-on; 361 regulator-always-on;
369 }; 362 };
370 363
371 regulator@8 { 364 ldo4 {
372 reg = <8>;
373 regulator-compatible = "ldo4";
374 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 365 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
375 regulator-min-microvolt = <1800000>; 366 regulator-min-microvolt = <1800000>;
376 regulator-max-microvolt = <1800000>; 367 regulator-max-microvolt = <1800000>;
377 regulator-always-on; 368 regulator-always-on;
378 }; 369 };
379 370
380 regulator@9 { 371 ldo5 {
381 reg = <9>;
382 regulator-compatible = "ldo5";
383 regulator-name = "vdd_ldo5,vcore_mmc"; 372 regulator-name = "vdd_ldo5,vcore_mmc";
384 regulator-min-microvolt = <2850000>; 373 regulator-min-microvolt = <2850000>;
385 regulator-max-microvolt = <2850000>; 374 regulator-max-microvolt = <2850000>;
386 regulator-always-on; 375 regulator-always-on;
387 }; 376 };
388 377
389 regulator@10 { 378 ldo6 {
390 reg = <10>;
391 regulator-compatible = "ldo6";
392 regulator-name = "vdd_ldo6,avdd_vdac"; 379 regulator-name = "vdd_ldo6,avdd_vdac";
393 regulator-min-microvolt = <1800000>; 380 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <1800000>; 381 regulator-max-microvolt = <1800000>;
395 }; 382 };
396 383
397 regulator@11 { 384 hdmi_vdd_reg: ldo7 {
398 reg = <11>;
399 regulator-compatible = "ldo7";
400 regulator-name = "vdd_ldo7,avdd_hdmi"; 385 regulator-name = "vdd_ldo7,avdd_hdmi";
401 regulator-min-microvolt = <3300000>; 386 regulator-min-microvolt = <3300000>;
402 regulator-max-microvolt = <3300000>; 387 regulator-max-microvolt = <3300000>;
403 }; 388 };
404 389
405 regulator@12 { 390 hdmi_pll_reg: ldo8 {
406 reg = <12>;
407 regulator-compatible = "ldo8";
408 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 391 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
409 regulator-min-microvolt = <1800000>; 392 regulator-min-microvolt = <1800000>;
410 regulator-max-microvolt = <1800000>; 393 regulator-max-microvolt = <1800000>;
411 }; 394 };
412 395
413 regulator@13 { 396 ldo9 {
414 reg = <13>;
415 regulator-compatible = "ldo9";
416 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 397 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
417 regulator-min-microvolt = <2850000>; 398 regulator-min-microvolt = <2850000>;
418 regulator-max-microvolt = <2850000>; 399 regulator-max-microvolt = <2850000>;
419 regulator-always-on; 400 regulator-always-on;
420 }; 401 };
421 402
422 regulator@14 { 403 ldo_rtc {
423 reg = <14>;
424 regulator-compatible = "ldo_rtc";
425 regulator-name = "vdd_rtc_out,vdd_cell"; 404 regulator-name = "vdd_rtc_out,vdd_cell";
426 regulator-min-microvolt = <3300000>; 405 regulator-min-microvolt = <3300000>;
427 regulator-max-microvolt = <3300000>; 406 regulator-max-microvolt = <3300000>;
@@ -429,6 +408,11 @@
429 }; 408 };
430 }; 409 };
431 }; 410 };
411
412 temperature-sensor@4c {
413 compatible = "adi,adt7461";
414 reg = <0x4c>;
415 };
432 }; 416 };
433 417
434 pmc { 418 pmc {
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index ddf287f52d49..6a93d1404c76 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -291,37 +291,26 @@
291 vinldo9-supply = <&sm2_reg>; 291 vinldo9-supply = <&sm2_reg>;
292 292
293 regulators { 293 regulators {
294 #address-cells = <1>; 294 sys_reg: sys {
295 #size-cells = <0>;
296
297 sys_reg: regulator@0 {
298 reg = <0>;
299 regulator-compatible = "sys";
300 regulator-name = "vdd_sys"; 295 regulator-name = "vdd_sys";
301 regulator-always-on; 296 regulator-always-on;
302 }; 297 };
303 298
304 regulator@1 { 299 sm0 {
305 reg = <1>;
306 regulator-compatible = "sm0";
307 regulator-name = "+1.2vs_sm0,vdd_core"; 300 regulator-name = "+1.2vs_sm0,vdd_core";
308 regulator-min-microvolt = <1200000>; 301 regulator-min-microvolt = <1200000>;
309 regulator-max-microvolt = <1200000>; 302 regulator-max-microvolt = <1200000>;
310 regulator-always-on; 303 regulator-always-on;
311 }; 304 };
312 305
313 regulator@2 { 306 sm1 {
314 reg = <2>;
315 regulator-compatible = "sm1";
316 regulator-name = "+1.0vs_sm1,vdd_cpu"; 307 regulator-name = "+1.0vs_sm1,vdd_cpu";
317 regulator-min-microvolt = <1000000>; 308 regulator-min-microvolt = <1000000>;
318 regulator-max-microvolt = <1000000>; 309 regulator-max-microvolt = <1000000>;
319 regulator-always-on; 310 regulator-always-on;
320 }; 311 };
321 312
322 sm2_reg: regulator@3 { 313 sm2_reg: sm2 {
323 reg = <3>;
324 regulator-compatible = "sm2";
325 regulator-name = "+3.7vs_sm2,vin_ldo*"; 314 regulator-name = "+3.7vs_sm2,vin_ldo*";
326 regulator-min-microvolt = <3700000>; 315 regulator-min-microvolt = <3700000>;
327 regulator-max-microvolt = <3700000>; 316 regulator-max-microvolt = <3700000>;
@@ -330,53 +319,41 @@
330 319
331 /* LDO0 is not connected to anything */ 320 /* LDO0 is not connected to anything */
332 321
333 regulator@5 { 322 ldo1 {
334 reg = <5>;
335 regulator-compatible = "ldo1";
336 regulator-name = "+1.1vs_ldo1,avdd_pll*"; 323 regulator-name = "+1.1vs_ldo1,avdd_pll*";
337 regulator-min-microvolt = <1100000>; 324 regulator-min-microvolt = <1100000>;
338 regulator-max-microvolt = <1100000>; 325 regulator-max-microvolt = <1100000>;
339 regulator-always-on; 326 regulator-always-on;
340 }; 327 };
341 328
342 regulator@6 { 329 ldo2 {
343 reg = <6>;
344 regulator-compatible = "ldo2";
345 regulator-name = "+1.2vs_ldo2,vdd_rtc"; 330 regulator-name = "+1.2vs_ldo2,vdd_rtc";
346 regulator-min-microvolt = <1200000>; 331 regulator-min-microvolt = <1200000>;
347 regulator-max-microvolt = <1200000>; 332 regulator-max-microvolt = <1200000>;
348 }; 333 };
349 334
350 regulator@7 { 335 ldo3 {
351 reg = <7>;
352 regulator-compatible = "ldo3";
353 regulator-name = "+3.3vs_ldo3,avdd_usb*"; 336 regulator-name = "+3.3vs_ldo3,avdd_usb*";
354 regulator-min-microvolt = <3300000>; 337 regulator-min-microvolt = <3300000>;
355 regulator-max-microvolt = <3300000>; 338 regulator-max-microvolt = <3300000>;
356 regulator-always-on; 339 regulator-always-on;
357 }; 340 };
358 341
359 regulator@8 { 342 ldo4 {
360 reg = <8>;
361 regulator-compatible = "ldo4";
362 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; 343 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
363 regulator-min-microvolt = <1800000>; 344 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>; 345 regulator-max-microvolt = <1800000>;
365 regulator-always-on; 346 regulator-always-on;
366 }; 347 };
367 348
368 regulator@9 { 349 ldo5 {
369 reg = <9>;
370 regulator-compatible = "ldo5";
371 regulator-name = "+2.85vs_ldo5,vcore_mmc"; 350 regulator-name = "+2.85vs_ldo5,vcore_mmc";
372 regulator-min-microvolt = <2850000>; 351 regulator-min-microvolt = <2850000>;
373 regulator-max-microvolt = <2850000>; 352 regulator-max-microvolt = <2850000>;
374 regulator-always-on; 353 regulator-always-on;
375 }; 354 };
376 355
377 regulator@10 { 356 ldo6 {
378 reg = <10>;
379 regulator-compatible = "ldo6";
380 /* 357 /*
381 * Research indicates this should be 358 * Research indicates this should be
382 * 1.8v; other boards that use this 359 * 1.8v; other boards that use this
@@ -390,34 +367,26 @@
390 regulator-max-microvolt = <1800000>; 367 regulator-max-microvolt = <1800000>;
391 }; 368 };
392 369
393 regulator@11 { 370 ldo7 {
394 reg = <11>;
395 regulator-compatible = "ldo7";
396 regulator-name = "+3.3vs_ldo7,avdd_hdmi"; 371 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
397 regulator-min-microvolt = <3300000>; 372 regulator-min-microvolt = <3300000>;
398 regulator-max-microvolt = <3300000>; 373 regulator-max-microvolt = <3300000>;
399 }; 374 };
400 375
401 regulator@12 { 376 ldo8 {
402 reg = <12>;
403 regulator-compatible = "ldo8";
404 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; 377 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
405 regulator-min-microvolt = <1800000>; 378 regulator-min-microvolt = <1800000>;
406 regulator-max-microvolt = <1800000>; 379 regulator-max-microvolt = <1800000>;
407 }; 380 };
408 381
409 regulator@13 { 382 ldo9 {
410 reg = <13>;
411 regulator-compatible = "ldo9";
412 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; 383 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
413 regulator-min-microvolt = <2850000>; 384 regulator-min-microvolt = <2850000>;
414 regulator-max-microvolt = <2850000>; 385 regulator-max-microvolt = <2850000>;
415 regulator-always-on; 386 regulator-always-on;
416 }; 387 };
417 388
418 regulator@14 { 389 ldo_rtc {
419 reg = <14>;
420 regulator-compatible = "ldo_rtc";
421 regulator-name = "+3.3vs_rtc"; 390 regulator-name = "+3.3vs_rtc";
422 regulator-min-microvolt = <3300000>; 391 regulator-min-microvolt = <3300000>;
423 regulator-max-microvolt = <3300000>; 392 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 331a3ef24d59..289480026fbf 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,6 +6,12 @@
6 model = "Avionic Design Plutux board"; 6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x {
10 hdmi {
11 status = "okay";
12 };
13 };
14
9 i2c@7000c000 { 15 i2c@7000c000 {
10 wm8903: wm8903@1a { 16 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903"; 17 compatible = "wlf,wm8903";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index f0ba901676ac..eafeca65eb21 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -395,37 +395,26 @@
395 vinldo9-supply = <&sm2_reg>; 395 vinldo9-supply = <&sm2_reg>;
396 396
397 regulators { 397 regulators {
398 #address-cells = <1>; 398 sys_reg: sys {
399 #size-cells = <0>;
400
401 sys_reg: regulator@0 {
402 reg = <0>;
403 regulator-compatible = "sys";
404 regulator-name = "vdd_sys"; 399 regulator-name = "vdd_sys";
405 regulator-always-on; 400 regulator-always-on;
406 }; 401 };
407 402
408 regulator@1 { 403 sm0 {
409 reg = <1>;
410 regulator-compatible = "sm0";
411 regulator-name = "vdd_sm0,vdd_core"; 404 regulator-name = "vdd_sm0,vdd_core";
412 regulator-min-microvolt = <1300000>; 405 regulator-min-microvolt = <1300000>;
413 regulator-max-microvolt = <1300000>; 406 regulator-max-microvolt = <1300000>;
414 regulator-always-on; 407 regulator-always-on;
415 }; 408 };
416 409
417 regulator@2 { 410 sm1 {
418 reg = <2>;
419 regulator-compatible = "sm1";
420 regulator-name = "vdd_sm1,vdd_cpu"; 411 regulator-name = "vdd_sm1,vdd_cpu";
421 regulator-min-microvolt = <1125000>; 412 regulator-min-microvolt = <1125000>;
422 regulator-max-microvolt = <1125000>; 413 regulator-max-microvolt = <1125000>;
423 regulator-always-on; 414 regulator-always-on;
424 }; 415 };
425 416
426 sm2_reg: regulator@3 { 417 sm2_reg: sm2 {
427 reg = <3>;
428 regulator-compatible = "sm2";
429 regulator-name = "vdd_sm2,vin_ldo*"; 418 regulator-name = "vdd_sm2,vin_ldo*";
430 regulator-min-microvolt = <3700000>; 419 regulator-min-microvolt = <3700000>;
431 regulator-max-microvolt = <3700000>; 420 regulator-max-microvolt = <3700000>;
@@ -434,86 +423,66 @@
434 423
435 /* LDO0 is not connected to anything */ 424 /* LDO0 is not connected to anything */
436 425
437 regulator@5 { 426 ldo1 {
438 reg = <5>;
439 regulator-compatible = "ldo1";
440 regulator-name = "vdd_ldo1,avdd_pll*"; 427 regulator-name = "vdd_ldo1,avdd_pll*";
441 regulator-min-microvolt = <1100000>; 428 regulator-min-microvolt = <1100000>;
442 regulator-max-microvolt = <1100000>; 429 regulator-max-microvolt = <1100000>;
443 regulator-always-on; 430 regulator-always-on;
444 }; 431 };
445 432
446 regulator@6 { 433 ldo2 {
447 reg = <6>;
448 regulator-compatible = "ldo2";
449 regulator-name = "vdd_ldo2,vdd_rtc"; 434 regulator-name = "vdd_ldo2,vdd_rtc";
450 regulator-min-microvolt = <1200000>; 435 regulator-min-microvolt = <1200000>;
451 regulator-max-microvolt = <1200000>; 436 regulator-max-microvolt = <1200000>;
452 }; 437 };
453 438
454 regulator@7 { 439 ldo3 {
455 reg = <7>;
456 regulator-compatible = "ldo3";
457 regulator-name = "vdd_ldo3,avdd_usb*"; 440 regulator-name = "vdd_ldo3,avdd_usb*";
458 regulator-min-microvolt = <3300000>; 441 regulator-min-microvolt = <3300000>;
459 regulator-max-microvolt = <3300000>; 442 regulator-max-microvolt = <3300000>;
460 regulator-always-on; 443 regulator-always-on;
461 }; 444 };
462 445
463 regulator@8 { 446 ldo4 {
464 reg = <8>;
465 regulator-compatible = "ldo4";
466 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 447 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
467 regulator-min-microvolt = <1800000>; 448 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <1800000>; 449 regulator-max-microvolt = <1800000>;
469 regulator-always-on; 450 regulator-always-on;
470 }; 451 };
471 452
472 regulator@9 { 453 ldo5 {
473 reg = <9>;
474 regulator-compatible = "ldo5";
475 regulator-name = "vdd_ldo5,vcore_mmc"; 454 regulator-name = "vdd_ldo5,vcore_mmc";
476 regulator-min-microvolt = <2850000>; 455 regulator-min-microvolt = <2850000>;
477 regulator-max-microvolt = <2850000>; 456 regulator-max-microvolt = <2850000>;
478 regulator-always-on; 457 regulator-always-on;
479 }; 458 };
480 459
481 regulator@10 { 460 ldo6 {
482 reg = <10>;
483 regulator-compatible = "ldo6";
484 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; 461 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
485 regulator-min-microvolt = <1800000>; 462 regulator-min-microvolt = <1800000>;
486 regulator-max-microvolt = <1800000>; 463 regulator-max-microvolt = <1800000>;
487 }; 464 };
488 465
489 regulator@11 { 466 ldo7 {
490 reg = <11>;
491 regulator-compatible = "ldo7";
492 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 467 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
493 regulator-min-microvolt = <3300000>; 468 regulator-min-microvolt = <3300000>;
494 regulator-max-microvolt = <3300000>; 469 regulator-max-microvolt = <3300000>;
495 }; 470 };
496 471
497 regulator@12 { 472 ldo8 {
498 reg = <12>;
499 regulator-compatible = "ldo8";
500 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 473 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
501 regulator-min-microvolt = <1800000>; 474 regulator-min-microvolt = <1800000>;
502 regulator-max-microvolt = <1800000>; 475 regulator-max-microvolt = <1800000>;
503 }; 476 };
504 477
505 regulator@13 { 478 ldo9 {
506 reg = <13>;
507 regulator-compatible = "ldo9";
508 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 479 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
509 regulator-min-microvolt = <2850000>; 480 regulator-min-microvolt = <2850000>;
510 regulator-max-microvolt = <2850000>; 481 regulator-max-microvolt = <2850000>;
511 regulator-always-on; 482 regulator-always-on;
512 }; 483 };
513 484
514 regulator@14 { 485 ldo_rtc {
515 reg = <14>;
516 regulator-compatible = "ldo_rtc";
517 regulator-name = "vdd_rtc_out,vdd_cell"; 486 regulator-name = "vdd_rtc_out,vdd_cell";
518 regulator-min-microvolt = <3300000>; 487 regulator-min-microvolt = <3300000>;
519 regulator-max-microvolt = <3300000>; 488 regulator-max-microvolt = <3300000>;
@@ -592,6 +561,12 @@
592 status = "okay"; 561 status = "okay";
593 }; 562 };
594 563
564 sdhci@c8000000 {
565 status = "okay";
566 power-gpios = <&gpio 86 0>; /* gpio PK6 */
567 bus-width = <4>;
568 };
569
595 sdhci@c8000400 { 570 sdhci@c8000400 {
596 status = "okay"; 571 status = "okay";
597 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 572 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index f18cec9f6a77..a239ccdfaa52 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -8,6 +8,16 @@
8 reg = <0x00000000 0x20000000>; 8 reg = <0x00000000 0x20000000>;
9 }; 9 };
10 10
11 host1x {
12 hdmi {
13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
15
16 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
18 };
19 };
20
11 pinmux { 21 pinmux {
12 pinctrl-names = "default"; 22 pinctrl-names = "default";
13 pinctrl-0 = <&state_default>; 23 pinctrl-0 = <&state_default>;
@@ -62,10 +72,6 @@
62 nvidia,pins = "dap4"; 72 nvidia,pins = "dap4";
63 nvidia,function = "dap4"; 73 nvidia,function = "dap4";
64 }; 74 };
65 ddc {
66 nvidia,pins = "ddc";
67 nvidia,function = "i2c2";
68 };
69 dta { 75 dta {
70 nvidia,pins = "dta", "dtd"; 76 nvidia,pins = "dta", "dtd";
71 nvidia,function = "sdio2"; 77 nvidia,function = "sdio2";
@@ -91,7 +97,7 @@
91 nvidia,function = "pcie"; 97 nvidia,function = "pcie";
92 }; 98 };
93 hdint { 99 hdint {
94 nvidia,pins = "hdint", "pta"; 100 nvidia,pins = "hdint";
95 nvidia,function = "hdmi"; 101 nvidia,function = "hdmi";
96 }; 102 };
97 i2cp { 103 i2cp {
@@ -230,6 +236,39 @@
230 nvidia,pull = <1>; 236 nvidia,pull = <1>;
231 }; 237 };
232 }; 238 };
239
240 state_i2cmux_ddc: pinmux_i2cmux_ddc {
241 ddc {
242 nvidia,pins = "ddc";
243 nvidia,function = "i2c2";
244 };
245 pta {
246 nvidia,pins = "pta";
247 nvidia,function = "rsvd4";
248 };
249 };
250
251 state_i2cmux_pta: pinmux_i2cmux_pta {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "rsvd4";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "i2c2";
259 };
260 };
261
262 state_i2cmux_idle: pinmux_i2cmux_idle {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "rsvd4";
270 };
271 };
233 }; 272 };
234 273
235 i2s@70002800 { 274 i2s@70002800 {
@@ -246,6 +285,36 @@
246 status = "okay"; 285 status = "okay";
247 }; 286 };
248 287
288 i2c@7000c400 {
289 clock-frequency = <100000>;
290 status = "okay";
291 };
292
293 i2cmux {
294 compatible = "i2c-mux-pinctrl";
295 #address-cells = <1>;
296 #size-cells = <0>;
297
298 i2c-parent = <&{/i2c@7000c400}>;
299
300 pinctrl-names = "ddc", "pta", "idle";
301 pinctrl-0 = <&state_i2cmux_ddc>;
302 pinctrl-1 = <&state_i2cmux_pta>;
303 pinctrl-2 = <&state_i2cmux_idle>;
304
305 hdmi_ddc: i2c@0 {
306 reg = <0>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 };
310
311 i2c@1 {
312 reg = <1>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 };
316 };
317
249 i2c@7000d000 { 318 i2c@7000d000 {
250 clock-frequency = <400000>; 319 clock-frequency = <400000>;
251 status = "okay"; 320 status = "okay";
@@ -271,97 +340,72 @@
271 vinldo9-supply = <&sm2_reg>; 340 vinldo9-supply = <&sm2_reg>;
272 341
273 regulators { 342 regulators {
274 #address-cells = <1>; 343 sys_reg: sys {
275 #size-cells = <0>;
276
277 sys_reg: regulator@0 {
278 reg = <0>;
279 regulator-compatible = "sys";
280 regulator-name = "vdd_sys"; 344 regulator-name = "vdd_sys";
281 regulator-always-on; 345 regulator-always-on;
282 }; 346 };
283 347
284 regulator@1 { 348 sm0 {
285 reg = <1>;
286 regulator-compatible = "sm0";
287 regulator-name = "vdd_sys_sm0,vdd_core"; 349 regulator-name = "vdd_sys_sm0,vdd_core";
288 regulator-min-microvolt = <1200000>; 350 regulator-min-microvolt = <1200000>;
289 regulator-max-microvolt = <1200000>; 351 regulator-max-microvolt = <1200000>;
290 regulator-always-on; 352 regulator-always-on;
291 }; 353 };
292 354
293 regulator@2 { 355 sm1 {
294 reg = <2>;
295 regulator-compatible = "sm1";
296 regulator-name = "vdd_sys_sm1,vdd_cpu"; 356 regulator-name = "vdd_sys_sm1,vdd_cpu";
297 regulator-min-microvolt = <1000000>; 357 regulator-min-microvolt = <1000000>;
298 regulator-max-microvolt = <1000000>; 358 regulator-max-microvolt = <1000000>;
299 regulator-always-on; 359 regulator-always-on;
300 }; 360 };
301 361
302 sm2_reg: regulator@3 { 362 sm2_reg: sm2 {
303 reg = <3>;
304 regulator-compatible = "sm2";
305 regulator-name = "vdd_sys_sm2,vin_ldo*"; 363 regulator-name = "vdd_sys_sm2,vin_ldo*";
306 regulator-min-microvolt = <3700000>; 364 regulator-min-microvolt = <3700000>;
307 regulator-max-microvolt = <3700000>; 365 regulator-max-microvolt = <3700000>;
308 regulator-always-on; 366 regulator-always-on;
309 }; 367 };
310 368
311 regulator@4 { 369 ldo0 {
312 reg = <4>;
313 regulator-compatible = "ldo0";
314 regulator-name = "vdd_ldo0,vddio_pex_clk"; 370 regulator-name = "vdd_ldo0,vddio_pex_clk";
315 regulator-min-microvolt = <3300000>; 371 regulator-min-microvolt = <3300000>;
316 regulator-max-microvolt = <3300000>; 372 regulator-max-microvolt = <3300000>;
317 }; 373 };
318 374
319 regulator@5 { 375 ldo1 {
320 reg = <5>;
321 regulator-compatible = "ldo1";
322 regulator-name = "vdd_ldo1,avdd_pll*"; 376 regulator-name = "vdd_ldo1,avdd_pll*";
323 regulator-min-microvolt = <1100000>; 377 regulator-min-microvolt = <1100000>;
324 regulator-max-microvolt = <1100000>; 378 regulator-max-microvolt = <1100000>;
325 regulator-always-on; 379 regulator-always-on;
326 }; 380 };
327 381
328 regulator@6 { 382 ldo2 {
329 reg = <6>;
330 regulator-compatible = "ldo2";
331 regulator-name = "vdd_ldo2,vdd_rtc"; 383 regulator-name = "vdd_ldo2,vdd_rtc";
332 regulator-min-microvolt = <1200000>; 384 regulator-min-microvolt = <1200000>;
333 regulator-max-microvolt = <1200000>; 385 regulator-max-microvolt = <1200000>;
334 }; 386 };
335 387
336 regulator@7 { 388 ldo3 {
337 reg = <7>;
338 regulator-compatible = "ldo3";
339 regulator-name = "vdd_ldo3,avdd_usb*"; 389 regulator-name = "vdd_ldo3,avdd_usb*";
340 regulator-min-microvolt = <3300000>; 390 regulator-min-microvolt = <3300000>;
341 regulator-max-microvolt = <3300000>; 391 regulator-max-microvolt = <3300000>;
342 regulator-always-on; 392 regulator-always-on;
343 }; 393 };
344 394
345 regulator@8 { 395 ldo4 {
346 reg = <8>;
347 regulator-compatible = "ldo4";
348 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 396 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
349 regulator-min-microvolt = <1800000>; 397 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <1800000>; 398 regulator-max-microvolt = <1800000>;
351 regulator-always-on; 399 regulator-always-on;
352 }; 400 };
353 401
354 regulator@9 { 402 ldo5 {
355 reg = <9>;
356 regulator-compatible = "ldo5";
357 regulator-name = "vdd_ldo5,vcore_mmc"; 403 regulator-name = "vdd_ldo5,vcore_mmc";
358 regulator-min-microvolt = <2850000>; 404 regulator-min-microvolt = <2850000>;
359 regulator-max-microvolt = <2850000>; 405 regulator-max-microvolt = <2850000>;
360 }; 406 };
361 407
362 regulator@10 { 408 ldo6 {
363 reg = <10>;
364 regulator-compatible = "ldo6";
365 regulator-name = "vdd_ldo6,avdd_vdac"; 409 regulator-name = "vdd_ldo6,avdd_vdac";
366 /* 410 /*
367 * According to the Tegra 2 Automotive 411 * According to the Tegra 2 Automotive
@@ -373,25 +417,19 @@
373 regulator-max-microvolt = <2850000>; 417 regulator-max-microvolt = <2850000>;
374 }; 418 };
375 419
376 regulator@11 { 420 hdmi_vdd_reg: ldo7 {
377 reg = <11>;
378 regulator-compatible = "ldo7";
379 regulator-name = "vdd_ldo7,avdd_hdmi"; 421 regulator-name = "vdd_ldo7,avdd_hdmi";
380 regulator-min-microvolt = <3300000>; 422 regulator-min-microvolt = <3300000>;
381 regulator-max-microvolt = <3300000>; 423 regulator-max-microvolt = <3300000>;
382 }; 424 };
383 425
384 regulator@12 { 426 hdmi_pll_reg: ldo8 {
385 reg = <12>;
386 regulator-compatible = "ldo8";
387 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 427 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
388 regulator-min-microvolt = <1800000>; 428 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>; 429 regulator-max-microvolt = <1800000>;
390 }; 430 };
391 431
392 regulator@13 { 432 ldo9 {
393 reg = <13>;
394 regulator-compatible = "ldo9";
395 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; 433 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
396 /* 434 /*
397 * According to the Tegra 2 Automotive 435 * According to the Tegra 2 Automotive
@@ -404,9 +442,7 @@
404 regulator-always-on; 442 regulator-always-on;
405 }; 443 };
406 444
407 regulator@14 { 445 ldo_rtc {
408 reg = <14>;
409 regulator-compatible = "ldo_rtc";
410 regulator-name = "vdd_rtc_out"; 446 regulator-name = "vdd_rtc_out";
411 regulator-min-microvolt = <3300000>; 447 regulator-min-microvolt = <3300000>;
412 regulator-max-microvolt = <3300000>; 448 regulator-max-microvolt = <3300000>;
@@ -414,6 +450,11 @@
414 }; 450 };
415 }; 451 };
416 }; 452 };
453
454 temperature-sensor@4c {
455 compatible = "onnn,nct1008";
456 reg = <0x4c>;
457 };
417 }; 458 };
418 459
419 pmc { 460 pmc {
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9aff31b0fe4a..402b21004bef 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,10 +6,13 @@
6 model = "Avionic Design Tamonten Evaluation Carrier"; 6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8 8
9 i2c@7000c000 { 9 host1x {
10 clock-frequency = <400000>; 10 hdmi {
11 status = "okay"; 11 status = "okay";
12 };
13 };
12 14
15 i2c@7000c000 {
13 wm8903: wm8903@1a { 16 wm8903: wm8903@1a {
14 compatible = "wlf,wm8903"; 17 compatible = "wlf,wm8903";
15 reg = <0x1a>; 18 reg = <0x1a>;
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 27fb8a67ea42..b70b4cb754c8 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -249,14 +261,24 @@
249 clock-frequency = <216000000>; 261 clock-frequency = <216000000>;
250 }; 262 };
251 263
252 i2c@7000c000 { 264 dvi_ddc: i2c@7000c000 {
253 status = "okay"; 265 status = "okay";
254 clock-frequency = <400000>; 266 clock-frequency = <100000>;
255 }; 267 };
256 268
257 i2c@7000c400 { 269 spi@7000c380 {
258 status = "okay"; 270 status = "okay";
259 clock-frequency = <400000>; 271 spi-max-frequency = <48000000>;
272 spi-flash@0 {
273 compatible = "winbond,w25q80bl";
274 reg = <0>;
275 spi-max-frequency = <48000000>;
276 };
277 };
278
279 hdmi_ddc: i2c@7000c400 {
280 status = "okay";
281 clock-frequency = <100000>;
260 }; 282 };
261 283
262 i2c@7000c500 { 284 i2c@7000c500 {
@@ -300,6 +322,30 @@
300 bus-width = <4>; 322 bus-width = <4>;
301 }; 323 };
302 324
325 regulators {
326 compatible = "simple-bus";
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 hdmi_vdd_reg: regulator@0 {
331 compatible = "regulator-fixed";
332 reg = <0>;
333 regulator-name = "avdd_hdmi";
334 regulator-min-microvolt = <3300000>;
335 regulator-max-microvolt = <3300000>;
336 regulator-always-on;
337 };
338
339 hdmi_pll_reg: regulator@1 {
340 compatible = "regulator-fixed";
341 reg = <1>;
342 regulator-name = "avdd_hdmi_pll";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>;
345 regulator-always-on;
346 };
347 };
348
303 sound { 349 sound {
304 compatible = "nvidia,tegra-audio-trimslice"; 350 compatible = "nvidia,tegra-audio-trimslice";
305 nvidia,i2s-controller = <&tegra_i2s1>; 351 nvidia,i2s-controller = <&tegra_i2s1>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 3e5952fcfbc5..adc47547eaae 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -64,11 +64,6 @@
64 nvidia,pins = "dap4"; 64 nvidia,pins = "dap4";
65 nvidia,function = "dap4"; 65 nvidia,function = "dap4";
66 }; 66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta { 67 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 68 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi"; 69 nvidia,function = "vi";
@@ -98,7 +93,7 @@
98 nvidia,function = "pcie"; 93 nvidia,function = "pcie";
99 }; 94 };
100 hdint { 95 hdint {
101 nvidia,pins = "hdint", "pta"; 96 nvidia,pins = "hdint";
102 nvidia,function = "hdmi"; 97 nvidia,function = "hdmi";
103 }; 98 };
104 i2cp { 99 i2cp {
@@ -129,6 +124,10 @@
129 "lspi", "lvp1", "lvs"; 124 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya"; 125 nvidia,function = "displaya";
131 }; 126 };
127 owc {
128 nvidia,pins = "owc", "spdi", "spdo", "uac";
129 nvidia,function = "rsvd2";
130 };
132 pmc { 131 pmc {
133 nvidia,pins = "pmc"; 132 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on"; 133 nvidia,function = "pwr_on";
@@ -237,6 +236,49 @@
237 "ld23_22"; 236 "ld23_22";
238 nvidia,pull = <1>; 237 nvidia,pull = <1>;
239 }; 238 };
239 drive_sdio1 {
240 nvidia,pins = "drive_sdio1";
241 nvidia,high-speed-mode = <0>;
242 nvidia,schmitt = <1>;
243 nvidia,low-power-mode = <3>;
244 nvidia,pull-down-strength = <31>;
245 nvidia,pull-up-strength = <31>;
246 nvidia,slew-rate-rising = <3>;
247 nvidia,slew-rate-falling = <3>;
248 };
249 };
250
251 state_i2cmux_ddc: pinmux_i2cmux_ddc {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "i2c2";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "rsvd4";
259 };
260 };
261
262 state_i2cmux_pta: pinmux_i2cmux_pta {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "i2c2";
270 };
271 };
272
273 state_i2cmux_idle: pinmux_i2cmux_idle {
274 ddc {
275 nvidia,pins = "ddc";
276 nvidia,function = "rsvd4";
277 };
278 pta {
279 nvidia,pins = "pta";
280 nvidia,function = "rsvd4";
281 };
240 }; 282 };
241 }; 283 };
242 284
@@ -281,6 +323,31 @@
281 clock-frequency = <400000>; 323 clock-frequency = <400000>;
282 }; 324 };
283 325
326 i2cmux {
327 compatible = "i2c-mux-pinctrl";
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 i2c-parent = <&{/i2c@7000c400}>;
332
333 pinctrl-names = "ddc", "pta", "idle";
334 pinctrl-0 = <&state_i2cmux_ddc>;
335 pinctrl-1 = <&state_i2cmux_pta>;
336 pinctrl-2 = <&state_i2cmux_idle>;
337
338 i2c@0 {
339 reg = <0>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 };
343
344 i2c@1 {
345 reg = <1>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 };
349 };
350
284 i2c@7000c500 { 351 i2c@7000c500 {
285 status = "okay"; 352 status = "okay";
286 clock-frequency = <400000>; 353 clock-frequency = <400000>;
@@ -311,37 +378,26 @@
311 vinldo9-supply = <&sm2_reg>; 378 vinldo9-supply = <&sm2_reg>;
312 379
313 regulators { 380 regulators {
314 #address-cells = <1>; 381 sys_reg: sys {
315 #size-cells = <0>;
316
317 sys_reg: regulator@0 {
318 reg = <0>;
319 regulator-compatible = "sys";
320 regulator-name = "vdd_sys"; 382 regulator-name = "vdd_sys";
321 regulator-always-on; 383 regulator-always-on;
322 }; 384 };
323 385
324 regulator@1 { 386 sm0 {
325 reg = <1>;
326 regulator-compatible = "sm0";
327 regulator-name = "vdd_sm0,vdd_core"; 387 regulator-name = "vdd_sm0,vdd_core";
328 regulator-min-microvolt = <1200000>; 388 regulator-min-microvolt = <1200000>;
329 regulator-max-microvolt = <1200000>; 389 regulator-max-microvolt = <1200000>;
330 regulator-always-on; 390 regulator-always-on;
331 }; 391 };
332 392
333 regulator@2 { 393 sm1 {
334 reg = <2>;
335 regulator-compatible = "sm1";
336 regulator-name = "vdd_sm1,vdd_cpu"; 394 regulator-name = "vdd_sm1,vdd_cpu";
337 regulator-min-microvolt = <1000000>; 395 regulator-min-microvolt = <1000000>;
338 regulator-max-microvolt = <1000000>; 396 regulator-max-microvolt = <1000000>;
339 regulator-always-on; 397 regulator-always-on;
340 }; 398 };
341 399
342 sm2_reg: regulator@3 { 400 sm2_reg: sm2 {
343 reg = <3>;
344 regulator-compatible = "sm2";
345 regulator-name = "vdd_sm2,vin_ldo*"; 401 regulator-name = "vdd_sm2,vin_ldo*";
346 regulator-min-microvolt = <3700000>; 402 regulator-min-microvolt = <3700000>;
347 regulator-max-microvolt = <3700000>; 403 regulator-max-microvolt = <3700000>;
@@ -350,86 +406,66 @@
350 406
351 /* LDO0 is not connected to anything */ 407 /* LDO0 is not connected to anything */
352 408
353 regulator@5 { 409 ldo1 {
354 reg = <5>;
355 regulator-compatible = "ldo1";
356 regulator-name = "vdd_ldo1,avdd_pll*"; 410 regulator-name = "vdd_ldo1,avdd_pll*";
357 regulator-min-microvolt = <1100000>; 411 regulator-min-microvolt = <1100000>;
358 regulator-max-microvolt = <1100000>; 412 regulator-max-microvolt = <1100000>;
359 regulator-always-on; 413 regulator-always-on;
360 }; 414 };
361 415
362 regulator@6 { 416 ldo2 {
363 reg = <6>;
364 regulator-compatible = "ldo2";
365 regulator-name = "vdd_ldo2,vdd_rtc"; 417 regulator-name = "vdd_ldo2,vdd_rtc";
366 regulator-min-microvolt = <1200000>; 418 regulator-min-microvolt = <1200000>;
367 regulator-max-microvolt = <1200000>; 419 regulator-max-microvolt = <1200000>;
368 }; 420 };
369 421
370 regulator@7 { 422 ldo3 {
371 reg = <7>;
372 regulator-compatible = "ldo3";
373 regulator-name = "vdd_ldo3,avdd_usb*"; 423 regulator-name = "vdd_ldo3,avdd_usb*";
374 regulator-min-microvolt = <3300000>; 424 regulator-min-microvolt = <3300000>;
375 regulator-max-microvolt = <3300000>; 425 regulator-max-microvolt = <3300000>;
376 regulator-always-on; 426 regulator-always-on;
377 }; 427 };
378 428
379 regulator@8 { 429 ldo4 {
380 reg = <8>;
381 regulator-compatible = "ldo4";
382 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 430 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
383 regulator-min-microvolt = <1800000>; 431 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>; 432 regulator-max-microvolt = <1800000>;
385 regulator-always-on; 433 regulator-always-on;
386 }; 434 };
387 435
388 regulator@9 { 436 ldo5 {
389 reg = <9>;
390 regulator-compatible = "ldo5";
391 regulator-name = "vdd_ldo5,vcore_mmc"; 437 regulator-name = "vdd_ldo5,vcore_mmc";
392 regulator-min-microvolt = <2850000>; 438 regulator-min-microvolt = <2850000>;
393 regulator-max-microvolt = <2850000>; 439 regulator-max-microvolt = <2850000>;
394 regulator-always-on; 440 regulator-always-on;
395 }; 441 };
396 442
397 regulator@10 { 443 ldo6 {
398 reg = <10>;
399 regulator-compatible = "ldo6";
400 regulator-name = "vdd_ldo6,avdd_vdac"; 444 regulator-name = "vdd_ldo6,avdd_vdac";
401 regulator-min-microvolt = <1800000>; 445 regulator-min-microvolt = <1800000>;
402 regulator-max-microvolt = <1800000>; 446 regulator-max-microvolt = <1800000>;
403 }; 447 };
404 448
405 regulator@11 { 449 ldo7 {
406 reg = <11>;
407 regulator-compatible = "ldo7";
408 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 450 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
409 regulator-min-microvolt = <3300000>; 451 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>; 452 regulator-max-microvolt = <3300000>;
411 }; 453 };
412 454
413 regulator@12 { 455 ldo8 {
414 reg = <12>;
415 regulator-compatible = "ldo8";
416 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 456 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
417 regulator-min-microvolt = <1800000>; 457 regulator-min-microvolt = <1800000>;
418 regulator-max-microvolt = <1800000>; 458 regulator-max-microvolt = <1800000>;
419 }; 459 };
420 460
421 regulator@13 { 461 ldo9 {
422 reg = <13>;
423 regulator-compatible = "ldo9";
424 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 462 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
425 regulator-min-microvolt = <2850000>; 463 regulator-min-microvolt = <2850000>;
426 regulator-max-microvolt = <2850000>; 464 regulator-max-microvolt = <2850000>;
427 regulator-always-on; 465 regulator-always-on;
428 }; 466 };
429 467
430 regulator@14 { 468 ldo_rtc {
431 reg = <14>;
432 regulator-compatible = "ldo_rtc";
433 regulator-name = "vdd_rtc_out,vdd_cell"; 469 regulator-name = "vdd_rtc_out,vdd_cell";
434 regulator-min-microvolt = <3300000>; 470 regulator-min-microvolt = <3300000>;
435 regulator-max-microvolt = <3300000>; 471 regulator-max-microvolt = <3300000>;
@@ -437,6 +473,11 @@
437 }; 473 };
438 }; 474 };
439 }; 475 };
476
477 temperature-sensor@4c {
478 compatible = "onnn,nct1008";
479 reg = <0x4c>;
480 };
440 }; 481 };
441 482
442 pmc { 483 pmc {
@@ -456,6 +497,12 @@
456 status = "okay"; 497 status = "okay";
457 }; 498 };
458 499
500 sdhci@c8000000 {
501 status = "okay";
502 power-gpios = <&gpio 86 0>; /* gpio PK6 */
503 bus-width = <4>;
504 };
505
459 sdhci@c8000400 { 506 sdhci@c8000400 {
460 status = "okay"; 507 status = "okay";
461 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 508 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index c636d002d6d8..20d576ecd555 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -10,6 +10,18 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
13 pinmux { 25 pinmux {
14 pinctrl-names = "default"; 26 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 27 pinctrl-0 = <&state_default>;
@@ -246,6 +258,11 @@
246 clock-frequency = <216000000>; 258 clock-frequency = <216000000>;
247 }; 259 };
248 260
261 hdmi_ddc: i2c@7000c400 {
262 status = "okay";
263 clock-frequency = <100000>;
264 };
265
249 i2c@7000d000 { 266 i2c@7000d000 {
250 status = "okay"; 267 status = "okay";
251 clock-frequency = <100000>; 268 clock-frequency = <100000>;
@@ -295,243 +312,182 @@
295 in20-supply = <&mbatt_reg>; 312 in20-supply = <&mbatt_reg>;
296 313
297 regulators { 314 regulators {
298 #address-cells = <1>; 315 mbatt_reg: mbatt {
299 #size-cells = <0>;
300
301 mbatt_reg: regulator@0 {
302 reg = <0>;
303 regulator-compatible = "mbatt";
304 regulator-name = "vbat_pmu"; 316 regulator-name = "vbat_pmu";
305 regulator-always-on; 317 regulator-always-on;
306 }; 318 };
307 319
308 regulator@1 { 320 sd1 {
309 reg = <1>;
310 regulator-compatible = "sd1";
311 regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; 321 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
312 regulator-min-microvolt = <1000000>; 322 regulator-min-microvolt = <1000000>;
313 regulator-max-microvolt = <1000000>; 323 regulator-max-microvolt = <1000000>;
314 regulator-always-on; 324 regulator-always-on;
315 }; 325 };
316 326
317 regulator@2 { 327 sd2 {
318 reg = <2>;
319 regulator-compatible = "sd2";
320 regulator-name = "nvvdd_sv2,vdd_core"; 328 regulator-name = "nvvdd_sv2,vdd_core";
321 regulator-min-microvolt = <1200000>; 329 regulator-min-microvolt = <1200000>;
322 regulator-max-microvolt = <1200000>; 330 regulator-max-microvolt = <1200000>;
323 regulator-always-on; 331 regulator-always-on;
324 }; 332 };
325 333
326 nvvdd_sv3_reg: regulator@3 { 334 nvvdd_sv3_reg: sd3 {
327 reg = <3>;
328 regulator-compatible = "sd3";
329 regulator-name = "nvvdd_sv3"; 335 regulator-name = "nvvdd_sv3";
330 regulator-min-microvolt = <1800000>; 336 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>; 337 regulator-max-microvolt = <1800000>;
332 regulator-always-on; 338 regulator-always-on;
333 }; 339 };
334 340
335 regulator@4 { 341 ldo1 {
336 reg = <4>;
337 regulator-compatible = "ldo1";
338 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; 342 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
339 regulator-min-microvolt = <3300000>; 343 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>; 344 regulator-max-microvolt = <3300000>;
341 regulator-always-on; 345 regulator-always-on;
342 }; 346 };
343 347
344 regulator@5 { 348 ldo2 {
345 reg = <5>;
346 regulator-compatible = "ldo2";
347 regulator-name = "nvvdd_ldo2,avdd_pll*"; 349 regulator-name = "nvvdd_ldo2,avdd_pll*";
348 regulator-min-microvolt = <1100000>; 350 regulator-min-microvolt = <1100000>;
349 regulator-max-microvolt = <1100000>; 351 regulator-max-microvolt = <1100000>;
350 regulator-always-on; 352 regulator-always-on;
351 }; 353 };
352 354
353 regulator@6 { 355 ldo3 {
354 reg = <6>;
355 regulator-compatible = "ldo3";
356 regulator-name = "nvvdd_ldo3,vcom_1v8b"; 356 regulator-name = "nvvdd_ldo3,vcom_1v8b";
357 regulator-min-microvolt = <1800000>; 357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>; 358 regulator-max-microvolt = <1800000>;
359 regulator-always-on; 359 regulator-always-on;
360 }; 360 };
361 361
362 regulator@7 { 362 ldo4 {
363 reg = <7>;
364 regulator-compatible = "ldo4";
365 regulator-name = "nvvdd_ldo4,avdd_usb*"; 363 regulator-name = "nvvdd_ldo4,avdd_usb*";
366 regulator-min-microvolt = <3300000>; 364 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>; 365 regulator-max-microvolt = <3300000>;
368 regulator-always-on; 366 regulator-always-on;
369 }; 367 };
370 368
371 regulator@8 { 369 ldo5 {
372 reg = <8>;
373 regulator-compatible = "ldo5";
374 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; 370 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
375 regulator-min-microvolt = <2800000>; 371 regulator-min-microvolt = <2800000>;
376 regulator-max-microvolt = <2800000>; 372 regulator-max-microvolt = <2800000>;
377 regulator-always-on; 373 regulator-always-on;
378 }; 374 };
379 375
380 regulator@9 { 376 hdmi_pll_reg: ldo6 {
381 reg = <9>;
382 regulator-compatible = "ldo6";
383 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; 377 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
384 regulator-min-microvolt = <1800000>; 378 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>; 379 regulator-max-microvolt = <1800000>;
386 }; 380 };
387 381
388 regulator@10 { 382 ldo7 {
389 reg = <10>;
390 regulator-compatible = "ldo7";
391 regulator-name = "nvvdd_ldo7,avddio_audio"; 383 regulator-name = "nvvdd_ldo7,avddio_audio";
392 regulator-min-microvolt = <2800000>; 384 regulator-min-microvolt = <2800000>;
393 regulator-max-microvolt = <2800000>; 385 regulator-max-microvolt = <2800000>;
394 regulator-always-on; 386 regulator-always-on;
395 }; 387 };
396 388
397 regulator@11 { 389 ldo8 {
398 reg = <11>;
399 regulator-compatible = "ldo8";
400 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; 390 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
401 regulator-min-microvolt = <3000000>; 391 regulator-min-microvolt = <3000000>;
402 regulator-max-microvolt = <3000000>; 392 regulator-max-microvolt = <3000000>;
403 }; 393 };
404 394
405 regulator@12 { 395 ldo9 {
406 reg = <12>;
407 regulator-compatible = "ldo9";
408 regulator-name = "nvvdd_ldo9,avdd_cam*"; 396 regulator-name = "nvvdd_ldo9,avdd_cam*";
409 regulator-min-microvolt = <2800000>; 397 regulator-min-microvolt = <2800000>;
410 regulator-max-microvolt = <2800000>; 398 regulator-max-microvolt = <2800000>;
411 }; 399 };
412 400
413 regulator@13 { 401 ldo10 {
414 reg = <13>;
415 regulator-compatible = "ldo10";
416 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; 402 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
417 regulator-min-microvolt = <3000000>; 403 regulator-min-microvolt = <3000000>;
418 regulator-max-microvolt = <3000000>; 404 regulator-max-microvolt = <3000000>;
419 regulator-always-on; 405 regulator-always-on;
420 }; 406 };
421 407
422 regulator@14 { 408 hdmi_vdd_reg: ldo11 {
423 reg = <14>;
424 regulator-compatible = "ldo11";
425 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; 409 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
426 regulator-min-microvolt = <3300000>; 410 regulator-min-microvolt = <3300000>;
427 regulator-max-microvolt = <3300000>; 411 regulator-max-microvolt = <3300000>;
428 }; 412 };
429 413
430 regulator@15 { 414 ldo12 {
431 reg = <15>;
432 regulator-compatible = "ldo12";
433 regulator-name = "nvvdd_ldo12,vddio_sdio"; 415 regulator-name = "nvvdd_ldo12,vddio_sdio";
434 regulator-min-microvolt = <2800000>; 416 regulator-min-microvolt = <2800000>;
435 regulator-max-microvolt = <2800000>; 417 regulator-max-microvolt = <2800000>;
436 regulator-always-on; 418 regulator-always-on;
437 }; 419 };
438 420
439 regulator@16 { 421 ldo13 {
440 reg = <16>;
441 regulator-compatible = "ldo13";
442 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; 422 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
443 regulator-min-microvolt = <2800000>; 423 regulator-min-microvolt = <2800000>;
444 regulator-max-microvolt = <2800000>; 424 regulator-max-microvolt = <2800000>;
445 }; 425 };
446 426
447 regulator@17 { 427 ldo14 {
448 reg = <17>;
449 regulator-compatible = "ldo14";
450 regulator-name = "nvvdd_ldo14,avdd_vdac"; 428 regulator-name = "nvvdd_ldo14,avdd_vdac";
451 regulator-min-microvolt = <2800000>; 429 regulator-min-microvolt = <2800000>;
452 regulator-max-microvolt = <2800000>; 430 regulator-max-microvolt = <2800000>;
453 }; 431 };
454 432
455 regulator@18 { 433 ldo15 {
456 reg = <18>;
457 regulator-compatible = "ldo15";
458 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; 434 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
459 regulator-min-microvolt = <3300000>; 435 regulator-min-microvolt = <3300000>;
460 regulator-max-microvolt = <3300000>; 436 regulator-max-microvolt = <3300000>;
461 }; 437 };
462 438
463 regulator@19 { 439 ldo16 {
464 reg = <19>;
465 regulator-compatible = "ldo16";
466 regulator-name = "nvvdd_ldo16,vdd_dbrtr"; 440 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
467 regulator-min-microvolt = <1300000>; 441 regulator-min-microvolt = <1300000>;
468 regulator-max-microvolt = <1300000>; 442 regulator-max-microvolt = <1300000>;
469 }; 443 };
470 444
471 regulator@20 { 445 ldo17 {
472 reg = <20>;
473 regulator-compatible = "ldo17";
474 regulator-name = "nvvdd_ldo17,vddio_mipi"; 446 regulator-name = "nvvdd_ldo17,vddio_mipi";
475 regulator-min-microvolt = <1200000>; 447 regulator-min-microvolt = <1200000>;
476 regulator-max-microvolt = <1200000>; 448 regulator-max-microvolt = <1200000>;
477 }; 449 };
478 450
479 regulator@21 { 451 ldo18 {
480 reg = <21>;
481 regulator-compatible = "ldo18";
482 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; 452 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
483 regulator-min-microvolt = <1800000>; 453 regulator-min-microvolt = <1800000>;
484 regulator-max-microvolt = <1800000>; 454 regulator-max-microvolt = <1800000>;
485 }; 455 };
486 456
487 regulator@22 { 457 ldo19 {
488 reg = <22>;
489 regulator-compatible = "ldo19";
490 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; 458 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
491 regulator-min-microvolt = <2800000>; 459 regulator-min-microvolt = <2800000>;
492 regulator-max-microvolt = <2800000>; 460 regulator-max-microvolt = <2800000>;
493 }; 461 };
494 462
495 regulator@23 { 463 ldo20 {
496 reg = <23>;
497 regulator-compatible = "ldo20";
498 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; 464 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
499 regulator-min-microvolt = <1200000>; 465 regulator-min-microvolt = <1200000>;
500 regulator-max-microvolt = <1200000>; 466 regulator-max-microvolt = <1200000>;
501 regulator-always-on; 467 regulator-always-on;
502 }; 468 };
503 469
504 regulator@24 { 470 out5v {
505 reg = <24>;
506 regulator-compatible = "out5v";
507 regulator-name = "usb0_vbus_reg"; 471 regulator-name = "usb0_vbus_reg";
508 }; 472 };
509 473
510 regulator@25 { 474 out33v {
511 reg = <25>;
512 regulator-compatible = "out33v";
513 regulator-name = "pmu_out3v3"; 475 regulator-name = "pmu_out3v3";
514 }; 476 };
515 477
516 regulator@26 { 478 bbat {
517 reg = <26>;
518 regulator-compatible = "bbat";
519 regulator-name = "pmu_bbat"; 479 regulator-name = "pmu_bbat";
520 regulator-min-microvolt = <2400000>; 480 regulator-min-microvolt = <2400000>;
521 regulator-max-microvolt = <2400000>; 481 regulator-max-microvolt = <2400000>;
522 regulator-always-on; 482 regulator-always-on;
523 }; 483 };
524 484
525 regulator@27 { 485 sdby {
526 reg = <27>;
527 regulator-compatible = "sdby";
528 regulator-name = "vdd_aon"; 486 regulator-name = "vdd_aon";
529 regulator-always-on; 487 regulator-always-on;
530 }; 488 };
531 489
532 regulator@28 { 490 vrtc {
533 reg = <28>;
534 regulator-compatible = "vrtc";
535 regulator-name = "vrtc,pmu_vccadc"; 491 regulator-name = "vrtc,pmu_vccadc";
536 regulator-always-on; 492 regulator-always-on;
537 }; 493 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f3a09d0d45bc..b8effa1cbda7 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,108 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 host1x {
8 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0x304>;
98 };
99
100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <5 5 2>;
104 arm,tag-latency = <4 4 2>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
7 intc: interrupt-controller { 109 intc: interrupt-controller {
8 compatible = "arm,cortex-a9-gic"; 110 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000 111 reg = <0x50041000 0x1000
@@ -12,6 +114,15 @@
12 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
13 }; 115 };
14 116
117 timer@60005000 {
118 compatible = "nvidia,tegra20-timer";
119 reg = <0x60005000 0x60>;
120 interrupts = <0 0 0x04
121 0 1 0x04
122 0 41 0x04
123 0 42 0x04>;
124 };
125
15 apbdma: dma { 126 apbdma: dma {
16 compatible = "nvidia,tegra20-apbdma"; 127 compatible = "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1200>; 128 reg = <0x6000a000 0x1200>;
@@ -129,6 +240,12 @@
129 #pwm-cells = <2>; 240 #pwm-cells = <2>;
130 }; 241 };
131 242
243 rtc {
244 compatible = "nvidia,tegra20-rtc";
245 reg = <0x7000e000 0x100>;
246 interrupts = <0 2 0x04>;
247 };
248
132 i2c@7000c000 { 249 i2c@7000c000 {
133 compatible = "nvidia,tegra20-i2c"; 250 compatible = "nvidia,tegra20-i2c";
134 reg = <0x7000c000 0x100>; 251 reg = <0x7000c000 0x100>;
@@ -138,6 +255,16 @@
138 status = "disabled"; 255 status = "disabled";
139 }; 256 };
140 257
258 spi@7000c380 {
259 compatible = "nvidia,tegra20-sflash";
260 reg = <0x7000c380 0x80>;
261 interrupts = <0 39 0x04>;
262 nvidia,dma-request-selector = <&apbdma 11>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
267
141 i2c@7000c400 { 268 i2c@7000c400 {
142 compatible = "nvidia,tegra20-i2c"; 269 compatible = "nvidia,tegra20-i2c";
143 reg = <0x7000c400 0x100>; 270 reg = <0x7000c400 0x100>;
@@ -165,6 +292,46 @@
165 status = "disabled"; 292 status = "disabled";
166 }; 293 };
167 294
295 spi@7000d400 {
296 compatible = "nvidia,tegra20-slink";
297 reg = <0x7000d400 0x200>;
298 interrupts = <0 59 0x04>;
299 nvidia,dma-request-selector = <&apbdma 15>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 status = "disabled";
303 };
304
305 spi@7000d600 {
306 compatible = "nvidia,tegra20-slink";
307 reg = <0x7000d600 0x200>;
308 interrupts = <0 82 0x04>;
309 nvidia,dma-request-selector = <&apbdma 16>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 spi@7000d800 {
316 compatible = "nvidia,tegra20-slink";
317 reg = <0x7000d480 0x200>;
318 interrupts = <0 83 0x04>;
319 nvidia,dma-request-selector = <&apbdma 17>;
320 #address-cells = <1>;
321 #size-cells = <0>;
322 status = "disabled";
323 };
324
325 spi@7000da00 {
326 compatible = "nvidia,tegra20-slink";
327 reg = <0x7000da00 0x200>;
328 interrupts = <0 93 0x04>;
329 nvidia,dma-request-selector = <&apbdma 18>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 status = "disabled";
333 };
334
168 pmc { 335 pmc {
169 compatible = "nvidia,tegra20-pmc"; 336 compatible = "nvidia,tegra20-pmc";
170 reg = <0x7000e400 0x400>; 337 reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index dd4222f00eca..adc88aa50eb6 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -83,5 +83,11 @@
83 gpio = <&gpio 83 0>; /* GPIO PK3 */ 83 gpio = <&gpio 83 0>; /* GPIO PK3 */
84 }; 84 };
85 }; 85 };
86
87 sdhci@78000400 {
88 status = "okay";
89 power-gpios = <&gpio 28 0>; /* gpio PD4 */
90 bus-width = <4>;
91 };
86}; 92};
87 93
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index 0828f097ca86..08163e145d57 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -95,4 +95,10 @@
95 gpio = <&gpio 232 0>; /* GPIO PDD0 */ 95 gpio = <&gpio 232 0>; /* GPIO PDD0 */
96 }; 96 };
97 }; 97 };
98
99 sdhci@78000400 {
100 status = "okay";
101 power-gpios = <&gpio 27 0>; /* gpio PD3 */
102 bus-width = <4>;
103 };
98}; 104};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index d10c9c5a3606..bdb2a660f376 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -52,6 +52,22 @@
52 nvidia,pull = <2>; 52 nvidia,pull = <2>;
53 nvidia,tristate = <0>; 53 nvidia,tristate = <0>;
54 }; 54 };
55 sdmmc3_clk_pa6 {
56 nvidia,pins = "sdmmc3_clk_pa6";
57 nvidia,function = "sdmmc3";
58 nvidia,pull = <0>;
59 nvidia,tristate = <0>;
60 };
61 sdmmc3_cmd_pa7 {
62 nvidia,pins = "sdmmc3_cmd_pa7",
63 "sdmmc3_dat0_pb7",
64 "sdmmc3_dat1_pb6",
65 "sdmmc3_dat2_pb5",
66 "sdmmc3_dat3_pb4";
67 nvidia,function = "sdmmc3";
68 nvidia,pull = <2>;
69 nvidia,tristate = <0>;
70 };
55 sdmmc4_clk_pcc4 { 71 sdmmc4_clk_pcc4 {
56 nvidia,pins = "sdmmc4_clk_pcc4", 72 nvidia,pins = "sdmmc4_clk_pcc4",
57 "sdmmc4_rst_n_pcc3"; 73 "sdmmc4_rst_n_pcc3";
@@ -81,6 +97,15 @@
81 nvidia,pull = <0>; 97 nvidia,pull = <0>;
82 nvidia,tristate = <0>; 98 nvidia,tristate = <0>;
83 }; 99 };
100 sdio3 {
101 nvidia,pins = "drive_sdio3";
102 nvidia,high-speed-mode = <0>;
103 nvidia,schmitt = <0>;
104 nvidia,pull-down-strength = <46>;
105 nvidia,pull-up-strength = <42>;
106 nvidia,slew-rate-rising = <1>;
107 nvidia,slew-rate-falling = <1>;
108 };
84 }; 109 };
85 }; 110 };
86 111
@@ -171,56 +196,41 @@
171 vccio-supply = <&vdd_ac_bat_reg>; 196 vccio-supply = <&vdd_ac_bat_reg>;
172 197
173 regulators { 198 regulators {
174 #address-cells = <1>; 199 vdd1_reg: vdd1 {
175 #size-cells = <0>;
176
177 vdd1_reg: regulator@0 {
178 reg = <0>;
179 regulator-compatible = "vdd1";
180 regulator-name = "vddio_ddr_1v2"; 200 regulator-name = "vddio_ddr_1v2";
181 regulator-min-microvolt = <1200000>; 201 regulator-min-microvolt = <1200000>;
182 regulator-max-microvolt = <1200000>; 202 regulator-max-microvolt = <1200000>;
183 regulator-always-on; 203 regulator-always-on;
184 }; 204 };
185 205
186 vdd2_reg: regulator@1 { 206 vdd2_reg: vdd2 {
187 reg = <1>;
188 regulator-compatible = "vdd2";
189 regulator-name = "vdd_1v5_gen"; 207 regulator-name = "vdd_1v5_gen";
190 regulator-min-microvolt = <1500000>; 208 regulator-min-microvolt = <1500000>;
191 regulator-max-microvolt = <1500000>; 209 regulator-max-microvolt = <1500000>;
192 regulator-always-on; 210 regulator-always-on;
193 }; 211 };
194 212
195 vddctrl_reg: regulator@2 { 213 vddctrl_reg: vddctrl {
196 reg = <2>;
197 regulator-compatible = "vddctrl";
198 regulator-name = "vdd_cpu,vdd_sys"; 214 regulator-name = "vdd_cpu,vdd_sys";
199 regulator-min-microvolt = <1000000>; 215 regulator-min-microvolt = <1000000>;
200 regulator-max-microvolt = <1000000>; 216 regulator-max-microvolt = <1000000>;
201 regulator-always-on; 217 regulator-always-on;
202 }; 218 };
203 219
204 vio_reg: regulator@3 { 220 vio_reg: vio {
205 reg = <3>;
206 regulator-compatible = "vio";
207 regulator-name = "vdd_1v8_gen"; 221 regulator-name = "vdd_1v8_gen";
208 regulator-min-microvolt = <1800000>; 222 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <1800000>; 223 regulator-max-microvolt = <1800000>;
210 regulator-always-on; 224 regulator-always-on;
211 }; 225 };
212 226
213 ldo1_reg: regulator@4 { 227 ldo1_reg: ldo1 {
214 reg = <4>;
215 regulator-compatible = "ldo1";
216 regulator-name = "vdd_pexa,vdd_pexb"; 228 regulator-name = "vdd_pexa,vdd_pexb";
217 regulator-min-microvolt = <1050000>; 229 regulator-min-microvolt = <1050000>;
218 regulator-max-microvolt = <1050000>; 230 regulator-max-microvolt = <1050000>;
219 }; 231 };
220 232
221 ldo2_reg: regulator@5 { 233 ldo2_reg: ldo2 {
222 reg = <5>;
223 regulator-compatible = "ldo2";
224 regulator-name = "vdd_sata,avdd_plle"; 234 regulator-name = "vdd_sata,avdd_plle";
225 regulator-min-microvolt = <1050000>; 235 regulator-min-microvolt = <1050000>;
226 regulator-max-microvolt = <1050000>; 236 regulator-max-microvolt = <1050000>;
@@ -228,44 +238,34 @@
228 238
229 /* LDO3 is not connected to anything */ 239 /* LDO3 is not connected to anything */
230 240
231 ldo4_reg: regulator@7 { 241 ldo4_reg: ldo4 {
232 reg = <7>;
233 regulator-compatible = "ldo4";
234 regulator-name = "vdd_rtc"; 242 regulator-name = "vdd_rtc";
235 regulator-min-microvolt = <1200000>; 243 regulator-min-microvolt = <1200000>;
236 regulator-max-microvolt = <1200000>; 244 regulator-max-microvolt = <1200000>;
237 regulator-always-on; 245 regulator-always-on;
238 }; 246 };
239 247
240 ldo5_reg: regulator@8 { 248 ldo5_reg: ldo5 {
241 reg = <8>;
242 regulator-compatible = "ldo5";
243 regulator-name = "vddio_sdmmc,avdd_vdac"; 249 regulator-name = "vddio_sdmmc,avdd_vdac";
244 regulator-min-microvolt = <3300000>; 250 regulator-min-microvolt = <3300000>;
245 regulator-max-microvolt = <3300000>; 251 regulator-max-microvolt = <3300000>;
246 regulator-always-on; 252 regulator-always-on;
247 }; 253 };
248 254
249 ldo6_reg: regulator@9 { 255 ldo6_reg: ldo6 {
250 reg = <9>;
251 regulator-compatible = "ldo6";
252 regulator-name = "avdd_dsi_csi,pwrdet_mipi"; 256 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
253 regulator-min-microvolt = <1200000>; 257 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1200000>; 258 regulator-max-microvolt = <1200000>;
255 }; 259 };
256 260
257 ldo7_reg: regulator@10 { 261 ldo7_reg: ldo7 {
258 reg = <10>;
259 regulator-compatible = "ldo7";
260 regulator-name = "vdd_pllm,x,u,a_p_c_s"; 262 regulator-name = "vdd_pllm,x,u,a_p_c_s";
261 regulator-min-microvolt = <1200000>; 263 regulator-min-microvolt = <1200000>;
262 regulator-max-microvolt = <1200000>; 264 regulator-max-microvolt = <1200000>;
263 regulator-always-on; 265 regulator-always-on;
264 }; 266 };
265 267
266 ldo8_reg: regulator@11 { 268 ldo8_reg: ldo8 {
267 reg = <11>;
268 regulator-compatible = "ldo8";
269 regulator-name = "vdd_ddr_hs"; 269 regulator-name = "vdd_ddr_hs";
270 regulator-min-microvolt = <1000000>; 270 regulator-min-microvolt = <1000000>;
271 regulator-max-microvolt = <1000000>; 271 regulator-max-microvolt = <1000000>;
@@ -275,6 +275,16 @@
275 }; 275 };
276 }; 276 };
277 277
278 spi@7000da00 {
279 status = "okay";
280 spi-max-frequency = <25000000>;
281 spi-flash@1 {
282 compatible = "winbond,w25q32";
283 reg = <1>;
284 spi-max-frequency = <20000000>;
285 };
286 };
287
278 ahub { 288 ahub {
279 i2s@70080400 { 289 i2s@70080400 {
280 status = "okay"; 290 status = "okay";
@@ -409,6 +419,8 @@
409 regulator-name = "vdd_com"; 419 regulator-name = "vdd_com";
410 regulator-min-microvolt = <3300000>; 420 regulator-min-microvolt = <3300000>;
411 regulator-max-microvolt = <3300000>; 421 regulator-max-microvolt = <3300000>;
422 regulator-always-on;
423 regulator-boot-on;
412 enable-active-high; 424 enable-active-high;
413 gpio = <&gpio 24 0>; /* gpio PD0 */ 425 gpio = <&gpio 24 0>; /* gpio PD0 */
414 vin-supply = <&sys_3v3_reg>; 426 vin-supply = <&sys_3v3_reg>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index b1497c7d7d68..547db83af266 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,108 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0xf04>;
98 };
99
100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <6 6 2>;
104 arm,tag-latency = <5 5 2>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
7 intc: interrupt-controller { 109 intc: interrupt-controller {
8 compatible = "arm,cortex-a9-gic"; 110 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000 111 reg = <0x50041000 0x1000
@@ -12,6 +114,17 @@
12 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
13 }; 115 };
14 116
117 timer@60005000 {
118 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
119 reg = <0x60005000 0x400>;
120 interrupts = <0 0 0x04
121 0 1 0x04
122 0 41 0x04
123 0 42 0x04
124 0 121 0x04
125 0 122 0x04>;
126 };
127
15 apbdma: dma { 128 apbdma: dma {
16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 129 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1400>; 130 reg = <0x6000a000 0x1400>;
@@ -123,6 +236,12 @@
123 #pwm-cells = <2>; 236 #pwm-cells = <2>;
124 }; 237 };
125 238
239 rtc {
240 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
241 reg = <0x7000e000 0x100>;
242 interrupts = <0 2 0x04>;
243 };
244
126 i2c@7000c000 { 245 i2c@7000c000 {
127 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 246 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
128 reg = <0x7000c000 0x100>; 247 reg = <0x7000c000 0x100>;
@@ -168,6 +287,66 @@
168 status = "disabled"; 287 status = "disabled";
169 }; 288 };
170 289
290 spi@7000d400 {
291 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
292 reg = <0x7000d400 0x200>;
293 interrupts = <0 59 0x04>;
294 nvidia,dma-request-selector = <&apbdma 15>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 spi@7000d600 {
301 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
302 reg = <0x7000d600 0x200>;
303 interrupts = <0 82 0x04>;
304 nvidia,dma-request-selector = <&apbdma 16>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 status = "disabled";
308 };
309
310 spi@7000d800 {
311 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
312 reg = <0x7000d480 0x200>;
313 interrupts = <0 83 0x04>;
314 nvidia,dma-request-selector = <&apbdma 17>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 status = "disabled";
318 };
319
320 spi@7000da00 {
321 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
322 reg = <0x7000da00 0x200>;
323 interrupts = <0 93 0x04>;
324 nvidia,dma-request-selector = <&apbdma 18>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 status = "disabled";
328 };
329
330 spi@7000dc00 {
331 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
332 reg = <0x7000dc00 0x200>;
333 interrupts = <0 94 0x04>;
334 nvidia,dma-request-selector = <&apbdma 27>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
339
340 spi@7000de00 {
341 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
342 reg = <0x7000de00 0x200>;
343 interrupts = <0 79 0x04>;
344 nvidia,dma-request-selector = <&apbdma 28>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349
171 pmc { 350 pmc {
172 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; 351 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
173 reg = <0x7000e400 0x400>; 352 reg = <0x7000e400 0x400>;
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
new file mode 100644
index 000000000000..883d7c22fd9d
--- /dev/null
+++ b/arch/arm/include/debug/tegra.S
@@ -0,0 +1,223 @@
1/*
2 * Copyright (C) 2010,2011 Google, Inc.
3 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
4 *
5 * Author:
6 * Colin Cross <ccross@google.com>
7 * Erik Gilling <konkers@google.com>
8 * Doug Anderson <dianders@chromium.org>
9 * Stephen Warren <swarren@nvidia.com>
10 *
11 * Portions based on mach-omap2's debug-macro.S
12 * Copyright (C) 1994-1999 Russell King
13 *
14 * This software is licensed under the terms of the GNU General Public
15 * License version 2, as published by the Free Software Foundation, and
16 * may be copied, distributed, and modified under those terms.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 */
24
25#include <linux/serial_reg.h>
26
27#define UART_SHIFT 2
28
29/* Physical addresses */
30#define TEGRA_CLK_RESET_BASE 0x60006000
31#define TEGRA_APB_MISC_BASE 0x70000000
32#define TEGRA_UARTA_BASE 0x70006000
33#define TEGRA_UARTB_BASE 0x70006040
34#define TEGRA_UARTC_BASE 0x70006200
35#define TEGRA_UARTD_BASE 0x70006300
36#define TEGRA_UARTE_BASE 0x70006400
37#define TEGRA_PMC_BASE 0x7000e400
38
39#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
40#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
41#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
42#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
43#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
44#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
45#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
46#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
47
48/*
49 * Must be 1MB-aligned since a 1MB mapping is used early on.
50 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
51 */
52#define UART_VIRTUAL_BASE 0xfe100000
53
54#define checkuart(rp, rv, lhu, bit, uart) \
55 /* Load address of CLK_RST register */ \
56 movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
57 movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
58 /* Load value from CLK_RST register */ \
59 ldr rp, [rp, #0] ; \
60 /* Test UART's reset bit */ \
61 tst rp, #(1 << bit) ; \
62 /* If set, can't use UART; jump to save no UART */ \
63 bne 90f ; \
64 /* Load address of CLK_OUT_ENB register */ \
65 movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
66 movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
67 /* Load value from CLK_OUT_ENB register */ \
68 ldr rp, [rp, #0] ; \
69 /* Test UART's clock enable bit */ \
70 tst rp, #(1 << bit) ; \
71 /* If clear, can't use UART; jump to save no UART */ \
72 beq 90f ; \
73 /* Passed all tests, load address of UART registers */ \
74 movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
75 movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
76 /* Jump to save UART address */ \
77 b 91f
78
79 .macro addruart, rp, rv, tmp
80 adr \rp, 99f @ actual addr of 99f
81 ldr \rv, [\rp] @ linked addr is stored there
82 sub \rv, \rv, \rp @ offset between the two
83 ldr \rp, [\rp, #4] @ linked tegra_uart_config
84 sub \tmp, \rp, \rv @ actual tegra_uart_config
85 ldr \rp, [\tmp] @ Load tegra_uart_config
86 cmp \rp, #1 @ needs initialization?
87 bne 100f @ no; go load the addresses
88 mov \rv, #0 @ yes; record init is done
89 str \rv, [\tmp]
90
91#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
92 /* Check ODMDATA */
9310: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
94 movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
95 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
96 ubfx \rv, \rp, #18, #2 @ 19:18 are console type
97 cmp \rv, #2 @ 2 and 3 mean DCC, UART
98 beq 11f @ some boards swap the meaning
99 cmp \rv, #3 @ so accept either
100 bne 90f
10111: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
102 cmp \rv, #0 @ UART 0?
103 beq 20f
104 cmp \rv, #1 @ UART 1?
105 beq 21f
106 cmp \rv, #2 @ UART 2?
107 beq 22f
108 cmp \rv, #3 @ UART 3?
109 beq 23f
110 cmp \rv, #4 @ UART 4?
111 beq 24f
112 b 90f @ invalid
113#endif
114
115#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
116 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
117 /* Check UART A validity */
11820: checkuart(\rp, \rv, L, 6, A)
119#endif
120
121#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
122 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
123 /* Check UART B validity */
12421: checkuart(\rp, \rv, L, 7, B)
125#endif
126
127#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
128 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
129 /* Check UART C validity */
13022: checkuart(\rp, \rv, H, 23, C)
131#endif
132
133#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
134 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
135 /* Check UART D validity */
13623: checkuart(\rp, \rv, U, 1, D)
137#endif
138
139#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
140 defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
141 /* Check UART E validity */
14224:
143 checkuart(\rp, \rv, U, 2, E)
144#endif
145
146 /* No valid UART found */
14790: mov \rp, #0
148 /* fall through */
149
150 /* Record whichever UART we chose */
15191: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
152 cmp \rp, #0 @ Valid UART address?
153 bne 92f @ Yes, go process it
154 str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
155 b 100f @ Done
15692: and \rv, \rp, #0xffffff @ offset within 1MB section
157 add \rv, \rv, #UART_VIRTUAL_BASE
158 str \rv, [\tmp, #8] @ Store in tegra_uart_virt
159 movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
160 movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
161 ldr \rv, [\rv, #0] @ Load HIDREV
162 ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
163 cmp \rv, #0x20 @ Tegra20?
164 moveq \rv, #0x75 @ Tegra20 divisor
165 movne \rv, #0xdd @ Tegra30 divisor
166 str \rv, [\tmp, #12] @ Save divisor to scratch
167 /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
168 mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
169 str \rv, [\rp, #UART_LCR << UART_SHIFT]
170 /* uart[UART_DLL] = div & 0xff; */
171 ldr \rv, [\tmp, #12]
172 and \rv, \rv, #0xff
173 str \rv, [\rp, #UART_DLL << UART_SHIFT]
174 /* uart[UART_DLM] = div >> 8; */
175 ldr \rv, [\tmp, #12]
176 lsr \rv, \rv, #8
177 str \rv, [\rp, #UART_DLM << UART_SHIFT]
178 /* uart[UART_LCR] = UART_LCR_WLEN8; */
179 mov \rv, #UART_LCR_WLEN8
180 str \rv, [\rp, #UART_LCR << UART_SHIFT]
181 b 100f
182
183 .align
18499: .word .
185 .word tegra_uart_config
186 .ltorg
187
188 /* Load previously selected UART address */
189100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
190 ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
191 .endm
192
193/*
194 * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
195 * check to make sure that the UART address is actually valid.
196 */
197
198 .macro senduart, rd, rx
199 cmp \rx, #0
200 strneb \rd, [\rx, #UART_TX << UART_SHIFT]
2011001:
202 .endm
203
204 .macro busyuart, rd, rx
205 cmp \rx, #0
206 beq 1002f
2071001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
208 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
209 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
210 bne 1001b
2111002:
212 .endm
213
214 .macro waituart, rd, rx
215#ifdef FLOW_CONTROL
216 cmp \rx, #0
217 beq 1002f
2181001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
219 tst \rd, #UART_MSR_CTS
220 beq 1001b
2211002:
222#endif
223 .endm
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 9ff6f6ea3617..e426d1b7747e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -57,57 +57,6 @@ config TEGRA_AHB
57 which controls AHB bus master arbitration and some 57 which controls AHB bus master arbitration and some
58 perfomance parameters(priority, prefech size). 58 perfomance parameters(priority, prefech size).
59 59
60choice
61 prompt "Default low-level debug console UART"
62 default TEGRA_DEBUG_UART_NONE
63
64config TEGRA_DEBUG_UART_NONE
65 bool "None"
66
67config TEGRA_DEBUG_UARTA
68 bool "UART-A"
69
70config TEGRA_DEBUG_UARTB
71 bool "UART-B"
72
73config TEGRA_DEBUG_UARTC
74 bool "UART-C"
75
76config TEGRA_DEBUG_UARTD
77 bool "UART-D"
78
79config TEGRA_DEBUG_UARTE
80 bool "UART-E"
81
82endchoice
83
84choice
85 prompt "Automatic low-level debug console UART"
86 default TEGRA_DEBUG_UART_AUTO_NONE
87
88config TEGRA_DEBUG_UART_AUTO_NONE
89 bool "None"
90
91config TEGRA_DEBUG_UART_AUTO_ODMDATA
92 bool "Via ODMDATA"
93 help
94 Automatically determines which UART to use for low-level debug based
95 on the ODMDATA value. This value is part of the BCT, and is written
96 to the boot memory device using nvflash, or other flashing tool.
97 When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
98 0/1/2/3/4 are UART A/B/C/D/E.
99
100config TEGRA_DEBUG_UART_AUTO_SCRATCH
101 bool "Via UART scratch register"
102 help
103 Automatically determines which UART to use for low-level debug based
104 on the UART scratch register value. Some bootloaders put ASCII 'D'
105 in this register when they initialize their own console UART output.
106 Using this option allows the kernel to automatically pick the same
107 UART.
108
109endchoice
110
111config TEGRA_EMC_SCALING_ENABLE 60config TEGRA_EMC_SCALING_ENABLE
112 bool "Enable scaling the memory frequency" 61 bool "Enable scaling the memory frequency"
113 62
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 9aa653b3eb32..6cc23cc83509 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,10 +12,12 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
12obj-$(CONFIG_CPU_IDLE) += sleep.o 12obj-$(CONFIG_CPU_IDLE) += sleep.o
13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o 13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o 17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o
17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o 19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o 21obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o
20obj-$(CONFIG_SMP) += platsmp.o headsmp.o 22obj-$(CONFIG_SMP) += platsmp.o headsmp.o
21obj-$(CONFIG_SMP) += reset.o 23obj-$(CONFIG_SMP) += reset.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index b5015d0f1912..d091675ba376 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -15,7 +15,6 @@
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <mach/iomap.h>
19#include <linux/of.h> 18#include <linux/of.h>
20#include <linux/dmaengine.h> 19#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h> 20#include <linux/dma-mapping.h>
@@ -24,9 +23,8 @@
24#include <linux/sched.h> 23#include <linux/sched.h>
25#include <linux/mutex.h> 24#include <linux/mutex.h>
26 25
27#include <mach/dma.h>
28
29#include "apbio.h" 26#include "apbio.h"
27#include "iomap.h"
30 28
31#if defined(CONFIG_TEGRA20_APB_DMA) 29#if defined(CONFIG_TEGRA20_APB_DMA)
32static DEFINE_MUTEX(tegra_apb_dma_lock); 30static DEFINE_MUTEX(tegra_apb_dma_lock);
@@ -71,7 +69,6 @@ bool tegra_apb_dma_init(void)
71 69
72 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 70 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
73 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 71 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
74 dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR;
75 dma_sconfig.src_maxburst = 1; 72 dma_sconfig.src_maxburst = 1;
76 dma_sconfig.dst_maxburst = 1; 73 dma_sconfig.dst_maxburst = 1;
77 74
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index aa5325cd1c42..734d9cc87f2e 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -40,12 +40,10 @@
40#include <asm/mach/time.h> 40#include <asm/mach/time.h>
41#include <asm/setup.h> 41#include <asm/setup.h>
42 42
43#include <mach/iomap.h>
44#include <mach/irqs.h>
45
46#include "board.h" 43#include "board.h"
47#include "clock.h" 44#include "clock.h"
48#include "common.h" 45#include "common.h"
46#include "iomap.h"
49 47
50struct tegra_ehci_platform_data tegra_ehci1_pdata = { 48struct tegra_ehci_platform_data tegra_ehci1_pdata = {
51 .operating_mode = TEGRA_USB_OTG, 49 .operating_mode = TEGRA_USB_OTG,
@@ -91,6 +89,17 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
91 &tegra_ehci3_pdata), 89 &tegra_ehci3_pdata),
92 OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL), 90 OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
93 OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), 91 OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
92 OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
93 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
94 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
95 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
96 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
97 OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
98 OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
99 OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
100 OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
101 OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
102 OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
94 {} 103 {}
95}; 104};
96 105
@@ -104,8 +113,20 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
104 { "pll_a", "pll_p_out1", 56448000, true }, 113 { "pll_a", "pll_p_out1", 56448000, true },
105 { "pll_a_out0", "pll_a", 11289600, true }, 114 { "pll_a_out0", "pll_a", 11289600, true },
106 { "cdev1", NULL, 0, true }, 115 { "cdev1", NULL, 0, true },
116 { "blink", "clk_32k", 32768, true },
107 { "i2s1", "pll_a_out0", 11289600, false}, 117 { "i2s1", "pll_a_out0", 11289600, false},
108 { "i2s2", "pll_a_out0", 11289600, false}, 118 { "i2s2", "pll_a_out0", 11289600, false},
119 { "sdmmc1", "pll_p", 48000000, false},
120 { "sdmmc3", "pll_p", 48000000, false},
121 { "sdmmc4", "pll_p", 48000000, false},
122 { "spi", "pll_p", 20000000, false },
123 { "sbc1", "pll_p", 100000000, false },
124 { "sbc2", "pll_p", 100000000, false },
125 { "sbc3", "pll_p", 100000000, false },
126 { "sbc4", "pll_p", 100000000, false },
127 { "host1x", "pll_c", 150000000, false },
128 { "disp1", "pll_p", 600000000, false },
129 { "disp2", "pll_p", 600000000, false },
109 { NULL, NULL, 0, 0}, 130 { NULL, NULL, 0, 0},
110}; 131};
111 132
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 5e92a81f9a2e..6497d1236b08 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -33,11 +33,10 @@
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <asm/hardware/gic.h> 34#include <asm/hardware/gic.h>
35 35
36#include <mach/iomap.h>
37
38#include "board.h" 36#include "board.h"
39#include "clock.h" 37#include "clock.h"
40#include "common.h" 38#include "common.h"
39#include "iomap.h"
41 40
42struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { 41struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
43 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL), 42 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
@@ -52,6 +51,18 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
52 OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL), 51 OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
53 OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL), 52 OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
54 OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), 53 OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
54 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
55 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
56 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
57 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
58 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
59 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
60 OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
61 OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
62 OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
63 OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
64 OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
65 OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
55 {} 66 {}
56}; 67};
57 68
@@ -62,11 +73,24 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
62 { "pll_a_out0", "pll_a", 11289600, true }, 73 { "pll_a_out0", "pll_a", 11289600, true },
63 { "extern1", "pll_a_out0", 0, true }, 74 { "extern1", "pll_a_out0", 0, true },
64 { "clk_out_1", "extern1", 0, true }, 75 { "clk_out_1", "extern1", 0, true },
76 { "blink", "clk_32k", 32768, true },
65 { "i2s0", "pll_a_out0", 11289600, false}, 77 { "i2s0", "pll_a_out0", 11289600, false},
66 { "i2s1", "pll_a_out0", 11289600, false}, 78 { "i2s1", "pll_a_out0", 11289600, false},
67 { "i2s2", "pll_a_out0", 11289600, false}, 79 { "i2s2", "pll_a_out0", 11289600, false},
68 { "i2s3", "pll_a_out0", 11289600, false}, 80 { "i2s3", "pll_a_out0", 11289600, false},
69 { "i2s4", "pll_a_out0", 11289600, false}, 81 { "i2s4", "pll_a_out0", 11289600, false},
82 { "sdmmc1", "pll_p", 48000000, false},
83 { "sdmmc3", "pll_p", 48000000, false},
84 { "sdmmc4", "pll_p", 48000000, false},
85 { "sbc1", "pll_p", 100000000, false},
86 { "sbc2", "pll_p", 100000000, false},
87 { "sbc3", "pll_p", 100000000, false},
88 { "sbc4", "pll_p", 100000000, false},
89 { "sbc5", "pll_p", 100000000, false},
90 { "sbc6", "pll_p", 100000000, false},
91 { "host1x", "pll_c", 150000000, false},
92 { "disp1", "pll_p", 600000000, false},
93 { "disp2", "pll_p", 600000000, false},
70 { NULL, NULL, 0, 0}, 94 { NULL, NULL, 0, 0},
71}; 95};
72 96
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index fd82085eca5d..867bf8bf5561 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -27,8 +27,6 @@
27#include <linux/seq_file.h> 27#include <linux/seq_file.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29 29
30#include <mach/clk.h>
31
32#include "board.h" 30#include "board.h"
33#include "clock.h" 31#include "clock.h"
34#include "tegra_cpu_car.h" 32#include "tegra_cpu_car.h"
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0b0a5f556d34..bce8591cb72b 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -26,13 +26,13 @@
26#include <asm/hardware/cache-l2x0.h> 26#include <asm/hardware/cache-l2x0.h>
27#include <asm/hardware/gic.h> 27#include <asm/hardware/gic.h>
28 28
29#include <mach/iomap.h>
30#include <mach/powergate.h> 29#include <mach/powergate.h>
31 30
32#include "board.h" 31#include "board.h"
33#include "clock.h" 32#include "clock.h"
34#include "common.h" 33#include "common.h"
35#include "fuse.h" 34#include "fuse.h"
35#include "iomap.h"
36#include "pmc.h" 36#include "pmc.h"
37#include "apbio.h" 37#include "apbio.h"
38#include "sleep.h" 38#include "sleep.h"
@@ -44,14 +44,15 @@
44 * kernel is loaded. The data is declared here rather than debug-macro.S so 44 * kernel is loaded. The data is declared here rather than debug-macro.S so
45 * that multiple inclusions of debug-macro.S point at the same data. 45 * that multiple inclusions of debug-macro.S point at the same data.
46 */ 46 */
47#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF) 47u32 tegra_uart_config[4] = {
48u32 tegra_uart_config[3] = {
49 /* Debug UART initialization required */ 48 /* Debug UART initialization required */
50 1, 49 1,
51 /* Debug UART physical address */ 50 /* Debug UART physical address */
52 (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET), 51 0,
53 /* Debug UART virtual address */ 52 /* Debug UART virtual address */
54 (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET), 53 0,
54 /* Scratch space for debug macro */
55 0,
55}; 56};
56 57
57#ifdef CONFIG_OF 58#ifdef CONFIG_OF
@@ -104,25 +105,26 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
104 { "clk_m", NULL, 0, true }, 105 { "clk_m", NULL, 0, true },
105 { "pll_p", "clk_m", 408000000, true }, 106 { "pll_p", "clk_m", 408000000, true },
106 { "pll_p_out1", "pll_p", 9600000, true }, 107 { "pll_p_out1", "pll_p", 9600000, true },
108 { "pll_p_out4", "pll_p", 102000000, true },
109 { "sclk", "pll_p_out4", 102000000, true },
110 { "hclk", "sclk", 102000000, true },
111 { "pclk", "hclk", 51000000, true },
107 { NULL, NULL, 0, 0}, 112 { NULL, NULL, 0, 0},
108}; 113};
109#endif 114#endif
110 115
111 116
112static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) 117static void __init tegra_init_cache(void)
113{ 118{
114#ifdef CONFIG_CACHE_L2X0 119#ifdef CONFIG_CACHE_L2X0
115 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; 120 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
116 u32 aux_ctrl, cache_type; 121 u32 aux_ctrl, cache_type;
117 122
118 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
119 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
120
121 cache_type = readl(p + L2X0_CACHE_TYPE); 123 cache_type = readl(p + L2X0_CACHE_TYPE);
122 aux_ctrl = (cache_type & 0x700) << (17-8); 124 aux_ctrl = (cache_type & 0x700) << (17-8);
123 aux_ctrl |= 0x6C000001; 125 aux_ctrl |= 0x7C400001;
124 126
125 l2x0_init(p, aux_ctrl, 0x8200c3fe); 127 l2x0_of_init(aux_ctrl, 0x8200c3fe);
126#endif 128#endif
127 129
128} 130}
@@ -134,7 +136,7 @@ void __init tegra20_init_early(void)
134 tegra_init_fuse(); 136 tegra_init_fuse();
135 tegra2_init_clocks(); 137 tegra2_init_clocks();
136 tegra_clk_init_from_table(tegra20_clk_init_table); 138 tegra_clk_init_from_table(tegra20_clk_init_table);
137 tegra_init_cache(0x331, 0x441); 139 tegra_init_cache();
138 tegra_pmc_init(); 140 tegra_pmc_init();
139 tegra_powergate_init(); 141 tegra_powergate_init();
140 tegra20_hotplug_init(); 142 tegra20_hotplug_init();
@@ -147,7 +149,7 @@ void __init tegra30_init_early(void)
147 tegra_init_fuse(); 149 tegra_init_fuse();
148 tegra30_init_clocks(); 150 tegra30_init_clocks();
149 tegra_clk_init_from_table(tegra30_clk_init_table); 151 tegra_clk_init_from_table(tegra30_clk_init_table);
150 tegra_init_cache(0x441, 0x551); 152 tegra_init_cache();
151 tegra_pmc_init(); 153 tegra_pmc_init();
152 tegra_powergate_init(); 154 tegra_powergate_init();
153 tegra30_hotplug_init(); 155 tegra30_hotplug_init();
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 627bf0f4262e..a74d3c7d2e26 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -30,9 +30,6 @@
30#include <linux/io.h> 30#include <linux/io.h>
31#include <linux/suspend.h> 31#include <linux/suspend.h>
32 32
33
34#include <mach/clk.h>
35
36/* Frequency table index must be sequential starting at 0 */ 33/* Frequency table index must be sequential starting at 0 */
37static struct cpufreq_frequency_table freq_table[] = { 34static struct cpufreq_frequency_table freq_table[] = {
38 { 0, 216000 }, 35 { 0, 216000 },
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 566e2f88899b..9a6f051b382e 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -29,8 +29,6 @@
29 29
30#include <asm/proc-fns.h> 30#include <asm/proc-fns.h>
31 31
32#include <mach/iomap.h>
33
34static int tegra_idle_enter_lp3(struct cpuidle_device *dev, 32static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
35 struct cpuidle_driver *drv, int index); 33 struct cpuidle_driver *drv, int index);
36 34
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index f07488e0bd32..ffaa286a71e1 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -22,9 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24 24
25#include <mach/iomap.h>
26
27#include "flowctrl.h" 25#include "flowctrl.h"
26#include "iomap.h"
28 27
29u8 flowctrl_offset_halt_cpu[] = { 28u8 flowctrl_offset_halt_cpu[] = {
30 FLOW_CTRL_HALT_CPU0_EVENTS, 29 FLOW_CTRL_HALT_CPU0_EVENTS,
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 0b7db174a5de..8121742711fe 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -21,22 +21,28 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/export.h> 22#include <linux/export.h>
23 23
24#include <mach/iomap.h>
25
26#include "fuse.h" 24#include "fuse.h"
25#include "iomap.h"
27#include "apbio.h" 26#include "apbio.h"
28 27
29#define FUSE_UID_LOW 0x108 28#define FUSE_UID_LOW 0x108
30#define FUSE_UID_HIGH 0x10c 29#define FUSE_UID_HIGH 0x10c
31#define FUSE_SKU_INFO 0x110 30#define FUSE_SKU_INFO 0x110
32#define FUSE_SPARE_BIT 0x200 31
32#define TEGRA20_FUSE_SPARE_BIT 0x200
33#define TEGRA30_FUSE_SPARE_BIT 0x244
33 34
34int tegra_sku_id; 35int tegra_sku_id;
35int tegra_cpu_process_id; 36int tegra_cpu_process_id;
36int tegra_core_process_id; 37int tegra_core_process_id;
37int tegra_chip_id; 38int tegra_chip_id;
39int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
40int tegra_soc_speedo_id;
38enum tegra_revision tegra_revision; 41enum tegra_revision tegra_revision;
39 42
43static int tegra_fuse_spare_bit;
44static void (*tegra_init_speedo_data)(void);
45
40/* The BCT to use at boot is specified by board straps that can be read 46/* The BCT to use at boot is specified by board straps that can be read
41 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs. 47 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
42 */ 48 */
@@ -57,14 +63,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
57 [TEGRA_REVISION_A04] = "A04", 63 [TEGRA_REVISION_A04] = "A04",
58}; 64};
59 65
60static inline u32 tegra_fuse_readl(unsigned long offset) 66u32 tegra_fuse_readl(unsigned long offset)
61{ 67{
62 return tegra_apb_readl(TEGRA_FUSE_BASE + offset); 68 return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
63} 69}
64 70
65static inline bool get_spare_fuse(int bit) 71bool tegra_spare_fuse(int bit)
66{ 72{
67 return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); 73 return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
68} 74}
69 75
70static enum tegra_revision tegra_get_revision(u32 id) 76static enum tegra_revision tegra_get_revision(u32 id)
@@ -78,7 +84,7 @@ static enum tegra_revision tegra_get_revision(u32 id)
78 return TEGRA_REVISION_A02; 84 return TEGRA_REVISION_A02;
79 case 3: 85 case 3:
80 if (tegra_chip_id == TEGRA20 && 86 if (tegra_chip_id == TEGRA20 &&
81 (get_spare_fuse(18) || get_spare_fuse(19))) 87 (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
82 return TEGRA_REVISION_A03p; 88 return TEGRA_REVISION_A03p;
83 else 89 else
84 return TEGRA_REVISION_A03; 90 return TEGRA_REVISION_A03;
@@ -89,6 +95,16 @@ static enum tegra_revision tegra_get_revision(u32 id)
89 } 95 }
90} 96}
91 97
98static void tegra_get_process_id(void)
99{
100 u32 reg;
101
102 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
103 tegra_cpu_process_id = (reg >> 6) & 3;
104 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
105 tegra_core_process_id = (reg >> 12) & 3;
106}
107
92void tegra_init_fuse(void) 108void tegra_init_fuse(void)
93{ 109{
94 u32 id; 110 u32 id;
@@ -100,19 +116,29 @@ void tegra_init_fuse(void)
100 reg = tegra_fuse_readl(FUSE_SKU_INFO); 116 reg = tegra_fuse_readl(FUSE_SKU_INFO);
101 tegra_sku_id = reg & 0xFF; 117 tegra_sku_id = reg & 0xFF;
102 118
103 reg = tegra_fuse_readl(FUSE_SPARE_BIT);
104 tegra_cpu_process_id = (reg >> 6) & 3;
105
106 reg = tegra_fuse_readl(FUSE_SPARE_BIT);
107 tegra_core_process_id = (reg >> 12) & 3;
108
109 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); 119 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
110 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; 120 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
111 121
112 id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); 122 id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
113 tegra_chip_id = (id >> 8) & 0xff; 123 tegra_chip_id = (id >> 8) & 0xff;
114 124
125 switch (tegra_chip_id) {
126 case TEGRA20:
127 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
128 tegra_init_speedo_data = &tegra20_init_speedo_data;
129 break;
130 case TEGRA30:
131 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
132 tegra_init_speedo_data = &tegra30_init_speedo_data;
133 break;
134 default:
135 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
136 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
137 tegra_init_speedo_data = &tegra_get_process_id;
138 }
139
115 tegra_revision = tegra_get_revision(id); 140 tegra_revision = tegra_get_revision(id);
141 tegra_init_speedo_data();
116 142
117 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", 143 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
118 tegra_revision_name[tegra_revision], 144 tegra_revision_name[tegra_revision],
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index d2107b2cb85a..ff1383dd61a7 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -42,11 +42,27 @@ extern int tegra_sku_id;
42extern int tegra_cpu_process_id; 42extern int tegra_cpu_process_id;
43extern int tegra_core_process_id; 43extern int tegra_core_process_id;
44extern int tegra_chip_id; 44extern int tegra_chip_id;
45extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
46extern int tegra_soc_speedo_id;
45extern enum tegra_revision tegra_revision; 47extern enum tegra_revision tegra_revision;
46 48
47extern int tegra_bct_strapping; 49extern int tegra_bct_strapping;
48 50
49unsigned long long tegra_chip_uid(void); 51unsigned long long tegra_chip_uid(void);
50void tegra_init_fuse(void); 52void tegra_init_fuse(void);
53bool tegra_spare_fuse(int bit);
54u32 tegra_fuse_readl(unsigned long offset);
55
56#ifdef CONFIG_ARCH_TEGRA_2x_SOC
57void tegra20_init_speedo_data(void);
58#else
59static inline void tegra20_init_speedo_data(void) {}
60#endif
61
62#ifdef CONFIG_ARCH_TEGRA_3x_SOC
63void tegra30_init_speedo_data(void);
64#else
65static inline void tegra30_init_speedo_data(void) {}
66#endif
51 67
52#endif 68#endif
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 6addc78cb6b2..93f0370cc95b 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -3,9 +3,8 @@
3 3
4#include <asm/cache.h> 4#include <asm/cache.h>
5 5
6#include <mach/iomap.h>
7
8#include "flowctrl.h" 6#include "flowctrl.h"
7#include "iomap.h"
9#include "reset.h" 8#include "reset.h"
10#include "sleep.h" 9#include "sleep.h"
11 10
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
deleted file mode 100644
index 8ce0661b8a3d..000000000000
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/debug-macro.S
3 *
4 * Copyright (C) 2010,2011 Google, Inc.
5 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 * Doug Anderson <dianders@chromium.org>
11 * Stephen Warren <swarren@nvidia.com>
12 *
13 * Portions based on mach-omap2's debug-macro.S
14 * Copyright (C) 1994-1999 Russell King
15 *
16 * This software is licensed under the terms of the GNU General Public
17 * License version 2, as published by the Free Software Foundation, and
18 * may be copied, distributed, and modified under those terms.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 */
26
27#include <linux/serial_reg.h>
28
29#include <mach/iomap.h>
30#include <mach/irammap.h>
31
32 .macro addruart, rp, rv, tmp
33 adr \rp, 99f @ actual addr of 99f
34 ldr \rv, [\rp] @ linked addr is stored there
35 sub \rv, \rv, \rp @ offset between the two
36 ldr \rp, [\rp, #4] @ linked tegra_uart_config
37 sub \tmp, \rp, \rv @ actual tegra_uart_config
38 ldr \rp, [\tmp] @ Load tegra_uart_config
39 cmp \rp, #1 @ needs intitialization?
40 bne 100f @ no; go load the addresses
41 mov \rv, #0 @ yes; record init is done
42 str \rv, [\tmp]
43 mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM
44 ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
45 movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
46 movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
47 cmp \rv, \rp @ Cookie present?
48 bne 100f @ No, use default UART
49 mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM
50 ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
51 str \rv, [\tmp, #4] @ Store in tegra_uart_phys
52 sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address
53 add \rv, \rv, #IO_APB_VIRT
54 str \rv, [\tmp, #8] @ Store in tegra_uart_virt
55 b 100f
56
57 .align
5899: .word .
59 .word tegra_uart_config
60 .ltorg
61
62100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
63 ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
64 .endm
65
66#define UART_SHIFT 2
67
68/*
69 * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
70 * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
71 * We use the fact that all 5 valid UART addresses all have something in the
72 * 2nd-to-lowest byte.
73 */
74
75 .macro senduart, rd, rx
76 tst \rx, #0x0000ff00
77 strneb \rd, [\rx, #UART_TX << UART_SHIFT]
781001:
79 .endm
80
81 .macro busyuart, rd, rx
82 tst \rx, #0x0000ff00
83 beq 1002f
841001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
85 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
86 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
87 bne 1001b
881002:
89 .endm
90
91 .macro waituart, rd, rx
92#ifdef FLOW_CONTROL
93 tst \rx, #0x0000ff00
94 beq 1002f
951001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
96 tst \rd, #UART_MSR_CTS
97 beq 1001b
981002:
99#endif
100 .endm
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
deleted file mode 100644
index 3081cc6dda3b..000000000000
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/dma.h
3 *
4 * Copyright (c) 2008-2009, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_TEGRA_DMA_H
22#define __MACH_TEGRA_DMA_H
23
24#include <linux/list.h>
25
26#define TEGRA_DMA_REQ_SEL_CNTR 0
27#define TEGRA_DMA_REQ_SEL_I2S_2 1
28#define TEGRA_DMA_REQ_SEL_I2S_1 2
29#define TEGRA_DMA_REQ_SEL_SPD_I 3
30#define TEGRA_DMA_REQ_SEL_UI_I 4
31#define TEGRA_DMA_REQ_SEL_MIPI 5
32#define TEGRA_DMA_REQ_SEL_I2S2_2 6
33#define TEGRA_DMA_REQ_SEL_I2S2_1 7
34#define TEGRA_DMA_REQ_SEL_UARTA 8
35#define TEGRA_DMA_REQ_SEL_UARTB 9
36#define TEGRA_DMA_REQ_SEL_UARTC 10
37#define TEGRA_DMA_REQ_SEL_SPI 11
38#define TEGRA_DMA_REQ_SEL_AC97 12
39#define TEGRA_DMA_REQ_SEL_ACMODEM 13
40#define TEGRA_DMA_REQ_SEL_SL4B 14
41#define TEGRA_DMA_REQ_SEL_SL2B1 15
42#define TEGRA_DMA_REQ_SEL_SL2B2 16
43#define TEGRA_DMA_REQ_SEL_SL2B3 17
44#define TEGRA_DMA_REQ_SEL_SL2B4 18
45#define TEGRA_DMA_REQ_SEL_UARTD 19
46#define TEGRA_DMA_REQ_SEL_UARTE 20
47#define TEGRA_DMA_REQ_SEL_I2C 21
48#define TEGRA_DMA_REQ_SEL_I2C2 22
49#define TEGRA_DMA_REQ_SEL_I2C3 23
50#define TEGRA_DMA_REQ_SEL_DVC_I2C 24
51#define TEGRA_DMA_REQ_SEL_OWR 25
52#define TEGRA_DMA_REQ_SEL_INVALID 31
53
54#endif
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
deleted file mode 100644
index aad1a2c1d714..000000000000
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ /dev/null
@@ -1,182 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/irqs.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_IRQS_H
22#define __MACH_TEGRA_IRQS_H
23
24#define INT_GIC_BASE 0
25
26#define IRQ_LOCALTIMER 29
27
28/* Primary Interrupt Controller */
29#define INT_PRI_BASE (INT_GIC_BASE + 32)
30#define INT_TMR1 (INT_PRI_BASE + 0)
31#define INT_TMR2 (INT_PRI_BASE + 1)
32#define INT_RTC (INT_PRI_BASE + 2)
33#define INT_I2S2 (INT_PRI_BASE + 3)
34#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4)
35#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5)
36#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6)
37#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7)
38#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8)
39#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9)
40#define INT_VDE_BSE_V (INT_PRI_BASE + 10)
41#define INT_VDE_BSE_A (INT_PRI_BASE + 11)
42#define INT_VDE_SXE (INT_PRI_BASE + 12)
43#define INT_I2S1 (INT_PRI_BASE + 13)
44#define INT_SDMMC1 (INT_PRI_BASE + 14)
45#define INT_SDMMC2 (INT_PRI_BASE + 15)
46#define INT_XIO (INT_PRI_BASE + 16)
47#define INT_VDE (INT_PRI_BASE + 17)
48#define INT_AVP_UCQ (INT_PRI_BASE + 18)
49#define INT_SDMMC3 (INT_PRI_BASE + 19)
50#define INT_USB (INT_PRI_BASE + 20)
51#define INT_USB2 (INT_PRI_BASE + 21)
52#define INT_PRI_RES_22 (INT_PRI_BASE + 22)
53#define INT_EIDE (INT_PRI_BASE + 23)
54#define INT_NANDFLASH (INT_PRI_BASE + 24)
55#define INT_VCP (INT_PRI_BASE + 25)
56#define INT_APB_DMA (INT_PRI_BASE + 26)
57#define INT_AHB_DMA (INT_PRI_BASE + 27)
58#define INT_GNT_0 (INT_PRI_BASE + 28)
59#define INT_GNT_1 (INT_PRI_BASE + 29)
60#define INT_OWR (INT_PRI_BASE + 30)
61#define INT_SDMMC4 (INT_PRI_BASE + 31)
62
63/* Secondary Interrupt Controller */
64#define INT_SEC_BASE (INT_PRI_BASE + 32)
65#define INT_GPIO1 (INT_SEC_BASE + 0)
66#define INT_GPIO2 (INT_SEC_BASE + 1)
67#define INT_GPIO3 (INT_SEC_BASE + 2)
68#define INT_GPIO4 (INT_SEC_BASE + 3)
69#define INT_UARTA (INT_SEC_BASE + 4)
70#define INT_UARTB (INT_SEC_BASE + 5)
71#define INT_I2C (INT_SEC_BASE + 6)
72#define INT_SPI (INT_SEC_BASE + 7)
73#define INT_TWC (INT_SEC_BASE + 8)
74#define INT_TMR3 (INT_SEC_BASE + 9)
75#define INT_TMR4 (INT_SEC_BASE + 10)
76#define INT_FLOW_RSM0 (INT_SEC_BASE + 11)
77#define INT_FLOW_RSM1 (INT_SEC_BASE + 12)
78#define INT_SPDIF (INT_SEC_BASE + 13)
79#define INT_UARTC (INT_SEC_BASE + 14)
80#define INT_MIPI (INT_SEC_BASE + 15)
81#define INT_EVENTA (INT_SEC_BASE + 16)
82#define INT_EVENTB (INT_SEC_BASE + 17)
83#define INT_EVENTC (INT_SEC_BASE + 18)
84#define INT_EVENTD (INT_SEC_BASE + 19)
85#define INT_VFIR (INT_SEC_BASE + 20)
86#define INT_DVC (INT_SEC_BASE + 21)
87#define INT_SYS_STATS_MON (INT_SEC_BASE + 22)
88#define INT_GPIO5 (INT_SEC_BASE + 23)
89#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24)
90#define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25)
91#define INT_SEC_RES_26 (INT_SEC_BASE + 26)
92#define INT_S_LINK1 (INT_SEC_BASE + 27)
93#define INT_APB_DMA_COP (INT_SEC_BASE + 28)
94#define INT_AHB_DMA_COP (INT_SEC_BASE + 29)
95#define INT_DMA_TX (INT_SEC_BASE + 30)
96#define INT_DMA_RX (INT_SEC_BASE + 31)
97
98/* Tertiary Interrupt Controller */
99#define INT_TRI_BASE (INT_SEC_BASE + 32)
100#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0)
101#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1)
102#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2)
103#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3)
104#define INT_MPE_GENERAL (INT_TRI_BASE + 4)
105#define INT_VI_GENERAL (INT_TRI_BASE + 5)
106#define INT_EPP_GENERAL (INT_TRI_BASE + 6)
107#define INT_ISP_GENERAL (INT_TRI_BASE + 7)
108#define INT_2D_GENERAL (INT_TRI_BASE + 8)
109#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9)
110#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10)
111#define INT_HDMI (INT_TRI_BASE + 11)
112#define INT_TVO_GENERAL (INT_TRI_BASE + 12)
113#define INT_MC_GENERAL (INT_TRI_BASE + 13)
114#define INT_EMC_GENERAL (INT_TRI_BASE + 14)
115#define INT_TRI_RES_15 (INT_TRI_BASE + 15)
116#define INT_TRI_RES_16 (INT_TRI_BASE + 16)
117#define INT_AC97 (INT_TRI_BASE + 17)
118#define INT_SPI_2 (INT_TRI_BASE + 18)
119#define INT_SPI_3 (INT_TRI_BASE + 19)
120#define INT_I2C2 (INT_TRI_BASE + 20)
121#define INT_KBC (INT_TRI_BASE + 21)
122#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22)
123#define INT_GPIO6 (INT_TRI_BASE + 23)
124#define INT_TVDAC (INT_TRI_BASE + 24)
125#define INT_GPIO7 (INT_TRI_BASE + 25)
126#define INT_UARTD (INT_TRI_BASE + 26)
127#define INT_UARTE (INT_TRI_BASE + 27)
128#define INT_I2C3 (INT_TRI_BASE + 28)
129#define INT_SPI_4 (INT_TRI_BASE + 29)
130#define INT_TRI_RES_30 (INT_TRI_BASE + 30)
131#define INT_SW_RESERVED (INT_TRI_BASE + 31)
132
133/* Quaternary Interrupt Controller */
134#define INT_QUAD_BASE (INT_TRI_BASE + 32)
135#define INT_SNOR (INT_QUAD_BASE + 0)
136#define INT_USB3 (INT_QUAD_BASE + 1)
137#define INT_PCIE_INTR (INT_QUAD_BASE + 2)
138#define INT_PCIE_MSI (INT_QUAD_BASE + 3)
139#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4)
140#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5)
141#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6)
142#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7)
143#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8)
144#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9)
145#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10)
146#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11)
147#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12)
148#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13)
149#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14)
150#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15)
151#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16)
152#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17)
153#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18)
154#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19)
155#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20)
156#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21)
157#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22)
158#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23)
159#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24)
160#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25)
161#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26)
162#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27)
163#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28)
164#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29)
165#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
166#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
167
168/* Tegra30 has 5 banks of 32 IRQs */
169#define INT_MAIN_NR (32 * 5)
170#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR)
171
172/* Tegra30 has 8 banks of 32 GPIOs */
173#define INT_GPIO_NR (32 * 8)
174
175#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
176
177#define INT_BOARD_BASE TEGRA_NR_IRQS
178#define NR_BOARD_IRQS 32
179
180#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
181
182#endif
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 4752b1a68f35..06763fe7529d 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -20,6 +20,8 @@
20#ifndef _MACH_TEGRA_POWERGATE_H_ 20#ifndef _MACH_TEGRA_POWERGATE_H_
21#define _MACH_TEGRA_POWERGATE_H_ 21#define _MACH_TEGRA_POWERGATE_H_
22 22
23struct clk;
24
23#define TEGRA_POWERGATE_CPU 0 25#define TEGRA_POWERGATE_CPU 0
24#define TEGRA_POWERGATE_3D 1 26#define TEGRA_POWERGATE_3D 1
25#define TEGRA_POWERGATE_VENC 2 27#define TEGRA_POWERGATE_VENC 2
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 937c4c50219e..485003f9b636 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -28,8 +28,7 @@
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/serial_reg.h> 29#include <linux/serial_reg.h>
30 30
31#include <mach/iomap.h> 31#include "../../iomap.h"
32#include <mach/irammap.h>
33 32
34#define BIT(x) (1 << (x)) 33#define BIT(x) (1 << (x))
35#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 34#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
@@ -52,17 +51,6 @@ static inline void flush(void)
52{ 51{
53} 52}
54 53
55static inline void save_uart_address(void)
56{
57 u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
58
59 if (uart) {
60 buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
61 buf[1] = (u32)uart;
62 } else
63 buf[0] = 0;
64}
65
66static const struct { 54static const struct {
67 u32 base; 55 u32 base;
68 u32 reset_reg; 56 u32 reset_reg;
@@ -139,51 +127,19 @@ int auto_odmdata(void)
139} 127}
140#endif 128#endif
141 129
142#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH
143int auto_scratch(void)
144{
145 int i;
146
147 /*
148 * Look for the first UART that:
149 * a) Is not in reset.
150 * b) Is clocked.
151 * c) Has a 'D' in the scratchpad register.
152 *
153 * Note that on Tegra30, the first two conditions are required, since
154 * if not true, accesses to the UART scratch register will hang.
155 * Tegra20 doesn't have this issue.
156 *
157 * The intent is that the bootloader will tell the kernel which UART
158 * to use by setting up those conditions. If nothing found, we'll fall
159 * back to what's specified in TEGRA_DEBUG_UART_BASE.
160 */
161 for (i = 0; i < ARRAY_SIZE(uarts); i++) {
162 if (!uart_clocked(i))
163 continue;
164
165 uart = (volatile u8 *)uarts[i].base;
166 if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
167 continue;
168
169 return i;
170 }
171
172 return -1;
173}
174#endif
175
176/* 130/*
177 * Setup before decompression. This is where we do UART selection for 131 * Setup before decompression. This is where we do UART selection for
178 * earlyprintk and init the uart_base register. 132 * earlyprintk and init the uart_base register.
179 */ 133 */
180static inline void arch_decomp_setup(void) 134static inline void arch_decomp_setup(void)
181{ 135{
182 int uart_id, auto_uart_id; 136 int uart_id;
183 volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE; 137 volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
184 u32 chip, div; 138 u32 chip, div;
185 139
186#if defined(CONFIG_TEGRA_DEBUG_UARTA) 140#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
141 uart_id = auto_odmdata();
142#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
187 uart_id = 0; 143 uart_id = 0;
188#elif defined(CONFIG_TEGRA_DEBUG_UARTB) 144#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
189 uart_id = 1; 145 uart_id = 1;
@@ -193,19 +149,7 @@ static inline void arch_decomp_setup(void)
193 uart_id = 3; 149 uart_id = 3;
194#elif defined(CONFIG_TEGRA_DEBUG_UARTE) 150#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
195 uart_id = 4; 151 uart_id = 4;
196#else
197 uart_id = -1;
198#endif
199
200#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
201 auto_uart_id = auto_odmdata();
202#elif defined(CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH)
203 auto_uart_id = auto_scratch();
204#else
205 auto_uart_id = -1;
206#endif 152#endif
207 if (auto_uart_id != -1)
208 uart_id = auto_uart_id;
209 153
210 if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) || 154 if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
211 !uart_clocked(uart_id)) 155 !uart_clocked(uart_id))
@@ -213,7 +157,6 @@ static inline void arch_decomp_setup(void)
213 else 157 else
214 uart = (volatile u8 *)uarts[uart_id].base; 158 uart = (volatile u8 *)uarts[uart_id].base;
215 159
216 save_uart_address();
217 if (uart == NULL) 160 if (uart == NULL)
218 return; 161 return;
219 162
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 58b4baf9c483..bb9c9c29d181 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -26,9 +26,9 @@
26 26
27#include <asm/page.h> 27#include <asm/page.h>
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <mach/iomap.h>
30 29
31#include "board.h" 30#include "board.h"
31#include "iomap.h"
32 32
33static struct map_desc tegra_io_desc[] __initdata = { 33static struct map_desc tegra_io_desc[] __initdata = {
34 { 34 {
@@ -59,5 +59,6 @@ static struct map_desc tegra_io_desc[] __initdata = {
59 59
60void __init tegra_map_common_io(void) 60void __init tegra_map_common_io(void)
61{ 61{
62 debug_ll_io_init();
62 iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc)); 63 iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
63} 64}
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/iomap.h
index fee3a94c4549..db8be51cad80 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -1,6 +1,4 @@
1/* 1/*
2 * arch/arm/mach-tegra/include/mach/iomap.h
3 *
4 * Copyright (C) 2010 Google, Inc. 2 * Copyright (C) 2010 Google, Inc.
5 * 3 *
6 * Author: 4 * Author:
@@ -263,20 +261,6 @@
263#define TEGRA_SDMMC4_BASE 0xC8000600 261#define TEGRA_SDMMC4_BASE 0xC8000600
264#define TEGRA_SDMMC4_SIZE SZ_512 262#define TEGRA_SDMMC4_SIZE SZ_512
265 263
266#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
267# define TEGRA_DEBUG_UART_BASE 0
268#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
269# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
270#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
271# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
272#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
273# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
274#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
275# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
276#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
277# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
278#endif
279
280/* On TEGRA, many peripherals are very closely packed in 264/* On TEGRA, many peripherals are very closely packed in
281 * two 256MB io windows (that actually only use about 64KB 265 * two 256MB io windows (that actually only use about 64KB
282 * at the start of each). 266 * at the start of each).
diff --git a/arch/arm/mach-tegra/include/mach/irammap.h b/arch/arm/mach-tegra/irammap.h
index 0cbe63261854..501952a84344 100644
--- a/arch/arm/mach-tegra/include/mach/irammap.h
+++ b/arch/arm/mach-tegra/irammap.h
@@ -23,13 +23,4 @@
23#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 23#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
24#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K 24#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
25 25
26/*
27 * These locations are written to by uncompress.h, and read by debug-macro.S.
28 * The first word holds the cookie value if the data is valid. The second
29 * word holds the UART physical address.
30 */
31#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K
32#define TEGRA_IRAM_DEBUG_UART_SIZE 8
33#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254
34
35#endif 26#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 2f5bd2db8e1f..b7886f183511 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -25,9 +25,8 @@
25 25
26#include <asm/hardware/gic.h> 26#include <asm/hardware/gic.h>
27 27
28#include <mach/iomap.h>
29
30#include "board.h" 28#include "board.h"
29#include "iomap.h"
31 30
32#define ICTLR_CPU_IEP_VFIQ 0x08 31#define ICTLR_CPU_IEP_VFIQ 0x08
33#define ICTLR_CPU_IEP_FIR 0x14 32#define ICTLR_CPU_IEP_FIR 0x14
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index a8dba6489c9b..53d085871798 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -37,11 +37,14 @@
37#include <asm/sizes.h> 37#include <asm/sizes.h>
38#include <asm/mach/pci.h> 38#include <asm/mach/pci.h>
39 39
40#include <mach/iomap.h>
41#include <mach/clk.h> 40#include <mach/clk.h>
42#include <mach/powergate.h> 41#include <mach/powergate.h>
43 42
44#include "board.h" 43#include "board.h"
44#include "iomap.h"
45
46/* Hack - need to parse this from DT */
47#define INT_PCIE_INTR 130
45 48
46/* register definitions */ 49/* register definitions */
47#define AFI_OFFSET 0x3800 50#define AFI_OFFSET 0x3800
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 81cb26591acf..1b926df99c4b 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -24,8 +24,6 @@
24#include <asm/mach-types.h> 24#include <asm/mach-types.h>
25#include <asm/smp_scu.h> 25#include <asm/smp_scu.h>
26 26
27#include <mach/clk.h>
28#include <mach/iomap.h>
29#include <mach/powergate.h> 27#include <mach/powergate.h>
30 28
31#include "fuse.h" 29#include "fuse.h"
@@ -34,6 +32,7 @@
34#include "tegra_cpu_car.h" 32#include "tegra_cpu_car.h"
35 33
36#include "common.h" 34#include "common.h"
35#include "iomap.h"
37 36
38extern void tegra_secondary_startup(void); 37extern void tegra_secondary_startup(void);
39 38
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 7af6a54404be..d4fdb5fcec20 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -19,7 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/of.h> 20#include <linux/of.h>
21 21
22#include <mach/iomap.h> 22#include "iomap.h"
23 23
24#define PMC_CTRL 0x0 24#define PMC_CTRL 0x0
25#define PMC_CTRL_INTR_LOW (1 << 17) 25#define PMC_CTRL_INTR_LOW (1 << 17)
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index de0662de28a0..2cc1185d902e 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -28,10 +28,10 @@
28#include <linux/spinlock.h> 28#include <linux/spinlock.h>
29 29
30#include <mach/clk.h> 30#include <mach/clk.h>
31#include <mach/iomap.h>
32#include <mach/powergate.h> 31#include <mach/powergate.h>
33 32
34#include "fuse.h" 33#include "fuse.h"
34#include "iomap.h"
35 35
36#define PWRGATE_TOGGLE 0x30 36#define PWRGATE_TOGGLE 0x30
37#define PWRGATE_TOGGLE_START (1 << 8) 37#define PWRGATE_TOGGLE_START (1 << 8)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 5beb7ebe2948..e05da7d10c3b 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -22,9 +22,8 @@
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <asm/hardware/cache-l2x0.h> 23#include <asm/hardware/cache-l2x0.h>
24 24
25#include <mach/iomap.h> 25#include "iomap.h"
26#include <mach/irammap.h> 26#include "irammap.h"
27
28#include "reset.h" 27#include "reset.h"
29#include "fuse.h" 28#include "fuse.h"
30 29
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
index a36ae413e2b8..72ce709799da 100644
--- a/arch/arm/mach-tegra/sleep-t20.S
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -22,8 +22,6 @@
22 22
23#include <asm/assembler.h> 23#include <asm/assembler.h>
24 24
25#include <mach/iomap.h>
26
27#include "sleep.h" 25#include "sleep.h"
28#include "flowctrl.h" 26#include "flowctrl.h"
29 27
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
index 777d9cee8b90..be7614b7c5cb 100644
--- a/arch/arm/mach-tegra/sleep-t30.S
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -18,8 +18,6 @@
18 18
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20 20
21#include <mach/iomap.h>
22
23#include "sleep.h" 21#include "sleep.h"
24#include "flowctrl.h" 22#include "flowctrl.h"
25 23
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index ea81554c4833..08e9481c049e 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -26,7 +26,7 @@
26 26
27#include <asm/assembler.h> 27#include <asm/assembler.h>
28 28
29#include <mach/iomap.h> 29#include "iomap.h"
30 30
31#include "flowctrl.h" 31#include "flowctrl.h"
32#include "sleep.h" 32#include "sleep.h"
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index e25a7cd703d9..4889b281c5f9 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -17,7 +17,7 @@
17#ifndef __MACH_TEGRA_SLEEP_H 17#ifndef __MACH_TEGRA_SLEEP_H
18#define __MACH_TEGRA_SLEEP_H 18#define __MACH_TEGRA_SLEEP_H
19 19
20#include <mach/iomap.h> 20#include "iomap.h"
21 21
22#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ 22#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
23 + IO_CPU_VIRT) 23 + IO_CPU_VIRT)
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index deb873fb12b6..4eb6bc81a87b 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -27,10 +27,9 @@
27#include <linux/clkdev.h> 27#include <linux/clkdev.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29 29
30#include <mach/iomap.h>
31
32#include "clock.h" 30#include "clock.h"
33#include "fuse.h" 31#include "fuse.h"
32#include "iomap.h"
34#include "tegra2_emc.h" 33#include "tegra2_emc.h"
35#include "tegra_cpu_car.h" 34#include "tegra_cpu_car.h"
36 35
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 8d398a33adf7..a23a0734e352 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -27,8 +27,6 @@
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29 29
30#include <mach/iomap.h>
31
32#include "clock.h" 30#include "clock.h"
33#include "fuse.h" 31#include "fuse.h"
34#include "tegra2_emc.h" 32#include "tegra2_emc.h"
@@ -248,11 +246,16 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
248 { 19200000, 216000000, 135, 12, 1, 3}, 246 { 19200000, 216000000, 135, 12, 1, 3},
249 { 26000000, 216000000, 216, 26, 1, 4}, 247 { 26000000, 216000000, 216, 26, 1, 4},
250 248
249 { 12000000, 297000000, 99, 4, 1, 4 },
250 { 12000000, 339000000, 113, 4, 1, 4 },
251
251 { 12000000, 594000000, 594, 12, 1, 8}, 252 { 12000000, 594000000, 594, 12, 1, 8},
252 { 13000000, 594000000, 594, 13, 1, 8}, 253 { 13000000, 594000000, 594, 13, 1, 8},
253 { 19200000, 594000000, 495, 16, 1, 8}, 254 { 19200000, 594000000, 495, 16, 1, 8},
254 { 26000000, 594000000, 594, 26, 1, 8}, 255 { 26000000, 594000000, 594, 26, 1, 8},
255 256
257 { 12000000, 616000000, 616, 12, 1, 8},
258
256 { 12000000, 1000000000, 1000, 12, 1, 12}, 259 { 12000000, 1000000000, 1000, 12, 1, 12},
257 { 13000000, 1000000000, 1000, 13, 1, 12}, 260 { 13000000, 1000000000, 1000, 13, 1, 12},
258 { 19200000, 1000000000, 625, 12, 1, 8}, 261 { 19200000, 1000000000, 625, 12, 1, 8},
@@ -1038,9 +1041,6 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
1038 CLK_DUPLICATE("usbd", "utmip-pad", NULL), 1041 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1039 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), 1042 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1040 CLK_DUPLICATE("usbd", "tegra-otg", NULL), 1043 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1041 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1042 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1043 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
1044 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), 1044 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1045 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), 1045 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1046 CLK_DUPLICATE("epp", "tegra_grhost", "epp"), 1046 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
@@ -1053,6 +1053,9 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
1053 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"), 1053 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1054 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"), 1054 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1055 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"), 1055 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1056 CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
1057 CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
1058 CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
1056}; 1059};
1057 1060
1058#define CLK(dev, con, ck) \ 1061#define CLK(dev, con, ck) \
diff --git a/arch/arm/mach-tegra/tegra20_speedo.c b/arch/arm/mach-tegra/tegra20_speedo.c
new file mode 100644
index 000000000000..fa6eb570623f
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_speedo.c
@@ -0,0 +1,109 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/bug.h>
19
20#include "fuse.h"
21
22#define CPU_SPEEDO_LSBIT 20
23#define CPU_SPEEDO_MSBIT 29
24#define CPU_SPEEDO_REDUND_LSBIT 30
25#define CPU_SPEEDO_REDUND_MSBIT 39
26#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
27
28#define CORE_SPEEDO_LSBIT 40
29#define CORE_SPEEDO_MSBIT 47
30#define CORE_SPEEDO_REDUND_LSBIT 48
31#define CORE_SPEEDO_REDUND_MSBIT 55
32#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
33
34#define SPEEDO_MULT 4
35
36#define PROCESS_CORNERS_NUM 4
37
38#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2)
39#define SPEEDO_ID_SELECT_1(sku) \
40 (((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
41 ((sku) != 27) && ((sku) != 28))
42
43enum {
44 SPEEDO_ID_0,
45 SPEEDO_ID_1,
46 SPEEDO_ID_2,
47 SPEEDO_ID_COUNT,
48};
49
50static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
51 {315, 366, 420, UINT_MAX},
52 {303, 368, 419, UINT_MAX},
53 {316, 331, 383, UINT_MAX},
54};
55
56static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
57 {165, 195, 224, UINT_MAX},
58 {165, 195, 224, UINT_MAX},
59 {165, 195, 224, UINT_MAX},
60};
61
62void tegra20_init_speedo_data(void)
63{
64 u32 reg;
65 u32 val;
66 int i;
67
68 BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
69 BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
70
71 if (SPEEDO_ID_SELECT_0(tegra_revision))
72 tegra_soc_speedo_id = SPEEDO_ID_0;
73 else if (SPEEDO_ID_SELECT_1(tegra_sku_id))
74 tegra_soc_speedo_id = SPEEDO_ID_1;
75 else
76 tegra_soc_speedo_id = SPEEDO_ID_2;
77
78 val = 0;
79 for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
80 reg = tegra_spare_fuse(i) |
81 tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS);
82 val = (val << 1) | (reg & 0x1);
83 }
84 val = val * SPEEDO_MULT;
85 pr_debug("%s CPU speedo value %u\n", __func__, val);
86
87 for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
88 if (val <= cpu_process_speedos[tegra_soc_speedo_id][i])
89 break;
90 }
91 tegra_cpu_process_id = i;
92
93 val = 0;
94 for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
95 reg = tegra_spare_fuse(i) |
96 tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS);
97 val = (val << 1) | (reg & 0x1);
98 }
99 val = val * SPEEDO_MULT;
100 pr_debug("%s Core speedo value %u\n", __func__, val);
101
102 for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
103 if (val <= core_process_speedos[tegra_soc_speedo_id][i])
104 break;
105 }
106 tegra_core_process_id = i;
107
108 pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id);
109}
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 5070d833bdd1..837c7b9ea63b 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -25,8 +25,6 @@
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/platform_data/tegra_emc.h> 26#include <linux/platform_data/tegra_emc.h>
27 27
28#include <mach/iomap.h>
29
30#include "tegra2_emc.h" 28#include "tegra2_emc.h"
31#include "fuse.h" 29#include "fuse.h"
32 30
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index e9de5dfd94ec..f5b453f4bf4d 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -31,10 +31,9 @@
31 31
32#include <asm/clkdev.h> 32#include <asm/clkdev.h>
33 33
34#include <mach/iomap.h>
35
36#include "clock.h" 34#include "clock.h"
37#include "fuse.h" 35#include "fuse.h"
36#include "iomap.h"
38#include "tegra_cpu_car.h" 37#include "tegra_cpu_car.h"
39 38
40#define USE_PLL_LOCK_BITS 0 39#define USE_PLL_LOCK_BITS 0
@@ -792,6 +791,112 @@ struct clk_ops tegra30_twd_ops = {
792 .recalc_rate = tegra30_twd_clk_recalc_rate, 791 .recalc_rate = tegra30_twd_clk_recalc_rate,
793}; 792};
794 793
794/* bus clock functions */
795static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
796{
797 struct clk_tegra *c = to_clk_tegra(hw);
798 u32 val = clk_readl(c->reg);
799
800 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
801 return c->state;
802}
803
804static int tegra30_bus_clk_enable(struct clk_hw *hw)
805{
806 struct clk_tegra *c = to_clk_tegra(hw);
807 u32 val;
808
809 val = clk_readl(c->reg);
810 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
811 clk_writel(val, c->reg);
812
813 return 0;
814}
815
816static void tegra30_bus_clk_disable(struct clk_hw *hw)
817{
818 struct clk_tegra *c = to_clk_tegra(hw);
819 u32 val;
820
821 val = clk_readl(c->reg);
822 val |= BUS_CLK_DISABLE << c->reg_shift;
823 clk_writel(val, c->reg);
824}
825
826static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
827 unsigned long prate)
828{
829 struct clk_tegra *c = to_clk_tegra(hw);
830 u32 val = clk_readl(c->reg);
831 u64 rate = prate;
832
833 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
834 c->mul = 1;
835
836 if (c->mul != 0 && c->div != 0) {
837 rate *= c->mul;
838 rate += c->div - 1; /* round up */
839 do_div(rate, c->div);
840 }
841 return rate;
842}
843
844static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
845 unsigned long parent_rate)
846{
847 struct clk_tegra *c = to_clk_tegra(hw);
848 int ret = -EINVAL;
849 u32 val;
850 int i;
851
852 val = clk_readl(c->reg);
853 for (i = 1; i <= 4; i++) {
854 if (rate == parent_rate / i) {
855 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
856 val |= (i - 1) << c->reg_shift;
857 clk_writel(val, c->reg);
858 c->div = i;
859 c->mul = 1;
860 ret = 0;
861 break;
862 }
863 }
864
865 return ret;
866}
867
868static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
869 unsigned long *prate)
870{
871 unsigned long parent_rate = *prate;
872 s64 divider;
873
874 if (rate >= parent_rate)
875 return parent_rate;
876
877 divider = parent_rate;
878 divider += rate - 1;
879 do_div(divider, rate);
880
881 if (divider < 0)
882 return divider;
883
884 if (divider > 4)
885 divider = 4;
886 do_div(parent_rate, divider);
887
888 return parent_rate;
889}
890
891struct clk_ops tegra30_bus_ops = {
892 .is_enabled = tegra30_bus_clk_is_enabled,
893 .enable = tegra30_bus_clk_enable,
894 .disable = tegra30_bus_clk_disable,
895 .set_rate = tegra30_bus_clk_set_rate,
896 .round_rate = tegra30_bus_clk_round_rate,
897 .recalc_rate = tegra30_bus_clk_recalc_rate,
898};
899
795/* Blink output functions */ 900/* Blink output functions */
796static int tegra30_blink_clk_is_enabled(struct clk_hw *hw) 901static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
797{ 902{
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
index f2f88fef6b8b..7a34adb2f72d 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -34,6 +34,7 @@ extern struct clk_ops tegra_clk_out_ops;
34extern struct clk_ops tegra30_super_ops; 34extern struct clk_ops tegra30_super_ops;
35extern struct clk_ops tegra30_blink_clk_ops; 35extern struct clk_ops tegra30_blink_clk_ops;
36extern struct clk_ops tegra30_twd_ops; 36extern struct clk_ops tegra30_twd_ops;
37extern struct clk_ops tegra30_bus_ops;
37extern struct clk_ops tegra30_periph_clk_ops; 38extern struct clk_ops tegra30_periph_clk_ops;
38extern struct clk_ops tegra30_dsib_clk_ops; 39extern struct clk_ops tegra30_dsib_clk_ops;
39extern struct clk_ops tegra_nand_clk_ops; 40extern struct clk_ops tegra_nand_clk_ops;
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 3d2e5532a9ea..6942c7add3bb 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -711,6 +711,50 @@ static struct clk tegra_clk_sclk = {
711 .num_parents = ARRAY_SIZE(mux_sclk), 711 .num_parents = ARRAY_SIZE(mux_sclk),
712}; 712};
713 713
714static const char *tegra_hclk_parent_names[] = {
715 "tegra_sclk",
716};
717
718static struct clk *tegra_hclk_parents[] = {
719 &tegra_clk_sclk,
720};
721
722static struct clk tegra_hclk;
723static struct clk_tegra tegra_hclk_hw = {
724 .hw = {
725 .clk = &tegra_hclk,
726 },
727 .flags = DIV_BUS,
728 .reg = 0x30,
729 .reg_shift = 4,
730 .max_rate = 378000000,
731 .min_rate = 12000000,
732};
733DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
734 tegra_hclk_parents, &tegra_clk_sclk);
735
736static const char *tegra_pclk_parent_names[] = {
737 "tegra_hclk",
738};
739
740static struct clk *tegra_pclk_parents[] = {
741 &tegra_hclk,
742};
743
744static struct clk tegra_pclk;
745static struct clk_tegra tegra_pclk_hw = {
746 .hw = {
747 .clk = &tegra_pclk,
748 },
749 .flags = DIV_BUS,
750 .reg = 0x30,
751 .reg_shift = 0,
752 .max_rate = 167000000,
753 .min_rate = 12000000,
754};
755DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
756 tegra_pclk_parents, &tegra_hclk);
757
714static const char *mux_blink[] = { 758static const char *mux_blink[] = {
715 "clk_32k", 759 "clk_32k",
716}; 760};
@@ -1254,8 +1298,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
1254 CLK_DUPLICATE("usbd", "utmip-pad", NULL), 1298 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1255 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), 1299 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1256 CLK_DUPLICATE("usbd", "tegra-otg", NULL), 1300 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1257 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1258 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1259 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), 1301 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1260 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), 1302 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1261 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), 1303 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
@@ -1293,6 +1335,9 @@ struct clk_duplicate tegra_clk_duplicates[] = {
1293 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"), 1335 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1294 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"), 1336 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1295 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"), 1337 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
1338 CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
1339 CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
1340 CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
1296}; 1341};
1297 1342
1298struct clk *tegra_ptr_clks[] = { 1343struct clk *tegra_ptr_clks[] = {
@@ -1325,6 +1370,8 @@ struct clk *tegra_ptr_clks[] = {
1325 &tegra_cml1, 1370 &tegra_cml1,
1326 &tegra_pciex, 1371 &tegra_pciex,
1327 &tegra_clk_sclk, 1372 &tegra_clk_sclk,
1373 &tegra_hclk,
1374 &tegra_pclk,
1328 &tegra_clk_blink, 1375 &tegra_clk_blink,
1329 &tegra30_clk_twd, 1376 &tegra30_clk_twd,
1330}; 1377};
diff --git a/arch/arm/mach-tegra/tegra30_speedo.c b/arch/arm/mach-tegra/tegra30_speedo.c
new file mode 100644
index 000000000000..125cb16424a6
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_speedo.c
@@ -0,0 +1,292 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/kernel.h>
18#include <linux/bug.h>
19
20#include "fuse.h"
21
22#define CORE_PROCESS_CORNERS_NUM 1
23#define CPU_PROCESS_CORNERS_NUM 6
24
25#define FUSE_SPEEDO_CALIB_0 0x114
26#define FUSE_PACKAGE_INFO 0X1FC
27#define FUSE_TEST_PROG_VER 0X128
28
29#define G_SPEEDO_BIT_MINUS1 58
30#define G_SPEEDO_BIT_MINUS1_R 59
31#define G_SPEEDO_BIT_MINUS2 60
32#define G_SPEEDO_BIT_MINUS2_R 61
33#define LP_SPEEDO_BIT_MINUS1 62
34#define LP_SPEEDO_BIT_MINUS1_R 63
35#define LP_SPEEDO_BIT_MINUS2 64
36#define LP_SPEEDO_BIT_MINUS2_R 65
37
38enum {
39 THRESHOLD_INDEX_0,
40 THRESHOLD_INDEX_1,
41 THRESHOLD_INDEX_2,
42 THRESHOLD_INDEX_3,
43 THRESHOLD_INDEX_4,
44 THRESHOLD_INDEX_5,
45 THRESHOLD_INDEX_6,
46 THRESHOLD_INDEX_7,
47 THRESHOLD_INDEX_8,
48 THRESHOLD_INDEX_9,
49 THRESHOLD_INDEX_10,
50 THRESHOLD_INDEX_11,
51 THRESHOLD_INDEX_COUNT,
52};
53
54static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
55 {180},
56 {170},
57 {195},
58 {180},
59 {168},
60 {192},
61 {180},
62 {170},
63 {195},
64 {180},
65 {180},
66 {180},
67};
68
69static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
70 {306, 338, 360, 376, UINT_MAX},
71 {295, 336, 358, 375, UINT_MAX},
72 {325, 325, 358, 375, UINT_MAX},
73 {325, 325, 358, 375, UINT_MAX},
74 {292, 324, 348, 364, UINT_MAX},
75 {324, 324, 348, 364, UINT_MAX},
76 {324, 324, 348, 364, UINT_MAX},
77 {295, 336, 358, 375, UINT_MAX},
78 {358, 358, 358, 358, 397, UINT_MAX},
79 {364, 364, 364, 364, 397, UINT_MAX},
80 {295, 336, 358, 375, 391, UINT_MAX},
81 {295, 336, 358, 375, 391, UINT_MAX},
82};
83
84static int threshold_index;
85static int package_id;
86
87static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
88{
89 u32 reg;
90 int ate_ver;
91 int bit_minus1;
92 int bit_minus2;
93
94 reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
95
96 *speedo_lp = (reg & 0xFFFF) * 4;
97 *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
98
99 ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
100 pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
101
102 if (ate_ver >= 26) {
103 bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
104 bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
105 bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
106 bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
107 *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
108
109 bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
110 bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
111 bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
112 bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
113 *speedo_g |= (bit_minus1 << 1) | bit_minus2;
114 } else {
115 *speedo_lp |= 0x3;
116 *speedo_g |= 0x3;
117 }
118}
119
120static void rev_sku_to_speedo_ids(int rev, int sku)
121{
122 switch (rev) {
123 case TEGRA_REVISION_A01:
124 tegra_cpu_speedo_id = 0;
125 tegra_soc_speedo_id = 0;
126 threshold_index = THRESHOLD_INDEX_0;
127 break;
128 case TEGRA_REVISION_A02:
129 case TEGRA_REVISION_A03:
130 switch (sku) {
131 case 0x87:
132 case 0x82:
133 tegra_cpu_speedo_id = 1;
134 tegra_soc_speedo_id = 1;
135 threshold_index = THRESHOLD_INDEX_1;
136 break;
137 case 0x81:
138 switch (package_id) {
139 case 1:
140 tegra_cpu_speedo_id = 2;
141 tegra_soc_speedo_id = 2;
142 threshold_index = THRESHOLD_INDEX_2;
143 break;
144 case 2:
145 tegra_cpu_speedo_id = 4;
146 tegra_soc_speedo_id = 1;
147 threshold_index = THRESHOLD_INDEX_7;
148 break;
149 default:
150 pr_err("Tegra30: Unknown pkg %d\n", package_id);
151 BUG();
152 break;
153 }
154 break;
155 case 0x80:
156 switch (package_id) {
157 case 1:
158 tegra_cpu_speedo_id = 5;
159 tegra_soc_speedo_id = 2;
160 threshold_index = THRESHOLD_INDEX_8;
161 break;
162 case 2:
163 tegra_cpu_speedo_id = 6;
164 tegra_soc_speedo_id = 2;
165 threshold_index = THRESHOLD_INDEX_9;
166 break;
167 default:
168 pr_err("Tegra30: Unknown pkg %d\n", package_id);
169 BUG();
170 break;
171 }
172 break;
173 case 0x83:
174 switch (package_id) {
175 case 1:
176 tegra_cpu_speedo_id = 7;
177 tegra_soc_speedo_id = 1;
178 threshold_index = THRESHOLD_INDEX_10;
179 break;
180 case 2:
181 tegra_cpu_speedo_id = 3;
182 tegra_soc_speedo_id = 2;
183 threshold_index = THRESHOLD_INDEX_3;
184 break;
185 default:
186 pr_err("Tegra30: Unknown pkg %d\n", package_id);
187 BUG();
188 break;
189 }
190 break;
191 case 0x8F:
192 tegra_cpu_speedo_id = 8;
193 tegra_soc_speedo_id = 1;
194 threshold_index = THRESHOLD_INDEX_11;
195 break;
196 case 0x08:
197 tegra_cpu_speedo_id = 1;
198 tegra_soc_speedo_id = 1;
199 threshold_index = THRESHOLD_INDEX_4;
200 break;
201 case 0x02:
202 tegra_cpu_speedo_id = 2;
203 tegra_soc_speedo_id = 2;
204 threshold_index = THRESHOLD_INDEX_5;
205 break;
206 case 0x04:
207 tegra_cpu_speedo_id = 3;
208 tegra_soc_speedo_id = 2;
209 threshold_index = THRESHOLD_INDEX_6;
210 break;
211 case 0:
212 switch (package_id) {
213 case 1:
214 tegra_cpu_speedo_id = 2;
215 tegra_soc_speedo_id = 2;
216 threshold_index = THRESHOLD_INDEX_2;
217 break;
218 case 2:
219 tegra_cpu_speedo_id = 3;
220 tegra_soc_speedo_id = 2;
221 threshold_index = THRESHOLD_INDEX_3;
222 break;
223 default:
224 pr_err("Tegra30: Unknown pkg %d\n", package_id);
225 BUG();
226 break;
227 }
228 break;
229 default:
230 pr_warn("Tegra30: Unknown SKU %d\n", sku);
231 tegra_cpu_speedo_id = 0;
232 tegra_soc_speedo_id = 0;
233 threshold_index = THRESHOLD_INDEX_0;
234 break;
235 }
236 break;
237 default:
238 pr_warn("Tegra30: Unknown chip rev %d\n", rev);
239 tegra_cpu_speedo_id = 0;
240 tegra_soc_speedo_id = 0;
241 threshold_index = THRESHOLD_INDEX_0;
242 break;
243 }
244}
245
246void tegra30_init_speedo_data(void)
247{
248 u32 cpu_speedo_val;
249 u32 core_speedo_val;
250 int i;
251
252 BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
253 THRESHOLD_INDEX_COUNT);
254 BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
255 THRESHOLD_INDEX_COUNT);
256
257 package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
258
259 rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
260 fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
261 pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
262 pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
263
264 for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
265 if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
266 break;
267 }
268 tegra_cpu_process_id = i - 1;
269
270 if (tegra_cpu_process_id == -1) {
271 pr_warn("Tegra30: CPU speedo value %3d out of range",
272 cpu_speedo_val);
273 tegra_cpu_process_id = 0;
274 tegra_cpu_speedo_id = 1;
275 }
276
277 for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
278 if (core_speedo_val < core_process_speedos[threshold_index][i])
279 break;
280 }
281 tegra_core_process_id = i - 1;
282
283 if (tegra_core_process_id == -1) {
284 pr_warn("Tegra30: CORE speedo value %3d out of range",
285 core_speedo_val);
286 tegra_core_process_id = 0;
287 tegra_soc_speedo_id = 1;
288 }
289
290 pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d",
291 tegra_cpu_speedo_id, tegra_soc_speedo_id);
292}
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index d3b8c8e7368f..e4863f3e9ee7 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -26,16 +26,14 @@
26#include <linux/clocksource.h> 26#include <linux/clocksource.h>
27#include <linux/clk.h> 27#include <linux/clk.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
29 31
30#include <asm/mach/time.h> 32#include <asm/mach/time.h>
31#include <asm/smp_twd.h> 33#include <asm/smp_twd.h>
32#include <asm/sched_clock.h> 34#include <asm/sched_clock.h>
33 35
34#include <mach/iomap.h>
35#include <mach/irqs.h>
36
37#include "board.h" 36#include "board.h"
38#include "clock.h"
39 37
40#define RTC_SECONDS 0x08 38#define RTC_SECONDS 0x08
41#define RTC_SHADOW_SECONDS 0x0c 39#define RTC_SHADOW_SECONDS 0x0c
@@ -53,8 +51,8 @@
53#define TIMER_PTV 0x0 51#define TIMER_PTV 0x0
54#define TIMER_PCR 0x4 52#define TIMER_PCR 0x4
55 53
56static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); 54static void __iomem *timer_reg_base;
57static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE); 55static void __iomem *rtc_base;
58 56
59static struct timespec persistent_ts; 57static struct timespec persistent_ts;
60static u64 persistent_ms, last_persistent_ms; 58static u64 persistent_ms, last_persistent_ms;
@@ -158,40 +156,66 @@ static struct irqaction tegra_timer_irq = {
158 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, 156 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
159 .handler = tegra_timer_interrupt, 157 .handler = tegra_timer_interrupt,
160 .dev_id = &tegra_clockevent, 158 .dev_id = &tegra_clockevent,
161 .irq = INT_TMR3,
162}; 159};
163 160
164#ifdef CONFIG_HAVE_ARM_TWD 161static const struct of_device_id timer_match[] __initconst = {
165static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 162 { .compatible = "nvidia,tegra20-timer" },
166 TEGRA_ARM_PERIF_BASE + 0x600, 163 {}
167 IRQ_LOCALTIMER); 164};
168 165
169static void __init tegra_twd_init(void) 166static const struct of_device_id rtc_match[] __initconst = {
170{ 167 { .compatible = "nvidia,tegra20-rtc" },
171 int err = twd_local_timer_register(&twd_local_timer); 168 {}
172 if (err) 169};
173 pr_err("twd_local_timer_register failed %d\n", err);
174}
175#else
176#define tegra_twd_init() do {} while(0)
177#endif
178 170
179static void __init tegra_init_timer(void) 171static void __init tegra_init_timer(void)
180{ 172{
173 struct device_node *np;
181 struct clk *clk; 174 struct clk *clk;
182 unsigned long rate; 175 unsigned long rate;
183 int ret; 176 int ret;
184 177
178 np = of_find_matching_node(NULL, timer_match);
179 if (!np) {
180 pr_err("Failed to find timer DT node\n");
181 BUG();
182 }
183
184 timer_reg_base = of_iomap(np, 0);
185 if (!timer_reg_base) {
186 pr_err("Can't map timer registers");
187 BUG();
188 }
189
190 tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
191 if (tegra_timer_irq.irq <= 0) {
192 pr_err("Failed to map timer IRQ\n");
193 BUG();
194 }
195
185 clk = clk_get_sys("timer", NULL); 196 clk = clk_get_sys("timer", NULL);
186 if (IS_ERR(clk)) { 197 if (IS_ERR(clk)) {
187 pr_warn("Unable to get timer clock." 198 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
188 " Assuming 12Mhz input clock.\n");
189 rate = 12000000; 199 rate = 12000000;
190 } else { 200 } else {
191 clk_prepare_enable(clk); 201 clk_prepare_enable(clk);
192 rate = clk_get_rate(clk); 202 rate = clk_get_rate(clk);
193 } 203 }
194 204
205 of_node_put(np);
206
207 np = of_find_matching_node(NULL, rtc_match);
208 if (!np) {
209 pr_err("Failed to find RTC DT node\n");
210 BUG();
211 }
212
213 rtc_base = of_iomap(np, 0);
214 if (!rtc_base) {
215 pr_err("Can't map RTC registers");
216 BUG();
217 }
218
195 /* 219 /*
196 * rtc registers are used by read_persistent_clock, keep the rtc clock 220 * rtc registers are used by read_persistent_clock, keep the rtc clock
197 * enabled 221 * enabled
@@ -202,6 +226,8 @@ static void __init tegra_init_timer(void)
202 else 226 else
203 clk_prepare_enable(clk); 227 clk_prepare_enable(clk);
204 228
229 of_node_put(np);
230
205 switch (rate) { 231 switch (rate) {
206 case 12000000: 232 case 12000000:
207 timer_writel(0x000b, TIMERUS_USEC_CFG); 233 timer_writel(0x000b, TIMERUS_USEC_CFG);
@@ -223,13 +249,13 @@ static void __init tegra_init_timer(void)
223 249
224 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, 250 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
225 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { 251 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
226 printk(KERN_ERR "Failed to register clocksource\n"); 252 pr_err("Failed to register clocksource\n");
227 BUG(); 253 BUG();
228 } 254 }
229 255
230 ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); 256 ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
231 if (ret) { 257 if (ret) {
232 printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret); 258 pr_err("Failed to register timer IRQ: %d\n", ret);
233 BUG(); 259 BUG();
234 } 260 }
235 261
@@ -241,7 +267,9 @@ static void __init tegra_init_timer(void)
241 tegra_clockevent.cpumask = cpu_all_mask; 267 tegra_clockevent.cpumask = cpu_all_mask;
242 tegra_clockevent.irq = tegra_timer_irq.irq; 268 tegra_clockevent.irq = tegra_timer_irq.irq;
243 clockevents_register_device(&tegra_clockevent); 269 clockevents_register_device(&tegra_clockevent);
244 tegra_twd_init(); 270#ifdef CONFIG_HAVE_ARM_TWD
271 twd_local_timer_of_register();
272#endif
245 register_persistent_clock(NULL, tegra_read_persistent_clock); 273 register_persistent_clock(NULL, tegra_read_persistent_clock);
246} 274}
247 275
diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c
index 0b6f0b28a487..bd5de08ad6fd 100644
--- a/drivers/amba/tegra-ahb.c
+++ b/drivers/amba/tegra-ahb.c
@@ -24,6 +24,7 @@
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/tegra-ahb.h>
27 28
28#define DRV_NAME "tegra-ahb" 29#define DRV_NAME "tegra-ahb"
29 30
diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c
index 37185e6630cd..e69f3bc473be 100644
--- a/drivers/crypto/tegra-aes.c
+++ b/drivers/crypto/tegra-aes.c
@@ -41,8 +41,6 @@
41#include <linux/completion.h> 41#include <linux/completion.h>
42#include <linux/workqueue.h> 42#include <linux/workqueue.h>
43 43
44#include <mach/clk.h>
45
46#include <crypto/scatterwalk.h> 44#include <crypto/scatterwalk.h>
47#include <crypto/aes.h> 45#include <crypto/aes.h>
48#include <crypto/internal/rng.h> 46#include <crypto/internal/rng.h>
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index a649f146d17b..41678639b7e3 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -34,13 +34,11 @@
34#include <linux/of_iommu.h> 34#include <linux/of_iommu.h>
35#include <linux/debugfs.h> 35#include <linux/debugfs.h>
36#include <linux/seq_file.h> 36#include <linux/seq_file.h>
37#include <linux/tegra-ahb.h>
37 38
38#include <asm/page.h> 39#include <asm/page.h>
39#include <asm/cacheflush.h> 40#include <asm/cacheflush.h>
40 41
41#include <mach/iomap.h>
42#include <mach/tegra-ahb.h>
43
44enum smmu_hwgrp { 42enum smmu_hwgrp {
45 HWGRP_AFI, 43 HWGRP_AFI,
46 HWGRP_AVPC, 44 HWGRP_AVPC,
diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 094fdc366f30..97cdf0856aed 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -39,7 +39,6 @@
39#include <linux/workqueue.h> 39#include <linux/workqueue.h>
40 40
41#include <mach/clk.h> 41#include <mach/clk.h>
42#include <mach/iomap.h>
43 42
44#include "nvec.h" 43#include "nvec.h"
45 44
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 6223d1757848..2de089001ae9 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -28,7 +28,10 @@
28#include <linux/pm_runtime.h> 28#include <linux/pm_runtime.h>
29 29
30#include <linux/usb/tegra_usb_phy.h> 30#include <linux/usb/tegra_usb_phy.h>
31#include <mach/iomap.h> 31
32#define TEGRA_USB_BASE 0xC5000000
33#define TEGRA_USB2_BASE 0xC5004000
34#define TEGRA_USB3_BASE 0xC5008000
32 35
33#define TEGRA_USB_DMA_ALIGN 32 36#define TEGRA_USB_DMA_ALIGN 32
34 37
diff --git a/drivers/usb/phy/tegra_usb_phy.c b/drivers/usb/phy/tegra_usb_phy.c
index 987116f9efcd..9d13c81754e0 100644
--- a/drivers/usb/phy/tegra_usb_phy.c
+++ b/drivers/usb/phy/tegra_usb_phy.c
@@ -29,7 +29,9 @@
29#include <linux/usb/ulpi.h> 29#include <linux/usb/ulpi.h>
30#include <asm/mach-types.h> 30#include <asm/mach-types.h>
31#include <linux/usb/tegra_usb_phy.h> 31#include <linux/usb/tegra_usb_phy.h>
32#include <mach/iomap.h> 32
33#define TEGRA_USB_BASE 0xC5000000
34#define TEGRA_USB_SIZE SZ_16K
33 35
34#define ULPI_VIEWPORT 0x170 36#define ULPI_VIEWPORT 0x170
35 37
diff --git a/arch/arm/mach-tegra/include/mach/tegra-ahb.h b/include/linux/tegra-ahb.h
index e0f8c84b1d8c..f1cd075ceee1 100644
--- a/arch/arm/mach-tegra/include/mach/tegra-ahb.h
+++ b/include/linux/tegra-ahb.h
@@ -11,9 +11,9 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#ifndef __MACH_TEGRA_AHB_H__ 14#ifndef __LINUX_AHB_H__
15#define __MACH_TEGRA_AHB_H__ 15#define __LINUX_AHB_H__
16 16
17extern int tegra_ahb_enable_smmu(struct device_node *ahb); 17extern int tegra_ahb_enable_smmu(struct device_node *ahb);
18 18
19#endif /* __MACH_TEGRA_AHB_H__ */ 19#endif /* __LINUX_AHB_H__ */
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index bf5610122c76..64b67a309196 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -26,7 +26,6 @@
26#include <linux/regmap.h> 26#include <linux/regmap.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28#include <mach/clk.h> 28#include <mach/clk.h>
29#include <mach/dma.h>
30#include <sound/soc.h> 29#include <sound/soc.h>
31#include "tegra30_ahub.h" 30#include "tegra30_ahub.h"
32 31
diff --git a/sound/soc/tegra/tegra_pcm.h b/sound/soc/tegra/tegra_pcm.h
index b40279b9f413..bc8b46af928e 100644
--- a/sound/soc/tegra/tegra_pcm.h
+++ b/sound/soc/tegra/tegra_pcm.h
@@ -31,8 +31,6 @@
31#ifndef __TEGRA_PCM_H__ 31#ifndef __TEGRA_PCM_H__
32#define __TEGRA_PCM_H__ 32#define __TEGRA_PCM_H__
33 33
34#include <mach/dma.h>
35
36struct tegra_pcm_dma_params { 34struct tegra_pcm_dma_params {
37 unsigned long addr; 35 unsigned long addr;
38 unsigned long wrap; 36 unsigned long wrap;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 19:16:32 -0400