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-rw-r--r--arch/arm/boot/dts/armada-370-db.dts134
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts176
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts96
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi301
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi328
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts200
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts208
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi252
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi308
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi428
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts260
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi193
12 files changed, 1452 insertions, 1432 deletions
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e766f8bfc86f..2353b1f13704 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,85 +30,87 @@
30 }; 30 };
31 31
32 soc { 32 soc {
33 serial@12000 { 33 internal-regs {
34 clock-frequency = <200000000>; 34 serial@12000 {
35 status = "okay"; 35 clock-frequency = <200000000>;
36 }; 36 status = "okay";
37 sata@a0000 {
38 nr-ports = <2>;
39 status = "okay";
40 };
41
42 mdio {
43 phy0: ethernet-phy@0 {
44 reg = <0>;
45 }; 37 };
46 38 sata@a0000 {
47 phy1: ethernet-phy@1 { 39 nr-ports = <2>;
48 reg = <1>; 40 status = "okay";
49 }; 41 };
50 };
51 42
52 ethernet@70000 { 43 mdio {
53 status = "okay"; 44 phy0: ethernet-phy@0 {
54 phy = <&phy0>; 45 reg = <0>;
55 phy-mode = "rgmii-id"; 46 };
56 };
57 ethernet@74000 {
58 status = "okay";
59 phy = <&phy1>;
60 phy-mode = "rgmii-id";
61 };
62 47
63 mvsdio@d4000 { 48 phy1: ethernet-phy@1 {
64 pinctrl-0 = <&sdio_pins1>; 49 reg = <1>;
65 pinctrl-names = "default"; 50 };
66 /* 51 };
67 * This device is disabled by default, because
68 * using the SD card connector requires
69 * changing the default CON40 connector
70 * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
71 * different connector
72 * "DB-88F6710_MPP_RGMII_SD_Jumper".
73 */
74 status = "disabled";
75 /* No CD or WP GPIOs */
76 };
77 52
78 usb@50000 { 53 ethernet@70000 {
79 status = "okay"; 54 status = "okay";
80 }; 55 phy = <&phy0>;
56 phy-mode = "rgmii-id";
57 };
58 ethernet@74000 {
59 status = "okay";
60 phy = <&phy1>;
61 phy-mode = "rgmii-id";
62 };
81 63
82 usb@51000 { 64 mvsdio@d4000 {
83 status = "okay"; 65 pinctrl-0 = <&sdio_pins1>;
84 }; 66 pinctrl-names = "default";
67 /*
68 * This device is disabled by default, because
69 * using the SD card connector requires
70 * changing the default CON40 connector
71 * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
72 * different connector
73 * "DB-88F6710_MPP_RGMII_SD_Jumper".
74 */
75 status = "disabled";
76 /* No CD or WP GPIOs */
77 };
85 78
86 spi0: spi@10600 { 79 usb@50000 {
87 status = "okay"; 80 status = "okay";
81 };
88 82
89 spi-flash@0 { 83 usb@51000 {
90 #address-cells = <1>; 84 status = "okay";
91 #size-cells = <1>;
92 compatible = "mx25l25635e";
93 reg = <0>; /* Chip select 0 */
94 spi-max-frequency = <50000000>;
95 }; 85 };
96 };
97 86
98 pcie-controller { 87 spi0: spi@10600 {
99 status = "okay";
100 /*
101 * The two PCIe units are accessible through
102 * both standard PCIe slots and mini-PCIe
103 * slots on the board.
104 */
105 pcie@1,0 {
106 /* Port 0, Lane 0 */
107 status = "okay"; 88 status = "okay";
89
90 spi-flash@0 {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "mx25l25635e";
94 reg = <0>; /* Chip select 0 */
95 spi-max-frequency = <50000000>;
96 };
108 }; 97 };
109 pcie@2,0 { 98
110 /* Port 1, Lane 0 */ 99 pcie-controller {
111 status = "okay"; 100 status = "okay";
101 /*
102 * The two PCIe units are accessible through
103 * both standard PCIe slots and mini-PCIe
104 * slots on the board.
105 */
106 pcie@1,0 {
107 /* Port 0, Lane 0 */
108 status = "okay";
109 };
110 pcie@2,0 {
111 /* Port 1, Lane 0 */
112 status = "okay";
113 };
112 }; 114 };
113 }; 115 };
114 }; 116 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 6530ae3ed661..14e36e19d515 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,113 +25,115 @@
25 }; 25 };
26 26
27 soc { 27 soc {
28 serial@12000 { 28 internal-regs {
29 clock-frequency = <200000000>; 29 serial@12000 {
30 status = "okay"; 30 clock-frequency = <200000000>;
31 }; 31 status = "okay";
32 timer@20300 {
33 clock-frequency = <600000000>;
34 status = "okay";
35 };
36
37 pinctrl {
38 pwr_led_pin: pwr-led-pin {
39 marvell,pins = "mpp63";
40 marvell,function = "gpo";
41 }; 32 };
42 33 timer@20300 {
43 stat_led_pins: stat-led-pins { 34 clock-frequency = <600000000>;
44 marvell,pins = "mpp64", "mpp65"; 35 status = "okay";
45 marvell,function = "gpio";
46 }; 36 };
47 };
48 37
49 gpio_leds { 38 pinctrl {
50 compatible = "gpio-leds"; 39 pwr_led_pin: pwr-led-pin {
51 pinctrl-names = "default"; 40 marvell,pins = "mpp63";
52 pinctrl-0 = <&pwr_led_pin &stat_led_pins>; 41 marvell,function = "gpo";
42 };
53 43
54 green_pwr_led { 44 stat_led_pins: stat-led-pins {
55 label = "mirabox:green:pwr"; 45 marvell,pins = "mpp64", "mpp65";
56 gpios = <&gpio1 31 1>; 46 marvell,function = "gpio";
57 linux,default-trigger = "heartbeat"; 47 };
58 }; 48 };
59 49
60 blue_stat_led { 50 gpio_leds {
61 label = "mirabox:blue:stat"; 51 compatible = "gpio-leds";
62 gpios = <&gpio2 0 1>; 52 pinctrl-names = "default";
63 linux,default-trigger = "cpu0"; 53 pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
54
55 green_pwr_led {
56 label = "mirabox:green:pwr";
57 gpios = <&gpio1 31 1>;
58 linux,default-trigger = "heartbeat";
59 };
60
61 blue_stat_led {
62 label = "mirabox:blue:stat";
63 gpios = <&gpio2 0 1>;
64 linux,default-trigger = "cpu0";
65 };
66
67 green_stat_led {
68 label = "mirabox:green:stat";
69 gpios = <&gpio2 1 1>;
70 default-state = "off";
71 };
64 }; 72 };
65 73
66 green_stat_led { 74 mdio {
67 label = "mirabox:green:stat"; 75 phy0: ethernet-phy@0 {
68 gpios = <&gpio2 1 1>; 76 reg = <0>;
69 default-state = "off"; 77 };
70 };
71 };
72 78
73 mdio { 79 phy1: ethernet-phy@1 {
74 phy0: ethernet-phy@0 { 80 reg = <1>;
75 reg = <0>; 81 };
76 }; 82 };
77 83 ethernet@70000 {
78 phy1: ethernet-phy@1 { 84 status = "okay";
79 reg = <1>; 85 phy = <&phy0>;
86 phy-mode = "rgmii-id";
87 };
88 ethernet@74000 {
89 status = "okay";
90 phy = <&phy1>;
91 phy-mode = "rgmii-id";
80 }; 92 };
81 };
82 ethernet@70000 {
83 status = "okay";
84 phy = <&phy0>;
85 phy-mode = "rgmii-id";
86 };
87 ethernet@74000 {
88 status = "okay";
89 phy = <&phy1>;
90 phy-mode = "rgmii-id";
91 };
92
93 mvsdio@d4000 {
94 pinctrl-0 = <&sdio_pins3>;
95 pinctrl-names = "default";
96 status = "okay";
97 /*
98 * No CD or WP GPIOs: SDIO interface used for
99 * Wifi/Bluetooth chip
100 */
101 };
102
103 usb@50000 {
104 status = "okay";
105 };
106 93
107 usb@51000 { 94 mvsdio@d4000 {
108 status = "okay"; 95 pinctrl-0 = <&sdio_pins3>;
109 }; 96 pinctrl-names = "default";
97 status = "okay";
98 /*
99 * No CD or WP GPIOs: SDIO interface used for
100 * Wifi/Bluetooth chip
101 */
102 };
110 103
111 i2c@11000 { 104 usb@50000 {
112 status = "okay"; 105 status = "okay";
113 clock-frequency = <100000>;
114 pca9505: pca9505@25 {
115 compatible = "nxp,pca9505";
116 gpio-controller;
117 #gpio-cells = <2>;
118 reg = <0x25>;
119 }; 106 };
120 };
121 107
122 pcie-controller { 108 usb@51000 {
123 status = "okay"; 109 status = "okay";
110 };
124 111
125 /* Internal mini-PCIe connector */ 112 i2c@11000 {
126 pcie@1,0 {
127 /* Port 0, Lane 0 */
128 status = "okay"; 113 status = "okay";
114 clock-frequency = <100000>;
115 pca9505: pca9505@25 {
116 compatible = "nxp,pca9505";
117 gpio-controller;
118 #gpio-cells = <2>;
119 reg = <0x25>;
120 };
129 }; 121 };
130 122
131 /* Connected on the PCB to a USB 3.0 XHCI controller */ 123 pcie-controller {
132 pcie@2,0 {
133 /* Port 1, Lane 0 */
134 status = "okay"; 124 status = "okay";
125
126 /* Internal mini-PCIe connector */
127 pcie@1,0 {
128 /* Port 0, Lane 0 */
129 status = "okay";
130 };
131
132 /* Connected on the PCB to a USB 3.0 XHCI controller */
133 pcie@2,0 {
134 /* Port 1, Lane 0 */
135 status = "okay";
136 };
135 }; 137 };
136 }; 138 };
137 }; 139 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 83d5c0419750..130f8390a7e4 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,60 +28,62 @@
28 }; 28 };
29 29
30 soc { 30 soc {
31 serial@12000 { 31 internal-regs {
32 clock-frequency = <200000000>; 32 serial@12000 {
33 status = "okay"; 33 clock-frequency = <200000000>;
34 }; 34 status = "okay";
35 sata@a0000 {
36 nr-ports = <2>;
37 status = "okay";
38 };
39
40 mdio {
41 phy0: ethernet-phy@0 {
42 reg = <0>;
43 }; 35 };
36 sata@a0000 {
37 nr-ports = <2>;
38 status = "okay";
39 };
40
41 mdio {
42 phy0: ethernet-phy@0 {
43 reg = <0>;
44 };
44 45
45 phy1: ethernet-phy@1 { 46 phy1: ethernet-phy@1 {
46 reg = <1>; 47 reg = <1>;
48 };
47 }; 49 };
48 };
49 50
50 ethernet@70000 { 51 ethernet@70000 {
51 status = "okay"; 52 status = "okay";
52 phy = <&phy0>; 53 phy = <&phy0>;
53 phy-mode = "sgmii"; 54 phy-mode = "sgmii";
54 }; 55 };
55 ethernet@74000 { 56 ethernet@74000 {
56 status = "okay"; 57 status = "okay";
57 phy = <&phy1>; 58 phy = <&phy1>;
58 phy-mode = "rgmii-id"; 59 phy-mode = "rgmii-id";
59 }; 60 };
60 61
61 mvsdio@d4000 { 62 mvsdio@d4000 {
62 pinctrl-0 = <&sdio_pins1>; 63 pinctrl-0 = <&sdio_pins1>;
63 pinctrl-names = "default"; 64 pinctrl-names = "default";
64 status = "okay"; 65 status = "okay";
65 /* No CD or WP GPIOs */ 66 /* No CD or WP GPIOs */
66 }; 67 };
67 68
68 usb@50000 { 69 usb@50000 {
69 status = "okay"; 70 status = "okay";
70 }; 71 };
71 72
72 usb@51000 { 73 usb@51000 {
73 status = "okay"; 74 status = "okay";
74 }; 75 };
75 };
76 76
77 gpio-keys { 77 gpio-keys {
78 compatible = "gpio-keys"; 78 compatible = "gpio-keys";
79 #address-cells = <1>; 79 #address-cells = <1>;
80 #size-cells = <0>; 80 #size-cells = <0>;
81 button@1 { 81 button@1 {
82 label = "Software Button"; 82 label = "Software Button";
83 linux,code = <116>; 83 linux,code = <116>;
84 gpios = <&gpio0 6 1>; 84 gpios = <&gpio0 6 1>;
85 };
86 };
85 }; 87 };
86 }; 88 };
87}; 89 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index da40ce5711b3..bf8f91113625 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -28,7 +28,6 @@
28 }; 28 };
29 }; 29 };
30 30
31
32 soc { 31 soc {
33 #address-cells = <1>; 32 #address-cells = <1>;
34 #size-cells = <1>; 33 #size-cells = <1>;
@@ -36,192 +35,196 @@
36 interrupt-parent = <&mpic>; 35 interrupt-parent = <&mpic>;
37 ranges = <0 0xd0000000 0x100000>; 36 ranges = <0 0xd0000000 0x100000>;
38 37
39 mpic: interrupt-controller@20000 { 38 internal-regs {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 ranges;
43
44 mpic: interrupt-controller@20000 {
40 compatible = "marvell,mpic"; 45 compatible = "marvell,mpic";
41 #interrupt-cells = <1>; 46 #interrupt-cells = <1>;
42 #size-cells = <1>; 47 #size-cells = <1>;
43 interrupt-controller; 48 interrupt-controller;
44 }; 49 };
45 50
46 coherency-fabric@20200 { 51 coherency-fabric@20200 {
47 compatible = "marvell,coherency-fabric"; 52 compatible = "marvell,coherency-fabric";
48 reg = <0x20200 0xb0>, 53 reg = <0x20200 0xb0>, <0x21810 0x1c>;
49 <0x21810 0x1c>; 54 };
50 };
51 55
52 serial@12000 { 56 serial@12000 {
53 compatible = "snps,dw-apb-uart"; 57 compatible = "snps,dw-apb-uart";
54 reg = <0x12000 0x100>; 58 reg = <0x12000 0x100>;
55 reg-shift = <2>; 59 reg-shift = <2>;
56 interrupts = <41>; 60 interrupts = <41>;
57 reg-io-width = <1>; 61 reg-io-width = <1>;
58 status = "disabled"; 62 status = "disabled";
59 }; 63 };
60 serial@12100 { 64 serial@12100 {
61 compatible = "snps,dw-apb-uart"; 65 compatible = "snps,dw-apb-uart";
62 reg = <0x12100 0x100>; 66 reg = <0x12100 0x100>;
63 reg-shift = <2>; 67 reg-shift = <2>;
64 interrupts = <42>; 68 interrupts = <42>;
65 reg-io-width = <1>; 69 reg-io-width = <1>;
66 status = "disabled"; 70 status = "disabled";
67 }; 71 };
68 72
69 timer@20300 { 73 timer@20300 {
70 compatible = "marvell,armada-370-xp-timer"; 74 compatible = "marvell,armada-370-xp-timer";
71 reg = <0x20300 0x30>, 75 reg = <0x20300 0x30>, <0x21040 0x30>;
72 <0x21040 0x30>; 76 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
73 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 77 clocks = <&coreclk 2>;
74 clocks = <&coreclk 2>; 78 };
75 }; 79
76 80 sata@a0000 {
77 sata@a0000 { 81 compatible = "marvell,orion-sata";
78 compatible = "marvell,orion-sata"; 82 reg = <0xa0000 0x2400>;
79 reg = <0xa0000 0x2400>; 83 interrupts = <55>;
80 interrupts = <55>; 84 clocks = <&gateclk 15>, <&gateclk 30>;
81 clocks = <&gateclk 15>, <&gateclk 30>; 85 clock-names = "0", "1";
82 clock-names = "0", "1"; 86 status = "disabled";
83 status = "disabled"; 87 };
84 };
85 88
86 mdio { 89 mdio {
87 #address-cells = <1>; 90 #address-cells = <1>;
88 #size-cells = <0>; 91 #size-cells = <0>;
89 compatible = "marvell,orion-mdio"; 92 compatible = "marvell,orion-mdio";
90 reg = <0x72004 0x4>; 93 reg = <0x72004 0x4>;
91 }; 94 };
92 95
93 ethernet@70000 { 96 ethernet@70000 {
94 compatible = "marvell,armada-370-neta"; 97 compatible = "marvell,armada-370-neta";
95 reg = <0x70000 0x2500>; 98 reg = <0x70000 0x2500>;
96 interrupts = <8>; 99 interrupts = <8>;
97 clocks = <&gateclk 4>; 100 clocks = <&gateclk 4>;
98 status = "disabled"; 101 status = "disabled";
99 }; 102 };
100 103
101 ethernet@74000 { 104 ethernet@74000 {
102 compatible = "marvell,armada-370-neta"; 105 compatible = "marvell,armada-370-neta";
103 reg = <0x74000 0x2500>; 106 reg = <0x74000 0x2500>;
104 interrupts = <10>; 107 interrupts = <10>;
105 clocks = <&gateclk 3>; 108 clocks = <&gateclk 3>;
106 status = "disabled"; 109 status = "disabled";
107 }; 110 };
108 111
109 i2c0: i2c@11000 { 112 i2c0: i2c@11000 {
110 compatible = "marvell,mv64xxx-i2c"; 113 compatible = "marvell,mv64xxx-i2c";
111 reg = <0x11000 0x20>; 114 reg = <0x11000 0x20>;
112 #address-cells = <1>; 115 #address-cells = <1>;
113 #size-cells = <0>; 116 #size-cells = <0>;
114 interrupts = <31>; 117 interrupts = <31>;
115 timeout-ms = <1000>; 118 timeout-ms = <1000>;
116 clocks = <&coreclk 0>; 119 clocks = <&coreclk 0>;
117 status = "disabled"; 120 status = "disabled";
118 }; 121 };
119 122
120 i2c1: i2c@11100 { 123 i2c1: i2c@11100 {
121 compatible = "marvell,mv64xxx-i2c"; 124 compatible = "marvell,mv64xxx-i2c";
122 reg = <0x11100 0x20>; 125 reg = <0x11100 0x20>;
123 #address-cells = <1>; 126 #address-cells = <1>;
124 #size-cells = <0>; 127 #size-cells = <0>;
125 interrupts = <32>; 128 interrupts = <32>;
126 timeout-ms = <1000>; 129 timeout-ms = <1000>;
127 clocks = <&coreclk 0>; 130 clocks = <&coreclk 0>;
128 status = "disabled"; 131 status = "disabled";
129 }; 132 };
130 133
131 rtc@10300 { 134 rtc@10300 {
132 compatible = "marvell,orion-rtc"; 135 compatible = "marvell,orion-rtc";
133 reg = <0x10300 0x20>; 136 reg = <0x10300 0x20>;
134 interrupts = <50>; 137 interrupts = <50>;
135 }; 138 };
136 139
137 mvsdio@d4000 { 140 mvsdio@d4000 {
138 compatible = "marvell,orion-sdio"; 141 compatible = "marvell,orion-sdio";
139 reg = <0xd4000 0x200>; 142 reg = <0xd4000 0x200>;
140 interrupts = <54>; 143 interrupts = <54>;
141 clocks = <&gateclk 17>; 144 clocks = <&gateclk 17>;
142 status = "disabled"; 145 status = "disabled";
143 }; 146 };
144
145 usb@50000 {
146 compatible = "marvell,orion-ehci";
147 reg = <0x50000 0x500>;
148 interrupts = <45>;
149 status = "disabled";
150 };
151
152 usb@51000 {
153 compatible = "marvell,orion-ehci";
154 reg = <0x51000 0x500>;
155 interrupts = <46>;
156 status = "disabled";
157 };
158 147
159 spi0: spi@10600 { 148 usb@50000 {
160 compatible = "marvell,orion-spi"; 149 compatible = "marvell,orion-ehci";
161 reg = <0x10600 0x28>; 150 reg = <0x50000 0x500>;
162 #address-cells = <1>; 151 interrupts = <45>;
163 #size-cells = <0>; 152 status = "disabled";
164 cell-index = <0>; 153 };
165 interrupts = <30>;
166 clocks = <&coreclk 0>;
167 status = "disabled";
168 };
169 154
170 spi1: spi@10680 { 155 usb@51000 {
171 compatible = "marvell,orion-spi"; 156 compatible = "marvell,orion-ehci";
172 reg = <0x10680 0x28>; 157 reg = <0x51000 0x500>;
173 #address-cells = <1>; 158 interrupts = <46>;
174 #size-cells = <0>; 159 status = "disabled";
175 cell-index = <1>; 160 };
176 interrupts = <92>; 161
177 clocks = <&coreclk 0>; 162 spi0: spi@10600 {
178 status = "disabled"; 163 compatible = "marvell,orion-spi";
179 }; 164 reg = <0x10600 0x28>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 cell-index = <0>;
168 interrupts = <30>;
169 clocks = <&coreclk 0>;
170 status = "disabled";
171 };
172
173 spi1: spi@10680 {
174 compatible = "marvell,orion-spi";
175 reg = <0x10680 0x28>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 cell-index = <1>;
179 interrupts = <92>;
180 clocks = <&coreclk 0>;
181 status = "disabled";
182 };
180 183
181 devbus-bootcs@10400 { 184 devbus-bootcs@10400 {
182 compatible = "marvell,mvebu-devbus"; 185 compatible = "marvell,mvebu-devbus";
183 reg = <0x10400 0x8>; 186 reg = <0x10400 0x8>;
184 #address-cells = <1>; 187 #address-cells = <1>;
185 #size-cells = <1>; 188 #size-cells = <1>;
186 clocks = <&coreclk 0>; 189 clocks = <&coreclk 0>;
187 status = "disabled"; 190 status = "disabled";
188 }; 191 };
189 192
190 devbus-cs0@10408 { 193 devbus-cs0@10408 {
191 compatible = "marvell,mvebu-devbus"; 194 compatible = "marvell,mvebu-devbus";
192 reg = <0x10408 0x8>; 195 reg = <0x10408 0x8>;
193 #address-cells = <1>; 196 #address-cells = <1>;
194 #size-cells = <1>; 197 #size-cells = <1>;
195 clocks = <&coreclk 0>; 198 clocks = <&coreclk 0>;
196 status = "disabled"; 199 status = "disabled";
197 }; 200 };
198 201
199 devbus-cs1@10410 { 202 devbus-cs1@10410 {
200 compatible = "marvell,mvebu-devbus"; 203 compatible = "marvell,mvebu-devbus";
201 reg = <0x10410 0x8>; 204 reg = <0x10410 0x8>;
202 #address-cells = <1>; 205 #address-cells = <1>;
203 #size-cells = <1>; 206 #size-cells = <1>;
204 clocks = <&coreclk 0>; 207 clocks = <&coreclk 0>;
205 status = "disabled"; 208 status = "disabled";
206 }; 209 };
207 210
208 devbus-cs2@10418 { 211 devbus-cs2@10418 {
209 compatible = "marvell,mvebu-devbus"; 212 compatible = "marvell,mvebu-devbus";
210 reg = <0x10418 0x8>; 213 reg = <0x10418 0x8>;
211 #address-cells = <1>; 214 #address-cells = <1>;
212 #size-cells = <1>; 215 #size-cells = <1>;
213 clocks = <&coreclk 0>; 216 clocks = <&coreclk 0>;
214 status = "disabled"; 217 status = "disabled";
215 }; 218 };
216 219
217 devbus-cs3@10420 { 220 devbus-cs3@10420 {
218 compatible = "marvell,mvebu-devbus"; 221 compatible = "marvell,mvebu-devbus";
219 reg = <0x10420 0x8>; 222 reg = <0x10420 0x8>;
220 #address-cells = <1>; 223 #address-cells = <1>;
221 #size-cells = <1>; 224 #size-cells = <1>;
222 clocks = <&coreclk 0>; 225 clocks = <&coreclk 0>;
223 status = "disabled"; 226 status = "disabled";
227 };
224 }; 228 };
225 }; 229 };
226}; 230 };
227
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 5c4fa655fc34..6ef95dd218ae 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -28,195 +28,195 @@
28 }; 28 };
29 29
30 soc { 30 soc {
31 31 internal-regs {
32 mpic: interrupt-controller@20000 { 32 system-controller@18200 {
33 reg = <0x20a00 0x1d0>,
34 <0x21870 0x58>;
35 };
36
37 system-controller@18200 {
38 compatible = "marvell,armada-370-xp-system-controller"; 33 compatible = "marvell,armada-370-xp-system-controller";
39 reg = <0x18200 0x100>; 34 reg = <0x18200 0x100>;
40 };
41
42 L2: l2-cache {
43 compatible = "marvell,aurora-outer-cache";
44 reg = <0xd0008000 0x1000>;
45 cache-id-part = <0x100>;
46 wt-override;
47 };
48
49 pinctrl {
50 compatible = "marvell,mv88f6710-pinctrl";
51 reg = <0x18000 0x38>;
52
53 sdio_pins1: sdio-pins1 {
54 marvell,pins = "mpp9", "mpp11", "mpp12",
55 "mpp13", "mpp14", "mpp15";
56 marvell,function = "sd0";
57 }; 35 };
58 36
59 sdio_pins2: sdio-pins2 { 37 L2: l2-cache {
60 marvell,pins = "mpp47", "mpp48", "mpp49", 38 compatible = "marvell,aurora-outer-cache";
61 "mpp50", "mpp51", "mpp52"; 39 reg = <0xd0008000 0x1000>;
62 marvell,function = "sd0"; 40 cache-id-part = <0x100>;
41 wt-override;
63 }; 42 };
64 43
65 sdio_pins3: sdio-pins3 { 44 mpic: interrupt-controller@20000 {
66 marvell,pins = "mpp48", "mpp49", "mpp50", 45 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
67 "mpp51", "mpp52", "mpp53";
68 marvell,function = "sd0";
69 }; 46 };
70 };
71
72 gpio0: gpio@18100 {
73 compatible = "marvell,orion-gpio";
74 reg = <0x18100 0x40>;
75 ngpios = <32>;
76 gpio-controller;
77 #gpio-cells = <2>;
78 interrupt-controller;
79 #interrupts-cells = <2>;
80 interrupts = <82>, <83>, <84>, <85>;
81 };
82
83 gpio1: gpio@18140 {
84 compatible = "marvell,orion-gpio";
85 reg = <0x18140 0x40>;
86 ngpios = <32>;
87 gpio-controller;
88 #gpio-cells = <2>;
89 interrupt-controller;
90 #interrupts-cells = <2>;
91 interrupts = <87>, <88>, <89>, <90>;
92 };
93 47
94 gpio2: gpio@18180 { 48 pinctrl {
95 compatible = "marvell,orion-gpio"; 49 compatible = "marvell,mv88f6710-pinctrl";
96 reg = <0x18180 0x40>; 50 reg = <0x18000 0x38>;
97 ngpios = <2>; 51
98 gpio-controller; 52 sdio_pins1: sdio-pins1 {
99 #gpio-cells = <2>; 53 marvell,pins = "mpp9", "mpp11", "mpp12",
100 interrupt-controller; 54 "mpp13", "mpp14", "mpp15";
101 #interrupts-cells = <2>; 55 marvell,function = "sd0";
102 interrupts = <91>; 56 };
103 }; 57
104 58 sdio_pins2: sdio-pins2 {
105 coreclk: mvebu-sar@18230 { 59 marvell,pins = "mpp47", "mpp48", "mpp49",
106 compatible = "marvell,armada-370-core-clock"; 60 "mpp50", "mpp51", "mpp52";
107 reg = <0x18230 0x08>; 61 marvell,function = "sd0";
108 #clock-cells = <1>; 62 };
109 }; 63
110 64 sdio_pins3: sdio-pins3 {
111 gateclk: clock-gating-control@18220 { 65 marvell,pins = "mpp48", "mpp49", "mpp50",
112 compatible = "marvell,armada-370-gating-clock"; 66 "mpp51", "mpp52", "mpp53";
113 reg = <0x18220 0x4>; 67 marvell,function = "sd0";
114 clocks = <&coreclk 0>; 68 };
115 #clock-cells = <1>;
116 };
117
118 xor@60800 {
119 compatible = "marvell,orion-xor";
120 reg = <0x60800 0x100
121 0x60A00 0x100>;
122 status = "okay";
123
124 xor00 {
125 interrupts = <51>;
126 dmacap,memcpy;
127 dmacap,xor;
128 };
129 xor01 {
130 interrupts = <52>;
131 dmacap,memcpy;
132 dmacap,xor;
133 dmacap,memset;
134 }; 69 };
135 };
136 70
137 xor@60900 { 71 gpio0: gpio@18100 {
138 compatible = "marvell,orion-xor"; 72 compatible = "marvell,orion-gpio";
139 reg = <0x60900 0x100 73 reg = <0x18100 0x40>;
140 0x60b00 0x100>; 74 ngpios = <32>;
141 status = "okay"; 75 gpio-controller;
142 76 #gpio-cells = <2>;
143 xor10 { 77 interrupt-controller;
144 interrupts = <94>; 78 #interrupts-cells = <2>;
145 dmacap,memcpy; 79 interrupts = <82>, <83>, <84>, <85>;
146 dmacap,xor;
147 };
148 xor11 {
149 interrupts = <95>;
150 dmacap,memcpy;
151 dmacap,xor;
152 dmacap,memset;
153 }; 80 };
154 };
155
156 usb@50000 {
157 clocks = <&coreclk 0>;
158 };
159 81
160 usb@51000 { 82 gpio1: gpio@18140 {
161 clocks = <&coreclk 0>; 83 compatible = "marvell,orion-gpio";
162 }; 84 reg = <0x18140 0x40>;
85 ngpios = <32>;
86 gpio-controller;
87 #gpio-cells = <2>;
88 interrupt-controller;
89 #interrupts-cells = <2>;
90 interrupts = <87>, <88>, <89>, <90>;
91 };
163 92
164 thermal@18300 { 93 gpio2: gpio@18180 {
165 compatible = "marvell,armada370-thermal"; 94 compatible = "marvell,orion-gpio";
166 reg = <0x18300 0x4 95 reg = <0x18180 0x40>;
167 0x18304 0x4>; 96 ngpios = <2>;
168 status = "okay"; 97 gpio-controller;
169 }; 98 #gpio-cells = <2>;
99 interrupt-controller;
100 #interrupts-cells = <2>;
101 interrupts = <91>;
102 };
170 103
171 pcie-controller { 104 coreclk: mvebu-sar@18230 {
172 compatible = "marvell,armada-370-pcie"; 105 compatible = "marvell,armada-370-core-clock";
173 status = "disabled"; 106 reg = <0x18230 0x08>;
174 device_type = "pci"; 107 #clock-cells = <1>;
108 };
175 109
176 #address-cells = <3>; 110 gateclk: clock-gating-control@18220 {
177 #size-cells = <2>; 111 compatible = "marvell,armada-370-gating-clock";
112 reg = <0x18220 0x4>;
113 clocks = <&coreclk 0>;
114 #clock-cells = <1>;
115 };
178 116
179 bus-range = <0x00 0xff>; 117 xor@60800 {
118 compatible = "marvell,orion-xor";
119 reg = <0x60800 0x100
120 0x60A00 0x100>;
121 status = "okay";
122
123 xor00 {
124 interrupts = <51>;
125 dmacap,memcpy;
126 dmacap,xor;
127 };
128 xor01 {
129 interrupts = <52>;
130 dmacap,memcpy;
131 dmacap,xor;
132 dmacap,memset;
133 };
134 };
180 135
181 reg = <0x40000 0x2000>, <0x80000 0x2000>; 136 xor@60900 {
137 compatible = "marvell,orion-xor";
138 reg = <0x60900 0x100
139 0x60b00 0x100>;
140 status = "okay";
141
142 xor10 {
143 interrupts = <94>;
144 dmacap,memcpy;
145 dmacap,xor;
146 };
147 xor11 {
148 interrupts = <95>;
149 dmacap,memcpy;
150 dmacap,xor;
151 dmacap,memset;
152 };
153 };
182 154
183 reg-names = "pcie0.0", "pcie1.0"; 155 usb@50000 {
156 clocks = <&coreclk 0>;
157 };
184 158
185 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ 159 usb@51000 {
186 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ 160 clocks = <&coreclk 0>;
187 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 161 };
188 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
189 162
190 pcie@1,0 { 163 thermal@18300 {
191 device_type = "pci"; 164 compatible = "marvell,armada370-thermal";
192 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 165 reg = <0x18300 0x4
193 reg = <0x0800 0 0 0 0>; 166 0x18304 0x4>;
194 #address-cells = <3>; 167 status = "okay";
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 58>;
200 marvell,pcie-port = <0>;
201 marvell,pcie-lane = <0>;
202 clocks = <&gateclk 5>;
203 status = "disabled";
204 }; 168 };
205 169
206 pcie@2,0 { 170 pcie-controller {
171 compatible = "marvell,armada-370-pcie";
172 status = "disabled";
207 device_type = "pci"; 173 device_type = "pci";
208 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 174
209 reg = <0x1000 0 0 0 0>;
210 #address-cells = <3>; 175 #address-cells = <3>;
211 #size-cells = <2>; 176 #size-cells = <2>;
212 #interrupt-cells = <1>; 177
213 ranges; 178 bus-range = <0x00 0xff>;
214 interrupt-map-mask = <0 0 0 0>; 179
215 interrupt-map = <0 0 0 0 &mpic 62>; 180 reg = <0x40000 0x2000>, <0x80000 0x2000>;
216 marvell,pcie-port = <1>; 181
217 marvell,pcie-lane = <0>; 182 reg-names = "pcie0.0", "pcie1.0";
218 clocks = <&gateclk 9>; 183
219 status = "disabled"; 184 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
185 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
186 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
187 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
188
189 pcie@1,0 {
190 device_type = "pci";
191 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
192 reg = <0x0800 0 0 0 0>;
193 #address-cells = <3>;
194 #size-cells = <2>;
195 #interrupt-cells = <1>;
196 ranges;
197 interrupt-map-mask = <0 0 0 0>;
198 interrupt-map = <0 0 0 0 &mpic 58>;
199 marvell,pcie-port = <0>;
200 marvell,pcie-lane = <0>;
201 clocks = <&gateclk 5>;
202 status = "disabled";
203 };
204
205 pcie@2,0 {
206 device_type = "pci";
207 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
208 reg = <0x1000 0 0 0 0>;
209 #address-cells = <3>;
210 #size-cells = <2>;
211 #interrupt-cells = <1>;
212 ranges;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &mpic 62>;
215 marvell,pcie-port = <1>;
216 marvell,pcie-lane = <0>;
217 clocks = <&gateclk 9>;
218 status = "disabled";
219 };
220 }; 220 };
221 }; 221 };
222 }; 222 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e37863f826b9..6c8b032ddbbb 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,128 +30,130 @@
30 }; 30 };
31 31
32 soc { 32 soc {
33 serial@12000 { 33 internal-regs {
34 clock-frequency = <250000000>; 34 serial@12000 {
35 status = "okay"; 35 clock-frequency = <250000000>;
36 }; 36 status = "okay";
37 serial@12100 {
38 clock-frequency = <250000000>;
39 status = "okay";
40 };
41 serial@12200 {
42 clock-frequency = <250000000>;
43 status = "okay";
44 };
45 serial@12300 {
46 clock-frequency = <250000000>;
47 status = "okay";
48 };
49
50 sata@a0000 {
51 nr-ports = <2>;
52 status = "okay";
53 };
54
55 mdio {
56 phy0: ethernet-phy@0 {
57 reg = <0>;
58 }; 37 };
59 38 serial@12100 {
60 phy1: ethernet-phy@1 { 39 clock-frequency = <250000000>;
61 reg = <1>; 40 status = "okay";
62 }; 41 };
63 42 serial@12200 {
64 phy2: ethernet-phy@2 { 43 clock-frequency = <250000000>;
65 reg = <25>; 44 status = "okay";
66 }; 45 };
67 46 serial@12300 {
68 phy3: ethernet-phy@3 { 47 clock-frequency = <250000000>;
69 reg = <27>; 48 status = "okay";
70 }; 49 };
71 };
72
73 ethernet@70000 {
74 status = "okay";
75 phy = <&phy0>;
76 phy-mode = "rgmii-id";
77 };
78 ethernet@74000 {
79 status = "okay";
80 phy = <&phy1>;
81 phy-mode = "rgmii-id";
82 };
83 ethernet@30000 {
84 status = "okay";
85 phy = <&phy2>;
86 phy-mode = "sgmii";
87 };
88 ethernet@34000 {
89 status = "okay";
90 phy = <&phy3>;
91 phy-mode = "sgmii";
92 };
93
94 mvsdio@d4000 {
95 pinctrl-0 = <&sdio_pins>;
96 pinctrl-names = "default";
97 status = "okay";
98 /* No CD or WP GPIOs */
99 };
100 50
101 usb@50000 { 51 sata@a0000 {
102 status = "okay"; 52 nr-ports = <2>;
103 }; 53 status = "okay";
54 };
104 55
105 usb@51000 { 56 mdio {
106 status = "okay"; 57 phy0: ethernet-phy@0 {
107 }; 58 reg = <0>;
59 };
108 60
109 usb@52000 { 61 phy1: ethernet-phy@1 {
110 status = "okay"; 62 reg = <1>;
111 }; 63 };
112 64
113 spi0: spi@10600 { 65 phy2: ethernet-phy@2 {
114 status = "okay"; 66 reg = <25>;
67 };
115 68
116 spi-flash@0 { 69 phy3: ethernet-phy@3 {
117 #address-cells = <1>; 70 reg = <27>;
118 #size-cells = <1>; 71 };
119 compatible = "m25p64";
120 reg = <0>; /* Chip select 0 */
121 spi-max-frequency = <20000000>;
122 }; 72 };
123 };
124 73
125 pcie-controller { 74 ethernet@70000 {
126 status = "okay"; 75 status = "okay";
76 phy = <&phy0>;
77 phy-mode = "rgmii-id";
78 };
79 ethernet@74000 {
80 status = "okay";
81 phy = <&phy1>;
82 phy-mode = "rgmii-id";
83 };
84 ethernet@30000 {
85 status = "okay";
86 phy = <&phy2>;
87 phy-mode = "sgmii";
88 };
89 ethernet@34000 {
90 status = "okay";
91 phy = <&phy3>;
92 phy-mode = "sgmii";
93 };
127 94
128 /* 95 mvsdio@d4000 {
129 * All 6 slots are physically present as 96 pinctrl-0 = <&sdio_pins>;
130 * standard PCIe slots on the board. 97 pinctrl-names = "default";
131 */
132 pcie@1,0 {
133 /* Port 0, Lane 0 */
134 status = "okay"; 98 status = "okay";
99 /* No CD or WP GPIOs */
135 }; 100 };
136 pcie@2,0 { 101
137 /* Port 0, Lane 1 */ 102 usb@50000 {
138 status = "okay"; 103 status = "okay";
139 }; 104 };
140 pcie@3,0 { 105
141 /* Port 0, Lane 2 */ 106 usb@51000 {
142 status = "okay"; 107 status = "okay";
143 }; 108 };
144 pcie@4,0 { 109
145 /* Port 0, Lane 3 */ 110 usb@52000 {
146 status = "okay"; 111 status = "okay";
147 }; 112 };
148 pcie@9,0 { 113
149 /* Port 2, Lane 0 */ 114 spi0: spi@10600 {
150 status = "okay"; 115 status = "okay";
116
117 spi-flash@0 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "m25p64";
121 reg = <0>; /* Chip select 0 */
122 spi-max-frequency = <20000000>;
123 };
151 }; 124 };
152 pcie@10,0 { 125
153 /* Port 3, Lane 0 */ 126 pcie-controller {
154 status = "okay"; 127 status = "okay";
128
129 /*
130 * All 6 slots are physically present as
131 * standard PCIe slots on the board.
132 */
133 pcie@1,0 {
134 /* Port 0, Lane 0 */
135 status = "okay";
136 };
137 pcie@2,0 {
138 /* Port 0, Lane 1 */
139 status = "okay";
140 };
141 pcie@3,0 {
142 /* Port 0, Lane 2 */
143 status = "okay";
144 };
145 pcie@4,0 {
146 /* Port 0, Lane 3 */
147 status = "okay";
148 };
149 pcie@9,0 {
150 /* Port 2, Lane 0 */
151 status = "okay";
152 };
153 pcie@10,0 {
154 /* Port 3, Lane 0 */
155 status = "okay";
156 };
155 }; 157 };
156 }; 158 };
157 }; 159 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 55bcbff39469..d9972c9a9279 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -37,126 +37,128 @@
37 }; 37 };
38 38
39 soc { 39 soc {
40 serial@12000 { 40 internal-regs {
41 clock-frequency = <250000000>; 41 serial@12000 {
42 status = "okay"; 42 clock-frequency = <250000000>;
43 }; 43 status = "okay";
44 serial@12100 {
45 clock-frequency = <250000000>;
46 status = "okay";
47 };
48 serial@12200 {
49 clock-frequency = <250000000>;
50 status = "okay";
51 };
52 serial@12300 {
53 clock-frequency = <250000000>;
54 status = "okay";
55 };
56
57 sata@a0000 {
58 nr-ports = <2>;
59 status = "okay";
60 };
61
62 mdio {
63 phy0: ethernet-phy@0 {
64 reg = <16>;
65 }; 44 };
66 45 serial@12100 {
67 phy1: ethernet-phy@1 { 46 clock-frequency = <250000000>;
68 reg = <17>; 47 status = "okay";
69 }; 48 };
70 49 serial@12200 {
71 phy2: ethernet-phy@2 { 50 clock-frequency = <250000000>;
72 reg = <18>; 51 status = "okay";
52 };
53 serial@12300 {
54 clock-frequency = <250000000>;
55 status = "okay";
73 }; 56 };
74 57
75 phy3: ethernet-phy@3 { 58 sata@a0000 {
76 reg = <19>; 59 nr-ports = <2>;
60 status = "okay";
77 }; 61 };
78 };
79 62
80 ethernet@70000 { 63 mdio {
81 status = "okay"; 64 phy0: ethernet-phy@0 {
82 phy = <&phy0>; 65 reg = <16>;
83 phy-mode = "rgmii-id"; 66 };
84 };
85 ethernet@74000 {
86 status = "okay";
87 phy = <&phy1>;
88 phy-mode = "rgmii-id";
89 };
90 ethernet@30000 {
91 status = "okay";
92 phy = <&phy2>;
93 phy-mode = "rgmii-id";
94 };
95 ethernet@34000 {
96 status = "okay";
97 phy = <&phy3>;
98 phy-mode = "rgmii-id";
99 };
100 67
101 spi0: spi@10600 { 68 phy1: ethernet-phy@1 {
102 status = "okay"; 69 reg = <17>;
70 };
103 71
104 spi-flash@0 { 72 phy2: ethernet-phy@2 {
105 #address-cells = <1>; 73 reg = <18>;
106 #size-cells = <1>; 74 };
107 compatible = "n25q128a13";
108 reg = <0>; /* Chip select 0 */
109 spi-max-frequency = <108000000>;
110 };
111 };
112 75
113 devbus-bootcs@10400 { 76 phy3: ethernet-phy@3 {
114 status = "okay"; 77 reg = <19>;
115 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ 78 };
116
117 /* Device Bus parameters are required */
118
119 /* Read parameters */
120 devbus,bus-width = <8>;
121 devbus,turn-off-ps = <60000>;
122 devbus,badr-skew-ps = <0>;
123 devbus,acc-first-ps = <124000>;
124 devbus,acc-next-ps = <248000>;
125 devbus,rd-setup-ps = <0>;
126 devbus,rd-hold-ps = <0>;
127
128 /* Write parameters */
129 devbus,sync-enable = <0>;
130 devbus,wr-high-ps = <60000>;
131 devbus,wr-low-ps = <60000>;
132 devbus,ale-wr-ps = <60000>;
133
134 /* NOR 16 MiB */
135 nor@0 {
136 compatible = "cfi-flash";
137 reg = <0 0x1000000>;
138 bank-width = <2>;
139 }; 79 };
140 };
141 80
142 pcie-controller { 81 ethernet@70000 {
143 status = "okay"; 82 status = "okay";
83 phy = <&phy0>;
84 phy-mode = "rgmii-id";
85 };
86 ethernet@74000 {
87 status = "okay";
88 phy = <&phy1>;
89 phy-mode = "rgmii-id";
90 };
91 ethernet@30000 {
92 status = "okay";
93 phy = <&phy2>;
94 phy-mode = "rgmii-id";
95 };
96 ethernet@34000 {
97 status = "okay";
98 phy = <&phy3>;
99 phy-mode = "rgmii-id";
100 };
144 101
145 /* 102 spi0: spi@10600 {
146 * The 3 slots are physically present as
147 * standard PCIe slots on the board.
148 */
149 pcie@1,0 {
150 /* Port 0, Lane 0 */
151 status = "okay"; 103 status = "okay";
104
105 spi-flash@0 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "n25q128a13";
109 reg = <0>; /* Chip select 0 */
110 spi-max-frequency = <108000000>;
111 };
152 }; 112 };
153 pcie@9,0 { 113
154 /* Port 2, Lane 0 */ 114 devbus-bootcs@10400 {
155 status = "okay"; 115 status = "okay";
116 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
117
118 /* Device Bus parameters are required */
119
120 /* Read parameters */
121 devbus,bus-width = <8>;
122 devbus,turn-off-ps = <60000>;
123 devbus,badr-skew-ps = <0>;
124 devbus,acc-first-ps = <124000>;
125 devbus,acc-next-ps = <248000>;
126 devbus,rd-setup-ps = <0>;
127 devbus,rd-hold-ps = <0>;
128
129 /* Write parameters */
130 devbus,sync-enable = <0>;
131 devbus,wr-high-ps = <60000>;
132 devbus,wr-low-ps = <60000>;
133 devbus,ale-wr-ps = <60000>;
134
135 /* NOR 16 MiB */
136 nor@0 {
137 compatible = "cfi-flash";
138 reg = <0 0x1000000>;
139 bank-width = <2>;
140 };
156 }; 141 };
157 pcie@10,0 { 142
158 /* Port 3, Lane 0 */ 143 pcie-controller {
159 status = "okay"; 144 status = "okay";
145
146 /*
147 * The 3 slots are physically present as
148 * standard PCIe slots on the board.
149 */
150 pcie@1,0 {
151 /* Port 0, Lane 0 */
152 status = "okay";
153 };
154 pcie@9,0 {
155 /* Port 2, Lane 0 */
156 status = "okay";
157 };
158 pcie@10,0 {
159 /* Port 3, Lane 0 */
160 status = "okay";
161 };
160 }; 162 };
161 }; 163 };
162 }; 164 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 12905abf4ca3..f8eaa383e07f 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -44,140 +44,142 @@
44 }; 44 };
45 45
46 soc { 46 soc {
47 pinctrl { 47 internal-regs {
48 compatible = "marvell,mv78230-pinctrl"; 48 pinctrl {
49 reg = <0x18000 0x38>; 49 compatible = "marvell,mv78230-pinctrl";
50 50 reg = <0x18000 0x38>;
51 sdio_pins: sdio-pins { 51
52 marvell,pins = "mpp30", "mpp31", "mpp32", 52 sdio_pins: sdio-pins {
53 "mpp33", "mpp34", "mpp35"; 53 marvell,pins = "mpp30", "mpp31", "mpp32",
54 marvell,function = "sd0"; 54 "mpp33", "mpp34", "mpp35";
55 marvell,function = "sd0";
56 };
55 }; 57 };
56 };
57
58 gpio0: gpio@18100 {
59 compatible = "marvell,orion-gpio";
60 reg = <0x18100 0x40>;
61 ngpios = <32>;
62 gpio-controller;
63 #gpio-cells = <2>;
64 interrupt-controller;
65 #interrupts-cells = <2>;
66 interrupts = <82>, <83>, <84>, <85>;
67 };
68
69 gpio1: gpio@18140 {
70 compatible = "marvell,orion-gpio";
71 reg = <0x18140 0x40>;
72 ngpios = <17>;
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupts-cells = <2>;
77 interrupts = <87>, <88>, <89>;
78 };
79 58
80 /* 59 gpio0: gpio@18100 {
81 * MV78230 has 2 PCIe units Gen2.0: One unit can be 60 compatible = "marvell,orion-gpio";
82 * configured as x4 or quad x1 lanes. One unit is 61 reg = <0x18100 0x40>;
83 * x4/x1. 62 ngpios = <32>;
84 */ 63 gpio-controller;
85 pcie-controller { 64 #gpio-cells = <2>;
86 compatible = "marvell,armada-xp-pcie"; 65 interrupt-controller;
87 status = "disabled"; 66 #interrupts-cells = <2>;
88 device_type = "pci"; 67 interrupts = <82>, <83>, <84>, <85>;
89
90 #address-cells = <3>;
91 #size-cells = <2>;
92
93 bus-range = <0x00 0xff>;
94
95 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
96 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
97 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
98 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
99 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
100 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
101 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
102
103 pcie@1,0 {
104 device_type = "pci";
105 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
106 reg = <0x0800 0 0 0 0>;
107 #address-cells = <3>;
108 #size-cells = <2>;
109 #interrupt-cells = <1>;
110 ranges;
111 interrupt-map-mask = <0 0 0 0>;
112 interrupt-map = <0 0 0 0 &mpic 58>;
113 marvell,pcie-port = <0>;
114 marvell,pcie-lane = <0>;
115 clocks = <&gateclk 5>;
116 status = "disabled";
117 }; 68 };
118 69
119 pcie@2,0 { 70 gpio1: gpio@18140 {
120 device_type = "pci"; 71 compatible = "marvell,orion-gpio";
121 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 72 reg = <0x18140 0x40>;
122 reg = <0x1000 0 0 0 0>; 73 ngpios = <17>;
123 #address-cells = <3>; 74 gpio-controller;
124 #size-cells = <2>; 75 #gpio-cells = <2>;
125 #interrupt-cells = <1>; 76 interrupt-controller;
126 ranges; 77 #interrupts-cells = <2>;
127 interrupt-map-mask = <0 0 0 0>; 78 interrupts = <87>, <88>, <89>;
128 interrupt-map = <0 0 0 0 &mpic 59>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <1>;
131 clocks = <&gateclk 6>;
132 status = "disabled";
133 }; 79 };
134 80
135 pcie@3,0 { 81 /*
136 device_type = "pci"; 82 * MV78230 has 2 PCIe units Gen2.0: One unit can be
137 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 83 * configured as x4 or quad x1 lanes. One unit is
138 reg = <0x1800 0 0 0 0>; 84 * x4/x1.
139 #address-cells = <3>; 85 */
140 #size-cells = <2>; 86 pcie-controller {
141 #interrupt-cells = <1>; 87 compatible = "marvell,armada-xp-pcie";
142 ranges;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &mpic 60>;
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <2>;
147 clocks = <&gateclk 7>;
148 status = "disabled"; 88 status = "disabled";
149 };
150
151 pcie@4,0 {
152 device_type = "pci"; 89 device_type = "pci";
153 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
154 reg = <0x2000 0 0 0 0>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 #interrupt-cells = <1>;
158 ranges;
159 interrupt-map-mask = <0 0 0 0>;
160 interrupt-map = <0 0 0 0 &mpic 61>;
161 marvell,pcie-port = <0>;
162 marvell,pcie-lane = <3>;
163 clocks = <&gateclk 8>;
164 status = "disabled";
165 };
166 90
167 pcie@9,0 { 91#address-cells = <3>;
168 device_type = "pci"; 92#size-cells = <2>;
169 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 93
170 reg = <0x4800 0 0 0 0>; 94 bus-range = <0x00 0xff>;
171 #address-cells = <3>; 95
172 #size-cells = <2>; 96 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
173 #interrupt-cells = <1>; 97 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
174 ranges; 98 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
175 interrupt-map-mask = <0 0 0 0>; 99 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
176 interrupt-map = <0 0 0 0 &mpic 99>; 100 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
177 marvell,pcie-port = <2>; 101 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
178 marvell,pcie-lane = <0>; 102 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
179 clocks = <&gateclk 26>; 103
180 status = "disabled"; 104 pcie@1,0 {
105 device_type = "pci";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 #address-cells = <3>;
109 #size-cells = <2>;
110 #interrupt-cells = <1>;
111 ranges;
112 interrupt-map-mask = <0 0 0 0>;
113 interrupt-map = <0 0 0 0 &mpic 58>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 5>;
117 status = "disabled";
118 };
119
120 pcie@2,0 {
121 device_type = "pci";
122 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
123 reg = <0x1000 0 0 0 0>;
124 #address-cells = <3>;
125 #size-cells = <2>;
126 #interrupt-cells = <1>;
127 ranges;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &mpic 59>;
130 marvell,pcie-port = <0>;
131 marvell,pcie-lane = <1>;
132 clocks = <&gateclk 6>;
133 status = "disabled";
134 };
135
136 pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 ranges;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 60>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <2>;
148 clocks = <&gateclk 7>;
149 status = "disabled";
150 };
151
152 pcie@4,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 61>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <3>;
164 clocks = <&gateclk 8>;
165 status = "disabled";
166 };
167
168 pcie@9,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171 reg = <0x4800 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 99>;
178 marvell,pcie-port = <2>;
179 marvell,pcie-lane = <0>;
180 clocks = <&gateclk 26>;
181 status = "disabled";
182 };
181 }; 183 };
182 }; 184 };
183 }; 185 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 1faacd13d514..f4029f015aff 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -45,177 +45,179 @@
45 }; 45 };
46 46
47 soc { 47 soc {
48 pinctrl { 48 internal-regs {
49 compatible = "marvell,mv78260-pinctrl"; 49 pinctrl {
50 reg = <0x18000 0x38>; 50 compatible = "marvell,mv78260-pinctrl";
51 51 reg = <0x18000 0x38>;
52 sdio_pins: sdio-pins { 52
53 marvell,pins = "mpp30", "mpp31", "mpp32", 53 sdio_pins: sdio-pins {
54 "mpp33", "mpp34", "mpp35"; 54 marvell,pins = "mpp30", "mpp31", "mpp32",
55 marvell,function = "sd0"; 55 "mpp33", "mpp34", "mpp35";
56 marvell,function = "sd0";
57 };
56 }; 58 };
57 };
58 59
59 gpio0: gpio@18100 { 60 gpio0: gpio@18100 {
60 compatible = "marvell,orion-gpio"; 61 compatible = "marvell,orion-gpio";
61 reg = <0x18100 0x40>; 62 reg = <0x18100 0x40>;
62 ngpios = <32>; 63 ngpios = <32>;
63 gpio-controller; 64 gpio-controller;
64 #gpio-cells = <2>; 65 #gpio-cells = <2>;
65 interrupt-controller; 66 interrupt-controller;
66 #interrupts-cells = <2>; 67 #interrupts-cells = <2>;
67 interrupts = <82>, <83>, <84>, <85>; 68 interrupts = <82>, <83>, <84>, <85>;
68 }; 69 };
69 70
70 gpio1: gpio@18140 { 71 gpio1: gpio@18140 {
71 compatible = "marvell,orion-gpio"; 72 compatible = "marvell,orion-gpio";
72 reg = <0x18140 0x40>; 73 reg = <0x18140 0x40>;
73 ngpios = <32>; 74 ngpios = <32>;
74 gpio-controller; 75 gpio-controller;
75 #gpio-cells = <2>; 76 #gpio-cells = <2>;
76 interrupt-controller; 77 interrupt-controller;
77 #interrupts-cells = <2>; 78 #interrupts-cells = <2>;
78 interrupts = <87>, <88>, <89>, <90>; 79 interrupts = <87>, <88>, <89>, <90>;
79 }; 80 };
80 81
81 gpio2: gpio@18180 { 82 gpio2: gpio@18180 {
82 compatible = "marvell,orion-gpio"; 83 compatible = "marvell,orion-gpio";
83 reg = <0x18180 0x40>; 84 reg = <0x18180 0x40>;
84 ngpios = <3>; 85 ngpios = <3>;
85 gpio-controller; 86 gpio-controller;
86 #gpio-cells = <2>; 87 #gpio-cells = <2>;
87 interrupt-controller; 88 interrupt-controller;
88 #interrupts-cells = <2>; 89 #interrupts-cells = <2>;
89 interrupts = <91>; 90 interrupts = <91>;
90 }; 91 };
91 92
92 ethernet@34000 { 93 ethernet@34000 {
93 compatible = "marvell,armada-370-neta"; 94 compatible = "marvell,armada-370-neta";
94 reg = <0x34000 0x2500>; 95 reg = <0x34000 0x2500>;
95 interrupts = <14>; 96 interrupts = <14>;
96 clocks = <&gateclk 1>; 97 clocks = <&gateclk 1>;
97 status = "disabled"; 98 status = "disabled";
98 };
99
100 /*
101 * MV78260 has 3 PCIe units Gen2.0: Two units can be
102 * configured as x4 or quad x1 lanes. One unit is
103 * x4/x1.
104 */
105 pcie-controller {
106 compatible = "marvell,armada-xp-pcie";
107 status = "disabled";
108 device_type = "pci";
109
110 #address-cells = <3>;
111 #size-cells = <2>;
112
113 bus-range = <0x00 0xff>;
114
115 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
116 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
117 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
118 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
119 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
120 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
121 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
122 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
123 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
124
125 pcie@1,0 {
126 device_type = "pci";
127 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
128 reg = <0x0800 0 0 0 0>;
129 #address-cells = <3>;
130 #size-cells = <2>;
131 #interrupt-cells = <1>;
132 ranges;
133 interrupt-map-mask = <0 0 0 0>;
134 interrupt-map = <0 0 0 0 &mpic 58>;
135 marvell,pcie-port = <0>;
136 marvell,pcie-lane = <0>;
137 clocks = <&gateclk 5>;
138 status = "disabled";
139 }; 99 };
140 100
141 pcie@2,0 { 101 /*
142 device_type = "pci"; 102 * MV78260 has 3 PCIe units Gen2.0: Two units can be
143 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 103 * configured as x4 or quad x1 lanes. One unit is
144 reg = <0x1000 0 0 0 0>; 104 * x4/x1.
145 #address-cells = <3>; 105 */
146 #size-cells = <2>; 106 pcie-controller {
147 #interrupt-cells = <1>; 107 compatible = "marvell,armada-xp-pcie";
148 ranges;
149 interrupt-map-mask = <0 0 0 0>;
150 interrupt-map = <0 0 0 0 &mpic 59>;
151 marvell,pcie-port = <0>;
152 marvell,pcie-lane = <1>;
153 clocks = <&gateclk 6>;
154 status = "disabled"; 108 status = "disabled";
155 };
156
157 pcie@3,0 {
158 device_type = "pci"; 109 device_type = "pci";
159 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
160 reg = <0x1800 0 0 0 0>;
161 #address-cells = <3>;
162 #size-cells = <2>;
163 #interrupt-cells = <1>;
164 ranges;
165 interrupt-map-mask = <0 0 0 0>;
166 interrupt-map = <0 0 0 0 &mpic 60>;
167 marvell,pcie-port = <0>;
168 marvell,pcie-lane = <2>;
169 clocks = <&gateclk 7>;
170 status = "disabled";
171 };
172 110
173 pcie@4,0 {
174 device_type = "pci";
175 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
176 reg = <0x2000 0 0 0 0>;
177 #address-cells = <3>; 111 #address-cells = <3>;
178 #size-cells = <2>; 112 #size-cells = <2>;
179 #interrupt-cells = <1>;
180 ranges;
181 interrupt-map-mask = <0 0 0 0>;
182 interrupt-map = <0 0 0 0 &mpic 61>;
183 marvell,pcie-port = <0>;
184 marvell,pcie-lane = <3>;
185 clocks = <&gateclk 8>;
186 status = "disabled";
187 };
188 113
189 pcie@9,0 { 114 bus-range = <0x00 0xff>;
190 device_type = "pci"; 115
191 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 116 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
192 reg = <0x4800 0 0 0 0>; 117 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
193 #address-cells = <3>; 118 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
194 #size-cells = <2>; 119 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
195 #interrupt-cells = <1>; 120 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
196 ranges; 121 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
197 interrupt-map-mask = <0 0 0 0>; 122 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
198 interrupt-map = <0 0 0 0 &mpic 99>; 123 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
199 marvell,pcie-port = <2>; 124 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
200 marvell,pcie-lane = <0>; 125
201 clocks = <&gateclk 26>; 126 pcie@1,0 {
202 status = "disabled"; 127 device_type = "pci";
203 }; 128 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
204 129 reg = <0x0800 0 0 0 0>;
205 pcie@10,0 { 130 #address-cells = <3>;
206 device_type = "pci"; 131 #size-cells = <2>;
207 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; 132 #interrupt-cells = <1>;
208 reg = <0x5000 0 0 0 0>; 133 ranges;
209 #address-cells = <3>; 134 interrupt-map-mask = <0 0 0 0>;
210 #size-cells = <2>; 135 interrupt-map = <0 0 0 0 &mpic 58>;
211 #interrupt-cells = <1>; 136 marvell,pcie-port = <0>;
212 ranges; 137 marvell,pcie-lane = <0>;
213 interrupt-map-mask = <0 0 0 0>; 138 clocks = <&gateclk 5>;
214 interrupt-map = <0 0 0 0 &mpic 103>; 139 status = "disabled";
215 marvell,pcie-port = <3>; 140 };
216 marvell,pcie-lane = <0>; 141
217 clocks = <&gateclk 27>; 142 pcie@2,0 {
218 status = "disabled"; 143 device_type = "pci";
144 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
145 reg = <0x1000 0 0 0 0>;
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 ranges;
150 interrupt-map-mask = <0 0 0 0>;
151 interrupt-map = <0 0 0 0 &mpic 59>;
152 marvell,pcie-port = <0>;
153 marvell,pcie-lane = <1>;
154 clocks = <&gateclk 6>;
155 status = "disabled";
156 };
157
158 pcie@3,0 {
159 device_type = "pci";
160 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
161 reg = <0x1800 0 0 0 0>;
162 #address-cells = <3>;
163 #size-cells = <2>;
164 #interrupt-cells = <1>;
165 ranges;
166 interrupt-map-mask = <0 0 0 0>;
167 interrupt-map = <0 0 0 0 &mpic 60>;
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
170 clocks = <&gateclk 7>;
171 status = "disabled";
172 };
173
174 pcie@4,0 {
175 device_type = "pci";
176 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
177 reg = <0x2000 0 0 0 0>;
178 #address-cells = <3>;
179 #size-cells = <2>;
180 #interrupt-cells = <1>;
181 ranges;
182 interrupt-map-mask = <0 0 0 0>;
183 interrupt-map = <0 0 0 0 &mpic 61>;
184 marvell,pcie-port = <0>;
185 marvell,pcie-lane = <3>;
186 clocks = <&gateclk 8>;
187 status = "disabled";
188 };
189
190 pcie@9,0 {
191 device_type = "pci";
192 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
193 reg = <0x4800 0 0 0 0>;
194 #address-cells = <3>;
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 99>;
200 marvell,pcie-port = <2>;
201 marvell,pcie-lane = <0>;
202 clocks = <&gateclk 26>;
203 status = "disabled";
204 };
205
206 pcie@10,0 {
207 device_type = "pci";
208 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
209 reg = <0x5000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 #interrupt-cells = <1>;
213 ranges;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 103>;
216 marvell,pcie-port = <3>;
217 marvell,pcie-lane = <0>;
218 clocks = <&gateclk 27>;
219 status = "disabled";
220 };
219 }; 221 };
220 }; 222 };
221 }; 223 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index ce4f80a82854..6ab56bd35de9 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -60,243 +60,245 @@
60 }; 60 };
61 61
62 soc { 62 soc {
63 pinctrl { 63 internal-regs {
64 compatible = "marvell,mv78460-pinctrl"; 64 pinctrl {
65 reg = <0x18000 0x38>; 65 compatible = "marvell,mv78460-pinctrl";
66 reg = <0x18000 0x38>;
66 67
67 sdio_pins: sdio-pins { 68 sdio_pins: sdio-pins {
68 marvell,pins = "mpp30", "mpp31", "mpp32", 69 marvell,pins = "mpp30", "mpp31", "mpp32",
69 "mpp33", "mpp34", "mpp35"; 70 "mpp33", "mpp34", "mpp35";
70 marvell,function = "sd0"; 71 marvell,function = "sd0";
72 };
71 }; 73 };
72 };
73 74
74 gpio0: gpio@18100 { 75 gpio0: gpio@18100 {
75 compatible = "marvell,orion-gpio"; 76 compatible = "marvell,orion-gpio";
76 reg = <0x18100 0x40>; 77 reg = <0x18100 0x40>;
77 ngpios = <32>; 78 ngpios = <32>;
78 gpio-controller; 79 gpio-controller;
79 #gpio-cells = <2>; 80 #gpio-cells = <2>;
80 interrupt-controller; 81 interrupt-controller;
81 #interrupts-cells = <2>; 82 #interrupts-cells = <2>;
82 interrupts = <82>, <83>, <84>, <85>; 83 interrupts = <82>, <83>, <84>, <85>;
83 }; 84 };
84 85
85 gpio1: gpio@18140 { 86 gpio1: gpio@18140 {
86 compatible = "marvell,orion-gpio"; 87 compatible = "marvell,orion-gpio";
87 reg = <0x18140 0x40>; 88 reg = <0x18140 0x40>;
88 ngpios = <32>; 89 ngpios = <32>;
89 gpio-controller; 90 gpio-controller;
90 #gpio-cells = <2>; 91 #gpio-cells = <2>;
91 interrupt-controller; 92 interrupt-controller;
92 #interrupts-cells = <2>; 93 #interrupts-cells = <2>;
93 interrupts = <87>, <88>, <89>, <90>; 94 interrupts = <87>, <88>, <89>, <90>;
94 }; 95 };
95 96
96 gpio2: gpio@18180 { 97 gpio2: gpio@18180 {
97 compatible = "marvell,orion-gpio"; 98 compatible = "marvell,orion-gpio";
98 reg = <0x18180 0x40>; 99 reg = <0x18180 0x40>;
99 ngpios = <3>; 100 ngpios = <3>;
100 gpio-controller; 101 gpio-controller;
101 #gpio-cells = <2>; 102 #gpio-cells = <2>;
102 interrupt-controller; 103 interrupt-controller;
103 #interrupts-cells = <2>; 104 #interrupts-cells = <2>;
104 interrupts = <91>; 105 interrupts = <91>;
105 }; 106 };
106 107
107 ethernet@34000 { 108 ethernet@34000 {
108 compatible = "marvell,armada-370-neta"; 109 compatible = "marvell,armada-370-neta";
109 reg = <0x34000 0x2500>; 110 reg = <0x34000 0x2500>;
110 interrupts = <14>; 111 interrupts = <14>;
111 clocks = <&gateclk 1>; 112 clocks = <&gateclk 1>;
112 status = "disabled"; 113 status = "disabled";
113 }; 114 };
114 115
115 /* 116 /*
116 * MV78460 has 4 PCIe units Gen2.0: Two units can be 117 * MV78460 has 4 PCIe units Gen2.0: Two units can be
117 * configured as x4 or quad x1 lanes. Two units are 118 * configured as x4 or quad x1 lanes. Two units are
118 * x4/x1. 119 * x4/x1.
119 */ 120 */
120 pcie-controller { 121 pcie-controller {
121 compatible = "marvell,armada-xp-pcie"; 122 compatible = "marvell,armada-xp-pcie";
122 status = "disabled"; 123 status = "disabled";
123 device_type = "pci"; 124 device_type = "pci";
124 125
125 #address-cells = <3>; 126 #address-cells = <3>;
126 #size-cells = <2>; 127 #size-cells = <2>;
127 128
128 bus-range = <0x00 0xff>; 129 bus-range = <0x00 0xff>;
129 130
130 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ 131 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
131 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ 132 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
132 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ 133 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
133 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ 134 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
134 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ 135 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
135 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ 136 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
136 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ 137 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
137 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */ 138 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
138 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */ 139 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
139 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */ 140 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
140 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 141 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
141 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ 142 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
142 143
143 pcie@1,0 { 144 pcie@1,0 {
144 device_type = "pci"; 145 device_type = "pci";
145 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 146 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
146 reg = <0x0800 0 0 0 0>; 147 reg = <0x0800 0 0 0 0>;
147 #address-cells = <3>; 148 #address-cells = <3>;
148 #size-cells = <2>; 149 #size-cells = <2>;
149 #interrupt-cells = <1>; 150 #interrupt-cells = <1>;
150 ranges; 151 ranges;
151 interrupt-map-mask = <0 0 0 0>; 152 interrupt-map-mask = <0 0 0 0>;
152 interrupt-map = <0 0 0 0 &mpic 58>; 153 interrupt-map = <0 0 0 0 &mpic 58>;
153 marvell,pcie-port = <0>; 154 marvell,pcie-port = <0>;
154 marvell,pcie-lane = <0>; 155 marvell,pcie-lane = <0>;
155 clocks = <&gateclk 5>; 156 clocks = <&gateclk 5>;
156 status = "disabled"; 157 status = "disabled";
157 }; 158 };
158 159
159 pcie@2,0 { 160 pcie@2,0 {
160 device_type = "pci"; 161 device_type = "pci";
161 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 162 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
162 reg = <0x1000 0 0 0 0>; 163 reg = <0x1000 0 0 0 0>;
163 #address-cells = <3>; 164 #address-cells = <3>;
164 #size-cells = <2>; 165 #size-cells = <2>;
165 #interrupt-cells = <1>; 166 #interrupt-cells = <1>;
166 ranges; 167 ranges;
167 interrupt-map-mask = <0 0 0 0>; 168 interrupt-map-mask = <0 0 0 0>;
168 interrupt-map = <0 0 0 0 &mpic 59>; 169 interrupt-map = <0 0 0 0 &mpic 59>;
169 marvell,pcie-port = <0>; 170 marvell,pcie-port = <0>;
170 marvell,pcie-lane = <1>; 171 marvell,pcie-lane = <1>;
171 clocks = <&gateclk 6>; 172 clocks = <&gateclk 6>;
172 status = "disabled"; 173 status = "disabled";
173 }; 174 };
174 175
175 pcie@3,0 { 176 pcie@3,0 {
176 device_type = "pci"; 177 device_type = "pci";
177 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 178 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
178 reg = <0x1800 0 0 0 0>; 179 reg = <0x1800 0 0 0 0>;
179 #address-cells = <3>; 180 #address-cells = <3>;
180 #size-cells = <2>; 181 #size-cells = <2>;
181 #interrupt-cells = <1>; 182 #interrupt-cells = <1>;
182 ranges; 183 ranges;
183 interrupt-map-mask = <0 0 0 0>; 184 interrupt-map-mask = <0 0 0 0>;
184 interrupt-map = <0 0 0 0 &mpic 60>; 185 interrupt-map = <0 0 0 0 &mpic 60>;
185 marvell,pcie-port = <0>; 186 marvell,pcie-port = <0>;
186 marvell,pcie-lane = <2>; 187 marvell,pcie-lane = <2>;
187 clocks = <&gateclk 7>; 188 clocks = <&gateclk 7>;
188 status = "disabled"; 189 status = "disabled";
189 }; 190 };
190 191
191 pcie@4,0 { 192 pcie@4,0 {
192 device_type = "pci"; 193 device_type = "pci";
193 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 194 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
194 reg = <0x2000 0 0 0 0>; 195 reg = <0x2000 0 0 0 0>;
195 #address-cells = <3>; 196 #address-cells = <3>;
196 #size-cells = <2>; 197 #size-cells = <2>;
197 #interrupt-cells = <1>; 198 #interrupt-cells = <1>;
198 ranges; 199 ranges;
199 interrupt-map-mask = <0 0 0 0>; 200 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 61>; 201 interrupt-map = <0 0 0 0 &mpic 61>;
201 marvell,pcie-port = <0>; 202 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <3>; 203 marvell,pcie-lane = <3>;
203 clocks = <&gateclk 8>; 204 clocks = <&gateclk 8>;
204 status = "disabled"; 205 status = "disabled";
205 }; 206 };
206 207
207 pcie@5,0 { 208 pcie@5,0 {
208 device_type = "pci"; 209 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 210 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x2800 0 0 0 0>; 211 reg = <0x2800 0 0 0 0>;
211 #address-cells = <3>; 212 #address-cells = <3>;
212 #size-cells = <2>; 213 #size-cells = <2>;
213 #interrupt-cells = <1>; 214 #interrupt-cells = <1>;
214 ranges; 215 ranges;
215 interrupt-map-mask = <0 0 0 0>; 216 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>; 217 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>; 218 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>; 219 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>; 220 clocks = <&gateclk 9>;
220 status = "disabled"; 221 status = "disabled";
221 }; 222 };
222 223
223 pcie@6,0 { 224 pcie@6,0 {
224 device_type = "pci"; 225 device_type = "pci";
225 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 226 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
226 reg = <0x3000 0 0 0 0>; 227 reg = <0x3000 0 0 0 0>;
227 #address-cells = <3>; 228 #address-cells = <3>;
228 #size-cells = <2>; 229 #size-cells = <2>;
229 #interrupt-cells = <1>; 230 #interrupt-cells = <1>;
230 ranges; 231 ranges;
231 interrupt-map-mask = <0 0 0 0>; 232 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 63>; 233 interrupt-map = <0 0 0 0 &mpic 63>;
233 marvell,pcie-port = <1>; 234 marvell,pcie-port = <1>;
234 marvell,pcie-lane = <1>; 235 marvell,pcie-lane = <1>;
235 clocks = <&gateclk 10>; 236 clocks = <&gateclk 10>;
236 status = "disabled"; 237 status = "disabled";
237 }; 238 };
238 239
239 pcie@7,0 { 240 pcie@7,0 {
240 device_type = "pci"; 241 device_type = "pci";
241 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; 242 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
242 reg = <0x3800 0 0 0 0>; 243 reg = <0x3800 0 0 0 0>;
243 #address-cells = <3>; 244 #address-cells = <3>;
244 #size-cells = <2>; 245 #size-cells = <2>;
245 #interrupt-cells = <1>; 246 #interrupt-cells = <1>;
246 ranges; 247 ranges;
247 interrupt-map-mask = <0 0 0 0>; 248 interrupt-map-mask = <0 0 0 0>;
248 interrupt-map = <0 0 0 0 &mpic 64>; 249 interrupt-map = <0 0 0 0 &mpic 64>;
249 marvell,pcie-port = <1>; 250 marvell,pcie-port = <1>;
250 marvell,pcie-lane = <2>; 251 marvell,pcie-lane = <2>;
251 clocks = <&gateclk 11>; 252 clocks = <&gateclk 11>;
252 status = "disabled"; 253 status = "disabled";
253 }; 254 };
254 255
255 pcie@8,0 { 256 pcie@8,0 {
256 device_type = "pci"; 257 device_type = "pci";
257 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; 258 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
258 reg = <0x4000 0 0 0 0>; 259 reg = <0x4000 0 0 0 0>;
259 #address-cells = <3>; 260 #address-cells = <3>;
260 #size-cells = <2>; 261 #size-cells = <2>;
261 #interrupt-cells = <1>; 262 #interrupt-cells = <1>;
262 ranges; 263 ranges;
263 interrupt-map-mask = <0 0 0 0>; 264 interrupt-map-mask = <0 0 0 0>;
264 interrupt-map = <0 0 0 0 &mpic 65>; 265 interrupt-map = <0 0 0 0 &mpic 65>;
265 marvell,pcie-port = <1>; 266 marvell,pcie-port = <1>;
266 marvell,pcie-lane = <3>; 267 marvell,pcie-lane = <3>;
267 clocks = <&gateclk 12>; 268 clocks = <&gateclk 12>;
268 status = "disabled"; 269 status = "disabled";
269 }; 270 };
270 pcie@9,0 { 271 pcie@9,0 {
271 device_type = "pci"; 272 device_type = "pci";
272 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; 273 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
273 reg = <0x4800 0 0 0 0>; 274 reg = <0x4800 0 0 0 0>;
274 #address-cells = <3>; 275 #address-cells = <3>;
275 #size-cells = <2>; 276 #size-cells = <2>;
276 #interrupt-cells = <1>; 277 #interrupt-cells = <1>;
277 ranges; 278 ranges;
278 interrupt-map-mask = <0 0 0 0>; 279 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map = <0 0 0 0 &mpic 99>; 280 interrupt-map = <0 0 0 0 &mpic 99>;
280 marvell,pcie-port = <2>; 281 marvell,pcie-port = <2>;
281 marvell,pcie-lane = <0>; 282 marvell,pcie-lane = <0>;
282 clocks = <&gateclk 26>; 283 clocks = <&gateclk 26>;
283 status = "disabled"; 284 status = "disabled";
284 }; 285 };
285 286
286 pcie@10,0 { 287 pcie@10,0 {
287 device_type = "pci"; 288 device_type = "pci";
288 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; 289 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
289 reg = <0x5000 0 0 0 0>; 290 reg = <0x5000 0 0 0 0>;
290 #address-cells = <3>; 291 #address-cells = <3>;
291 #size-cells = <2>; 292 #size-cells = <2>;
292 #interrupt-cells = <1>; 293 #interrupt-cells = <1>;
293 ranges; 294 ranges;
294 interrupt-map-mask = <0 0 0 0>; 295 interrupt-map-mask = <0 0 0 0>;
295 interrupt-map = <0 0 0 0 &mpic 103>; 296 interrupt-map = <0 0 0 0 &mpic 103>;
296 marvell,pcie-port = <3>; 297 marvell,pcie-port = <3>;
297 marvell,pcie-lane = <0>; 298 marvell,pcie-lane = <0>;
298 clocks = <&gateclk 27>; 299 clocks = <&gateclk 27>;
299 status = "disabled"; 300 status = "disabled";
301 };
300 }; 302 };
301 }; 303 };
302 }; 304 };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index e9bc8bf90263..15a66a8bb238 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,154 +27,156 @@
27 }; 27 };
28 28
29 soc { 29 soc {
30 serial@12000 { 30 internal-regs {
31 clock-frequency = <250000000>; 31 serial@12000 {
32 status = "okay"; 32 clock-frequency = <250000000>;
33 }; 33 status = "okay";
34 serial@12100 {
35 clock-frequency = <250000000>;
36 status = "okay";
37 };
38 pinctrl {
39 led_pins: led-pins-0 {
40 marvell,pins = "mpp49", "mpp51", "mpp53";
41 marvell,function = "gpio";
42 }; 34 };
43 }; 35 serial@12100 {
44 leds { 36 clock-frequency = <250000000>;
45 compatible = "gpio-leds"; 37 status = "okay";
46 pinctrl-names = "default";
47 pinctrl-0 = <&led_pins>;
48
49 red_led {
50 label = "red_led";
51 gpios = <&gpio1 17 1>;
52 default-state = "off";
53 }; 38 };
54 39 pinctrl {
55 yellow_led { 40 led_pins: led-pins-0 {
56 label = "yellow_led"; 41 marvell,pins = "mpp49", "mpp51", "mpp53";
57 gpios = <&gpio1 19 1>; 42 marvell,function = "gpio";
58 default-state = "off"; 43 };
59 }; 44 };
60 45 leds {
61 green_led { 46 compatible = "gpio-leds";
62 label = "green_led"; 47 pinctrl-names = "default";
63 gpios = <&gpio1 21 1>; 48 pinctrl-0 = <&led_pins>;
64 default-state = "off"; 49
65 linux,default-trigger = "heartbeat"; 50 red_led {
51 label = "red_led";
52 gpios = <&gpio1 17 1>;
53 default-state = "off";
54 };
55
56 yellow_led {
57 label = "yellow_led";
58 gpios = <&gpio1 19 1>;
59 default-state = "off";
60 };
61
62 green_led {
63 label = "green_led";
64 gpios = <&gpio1 21 1>;
65 default-state = "off";
66 linux,default-trigger = "heartbeat";
67 };
66 }; 68 };
67 };
68 69
69 gpio_keys { 70 gpio_keys {
70 compatible = "gpio-keys"; 71 compatible = "gpio-keys";
71 #address-cells = <1>; 72 #address-cells = <1>;
72 #size-cells = <0>; 73 #size-cells = <0>;
73 74
74 button@1 { 75 button@1 {
75 label = "Init Button"; 76 label = "Init Button";
76 linux,code = <116>; 77 linux,code = <116>;
77 gpios = <&gpio1 28 0>; 78 gpios = <&gpio1 28 0>;
79 };
78 }; 80 };
79 };
80 81
81 mdio { 82 mdio {
82 phy0: ethernet-phy@0 { 83 phy0: ethernet-phy@0 {
83 reg = <0>; 84 reg = <0>;
84 }; 85 };
85 86
86 phy1: ethernet-phy@1 { 87 phy1: ethernet-phy@1 {
87 reg = <1>; 88 reg = <1>;
88 }; 89 };
89 90
90 phy2: ethernet-phy@2 { 91 phy2: ethernet-phy@2 {
91 reg = <2>; 92 reg = <2>;
92 }; 93 };
93 94
94 phy3: ethernet-phy@3 { 95 phy3: ethernet-phy@3 {
95 reg = <3>; 96 reg = <3>;
97 };
96 }; 98 };
97 };
98 99
99 ethernet@70000 { 100 ethernet@70000 {
100 status = "okay"; 101 status = "okay";
101 phy = <&phy0>; 102 phy = <&phy0>;
102 phy-mode = "sgmii"; 103 phy-mode = "sgmii";
103 }; 104 };
104 ethernet@74000 { 105 ethernet@74000 {
105 status = "okay"; 106 status = "okay";
106 phy = <&phy1>; 107 phy = <&phy1>;
107 phy-mode = "sgmii"; 108 phy-mode = "sgmii";
108 }; 109 };
109 ethernet@30000 { 110 ethernet@30000 {
110 status = "okay"; 111 status = "okay";
111 phy = <&phy2>; 112 phy = <&phy2>;
112 phy-mode = "sgmii"; 113 phy-mode = "sgmii";
113 }; 114 };
114 ethernet@34000 { 115 ethernet@34000 {
115 status = "okay"; 116 status = "okay";
116 phy = <&phy3>; 117 phy = <&phy3>;
117 phy-mode = "sgmii"; 118 phy-mode = "sgmii";
118 }; 119 };
119 i2c@11000 { 120 i2c@11000 {
120 status = "okay"; 121 status = "okay";
121 clock-frequency = <400000>; 122 clock-frequency = <400000>;
122 }; 123 };
123 i2c@11100 { 124 i2c@11100 {
124 status = "okay"; 125 status = "okay";
125 clock-frequency = <400000>; 126 clock-frequency = <400000>;
126 127
127 s35390a: s35390a@30 { 128 s35390a: s35390a@30 {
128 compatible = "s35390a"; 129 compatible = "s35390a";
129 reg = <0x30>; 130 reg = <0x30>;
131 };
132 };
133 sata@a0000 {
134 nr-ports = <2>;
135 status = "okay";
136 };
137 usb@50000 {
138 status = "okay";
139 };
140 usb@51000 {
141 status = "okay";
130 }; 142 };
131 };
132 sata@a0000 {
133 nr-ports = <2>;
134 status = "okay";
135 };
136 usb@50000 {
137 status = "okay";
138 };
139 usb@51000 {
140 status = "okay";
141 };
142 143
143 devbus-bootcs@10400 { 144 devbus-bootcs@10400 {
144 status = "okay"; 145 status = "okay";
145 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ 146 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
146 147
147 /* Device Bus parameters are required */ 148 /* Device Bus parameters are required */
148 149
149 /* Read parameters */ 150 /* Read parameters */
150 devbus,bus-width = <8>; 151 devbus,bus-width = <8>;
151 devbus,turn-off-ps = <60000>; 152 devbus,turn-off-ps = <60000>;
152 devbus,badr-skew-ps = <0>; 153 devbus,badr-skew-ps = <0>;
153 devbus,acc-first-ps = <124000>; 154 devbus,acc-first-ps = <124000>;
154 devbus,acc-next-ps = <248000>; 155 devbus,acc-next-ps = <248000>;
155 devbus,rd-setup-ps = <0>; 156 devbus,rd-setup-ps = <0>;
156 devbus,rd-hold-ps = <0>; 157 devbus,rd-hold-ps = <0>;
157 158
158 /* Write parameters */ 159 /* Write parameters */
159 devbus,sync-enable = <0>; 160 devbus,sync-enable = <0>;
160 devbus,wr-high-ps = <60000>; 161 devbus,wr-high-ps = <60000>;
161 devbus,wr-low-ps = <60000>; 162 devbus,wr-low-ps = <60000>;
162 devbus,ale-wr-ps = <60000>; 163 devbus,ale-wr-ps = <60000>;
163 164
164 /* NOR 128 MiB */ 165 /* NOR 128 MiB */
165 nor@0 { 166 nor@0 {
166 compatible = "cfi-flash"; 167 compatible = "cfi-flash";
167 reg = <0 0x8000000>; 168 reg = <0 0x8000000>;
168 bank-width = <2>; 169 bank-width = <2>;
170 };
169 }; 171 };
170 };
171 172
172 pcie-controller { 173 pcie-controller {
173 status = "okay";
174 /* Internal mini-PCIe connector */
175 pcie@1,0 {
176 /* Port 0, Lane 0 */
177 status = "okay"; 174 status = "okay";
175 /* Internal mini-PCIe connector */
176 pcie@1,0 {
177 /* Port 0, Lane 0 */
178 status = "okay";
179 };
178 }; 180 };
179 }; 181 };
180 }; 182 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 465b9fa116ea..bacab11c10dc 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,141 +22,140 @@
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25
26 soc { 25 soc {
27 L2: l2-cache { 26 internal-regs {
28 compatible = "marvell,aurora-system-cache"; 27 L2: l2-cache {
29 reg = <0x08000 0x1000>; 28 compatible = "marvell,aurora-system-cache";
30 cache-id-part = <0x100>; 29 reg = <0x08000 0x1000>;
31 wt-override; 30 cache-id-part = <0x100>;
32 }; 31 wt-override;
32 };
33 33
34 mpic: interrupt-controller@20000 { 34 mpic: interrupt-controller@20000 {
35 reg = <0x20a00 0x2d0>, 35 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
36 <0x21070 0x58>; 36 };
37 };
38 37
39 armada-370-xp-pmsu@22000 { 38 armada-370-xp-pmsu@22000 {
40 compatible = "marvell,armada-370-xp-pmsu"; 39 compatible = "marvell,armada-370-xp-pmsu";
41 reg = <0x22100 0x430>, 40 reg = <0x22100 0x430>, <0x20800 0x20>;
42 <0x20800 0x20>; 41 };
43 };
44 42
45 serial@12200 { 43 serial@12200 {
46 compatible = "snps,dw-apb-uart"; 44 compatible = "snps,dw-apb-uart";
47 reg = <0x12200 0x100>; 45 reg = <0x12200 0x100>;
48 reg-shift = <2>; 46 reg-shift = <2>;
49 interrupts = <43>; 47 interrupts = <43>;
50 reg-io-width = <1>; 48 reg-io-width = <1>;
51 status = "disabled"; 49 status = "disabled";
52 }; 50 };
53 serial@12300 { 51 serial@12300 {
54 compatible = "snps,dw-apb-uart"; 52 compatible = "snps,dw-apb-uart";
55 reg = <0x12300 0x100>; 53 reg = <0x12300 0x100>;
56 reg-shift = <2>; 54 reg-shift = <2>;
57 interrupts = <44>; 55 interrupts = <44>;
58 reg-io-width = <1>; 56 reg-io-width = <1>;
59 status = "disabled"; 57 status = "disabled";
60 }; 58 };
61 59
62 timer@20300 { 60 timer@20300 {
63 marvell,timer-25Mhz; 61 marvell,timer-25Mhz;
64 }; 62 };
65 63
66 coreclk: mvebu-sar@18230 { 64 coreclk: mvebu-sar@18230 {
67 compatible = "marvell,armada-xp-core-clock"; 65 compatible = "marvell,armada-xp-core-clock";
68 reg = <0x18230 0x08>; 66 reg = <0x18230 0x08>;
69 #clock-cells = <1>; 67 #clock-cells = <1>;
70 }; 68 };
71 69
72 cpuclk: clock-complex@18700 { 70 cpuclk: clock-complex@18700 {
73 #clock-cells = <1>; 71 #clock-cells = <1>;
74 compatible = "marvell,armada-xp-cpu-clock"; 72 compatible = "marvell,armada-xp-cpu-clock";
75 reg = <0x18700 0xA0>; 73 reg = <0x18700 0xA0>;
76 clocks = <&coreclk 1>; 74 clocks = <&coreclk 1>;
77 }; 75 };
78 76
79 gateclk: clock-gating-control@18220 { 77 gateclk: clock-gating-control@18220 {
80 compatible = "marvell,armada-xp-gating-clock"; 78 compatible = "marvell,armada-xp-gating-clock";
81 reg = <0x18220 0x4>; 79 reg = <0x18220 0x4>;
82 clocks = <&coreclk 0>; 80 clocks = <&coreclk 0>;
83 #clock-cells = <1>; 81 #clock-cells = <1>;
84 }; 82 };
85 83
86 system-controller@18200 { 84 system-controller@18200 {
87 compatible = "marvell,armada-370-xp-system-controller"; 85 compatible = "marvell,armada-370-xp-system-controller";
88 reg = <0x18200 0x500>; 86 reg = <0x18200 0x500>;
89 }; 87 };
90 88
91 ethernet@30000 { 89 ethernet@30000 {
92 compatible = "marvell,armada-370-neta"; 90 compatible = "marvell,armada-370-neta";
93 reg = <0x30000 0x2500>; 91 reg = <0x30000 0x2500>;
94 interrupts = <12>; 92 interrupts = <12>;
95 clocks = <&gateclk 2>; 93 clocks = <&gateclk 2>;
96 status = "disabled"; 94 status = "disabled";
97 };
98
99 xor@60900 {
100 compatible = "marvell,orion-xor";
101 reg = <0x60900 0x100
102 0x60b00 0x100>;
103 clocks = <&gateclk 22>;
104 status = "okay";
105
106 xor10 {
107 interrupts = <51>;
108 dmacap,memcpy;
109 dmacap,xor;
110 }; 95 };
111 xor11 {
112 interrupts = <52>;
113 dmacap,memcpy;
114 dmacap,xor;
115 dmacap,memset;
116 };
117 };
118 96
119 xor@f0900 { 97 xor@60900 {
120 compatible = "marvell,orion-xor"; 98 compatible = "marvell,orion-xor";
121 reg = <0xF0900 0x100 99 reg = <0x60900 0x100
122 0xF0B00 0x100>; 100 0x60b00 0x100>;
123 clocks = <&gateclk 28>; 101 clocks = <&gateclk 22>;
124 status = "okay"; 102 status = "okay";
125 103
126 xor00 { 104 xor10 {
127 interrupts = <94>; 105 interrupts = <51>;
128 dmacap,memcpy; 106 dmacap,memcpy;
129 dmacap,xor; 107 dmacap,xor;
108 };
109 xor11 {
110 interrupts = <52>;
111 dmacap,memcpy;
112 dmacap,xor;
113 dmacap,memset;
114 };
130 }; 115 };
131 xor01 { 116
132 interrupts = <95>; 117 xor@f0900 {
133 dmacap,memcpy; 118 compatible = "marvell,orion-xor";
134 dmacap,xor; 119 reg = <0xF0900 0x100
135 dmacap,memset; 120 0xF0B00 0x100>;
121 clocks = <&gateclk 28>;
122 status = "okay";
123
124 xor00 {
125 interrupts = <94>;
126 dmacap,memcpy;
127 dmacap,xor;
128 };
129 xor01 {
130 interrupts = <95>;
131 dmacap,memcpy;
132 dmacap,xor;
133 dmacap,memset;
134 };
136 }; 135 };
137 };
138 136
139 usb@50000 { 137 usb@50000 {
140 clocks = <&gateclk 18>; 138 clocks = <&gateclk 18>;
141 }; 139 };
142 140
143 usb@51000 { 141 usb@51000 {
144 clocks = <&gateclk 19>; 142 clocks = <&gateclk 19>;
145 }; 143 };
146 144
147 usb@52000 { 145 usb@52000 {
148 compatible = "marvell,orion-ehci"; 146 compatible = "marvell,orion-ehci";
149 reg = <0x52000 0x500>; 147 reg = <0x52000 0x500>;
150 interrupts = <47>; 148 interrupts = <47>;
151 clocks = <&gateclk 20>; 149 clocks = <&gateclk 20>;
152 status = "disabled"; 150 status = "disabled";
153 }; 151 };
154 152
155 thermal@182b0 { 153 thermal@182b0 {
156 compatible = "marvell,armadaxp-thermal"; 154 compatible = "marvell,armadaxp-thermal";
157 reg = <0x182b0 0x4 155 reg = <0x182b0 0x4
158 0x184d0 0x4>; 156 0x184d0 0x4>;
159 status = "okay"; 157 status = "okay";
158 };
160 }; 159 };
161 }; 160 };
162}; 161};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 08:19:51 -0400