3 files changed, 361 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121e6ecf..ecdd51dc9c0f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -205,6 +205,7 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
 dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
        wm8505-ref.dtb \
        wm8650-mid.dtb \
+        wm8750-apc8750.dtb \
        wm8850-w70v2.dtb
 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts
new file mode 100644
index 000000000000..62675eba9666
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750-apc8750.dts
@@ -0,0 +1,26 @@
+/*
+ * wm8750-apc8750.dts
+ *  - Device tree file for VIA APC8750
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/dts-v1/;
+/include/ "wm8750.dtsi"
+/ {
+        model = "VIA APC8750";
+};
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c>;
+        i2c: i2c {
+                wm,pins = <168 169 170 171>;
+                wm,function = <2>;      /* alt */
+                wm,pull = <2>;  /* pull-up */
+        };
+};
diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi
new file mode 100644
index 000000000000..462de589a2fe
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750.dtsi
@@ -0,0 +1,334 @@
+/*
+ * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "wm,wm8750";
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm1176ej-s";
+                };
+        };
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8750-pinctrl";
+                        reg = <0xd8110000 0x10000>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20C>;
+                                };
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x210>;
+                                };
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <24>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <25>;
+                                };
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <26>;
+                                };
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <27>;
+                                };
+                                clkuart4: uart4 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <28>;
+                                };
+                                clkuart5: uart5 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <29>;
+                                };
+                                clkpwm: pwm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x350>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <17>;
+                                };
+                                clksdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x330>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <0>;
+                                };
+                                clki2c0: i2c0clk {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x3A0>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <8>;
+                                };
+                                clki2c1: i2c1clk {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x3A4>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <9>;
+                                };
+                        };
+                };
+                pwm: pwm@d8220000 {
+                        #pwm-cells = <3>;
+                        compatible = "via,vt8500-pwm";
+                        reg = <0xd8220000 0x100>;
+                        clocks = <&clkpwm>;
+                };
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <26>;
+                };
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <26>;
+                };
+                uhci@d8008d00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8008d00 0x200>;
+                        interrupts = <26>;
+                };
+                uart0: uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&clkuart0>;
+                };
+                uart1: uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&clkuart1>;
+                };
+                uart2: uart@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&clkuart2>;
+                };
+                uart3: uart@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&clkuart3>;
+                };
+                uart4: uart@d8370000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8370000 0x1040>;
+                        interrupts = <30>;
+                        clocks = <&clkuart4>;
+                };
+                uart5: uart@d8380000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8380000 0x1040>;
+                        interrupts = <43>;
+                        clocks = <&clkuart5>;
+                };
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+                sdhc@d800a000 {
+                        compatible = "wm,wm8505-sdhc";
+                        reg = <0xd800a000 0x1000>;
+                        interrupts = <20 21>;
+                        clocks = <&clksdhc>;
+                        bus-width = <4>;
+                        sdon-inverted;
+                };
+                i2c_0: i2c@d8280000 {
+                        compatible = "wm,wm8505-i2c";
+                        reg = <0xd8280000 0x1000>;
+                        interrupts = <19>;
+                        clocks = <&clki2c0>;
+                        clock-frequency = <400000>;
+                };
+                i2c_1: i2c@d8320000 {
+                        compatible = "wm,wm8505-i2c";
+                        reg = <0xd8320000 0x1000>;
+                        interrupts = <18>;
+                        clocks = <&clki2c1>;
+                        clock-frequency = <400000>;
+                };
+        };
+};

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9f7121e6ecf..ecdd51dc9c0f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile
@@ -205,6 +205,7 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
205	dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \	205	dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
206	wm8505-ref.dtb \	206	wm8505-ref.dtb \
207	wm8650-mid.dtb \	207	wm8650-mid.dtb \
		208	wm8750-apc8750.dtb \
208	wm8850-w70v2.dtb	209	wm8850-w70v2.dtb
209	dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb	210	dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
210		211


diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts new file mode 100644 index 000000000000..62675eba9666 --- /dev/null +++ b/arch/arm/boot/dts/wm8750-apc8750.dts
@@ -0,0 +1,26 @@
		1	/*
		2	* wm8750-apc8750.dts
		3	* - Device tree file for VIA APC8750
		4	*
		5	* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
		6	*
		7	* Licensed under GPLv2 or later
		8	*/
		9
		10	/dts-v1/;
		11	/include/ "wm8750.dtsi"
		12
		13	/ {
		14	model = "VIA APC8750";
		15	};
		16
		17	&pinctrl {
		18	pinctrl-names = "default";
		19	pinctrl-0 = <&i2c>;
		20
		21	i2c: i2c {
		22	wm,pins = <168 169 170 171>;
		23	wm,function = <2>; /* alt */
		24	wm,pull = <2>; /* pull-up */
		25	};
		26	};


diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi new file mode 100644 index 000000000000..462de589a2fe --- /dev/null +++ b/arch/arm/boot/dts/wm8750.dtsi
@@ -0,0 +1,334 @@
		1	/*
		2	* wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
		3	*
		4	* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
		5	*
		6	* Licensed under GPLv2 or later
		7	*/
		8
		9	/include/ "skeleton.dtsi"
		10
		11	/ {
		12	compatible = "wm,wm8750";
		13
		14	cpus {
		15	#address-cells = <0>;
		16	#size-cells = <0>;
		17
		18	cpu {
		19	device_type = "cpu";
		20	compatible = "arm,arm1176ej-s";
		21	};
		22	};
		23
		24	aliases {
		25	serial0 = &uart0;
		26	serial1 = &uart1;
		27	serial2 = &uart2;
		28	serial3 = &uart3;
		29	serial4 = &uart4;
		30	serial5 = &uart5;
		31	i2c0 = &i2c_0;
		32	i2c1 = &i2c_1;
		33	};
		34
		35	soc {
		36	#address-cells = <1>;
		37	#size-cells = <1>;
		38	compatible = "simple-bus";
		39	ranges;
		40	interrupt-parent = <&intc0>;
		41
		42	intc0: interrupt-controller@d8140000 {
		43	compatible = "via,vt8500-intc";
		44	interrupt-controller;
		45	reg = <0xd8140000 0x10000>;
		46	#interrupt-cells = <1>;
		47	};
		48
		49	/* Secondary IC cascaded to intc0 */
		50	intc1: interrupt-controller@d8150000 {
		51	compatible = "via,vt8500-intc";
		52	interrupt-controller;
		53	#interrupt-cells = <1>;
		54	reg = <0xD8150000 0x10000>;
		55	interrupts = <56 57 58 59 60 61 62 63>;
		56	};
		57
		58	pinctrl: pinctrl@d8110000 {
		59	compatible = "wm,wm8750-pinctrl";
		60	reg = <0xd8110000 0x10000>;
		61	interrupt-controller;
		62	#interrupt-cells = <2>;
		63	gpio-controller;
		64	#gpio-cells = <2>;
		65	};
		66
		67	pmc@d8130000 {
		68	compatible = "via,vt8500-pmc";
		69	reg = <0xd8130000 0x1000>;
		70
		71	clocks {
		72	#address-cells = <1>;
		73	#size-cells = <0>;
		74
		75	ref24: ref24M {
		76	#clock-cells = <0>;
		77	compatible = "fixed-clock";
		78	clock-frequency = <24000000>;
		79	};
		80
		81	ref25: ref25M {
		82	#clock-cells = <0>;
		83	compatible = "fixed-clock";
		84	clock-frequency = <25000000>;
		85	};
		86
		87	plla: plla {
		88	#clock-cells = <0>;
		89	compatible = "wm,wm8750-pll-clock";
		90	clocks = <&ref25>;
		91	reg = <0x200>;
		92	};
		93
		94	pllb: pllb {
		95	#clock-cells = <0>;
		96	compatible = "wm,wm8750-pll-clock";
		97	clocks = <&ref25>;
		98	reg = <0x204>;
		99	};
		100
		101	pllc: pllc {
		102	#clock-cells = <0>;
		103	compatible = "wm,wm8750-pll-clock";
		104	clocks = <&ref25>;
		105	reg = <0x208>;
		106	};
		107
		108	plld: plld {
		109	#clock-cells = <0>;
		110	compatible = "wm,wm8750-pll-clock";
		111	clocks = <&ref25>;
		112	reg = <0x20C>;
		113	};
		114
		115	plle: plle {
		116	#clock-cells = <0>;
		117	compatible = "wm,wm8750-pll-clock";
		118	clocks = <&ref25>;
		119	reg = <0x210>;
		120	};
		121
		122	clkarm: arm {
		123	#clock-cells = <0>;
		124	compatible = "via,vt8500-device-clock";
		125	clocks = <&plla>;
		126	divisor-reg = <0x300>;
		127	};
		128
		129	clkahb: ahb {
		130	#clock-cells = <0>;
		131	compatible = "via,vt8500-device-clock";
		132	clocks = <&pllb>;
		133	divisor-reg = <0x304>;
		134	};
		135
		136	clkddr: ddr {
		137	#clock-cells = <0>;
		138	compatible = "via,vt8500-device-clock";
		139	clocks = <&plld>;
		140	divisor-reg = <0x310>;
		141	};
		142
		143	clkuart0: uart0 {
		144	#clock-cells = <0>;
		145	compatible = "via,vt8500-device-clock";
		146	clocks = <&ref24>;
		147	enable-reg = <0x254>;
		148	enable-bit = <24>;
		149	};
		150
		151	clkuart1: uart1 {
		152	#clock-cells = <0>;
		153	compatible = "via,vt8500-device-clock";
		154	clocks = <&ref24>;
		155	enable-reg = <0x254>;
		156	enable-bit = <25>;
		157	};
		158
		159	clkuart2: uart2 {
		160	#clock-cells = <0>;
		161	compatible = "via,vt8500-device-clock";
		162	clocks = <&ref24>;
		163	enable-reg = <0x254>;
		164	enable-bit = <26>;
		165	};
		166
		167	clkuart3: uart3 {
		168	#clock-cells = <0>;
		169	compatible = "via,vt8500-device-clock";
		170	clocks = <&ref24>;
		171	enable-reg = <0x254>;
		172	enable-bit = <27>;
		173	};
		174
		175	clkuart4: uart4 {
		176	#clock-cells = <0>;
		177	compatible = "via,vt8500-device-clock";
		178	clocks = <&ref24>;
		179	enable-reg = <0x254>;
		180	enable-bit = <28>;
		181	};
		182
		183	clkuart5: uart5 {
		184	#clock-cells = <0>;
		185	compatible = "via,vt8500-device-clock";
		186	clocks = <&ref24>;
		187	enable-reg = <0x254>;
		188	enable-bit = <29>;
		189	};
		190
		191	clkpwm: pwm {
		192	#clock-cells = <0>;
		193	compatible = "via,vt8500-device-clock";
		194	clocks = <&pllb>;
		195	divisor-reg = <0x350>;
		196	enable-reg = <0x250>;
		197	enable-bit = <17>;
		198	};
		199
		200	clksdhc: sdhc {
		201	#clock-cells = <0>;
		202	compatible = "via,vt8500-device-clock";
		203	clocks = <&pllb>;
		204	divisor-reg = <0x330>;
		205	divisor-mask = <0x3f>;
		206	enable-reg = <0x250>;
		207	enable-bit = <0>;
		208	};
		209
		210	clki2c0: i2c0clk {
		211	#clock-cells = <0>;
		212	compatible = "via,vt8500-device-clock";
		213	clocks = <&pllb>;
		214	divisor-reg = <0x3A0>;
		215	enable-reg = <0x250>;
		216	enable-bit = <8>;
		217	};
		218
		219	clki2c1: i2c1clk {
		220	#clock-cells = <0>;
		221	compatible = "via,vt8500-device-clock";
		222	clocks = <&pllb>;
		223	divisor-reg = <0x3A4>;
		224	enable-reg = <0x250>;
		225	enable-bit = <9>;
		226	};
		227	};
		228	};
		229
		230	pwm: pwm@d8220000 {
		231	#pwm-cells = <3>;
		232	compatible = "via,vt8500-pwm";
		233	reg = <0xd8220000 0x100>;
		234	clocks = <&clkpwm>;
		235	};
		236
		237	timer@d8130100 {
		238	compatible = "via,vt8500-timer";
		239	reg = <0xd8130100 0x28>;
		240	interrupts = <36>;
		241	};
		242
		243	ehci@d8007900 {
		244	compatible = "via,vt8500-ehci";
		245	reg = <0xd8007900 0x200>;
		246	interrupts = <26>;
		247	};
		248
		249	uhci@d8007b00 {
		250	compatible = "platform-uhci";
		251	reg = <0xd8007b00 0x200>;
		252	interrupts = <26>;
		253	};
		254
		255	uhci@d8008d00 {
		256	compatible = "platform-uhci";
		257	reg = <0xd8008d00 0x200>;
		258	interrupts = <26>;
		259	};
		260
		261	uart0: uart@d8200000 {
		262	compatible = "via,vt8500-uart";
		263	reg = <0xd8200000 0x1040>;
		264	interrupts = <32>;
		265	clocks = <&clkuart0>;
		266	};
		267
		268	uart1: uart@d82b0000 {
		269	compatible = "via,vt8500-uart";
		270	reg = <0xd82b0000 0x1040>;
		271	interrupts = <33>;
		272	clocks = <&clkuart1>;
		273	};
		274
		275	uart2: uart@d8210000 {
		276	compatible = "via,vt8500-uart";
		277	reg = <0xd8210000 0x1040>;
		278	interrupts = <47>;
		279	clocks = <&clkuart2>;
		280	};
		281
		282	uart3: uart@d82c0000 {
		283	compatible = "via,vt8500-uart";
		284	reg = <0xd82c0000 0x1040>;
		285	interrupts = <50>;
		286	clocks = <&clkuart3>;
		287	};
		288
		289	uart4: uart@d8370000 {
		290	compatible = "via,vt8500-uart";
		291	reg = <0xd8370000 0x1040>;
		292	interrupts = <30>;
		293	clocks = <&clkuart4>;
		294	};
		295
		296	uart5: uart@d8380000 {
		297	compatible = "via,vt8500-uart";
		298	reg = <0xd8380000 0x1040>;
		299	interrupts = <43>;
		300	clocks = <&clkuart5>;
		301	};
		302
		303	rtc@d8100000 {
		304	compatible = "via,vt8500-rtc";
		305	reg = <0xd8100000 0x10000>;
		306	interrupts = <48>;
		307	};
		308
		309	sdhc@d800a000 {
		310	compatible = "wm,wm8505-sdhc";
		311	reg = <0xd800a000 0x1000>;
		312	interrupts = <20 21>;
		313	clocks = <&clksdhc>;
		314	bus-width = <4>;
		315	sdon-inverted;
		316	};
		317
		318	i2c_0: i2c@d8280000 {
		319	compatible = "wm,wm8505-i2c";
		320	reg = <0xd8280000 0x1000>;
		321	interrupts = <19>;
		322	clocks = <&clki2c0>;
		323	clock-frequency = <400000>;
		324	};
		325
		326	i2c_1: i2c@d8320000 {
		327	compatible = "wm,wm8505-i2c";
		328	reg = <0xd8320000 0x1000>;
		329	interrupts = <18>;
		330	clocks = <&clki2c1>;
		331	clock-frequency = <400000>;
		332	};
		333	};
		334	};