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-rw-r--r--arch/sparc/include/asm/io_64.h100
1 files changed, 15 insertions, 85 deletions
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 6c55c532d09a..80b54b326d49 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -187,67 +187,37 @@ static inline void writeq(u64 q, volatile void __iomem *addr)
187#define inb inb 187#define inb inb
188static inline u8 inb(unsigned long addr) 188static inline u8 inb(unsigned long addr)
189{ 189{
190 u8 ret; 190 return readb((volatile void __iomem *)addr);
191
192 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
193 : "=r" (ret)
194 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
195 : "memory");
196
197 return ret;
198} 191}
199 192
200#define inw inw 193#define inw inw
201static inline u16 inw(unsigned long addr) 194static inline u16 inw(unsigned long addr)
202{ 195{
203 u16 ret; 196 return readw((volatile void __iomem *)addr);
204
205 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
206 : "=r" (ret)
207 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
208 : "memory");
209
210 return ret;
211} 197}
212 198
213#define inl inl 199#define inl inl
214static inline u32 inl(unsigned long addr) 200static inline u32 inl(unsigned long addr)
215{ 201{
216 u32 ret; 202 return readl((volatile void __iomem *)addr);
217
218 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
219 : "=r" (ret)
220 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
221 : "memory");
222
223 return ret;
224} 203}
225 204
226#define outb outb 205#define outb outb
227static inline void outb(u8 b, unsigned long addr) 206static inline void outb(u8 b, unsigned long addr)
228{ 207{
229 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */" 208 writeb(b, (volatile void __iomem *)addr);
230 : /* no outputs */
231 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
232 : "memory");
233} 209}
234 210
235#define outw outw 211#define outw outw
236static inline void outw(u16 w, unsigned long addr) 212static inline void outw(u16 w, unsigned long addr)
237{ 213{
238 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */" 214 writew(w, (volatile void __iomem *)addr);
239 : /* no outputs */
240 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
241 : "memory");
242} 215}
243 216
244#define outl outl 217#define outl outl
245static inline void outl(u32 l, unsigned long addr) 218static inline void outl(u32 l, unsigned long addr)
246{ 219{
247 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */" 220 writel(l, (volatile void __iomem *)addr);
248 : /* no outputs */
249 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
250 : "memory");
251} 221}
252 222
253 223
@@ -309,82 +279,42 @@ static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned l
309 */ 279 */
310static inline u8 sbus_readb(const volatile void __iomem *addr) 280static inline u8 sbus_readb(const volatile void __iomem *addr)
311{ 281{
312 u8 ret; 282 return __raw_readb(addr);
313
314 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
315 : "=r" (ret)
316 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
317 : "memory");
318
319 return ret;
320} 283}
321 284
322static inline u16 sbus_readw(const volatile void __iomem *addr) 285static inline u16 sbus_readw(const volatile void __iomem *addr)
323{ 286{
324 u16 ret; 287 return __raw_readw(addr);
325
326 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
327 : "=r" (ret)
328 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
329 : "memory");
330
331 return ret;
332} 288}
333 289
334static inline u32 sbus_readl(const volatile void __iomem *addr) 290static inline u32 sbus_readl(const volatile void __iomem *addr)
335{ 291{
336 u32 ret; 292 return __raw_readl(addr);
337
338 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
339 : "=r" (ret)
340 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
341 : "memory");
342
343 return ret;
344} 293}
345 294
346static inline u64 sbus_readq(const volatile void __iomem *addr) 295static inline u64 sbus_readq(const volatile void __iomem *addr)
347{ 296{
348 u64 ret; 297 return __raw_readq(addr);
349
350 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
351 : "=r" (ret)
352 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
353 : "memory");
354
355 return ret;
356} 298}
357 299
358static inline void sbus_writeb(u8 b, volatile void __iomem *addr) 300static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
359{ 301{
360 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */" 302 __raw_writeb(b, addr);
361 : /* no outputs */
362 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
363 : "memory");
364} 303}
365 304
366static inline void sbus_writew(u16 w, volatile void __iomem *addr) 305static inline void sbus_writew(u16 w, volatile void __iomem *addr)
367{ 306{
368 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */" 307 __raw_writew(w, addr);
369 : /* no outputs */
370 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
371 : "memory");
372} 308}
373 309
374static inline void sbus_writel(u32 l, volatile void __iomem *addr) 310static inline void sbus_writel(u32 l, volatile void __iomem *addr)
375{ 311{
376 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */" 312 __raw_writel(l, addr);
377 : /* no outputs */
378 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
379 : "memory");
380} 313}
381 314
382static inline void sbus_writeq(u64 l, volatile void __iomem *addr) 315static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
383{ 316{
384 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */" 317 __raw_writeq(q, addr);
385 : /* no outputs */
386 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
387 : "memory");
388} 318}
389 319
390static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n) 320static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)