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-rw-r--r--drivers/extcon/extcon-max77693.c35
-rw-r--r--drivers/mfd/Kconfig1
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/max77693-irq.c336
-rw-r--r--drivers/mfd/max77693.c210
-rw-r--r--drivers/regulator/max77693.c12
-rw-r--r--include/linux/mfd/max77693-private.h54
7 files changed, 217 insertions, 433 deletions
diff --git a/drivers/extcon/extcon-max77693.c b/drivers/extcon/extcon-max77693.c
index 2c7c3e191591..c7278b1649da 100644
--- a/drivers/extcon/extcon-max77693.c
+++ b/drivers/extcon/extcon-max77693.c
@@ -255,10 +255,10 @@ static int max77693_muic_set_debounce_time(struct max77693_muic_info *info,
255 case ADC_DEBOUNCE_TIME_10MS: 255 case ADC_DEBOUNCE_TIME_10MS:
256 case ADC_DEBOUNCE_TIME_25MS: 256 case ADC_DEBOUNCE_TIME_25MS:
257 case ADC_DEBOUNCE_TIME_38_62MS: 257 case ADC_DEBOUNCE_TIME_38_62MS:
258 ret = max77693_update_reg(info->max77693->regmap_muic, 258 ret = regmap_update_bits(info->max77693->regmap_muic,
259 MAX77693_MUIC_REG_CTRL3, 259 MAX77693_MUIC_REG_CTRL3,
260 time << CONTROL3_ADCDBSET_SHIFT, 260 CONTROL3_ADCDBSET_MASK,
261 CONTROL3_ADCDBSET_MASK); 261 time << CONTROL3_ADCDBSET_SHIFT);
262 if (ret) { 262 if (ret) {
263 dev_err(info->dev, "failed to set ADC debounce time\n"); 263 dev_err(info->dev, "failed to set ADC debounce time\n");
264 return ret; 264 return ret;
@@ -286,15 +286,15 @@ static int max77693_muic_set_path(struct max77693_muic_info *info,
286 u8 val, bool attached) 286 u8 val, bool attached)
287{ 287{
288 int ret = 0; 288 int ret = 0;
289 u8 ctrl1, ctrl2 = 0; 289 unsigned int ctrl1, ctrl2 = 0;
290 290
291 if (attached) 291 if (attached)
292 ctrl1 = val; 292 ctrl1 = val;
293 else 293 else
294 ctrl1 = CONTROL1_SW_OPEN; 294 ctrl1 = CONTROL1_SW_OPEN;
295 295
296 ret = max77693_update_reg(info->max77693->regmap_muic, 296 ret = regmap_update_bits(info->max77693->regmap_muic,
297 MAX77693_MUIC_REG_CTRL1, ctrl1, COMP_SW_MASK); 297 MAX77693_MUIC_REG_CTRL1, COMP_SW_MASK, ctrl1);
298 if (ret < 0) { 298 if (ret < 0) {
299 dev_err(info->dev, "failed to update MUIC register\n"); 299 dev_err(info->dev, "failed to update MUIC register\n");
300 return ret; 300 return ret;
@@ -305,9 +305,9 @@ static int max77693_muic_set_path(struct max77693_muic_info *info,
305 else 305 else
306 ctrl2 |= CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ 306 ctrl2 |= CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */
307 307
308 ret = max77693_update_reg(info->max77693->regmap_muic, 308 ret = regmap_update_bits(info->max77693->regmap_muic,
309 MAX77693_MUIC_REG_CTRL2, ctrl2, 309 MAX77693_MUIC_REG_CTRL2,
310 CONTROL2_LOWPWR_MASK | CONTROL2_CPEN_MASK); 310 CONTROL2_LOWPWR_MASK | CONTROL2_CPEN_MASK, ctrl2);
311 if (ret < 0) { 311 if (ret < 0) {
312 dev_err(info->dev, "failed to update MUIC register\n"); 312 dev_err(info->dev, "failed to update MUIC register\n");
313 return ret; 313 return ret;
@@ -969,8 +969,8 @@ static void max77693_muic_irq_work(struct work_struct *work)
969 if (info->irq == muic_irqs[i].virq) 969 if (info->irq == muic_irqs[i].virq)
970 irq_type = muic_irqs[i].irq; 970 irq_type = muic_irqs[i].irq;
971 971
972 ret = max77693_bulk_read(info->max77693->regmap_muic, 972 ret = regmap_bulk_read(info->max77693->regmap_muic,
973 MAX77693_MUIC_REG_STATUS1, 2, info->status); 973 MAX77693_MUIC_REG_STATUS1, info->status, 2);
974 if (ret) { 974 if (ret) {
975 dev_err(info->dev, "failed to read MUIC register\n"); 975 dev_err(info->dev, "failed to read MUIC register\n");
976 mutex_unlock(&info->mutex); 976 mutex_unlock(&info->mutex);
@@ -1042,8 +1042,8 @@ static int max77693_muic_detect_accessory(struct max77693_muic_info *info)
1042 mutex_lock(&info->mutex); 1042 mutex_lock(&info->mutex);
1043 1043
1044 /* Read STATUSx register to detect accessory */ 1044 /* Read STATUSx register to detect accessory */
1045 ret = max77693_bulk_read(info->max77693->regmap_muic, 1045 ret = regmap_bulk_read(info->max77693->regmap_muic,
1046 MAX77693_MUIC_REG_STATUS1, 2, info->status); 1046 MAX77693_MUIC_REG_STATUS1, info->status, 2);
1047 if (ret) { 1047 if (ret) {
1048 dev_err(info->dev, "failed to read MUIC register\n"); 1048 dev_err(info->dev, "failed to read MUIC register\n");
1049 mutex_unlock(&info->mutex); 1049 mutex_unlock(&info->mutex);
@@ -1095,7 +1095,7 @@ static int max77693_muic_probe(struct platform_device *pdev)
1095 int delay_jiffies; 1095 int delay_jiffies;
1096 int ret; 1096 int ret;
1097 int i; 1097 int i;
1098 u8 id; 1098 unsigned int id;
1099 1099
1100 info = devm_kzalloc(&pdev->dev, sizeof(struct max77693_muic_info), 1100 info = devm_kzalloc(&pdev->dev, sizeof(struct max77693_muic_info),
1101 GFP_KERNEL); 1101 GFP_KERNEL);
@@ -1154,7 +1154,8 @@ static int max77693_muic_probe(struct platform_device *pdev)
1154 struct max77693_muic_irq *muic_irq = &muic_irqs[i]; 1154 struct max77693_muic_irq *muic_irq = &muic_irqs[i];
1155 unsigned int virq = 0; 1155 unsigned int virq = 0;
1156 1156
1157 virq = irq_create_mapping(max77693->irq_domain, muic_irq->irq); 1157 virq = regmap_irq_get_virq(max77693->irq_data_muic,
1158 muic_irq->irq);
1158 if (!virq) { 1159 if (!virq) {
1159 ret = -EINVAL; 1160 ret = -EINVAL;
1160 goto err_irq; 1161 goto err_irq;
@@ -1204,7 +1205,7 @@ static int max77693_muic_probe(struct platform_device *pdev)
1204 enum max77693_irq_source irq_src 1205 enum max77693_irq_source irq_src
1205 = MAX77693_IRQ_GROUP_NR; 1206 = MAX77693_IRQ_GROUP_NR;
1206 1207
1207 max77693_write_reg(info->max77693->regmap_muic, 1208 regmap_write(info->max77693->regmap_muic,
1208 init_data[i].addr, 1209 init_data[i].addr,
1209 init_data[i].data); 1210 init_data[i].data);
1210 1211
@@ -1262,7 +1263,7 @@ static int max77693_muic_probe(struct platform_device *pdev)
1262 max77693_muic_set_path(info, info->path_uart, true); 1263 max77693_muic_set_path(info, info->path_uart, true);
1263 1264
1264 /* Check revision number of MUIC device*/ 1265 /* Check revision number of MUIC device*/
1265 ret = max77693_read_reg(info->max77693->regmap_muic, 1266 ret = regmap_read(info->max77693->regmap_muic,
1266 MAX77693_MUIC_REG_ID, &id); 1267 MAX77693_MUIC_REG_ID, &id);
1267 if (ret < 0) { 1268 if (ret < 0) {
1268 dev_err(&pdev->dev, "failed to read revision number\n"); 1269 dev_err(&pdev->dev, "failed to read revision number\n");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index ee8204cc31e9..2feac14d1085 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -384,6 +384,7 @@ config MFD_MAX77693
384 depends on I2C=y 384 depends on I2C=y
385 select MFD_CORE 385 select MFD_CORE
386 select REGMAP_I2C 386 select REGMAP_I2C
387 select REGMAP_IRQ
387 help 388 help
388 Say yes here to add support for Maxim Semiconductor MAX77693. 389 Say yes here to add support for Maxim Semiconductor MAX77693.
389 This is a companion Power Management IC with Flash, Haptic, Charger, 390 This is a companion Power Management IC with Flash, Haptic, Charger,
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8afedba535c7..8c6e7bba4660 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -116,7 +116,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
116 116
117obj-$(CONFIG_MFD_MAX14577) += max14577.o 117obj-$(CONFIG_MFD_MAX14577) += max14577.o
118obj-$(CONFIG_MFD_MAX77686) += max77686.o max77686-irq.o 118obj-$(CONFIG_MFD_MAX77686) += max77686.o max77686-irq.o
119obj-$(CONFIG_MFD_MAX77693) += max77693.o max77693-irq.o 119obj-$(CONFIG_MFD_MAX77693) += max77693.o
120obj-$(CONFIG_MFD_MAX8907) += max8907.o 120obj-$(CONFIG_MFD_MAX8907) += max8907.o
121max8925-objs := max8925-core.o max8925-i2c.o 121max8925-objs := max8925-core.o max8925-i2c.o
122obj-$(CONFIG_MFD_MAX8925) += max8925.o 122obj-$(CONFIG_MFD_MAX8925) += max8925.o
diff --git a/drivers/mfd/max77693-irq.c b/drivers/mfd/max77693-irq.c
deleted file mode 100644
index 66b58fe77094..000000000000
--- a/drivers/mfd/max77693-irq.c
+++ /dev/null
@@ -1,336 +0,0 @@
1/*
2 * max77693-irq.c - Interrupt controller support for MAX77693
3 *
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * SangYoung Son <hello.son@samsung.com>
6 *
7 * This program is not provided / owned by Maxim Integrated Products.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 * This driver is based on max8997-irq.c
24 */
25
26#include <linux/err.h>
27#include <linux/irq.h>
28#include <linux/interrupt.h>
29#include <linux/module.h>
30#include <linux/irqdomain.h>
31#include <linux/mfd/max77693.h>
32#include <linux/mfd/max77693-private.h>
33
34static const u8 max77693_mask_reg[] = {
35 [LED_INT] = MAX77693_LED_REG_FLASH_INT_MASK,
36 [TOPSYS_INT] = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
37 [CHG_INT] = MAX77693_CHG_REG_CHG_INT_MASK,
38 [MUIC_INT1] = MAX77693_MUIC_REG_INTMASK1,
39 [MUIC_INT2] = MAX77693_MUIC_REG_INTMASK2,
40 [MUIC_INT3] = MAX77693_MUIC_REG_INTMASK3,
41};
42
43static struct regmap *max77693_get_regmap(struct max77693_dev *max77693,
44 enum max77693_irq_source src)
45{
46 switch (src) {
47 case LED_INT ... CHG_INT:
48 return max77693->regmap;
49 case MUIC_INT1 ... MUIC_INT3:
50 return max77693->regmap_muic;
51 default:
52 return ERR_PTR(-EINVAL);
53 }
54}
55
56struct max77693_irq_data {
57 int mask;
58 enum max77693_irq_source group;
59};
60
61#define DECLARE_IRQ(idx, _group, _mask) \
62 [(idx)] = { .group = (_group), .mask = (_mask) }
63static const struct max77693_irq_data max77693_irqs[] = {
64 DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0),
65 DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1),
66 DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2),
67 DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3),
68 DECLARE_IRQ(MAX77693_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4),
69
70 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0),
71 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1),
72 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_LOWSYS_INT, TOPSYS_INT, 1 << 3),
73
74 DECLARE_IRQ(MAX77693_CHG_IRQ_BYP_I, CHG_INT, 1 << 0),
75 DECLARE_IRQ(MAX77693_CHG_IRQ_THM_I, CHG_INT, 1 << 2),
76 DECLARE_IRQ(MAX77693_CHG_IRQ_BAT_I, CHG_INT, 1 << 3),
77 DECLARE_IRQ(MAX77693_CHG_IRQ_CHG_I, CHG_INT, 1 << 4),
78 DECLARE_IRQ(MAX77693_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6),
79
80 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0),
81 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_LOW, MUIC_INT1, 1 << 1),
82 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_ERR, MUIC_INT1, 1 << 2),
83 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3),
84
85 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0),
86 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1),
87 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2),
88 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3),
89 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4),
90 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VIDRM, MUIC_INT2, 1 << 5),
91
92 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_EOC, MUIC_INT3, 1 << 0),
93 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CGMBC, MUIC_INT3, 1 << 1),
94 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_OVP, MUIC_INT3, 1 << 2),
95 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, MUIC_INT3, 1 << 3),
96 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, MUIC_INT3, 1 << 4),
97 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_BAT_DET, MUIC_INT3, 1 << 5),
98};
99
100static void max77693_irq_lock(struct irq_data *data)
101{
102 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
103
104 mutex_lock(&max77693->irqlock);
105}
106
107static void max77693_irq_sync_unlock(struct irq_data *data)
108{
109 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
110 int i;
111
112 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
113 u8 mask_reg = max77693_mask_reg[i];
114 struct regmap *map = max77693_get_regmap(max77693, i);
115
116 if (mask_reg == MAX77693_REG_INVALID ||
117 IS_ERR_OR_NULL(map))
118 continue;
119 max77693->irq_masks_cache[i] = max77693->irq_masks_cur[i];
120
121 max77693_write_reg(map, max77693_mask_reg[i],
122 max77693->irq_masks_cur[i]);
123 }
124
125 mutex_unlock(&max77693->irqlock);
126}
127
128static const inline struct max77693_irq_data *
129irq_to_max77693_irq(struct max77693_dev *max77693, int irq)
130{
131 struct irq_data *data = irq_get_irq_data(irq);
132 return &max77693_irqs[data->hwirq];
133}
134
135static void max77693_irq_mask(struct irq_data *data)
136{
137 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
138 const struct max77693_irq_data *irq_data =
139 irq_to_max77693_irq(max77693, data->irq);
140
141 if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
142 return;
143
144 if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
145 max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
146 else
147 max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
148}
149
150static void max77693_irq_unmask(struct irq_data *data)
151{
152 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
153 const struct max77693_irq_data *irq_data =
154 irq_to_max77693_irq(max77693, data->irq);
155
156 if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
157 return;
158
159 if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
160 max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
161 else
162 max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
163}
164
165static struct irq_chip max77693_irq_chip = {
166 .name = "max77693",
167 .irq_bus_lock = max77693_irq_lock,
168 .irq_bus_sync_unlock = max77693_irq_sync_unlock,
169 .irq_mask = max77693_irq_mask,
170 .irq_unmask = max77693_irq_unmask,
171};
172
173#define MAX77693_IRQSRC_CHG (1 << 0)
174#define MAX77693_IRQSRC_TOP (1 << 1)
175#define MAX77693_IRQSRC_FLASH (1 << 2)
176#define MAX77693_IRQSRC_MUIC (1 << 3)
177static irqreturn_t max77693_irq_thread(int irq, void *data)
178{
179 struct max77693_dev *max77693 = data;
180 u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {};
181 u8 irq_src;
182 int ret;
183 int i, cur_irq;
184
185 ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_INTSRC,
186 &irq_src);
187 if (ret < 0) {
188 dev_err(max77693->dev, "Failed to read interrupt source: %d\n",
189 ret);
190 return IRQ_NONE;
191 }
192
193 if (irq_src & MAX77693_IRQSRC_CHG)
194 /* CHG_INT */
195 ret = max77693_read_reg(max77693->regmap, MAX77693_CHG_REG_CHG_INT,
196 &irq_reg[CHG_INT]);
197
198 if (irq_src & MAX77693_IRQSRC_TOP)
199 /* TOPSYS_INT */
200 ret = max77693_read_reg(max77693->regmap,
201 MAX77693_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]);
202
203 if (irq_src & MAX77693_IRQSRC_FLASH)
204 /* LED_INT */
205 ret = max77693_read_reg(max77693->regmap,
206 MAX77693_LED_REG_FLASH_INT, &irq_reg[LED_INT]);
207
208 if (irq_src & MAX77693_IRQSRC_MUIC)
209 /* MUIC INT1 ~ INT3 */
210 max77693_bulk_read(max77693->regmap_muic, MAX77693_MUIC_REG_INT1,
211 MAX77693_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]);
212
213 /* Apply masking */
214 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
215 if (i >= MUIC_INT1 && i <= MUIC_INT3)
216 irq_reg[i] &= max77693->irq_masks_cur[i];
217 else
218 irq_reg[i] &= ~max77693->irq_masks_cur[i];
219 }
220
221 /* Report */
222 for (i = 0; i < MAX77693_IRQ_NR; i++) {
223 if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask) {
224 cur_irq = irq_find_mapping(max77693->irq_domain, i);
225 if (cur_irq)
226 handle_nested_irq(cur_irq);
227 }
228 }
229
230 return IRQ_HANDLED;
231}
232
233int max77693_irq_resume(struct max77693_dev *max77693)
234{
235 if (max77693->irq)
236 max77693_irq_thread(0, max77693);
237
238 return 0;
239}
240
241static int max77693_irq_domain_map(struct irq_domain *d, unsigned int irq,
242 irq_hw_number_t hw)
243{
244 struct max77693_dev *max77693 = d->host_data;
245
246 irq_set_chip_data(irq, max77693);
247 irq_set_chip_and_handler(irq, &max77693_irq_chip, handle_edge_irq);
248 irq_set_nested_thread(irq, 1);
249#ifdef CONFIG_ARM
250 set_irq_flags(irq, IRQF_VALID);
251#else
252 irq_set_noprobe(irq);
253#endif
254 return 0;
255}
256
257static struct irq_domain_ops max77693_irq_domain_ops = {
258 .map = max77693_irq_domain_map,
259};
260
261int max77693_irq_init(struct max77693_dev *max77693)
262{
263 struct irq_domain *domain;
264 int i;
265 int ret = 0;
266 u8 intsrc_mask;
267
268 mutex_init(&max77693->irqlock);
269
270 /* Mask individual interrupt sources */
271 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
272 struct regmap *map;
273 /* MUIC IRQ 0:MASK 1:NOT MASK */
274 /* Other IRQ 1:MASK 0:NOT MASK */
275 if (i >= MUIC_INT1 && i <= MUIC_INT3) {
276 max77693->irq_masks_cur[i] = 0x00;
277 max77693->irq_masks_cache[i] = 0x00;
278 } else {
279 max77693->irq_masks_cur[i] = 0xff;
280 max77693->irq_masks_cache[i] = 0xff;
281 }
282 map = max77693_get_regmap(max77693, i);
283
284 if (IS_ERR_OR_NULL(map))
285 continue;
286 if (max77693_mask_reg[i] == MAX77693_REG_INVALID)
287 continue;
288 if (i >= MUIC_INT1 && i <= MUIC_INT3)
289 max77693_write_reg(map, max77693_mask_reg[i], 0x00);
290 else
291 max77693_write_reg(map, max77693_mask_reg[i], 0xff);
292 }
293
294 domain = irq_domain_add_linear(NULL, MAX77693_IRQ_NR,
295 &max77693_irq_domain_ops, max77693);
296 if (!domain) {
297 dev_err(max77693->dev, "could not create irq domain\n");
298 ret = -ENODEV;
299 goto err_irq;
300 }
301 max77693->irq_domain = domain;
302
303 /* Unmask max77693 interrupt */
304 ret = max77693_read_reg(max77693->regmap,
305 MAX77693_PMIC_REG_INTSRC_MASK, &intsrc_mask);
306 if (ret < 0) {
307 dev_err(max77693->dev, "fail to read PMIC register\n");
308 goto err_irq;
309 }
310
311 intsrc_mask &= ~(MAX77693_IRQSRC_CHG);
312 intsrc_mask &= ~(MAX77693_IRQSRC_FLASH);
313 intsrc_mask &= ~(MAX77693_IRQSRC_MUIC);
314 ret = max77693_write_reg(max77693->regmap,
315 MAX77693_PMIC_REG_INTSRC_MASK, intsrc_mask);
316 if (ret < 0) {
317 dev_err(max77693->dev, "fail to write PMIC register\n");
318 goto err_irq;
319 }
320
321 ret = request_threaded_irq(max77693->irq, NULL, max77693_irq_thread,
322 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
323 "max77693-irq", max77693);
324 if (ret)
325 dev_err(max77693->dev, "Failed to request IRQ %d: %d\n",
326 max77693->irq, ret);
327
328err_irq:
329 return ret;
330}
331
332void max77693_irq_exit(struct max77693_dev *max77693)
333{
334 if (max77693->irq)
335 free_irq(max77693->irq, max77693);
336}
diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c
index 7e05428c756d..249c139ef04a 100644
--- a/drivers/mfd/max77693.c
+++ b/drivers/mfd/max77693.c
@@ -49,62 +49,62 @@ static const struct mfd_cell max77693_devs[] = {
49 { .name = "max77693-haptic", }, 49 { .name = "max77693-haptic", },
50}; 50};
51 51
52int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest) 52static const struct regmap_config max77693_regmap_config = {
53{ 53 .reg_bits = 8,
54 unsigned int val; 54 .val_bits = 8,
55 int ret; 55 .max_register = MAX77693_PMIC_REG_END,
56 56};
57 ret = regmap_read(map, reg, &val);
58 *dest = val;
59
60 return ret;
61}
62EXPORT_SYMBOL_GPL(max77693_read_reg);
63
64int max77693_bulk_read(struct regmap *map, u8 reg, int count, u8 *buf)
65{
66 int ret;
67
68 ret = regmap_bulk_read(map, reg, buf, count);
69
70 return ret;
71}
72EXPORT_SYMBOL_GPL(max77693_bulk_read);
73
74int max77693_write_reg(struct regmap *map, u8 reg, u8 value)
75{
76 int ret;
77
78 ret = regmap_write(map, reg, value);
79
80 return ret;
81}
82EXPORT_SYMBOL_GPL(max77693_write_reg);
83
84int max77693_bulk_write(struct regmap *map, u8 reg, int count, u8 *buf)
85{
86 int ret;
87 57
88 ret = regmap_bulk_write(map, reg, buf, count); 58static const struct regmap_irq max77693_led_irqs[] = {
59 { .mask = LED_IRQ_FLED2_OPEN, },
60 { .mask = LED_IRQ_FLED2_SHORT, },
61 { .mask = LED_IRQ_FLED1_OPEN, },
62 { .mask = LED_IRQ_FLED1_SHORT, },
63 { .mask = LED_IRQ_MAX_FLASH, },
64};
89 65
90 return ret; 66static const struct regmap_irq_chip max77693_led_irq_chip = {
91} 67 .name = "max77693-led",
92EXPORT_SYMBOL_GPL(max77693_bulk_write); 68 .status_base = MAX77693_LED_REG_FLASH_INT,
69 .mask_base = MAX77693_LED_REG_FLASH_INT_MASK,
70 .mask_invert = false,
71 .num_regs = 1,
72 .irqs = max77693_led_irqs,
73 .num_irqs = ARRAY_SIZE(max77693_led_irqs),
74};
93 75
94int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask) 76static const struct regmap_irq max77693_topsys_irqs[] = {
95{ 77 { .mask = TOPSYS_IRQ_T120C_INT, },
96 int ret; 78 { .mask = TOPSYS_IRQ_T140C_INT, },
79 { .mask = TOPSYS_IRQ_LOWSYS_INT, },
80};
97 81
98 ret = regmap_update_bits(map, reg, mask, val); 82static const struct regmap_irq_chip max77693_topsys_irq_chip = {
83 .name = "max77693-topsys",
84 .status_base = MAX77693_PMIC_REG_TOPSYS_INT,
85 .mask_base = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
86 .mask_invert = false,
87 .num_regs = 1,
88 .irqs = max77693_topsys_irqs,
89 .num_irqs = ARRAY_SIZE(max77693_topsys_irqs),
90};
99 91
100 return ret; 92static const struct regmap_irq max77693_charger_irqs[] = {
101} 93 { .mask = CHG_IRQ_BYP_I, },
102EXPORT_SYMBOL_GPL(max77693_update_reg); 94 { .mask = CHG_IRQ_THM_I, },
95 { .mask = CHG_IRQ_BAT_I, },
96 { .mask = CHG_IRQ_CHG_I, },
97 { .mask = CHG_IRQ_CHGIN_I, },
98};
103 99
104static const struct regmap_config max77693_regmap_config = { 100static const struct regmap_irq_chip max77693_charger_irq_chip = {
105 .reg_bits = 8, 101 .name = "max77693-charger",
106 .val_bits = 8, 102 .status_base = MAX77693_CHG_REG_CHG_INT,
107 .max_register = MAX77693_PMIC_REG_END, 103 .mask_base = MAX77693_CHG_REG_CHG_INT_MASK,
104 .mask_invert = false,
105 .num_regs = 1,
106 .irqs = max77693_charger_irqs,
107 .num_irqs = ARRAY_SIZE(max77693_charger_irqs),
108}; 108};
109 109
110static const struct regmap_config max77693_regmap_muic_config = { 110static const struct regmap_config max77693_regmap_muic_config = {
@@ -113,11 +113,42 @@ static const struct regmap_config max77693_regmap_muic_config = {
113 .max_register = MAX77693_MUIC_REG_END, 113 .max_register = MAX77693_MUIC_REG_END,
114}; 114};
115 115
116static const struct regmap_irq max77693_muic_irqs[] = {
117 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },
118 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },
119 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, },
120 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },
121
122 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },
123 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, },
124 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },
125 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },
126 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },
127 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, },
128
129 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, },
130 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, },
131 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_OVP, },
132 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_MBCCHG_ERR, },
133 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CHG_ENABLED, },
134 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_BAT_DET, },
135};
136
137static const struct regmap_irq_chip max77693_muic_irq_chip = {
138 .name = "max77693-muic",
139 .status_base = MAX77693_MUIC_REG_INT1,
140 .mask_base = MAX77693_MUIC_REG_INTMASK1,
141 .mask_invert = true,
142 .num_regs = 3,
143 .irqs = max77693_muic_irqs,
144 .num_irqs = ARRAY_SIZE(max77693_muic_irqs),
145};
146
116static int max77693_i2c_probe(struct i2c_client *i2c, 147static int max77693_i2c_probe(struct i2c_client *i2c,
117 const struct i2c_device_id *id) 148 const struct i2c_device_id *id)
118{ 149{
119 struct max77693_dev *max77693; 150 struct max77693_dev *max77693;
120 u8 reg_data; 151 unsigned int reg_data;
121 int ret = 0; 152 int ret = 0;
122 153
123 max77693 = devm_kzalloc(&i2c->dev, 154 max77693 = devm_kzalloc(&i2c->dev,
@@ -139,7 +170,7 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
139 return ret; 170 return ret;
140 } 171 }
141 172
142 ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_PMIC_ID2, 173 ret = regmap_read(max77693->regmap, MAX77693_PMIC_REG_PMIC_ID2,
143 &reg_data); 174 &reg_data);
144 if (ret < 0) { 175 if (ret < 0) {
145 dev_err(max77693->dev, "device not found on this channel\n"); 176 dev_err(max77693->dev, "device not found on this channel\n");
@@ -176,9 +207,45 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
176 goto err_regmap_muic; 207 goto err_regmap_muic;
177 } 208 }
178 209
179 ret = max77693_irq_init(max77693); 210 ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
180 if (ret < 0) 211 IRQF_ONESHOT | IRQF_SHARED |
181 goto err_irq; 212 IRQF_TRIGGER_FALLING, 0,
213 &max77693_led_irq_chip,
214 &max77693->irq_data_led);
215 if (ret) {
216 dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
217 goto err_regmap_muic;
218 }
219
220 ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
221 IRQF_ONESHOT | IRQF_SHARED |
222 IRQF_TRIGGER_FALLING, 0,
223 &max77693_topsys_irq_chip,
224 &max77693->irq_data_topsys);
225 if (ret) {
226 dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
227 goto err_irq_topsys;
228 }
229
230 ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
231 IRQF_ONESHOT | IRQF_SHARED |
232 IRQF_TRIGGER_FALLING, 0,
233 &max77693_charger_irq_chip,
234 &max77693->irq_data_charger);
235 if (ret) {
236 dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
237 goto err_irq_charger;
238 }
239
240 ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
241 IRQF_ONESHOT | IRQF_SHARED |
242 IRQF_TRIGGER_FALLING, 0,
243 &max77693_muic_irq_chip,
244 &max77693->irq_data_muic);
245 if (ret) {
246 dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
247 goto err_irq_muic;
248 }
182 249
183 pm_runtime_set_active(max77693->dev); 250 pm_runtime_set_active(max77693->dev);
184 251
@@ -190,8 +257,14 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
190 return ret; 257 return ret;
191 258
192err_mfd: 259err_mfd:
193 max77693_irq_exit(max77693); 260 mfd_remove_devices(max77693->dev);
194err_irq: 261 regmap_del_irq_chip(max77693->irq, max77693->irq_data_muic);
262err_irq_muic:
263 regmap_del_irq_chip(max77693->irq, max77693->irq_data_charger);
264err_irq_charger:
265 regmap_del_irq_chip(max77693->irq, max77693->irq_data_topsys);
266err_irq_topsys:
267 regmap_del_irq_chip(max77693->irq, max77693->irq_data_led);
195err_regmap_muic: 268err_regmap_muic:
196 i2c_unregister_device(max77693->haptic); 269 i2c_unregister_device(max77693->haptic);
197err_i2c_haptic: 270err_i2c_haptic:
@@ -204,7 +277,12 @@ static int max77693_i2c_remove(struct i2c_client *i2c)
204 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 277 struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
205 278
206 mfd_remove_devices(max77693->dev); 279 mfd_remove_devices(max77693->dev);
207 max77693_irq_exit(max77693); 280
281 regmap_del_irq_chip(max77693->irq, max77693->irq_data_muic);
282 regmap_del_irq_chip(max77693->irq, max77693->irq_data_charger);
283 regmap_del_irq_chip(max77693->irq, max77693->irq_data_topsys);
284 regmap_del_irq_chip(max77693->irq, max77693->irq_data_led);
285
208 i2c_unregister_device(max77693->muic); 286 i2c_unregister_device(max77693->muic);
209 i2c_unregister_device(max77693->haptic); 287 i2c_unregister_device(max77693->haptic);
210 288
@@ -222,8 +300,11 @@ static int max77693_suspend(struct device *dev)
222 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 300 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
223 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 301 struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
224 302
225 if (device_may_wakeup(dev)) 303 if (device_may_wakeup(dev)) {
226 irq_set_irq_wake(max77693->irq, 1); 304 enable_irq_wake(max77693->irq);
305 disable_irq(max77693->irq);
306 }
307
227 return 0; 308 return 0;
228} 309}
229 310
@@ -232,9 +313,12 @@ static int max77693_resume(struct device *dev)
232 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 313 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
233 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 314 struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
234 315
235 if (device_may_wakeup(dev)) 316 if (device_may_wakeup(dev)) {
236 irq_set_irq_wake(max77693->irq, 0); 317 disable_irq_wake(max77693->irq);
237 return max77693_irq_resume(max77693); 318 enable_irq(max77693->irq);
319 }
320
321 return 0;
238} 322}
239 323
240static const struct dev_pm_ops max77693_pm = { 324static const struct dev_pm_ops max77693_pm = {
diff --git a/drivers/regulator/max77693.c b/drivers/regulator/max77693.c
index 653a58b49cdf..c67ff05fc1dd 100644
--- a/drivers/regulator/max77693.c
+++ b/drivers/regulator/max77693.c
@@ -31,6 +31,7 @@
31#include <linux/mfd/max77693.h> 31#include <linux/mfd/max77693.h>
32#include <linux/mfd/max77693-private.h> 32#include <linux/mfd/max77693-private.h>
33#include <linux/regulator/of_regulator.h> 33#include <linux/regulator/of_regulator.h>
34#include <linux/regmap.h>
34 35
35#define CHGIN_ILIM_STEP_20mA 20000 36#define CHGIN_ILIM_STEP_20mA 20000
36 37
@@ -39,9 +40,9 @@
39static int max77693_chg_is_enabled(struct regulator_dev *rdev) 40static int max77693_chg_is_enabled(struct regulator_dev *rdev)
40{ 41{
41 int ret; 42 int ret;
42 u8 val; 43 unsigned int val;
43 44
44 ret = max77693_read_reg(rdev->regmap, rdev->desc->enable_reg, &val); 45 ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val);
45 if (ret) 46 if (ret)
46 return ret; 47 return ret;
47 48
@@ -57,12 +58,11 @@ static int max77693_chg_get_current_limit(struct regulator_dev *rdev)
57{ 58{
58 unsigned int chg_min_uA = rdev->constraints->min_uA; 59 unsigned int chg_min_uA = rdev->constraints->min_uA;
59 unsigned int chg_max_uA = rdev->constraints->max_uA; 60 unsigned int chg_max_uA = rdev->constraints->max_uA;
60 u8 reg, sel; 61 unsigned int reg, sel;
61 unsigned int val; 62 unsigned int val;
62 int ret; 63 int ret;
63 64
64 ret = max77693_read_reg(rdev->regmap, 65 ret = regmap_read(rdev->regmap, MAX77693_CHG_REG_CHG_CNFG_09, &reg);
65 MAX77693_CHG_REG_CHG_CNFG_09, &reg);
66 if (ret < 0) 66 if (ret < 0)
67 return ret; 67 return ret;
68 68
@@ -96,7 +96,7 @@ static int max77693_chg_set_current_limit(struct regulator_dev *rdev,
96 /* the first four codes for charger current are all 60mA */ 96 /* the first four codes for charger current are all 60mA */
97 sel += 3; 97 sel += 3;
98 98
99 return max77693_write_reg(rdev->regmap, 99 return regmap_write(rdev->regmap,
100 MAX77693_CHG_REG_CHG_CNFG_09, sel); 100 MAX77693_CHG_REG_CHG_CNFG_09, sel);
101} 101}
102/* end of CHARGER regulator ops */ 102/* end of CHARGER regulator ops */
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
index 3e050b933dd0..c466ff3e16b8 100644
--- a/include/linux/mfd/max77693-private.h
+++ b/include/linux/mfd/max77693-private.h
@@ -262,6 +262,41 @@ enum max77693_irq_source {
262 MAX77693_IRQ_GROUP_NR, 262 MAX77693_IRQ_GROUP_NR,
263}; 263};
264 264
265#define LED_IRQ_FLED2_OPEN BIT(0)
266#define LED_IRQ_FLED2_SHORT BIT(1)
267#define LED_IRQ_FLED1_OPEN BIT(2)
268#define LED_IRQ_FLED1_SHORT BIT(3)
269#define LED_IRQ_MAX_FLASH BIT(4)
270
271#define TOPSYS_IRQ_T120C_INT BIT(0)
272#define TOPSYS_IRQ_T140C_INT BIT(1)
273#define TOPSYS_IRQ_LOWSYS_INT BIT(3)
274
275#define CHG_IRQ_BYP_I BIT(0)
276#define CHG_IRQ_THM_I BIT(2)
277#define CHG_IRQ_BAT_I BIT(3)
278#define CHG_IRQ_CHG_I BIT(4)
279#define CHG_IRQ_CHGIN_I BIT(6)
280
281#define MUIC_IRQ_INT1_ADC BIT(0)
282#define MUIC_IRQ_INT1_ADC_LOW BIT(1)
283#define MUIC_IRQ_INT1_ADC_ERR BIT(2)
284#define MUIC_IRQ_INT1_ADC1K BIT(3)
285
286#define MUIC_IRQ_INT2_CHGTYP BIT(0)
287#define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
288#define MUIC_IRQ_INT2_DCDTMR BIT(2)
289#define MUIC_IRQ_INT2_DXOVP BIT(3)
290#define MUIC_IRQ_INT2_VBVOLT BIT(4)
291#define MUIC_IRQ_INT2_VIDRM BIT(5)
292
293#define MUIC_IRQ_INT3_EOC BIT(0)
294#define MUIC_IRQ_INT3_CGMBC BIT(1)
295#define MUIC_IRQ_INT3_OVP BIT(2)
296#define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
297#define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
298#define MUIC_IRQ_INT3_BAT_DET BIT(5)
299
265enum max77693_irq { 300enum max77693_irq {
266 /* PMIC - FLASH */ 301 /* PMIC - FLASH */
267 MAX77693_LED_IRQ_FLED2_OPEN, 302 MAX77693_LED_IRQ_FLED2_OPEN,
@@ -282,6 +317,10 @@ enum max77693_irq {
282 MAX77693_CHG_IRQ_CHG_I, 317 MAX77693_CHG_IRQ_CHG_I,
283 MAX77693_CHG_IRQ_CHGIN_I, 318 MAX77693_CHG_IRQ_CHGIN_I,
284 319
320 MAX77693_IRQ_NR,
321};
322
323enum max77693_irq_muic {
285 /* MUIC INT1 */ 324 /* MUIC INT1 */
286 MAX77693_MUIC_IRQ_INT1_ADC, 325 MAX77693_MUIC_IRQ_INT1_ADC,
287 MAX77693_MUIC_IRQ_INT1_ADC_LOW, 326 MAX77693_MUIC_IRQ_INT1_ADC_LOW,
@@ -304,7 +343,7 @@ enum max77693_irq {
304 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, 343 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
305 MAX77693_MUIC_IRQ_INT3_BAT_DET, 344 MAX77693_MUIC_IRQ_INT3_BAT_DET,
306 345
307 MAX77693_IRQ_NR, 346 MAX77693_MUIC_IRQ_NR,
308}; 347};
309 348
310struct max77693_dev { 349struct max77693_dev {
@@ -319,7 +358,10 @@ struct max77693_dev {
319 struct regmap *regmap_muic; 358 struct regmap *regmap_muic;
320 struct regmap *regmap_haptic; 359 struct regmap *regmap_haptic;
321 360
322 struct irq_domain *irq_domain; 361 struct regmap_irq_chip_data *irq_data_led;
362 struct regmap_irq_chip_data *irq_data_topsys;
363 struct regmap_irq_chip_data *irq_data_charger;
364 struct regmap_irq_chip_data *irq_data_muic;
323 365
324 int irq; 366 int irq;
325 int irq_gpio; 367 int irq_gpio;
@@ -332,14 +374,6 @@ enum max77693_types {
332 TYPE_MAX77693, 374 TYPE_MAX77693,
333}; 375};
334 376
335extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest);
336extern int max77693_bulk_read(struct regmap *map, u8 reg, int count,
337 u8 *buf);
338extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value);
339extern int max77693_bulk_write(struct regmap *map, u8 reg, int count,
340 u8 *buf);
341extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask);
342
343extern int max77693_irq_init(struct max77693_dev *max77686); 377extern int max77693_irq_init(struct max77693_dev *max77686);
344extern void max77693_irq_exit(struct max77693_dev *max77686); 378extern void max77693_irq_exit(struct max77693_dev *max77686);
345extern int max77693_irq_resume(struct max77693_dev *max77686); 379extern int max77693_irq_resume(struct max77693_dev *max77686);