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-rw-r--r--drivers/media/platform/ti-vpe/Makefile2
-rw-r--r--drivers/media/platform/ti-vpe/sc.c91
-rw-r--r--drivers/media/platform/ti-vpe/sc.h175
-rw-r--r--drivers/media/platform/ti-vpe/vpe.c60
-rw-r--r--drivers/media/platform/ti-vpe/vpe_regs.h149
5 files changed, 288 insertions, 189 deletions
diff --git a/drivers/media/platform/ti-vpe/Makefile b/drivers/media/platform/ti-vpe/Makefile
index cbf0a806ba1d..54c30b31c4cb 100644
--- a/drivers/media/platform/ti-vpe/Makefile
+++ b/drivers/media/platform/ti-vpe/Makefile
@@ -1,5 +1,5 @@
1obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe.o 1obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe.o
2 2
3ti-vpe-y := vpe.o vpdma.o 3ti-vpe-y := vpe.o sc.o vpdma.o
4 4
5ccflags-$(CONFIG_VIDEO_TI_VPE_DEBUG) += -DDEBUG 5ccflags-$(CONFIG_VIDEO_TI_VPE_DEBUG) += -DDEBUG
diff --git a/drivers/media/platform/ti-vpe/sc.c b/drivers/media/platform/ti-vpe/sc.c
new file mode 100644
index 000000000000..f21dfbb77057
--- /dev/null
+++ b/drivers/media/platform/ti-vpe/sc.c
@@ -0,0 +1,91 @@
1/*
2 * Scaler library
3 *
4 * Copyright (c) 2013 Texas Instruments Inc.
5 *
6 * David Griego, <dagriego@biglakesoftware.com>
7 * Dale Farnsworth, <dale@farnsworth.org>
8 * Archit Taneja, <archit@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 */
14
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19
20#include "sc.h"
21
22void sc_set_regs_bypass(struct sc_data *sc, u32 *sc_reg0)
23{
24 *sc_reg0 |= CFG_SC_BYPASS;
25}
26
27void sc_dump_regs(struct sc_data *sc)
28{
29 struct device *dev = &sc->pdev->dev;
30
31 u32 read_reg(struct sc_data *sc, int offset)
32 {
33 return ioread32(sc->base + offset);
34 }
35
36#define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(sc, CFG_##r))
37
38 DUMPREG(SC0);
39 DUMPREG(SC1);
40 DUMPREG(SC2);
41 DUMPREG(SC3);
42 DUMPREG(SC4);
43 DUMPREG(SC5);
44 DUMPREG(SC6);
45 DUMPREG(SC8);
46 DUMPREG(SC9);
47 DUMPREG(SC10);
48 DUMPREG(SC11);
49 DUMPREG(SC12);
50 DUMPREG(SC13);
51 DUMPREG(SC17);
52 DUMPREG(SC18);
53 DUMPREG(SC19);
54 DUMPREG(SC20);
55 DUMPREG(SC21);
56 DUMPREG(SC22);
57 DUMPREG(SC23);
58 DUMPREG(SC24);
59 DUMPREG(SC25);
60
61#undef DUMPREG
62}
63
64struct sc_data *sc_create(struct platform_device *pdev)
65{
66 struct sc_data *sc;
67
68 dev_dbg(&pdev->dev, "sc_create\n");
69
70 sc = devm_kzalloc(&pdev->dev, sizeof(*sc), GFP_KERNEL);
71 if (!sc) {
72 dev_err(&pdev->dev, "couldn't alloc sc_data\n");
73 return ERR_PTR(-ENOMEM);
74 }
75
76 sc->pdev = pdev;
77
78 sc->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sc");
79 if (!sc->res) {
80 dev_err(&pdev->dev, "missing platform resources data\n");
81 return ERR_PTR(-ENODEV);
82 }
83
84 sc->base = devm_ioremap_resource(&pdev->dev, sc->res);
85 if (!sc->base) {
86 dev_err(&pdev->dev, "failed to ioremap\n");
87 return ERR_PTR(-ENOMEM);
88 }
89
90 return sc;
91}
diff --git a/drivers/media/platform/ti-vpe/sc.h b/drivers/media/platform/ti-vpe/sc.h
new file mode 100644
index 000000000000..924854465c5d
--- /dev/null
+++ b/drivers/media/platform/ti-vpe/sc.h
@@ -0,0 +1,175 @@
1/*
2 * Copyright (c) 2013 Texas Instruments Inc.
3 *
4 * David Griego, <dagriego@biglakesoftware.com>
5 * Dale Farnsworth, <dale@farnsworth.org>
6 * Archit Taneja, <archit@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 */
12#ifndef TI_SC_H
13#define TI_SC_H
14
15/* Scaler regs */
16#define CFG_SC0 0x0
17#define CFG_INTERLACE_O (1 << 0)
18#define CFG_LINEAR (1 << 1)
19#define CFG_SC_BYPASS (1 << 2)
20#define CFG_INVT_FID (1 << 3)
21#define CFG_USE_RAV (1 << 4)
22#define CFG_ENABLE_EV (1 << 5)
23#define CFG_AUTO_HS (1 << 6)
24#define CFG_DCM_2X (1 << 7)
25#define CFG_DCM_4X (1 << 8)
26#define CFG_HP_BYPASS (1 << 9)
27#define CFG_INTERLACE_I (1 << 10)
28#define CFG_ENABLE_SIN2_VER_INTP (1 << 11)
29#define CFG_Y_PK_EN (1 << 14)
30#define CFG_TRIM (1 << 15)
31#define CFG_SELFGEN_FID (1 << 16)
32
33#define CFG_SC1 0x4
34#define CFG_ROW_ACC_INC_MASK 0x07ffffff
35#define CFG_ROW_ACC_INC_SHIFT 0
36
37#define CFG_SC2 0x08
38#define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff
39#define CFG_ROW_ACC_OFFSET_SHIFT 0
40
41#define CFG_SC3 0x0c
42#define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff
43#define CFG_ROW_ACC_OFFSET_B_SHIFT 0
44
45#define CFG_SC4 0x10
46#define CFG_TAR_H_MASK 0x07ff
47#define CFG_TAR_H_SHIFT 0
48#define CFG_TAR_W_MASK 0x07ff
49#define CFG_TAR_W_SHIFT 12
50#define CFG_LIN_ACC_INC_U_MASK 0x07
51#define CFG_LIN_ACC_INC_U_SHIFT 24
52#define CFG_NLIN_ACC_INIT_U_MASK 0x07
53#define CFG_NLIN_ACC_INIT_U_SHIFT 28
54
55#define CFG_SC5 0x14
56#define CFG_SRC_H_MASK 0x07ff
57#define CFG_SRC_H_SHIFT 0
58#define CFG_SRC_W_MASK 0x07ff
59#define CFG_SRC_W_SHIFT 12
60#define CFG_NLIN_ACC_INC_U_MASK 0x07
61#define CFG_NLIN_ACC_INC_U_SHIFT 24
62
63#define CFG_SC6 0x18
64#define CFG_ROW_ACC_INIT_RAV_MASK 0x03ff
65#define CFG_ROW_ACC_INIT_RAV_SHIFT 0
66#define CFG_ROW_ACC_INIT_RAV_B_MASK 0x03ff
67#define CFG_ROW_ACC_INIT_RAV_B_SHIFT 10
68
69#define CFG_SC8 0x20
70#define CFG_NLIN_LEFT_MASK 0x07ff
71#define CFG_NLIN_LEFT_SHIFT 0
72#define CFG_NLIN_RIGHT_MASK 0x07ff
73#define CFG_NLIN_RIGHT_SHIFT 12
74
75#define CFG_SC9 0x24
76#define CFG_LIN_ACC_INC CFG_SC9
77
78#define CFG_SC10 0x28
79#define CFG_NLIN_ACC_INIT CFG_SC10
80
81#define CFG_SC11 0x2c
82#define CFG_NLIN_ACC_INC CFG_SC11
83
84#define CFG_SC12 0x30
85#define CFG_COL_ACC_OFFSET_MASK 0x01ffffff
86#define CFG_COL_ACC_OFFSET_SHIFT 0
87
88#define CFG_SC13 0x34
89#define CFG_SC_FACTOR_RAV_MASK 0xff
90#define CFG_SC_FACTOR_RAV_SHIFT 0
91#define CFG_CHROMA_INTP_THR_MASK 0x03ff
92#define CFG_CHROMA_INTP_THR_SHIFT 12
93#define CFG_DELTA_CHROMA_THR_MASK 0x0f
94#define CFG_DELTA_CHROMA_THR_SHIFT 24
95
96#define CFG_SC17 0x44
97#define CFG_EV_THR_MASK 0x03ff
98#define CFG_EV_THR_SHIFT 12
99#define CFG_DELTA_LUMA_THR_MASK 0x0f
100#define CFG_DELTA_LUMA_THR_SHIFT 24
101#define CFG_DELTA_EV_THR_MASK 0x0f
102#define CFG_DELTA_EV_THR_SHIFT 28
103
104#define CFG_SC18 0x48
105#define CFG_HS_FACTOR_MASK 0x03ff
106#define CFG_HS_FACTOR_SHIFT 0
107#define CFG_CONF_DEFAULT_MASK 0x01ff
108#define CFG_CONF_DEFAULT_SHIFT 16
109
110#define CFG_SC19 0x4c
111#define CFG_HPF_COEFF0_MASK 0xff
112#define CFG_HPF_COEFF0_SHIFT 0
113#define CFG_HPF_COEFF1_MASK 0xff
114#define CFG_HPF_COEFF1_SHIFT 8
115#define CFG_HPF_COEFF2_MASK 0xff
116#define CFG_HPF_COEFF2_SHIFT 16
117#define CFG_HPF_COEFF3_MASK 0xff
118#define CFG_HPF_COEFF3_SHIFT 23
119
120#define CFG_SC20 0x50
121#define CFG_HPF_COEFF4_MASK 0xff
122#define CFG_HPF_COEFF4_SHIFT 0
123#define CFG_HPF_COEFF5_MASK 0xff
124#define CFG_HPF_COEFF5_SHIFT 8
125#define CFG_HPF_NORM_SHIFT_MASK 0x07
126#define CFG_HPF_NORM_SHIFT_SHIFT 16
127#define CFG_NL_LIMIT_MASK 0x1ff
128#define CFG_NL_LIMIT_SHIFT 20
129
130#define CFG_SC21 0x54
131#define CFG_NL_LO_THR_MASK 0x01ff
132#define CFG_NL_LO_THR_SHIFT 0
133#define CFG_NL_LO_SLOPE_MASK 0xff
134#define CFG_NL_LO_SLOPE_SHIFT 16
135
136#define CFG_SC22 0x58
137#define CFG_NL_HI_THR_MASK 0x01ff
138#define CFG_NL_HI_THR_SHIFT 0
139#define CFG_NL_HI_SLOPE_SH_MASK 0x07
140#define CFG_NL_HI_SLOPE_SH_SHIFT 16
141
142#define CFG_SC23 0x5c
143#define CFG_GRADIENT_THR_MASK 0x07ff
144#define CFG_GRADIENT_THR_SHIFT 0
145#define CFG_GRADIENT_THR_RANGE_MASK 0x0f
146#define CFG_GRADIENT_THR_RANGE_SHIFT 12
147#define CFG_MIN_GY_THR_MASK 0xff
148#define CFG_MIN_GY_THR_SHIFT 16
149#define CFG_MIN_GY_THR_RANGE_MASK 0x0f
150#define CFG_MIN_GY_THR_RANGE_SHIFT 28
151
152#define CFG_SC24 0x60
153#define CFG_ORG_H_MASK 0x07ff
154#define CFG_ORG_H_SHIFT 0
155#define CFG_ORG_W_MASK 0x07ff
156#define CFG_ORG_W_SHIFT 16
157
158#define CFG_SC25 0x64
159#define CFG_OFF_H_MASK 0x07ff
160#define CFG_OFF_H_SHIFT 0
161#define CFG_OFF_W_MASK 0x07ff
162#define CFG_OFF_W_SHIFT 16
163
164struct sc_data {
165 void __iomem *base;
166 struct resource *res;
167
168 struct platform_device *pdev;
169};
170
171void sc_set_regs_bypass(struct sc_data *sc, u32 *sc_reg0);
172void sc_dump_regs(struct sc_data *sc);
173struct sc_data *sc_create(struct platform_device *pdev);
174
175#endif
diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c
index 669777052a16..ecb85f9ae3ab 100644
--- a/drivers/media/platform/ti-vpe/vpe.c
+++ b/drivers/media/platform/ti-vpe/vpe.c
@@ -43,6 +43,7 @@
43 43
44#include "vpdma.h" 44#include "vpdma.h"
45#include "vpe_regs.h" 45#include "vpe_regs.h"
46#include "sc.h"
46 47
47#define VPE_MODULE_NAME "vpe" 48#define VPE_MODULE_NAME "vpe"
48 49
@@ -324,9 +325,11 @@ struct vpe_dev {
324 325
325 int irq; 326 int irq;
326 void __iomem *base; 327 void __iomem *base;
328 struct resource *res;
327 329
328 struct vb2_alloc_ctx *alloc_ctx; 330 struct vb2_alloc_ctx *alloc_ctx;
329 struct vpdma_data *vpdma; /* vpdma data handle */ 331 struct vpdma_data *vpdma; /* vpdma data handle */
332 struct sc_data *sc; /* scaler data handle */
330}; 333};
331 334
332/* 335/*
@@ -443,6 +446,9 @@ struct vpe_mmr_adb {
443 u32 csc_pad[2]; 446 u32 csc_pad[2];
444}; 447};
445 448
449#define GET_OFFSET_TOP(ctx, obj, reg) \
450 ((obj)->res->start - ctx->dev->res->start + reg)
451
446#define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \ 452#define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
447 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a) 453 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
448/* 454/*
@@ -455,7 +461,8 @@ static void init_adb_hdrs(struct vpe_ctx *ctx)
455 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0); 461 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
456 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0); 462 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
457 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE); 463 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
458 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr, sc_regs, VPE_SC_MP_SC0); 464 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr, sc_regs,
465 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
459 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs, VPE_CSC_CSC00); 466 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs, VPE_CSC_CSC00);
460}; 467};
461 468
@@ -749,18 +756,6 @@ static void set_csc_coeff_bypass(struct vpe_ctx *ctx)
749 ctx->load_mmrs = true; 756 ctx->load_mmrs = true;
750} 757}
751 758
752static void set_sc_regs_bypass(struct vpe_ctx *ctx)
753{
754 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
755 u32 *sc_reg0 = &mmr_adb->sc_regs[0];
756 u32 val = 0;
757
758 val |= VPE_SC_BYPASS;
759 *sc_reg0 = val;
760
761 ctx->load_mmrs = true;
762}
763
764/* 759/*
765 * Set the shadow registers whose values are modified when either the 760 * Set the shadow registers whose values are modified when either the
766 * source or destination format is changed. 761 * source or destination format is changed.
@@ -769,6 +764,7 @@ static int set_srcdst_params(struct vpe_ctx *ctx)
769{ 764{
770 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; 765 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
771 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST]; 766 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
767 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
772 size_t mv_buf_size; 768 size_t mv_buf_size;
773 int ret; 769 int ret;
774 770
@@ -806,7 +802,7 @@ static int set_srcdst_params(struct vpe_ctx *ctx)
806 set_cfg_and_line_modes(ctx); 802 set_cfg_and_line_modes(ctx);
807 set_dei_regs(ctx); 803 set_dei_regs(ctx);
808 set_csc_coeff_bypass(ctx); 804 set_csc_coeff_bypass(ctx);
809 set_sc_regs_bypass(ctx); 805 sc_set_regs_bypass(ctx->dev->sc, &mmr_adb->sc_regs[0]);
810 806
811 return 0; 807 return 0;
812} 808}
@@ -922,28 +918,6 @@ static void vpe_dump_regs(struct vpe_dev *dev)
922 DUMPREG(DEI_FMD_STATUS_R0); 918 DUMPREG(DEI_FMD_STATUS_R0);
923 DUMPREG(DEI_FMD_STATUS_R1); 919 DUMPREG(DEI_FMD_STATUS_R1);
924 DUMPREG(DEI_FMD_STATUS_R2); 920 DUMPREG(DEI_FMD_STATUS_R2);
925 DUMPREG(SC_MP_SC0);
926 DUMPREG(SC_MP_SC1);
927 DUMPREG(SC_MP_SC2);
928 DUMPREG(SC_MP_SC3);
929 DUMPREG(SC_MP_SC4);
930 DUMPREG(SC_MP_SC5);
931 DUMPREG(SC_MP_SC6);
932 DUMPREG(SC_MP_SC8);
933 DUMPREG(SC_MP_SC9);
934 DUMPREG(SC_MP_SC10);
935 DUMPREG(SC_MP_SC11);
936 DUMPREG(SC_MP_SC12);
937 DUMPREG(SC_MP_SC13);
938 DUMPREG(SC_MP_SC17);
939 DUMPREG(SC_MP_SC18);
940 DUMPREG(SC_MP_SC19);
941 DUMPREG(SC_MP_SC20);
942 DUMPREG(SC_MP_SC21);
943 DUMPREG(SC_MP_SC22);
944 DUMPREG(SC_MP_SC23);
945 DUMPREG(SC_MP_SC24);
946 DUMPREG(SC_MP_SC25);
947 DUMPREG(CSC_CSC00); 921 DUMPREG(CSC_CSC00);
948 DUMPREG(CSC_CSC01); 922 DUMPREG(CSC_CSC01);
949 DUMPREG(CSC_CSC02); 923 DUMPREG(CSC_CSC02);
@@ -951,6 +925,8 @@ static void vpe_dump_regs(struct vpe_dev *dev)
951 DUMPREG(CSC_CSC04); 925 DUMPREG(CSC_CSC04);
952 DUMPREG(CSC_CSC05); 926 DUMPREG(CSC_CSC05);
953#undef DUMPREG 927#undef DUMPREG
928
929 sc_dump_regs(dev->sc);
954} 930}
955 931
956static void add_out_dtd(struct vpe_ctx *ctx, int port) 932static void add_out_dtd(struct vpe_ctx *ctx, int port)
@@ -1965,7 +1941,6 @@ static int vpe_probe(struct platform_device *pdev)
1965{ 1941{
1966 struct vpe_dev *dev; 1942 struct vpe_dev *dev;
1967 struct video_device *vfd; 1943 struct video_device *vfd;
1968 struct resource *res;
1969 int ret, irq, func; 1944 int ret, irq, func;
1970 1945
1971 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1946 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
@@ -1981,14 +1956,15 @@ static int vpe_probe(struct platform_device *pdev)
1981 atomic_set(&dev->num_instances, 0); 1956 atomic_set(&dev->num_instances, 0);
1982 mutex_init(&dev->dev_mutex); 1957 mutex_init(&dev->dev_mutex);
1983 1958
1984 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpe_top"); 1959 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1960 "vpe_top");
1985 /* 1961 /*
1986 * HACK: we get resource info from device tree in the form of a list of 1962 * HACK: we get resource info from device tree in the form of a list of
1987 * VPE sub blocks, the driver currently uses only the base of vpe_top 1963 * VPE sub blocks, the driver currently uses only the base of vpe_top
1988 * for register access, the driver should be changed later to access 1964 * for register access, the driver should be changed later to access
1989 * registers based on the sub block base addresses 1965 * registers based on the sub block base addresses
1990 */ 1966 */
1991 dev->base = devm_ioremap(&pdev->dev, res->start, SZ_32K); 1967 dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
1992 if (!dev->base) { 1968 if (!dev->base) {
1993 ret = -ENOMEM; 1969 ret = -ENOMEM;
1994 goto v4l2_dev_unreg; 1970 goto v4l2_dev_unreg;
@@ -2033,6 +2009,12 @@ static int vpe_probe(struct platform_device *pdev)
2033 2009
2034 vpe_top_vpdma_reset(dev); 2010 vpe_top_vpdma_reset(dev);
2035 2011
2012 dev->sc = sc_create(pdev);
2013 if (IS_ERR(dev->sc)) {
2014 ret = PTR_ERR(dev->sc);
2015 goto runtime_put;
2016 }
2017
2036 dev->vpdma = vpdma_create(pdev); 2018 dev->vpdma = vpdma_create(pdev);
2037 if (IS_ERR(dev->vpdma)) { 2019 if (IS_ERR(dev->vpdma)) {
2038 ret = PTR_ERR(dev->vpdma); 2020 ret = PTR_ERR(dev->vpdma);
diff --git a/drivers/media/platform/ti-vpe/vpe_regs.h b/drivers/media/platform/ti-vpe/vpe_regs.h
index ed214e828398..d8dbdd375a7d 100644
--- a/drivers/media/platform/ti-vpe/vpe_regs.h
+++ b/drivers/media/platform/ti-vpe/vpe_regs.h
@@ -306,155 +306,6 @@
306#define VPE_FMD_FRAME_DIFF_MASK 0x000fffff 306#define VPE_FMD_FRAME_DIFF_MASK 0x000fffff
307#define VPE_FMD_FRAME_DIFF_SHIFT 0 307#define VPE_FMD_FRAME_DIFF_SHIFT 0
308 308
309/* VPE scaler regs */
310#define VPE_SC_MP_SC0 0x0700
311#define VPE_INTERLACE_O (1 << 0)
312#define VPE_LINEAR (1 << 1)
313#define VPE_SC_BYPASS (1 << 2)
314#define VPE_INVT_FID (1 << 3)
315#define VPE_USE_RAV (1 << 4)
316#define VPE_ENABLE_EV (1 << 5)
317#define VPE_AUTO_HS (1 << 6)
318#define VPE_DCM_2X (1 << 7)
319#define VPE_DCM_4X (1 << 8)
320#define VPE_HP_BYPASS (1 << 9)
321#define VPE_INTERLACE_I (1 << 10)
322#define VPE_ENABLE_SIN2_VER_INTP (1 << 11)
323#define VPE_Y_PK_EN (1 << 14)
324#define VPE_TRIM (1 << 15)
325#define VPE_SELFGEN_FID (1 << 16)
326
327#define VPE_SC_MP_SC1 0x0704
328#define VPE_ROW_ACC_INC_MASK 0x07ffffff
329#define VPE_ROW_ACC_INC_SHIFT 0
330
331#define VPE_SC_MP_SC2 0x0708
332#define VPE_ROW_ACC_OFFSET_MASK 0x0fffffff
333#define VPE_ROW_ACC_OFFSET_SHIFT 0
334
335#define VPE_SC_MP_SC3 0x070c
336#define VPE_ROW_ACC_OFFSET_B_MASK 0x0fffffff
337#define VPE_ROW_ACC_OFFSET_B_SHIFT 0
338
339#define VPE_SC_MP_SC4 0x0710
340#define VPE_TAR_H_MASK 0x07ff
341#define VPE_TAR_H_SHIFT 0
342#define VPE_TAR_W_MASK 0x07ff
343#define VPE_TAR_W_SHIFT 12
344#define VPE_LIN_ACC_INC_U_MASK 0x07
345#define VPE_LIN_ACC_INC_U_SHIFT 24
346#define VPE_NLIN_ACC_INIT_U_MASK 0x07
347#define VPE_NLIN_ACC_INIT_U_SHIFT 28
348
349#define VPE_SC_MP_SC5 0x0714
350#define VPE_SRC_H_MASK 0x07ff
351#define VPE_SRC_H_SHIFT 0
352#define VPE_SRC_W_MASK 0x07ff
353#define VPE_SRC_W_SHIFT 12
354#define VPE_NLIN_ACC_INC_U_MASK 0x07
355#define VPE_NLIN_ACC_INC_U_SHIFT 24
356
357#define VPE_SC_MP_SC6 0x0718
358#define VPE_ROW_ACC_INIT_RAV_MASK 0x03ff
359#define VPE_ROW_ACC_INIT_RAV_SHIFT 0
360#define VPE_ROW_ACC_INIT_RAV_B_MASK 0x03ff
361#define VPE_ROW_ACC_INIT_RAV_B_SHIFT 10
362
363#define VPE_SC_MP_SC8 0x0720
364#define VPE_NLIN_LEFT_MASK 0x07ff
365#define VPE_NLIN_LEFT_SHIFT 0
366#define VPE_NLIN_RIGHT_MASK 0x07ff
367#define VPE_NLIN_RIGHT_SHIFT 12
368
369#define VPE_SC_MP_SC9 0x0724
370#define VPE_LIN_ACC_INC VPE_SC_MP_SC9
371
372#define VPE_SC_MP_SC10 0x0728
373#define VPE_NLIN_ACC_INIT VPE_SC_MP_SC10
374
375#define VPE_SC_MP_SC11 0x072c
376#define VPE_NLIN_ACC_INC VPE_SC_MP_SC11
377
378#define VPE_SC_MP_SC12 0x0730
379#define VPE_COL_ACC_OFFSET_MASK 0x01ffffff
380#define VPE_COL_ACC_OFFSET_SHIFT 0
381
382#define VPE_SC_MP_SC13 0x0734
383#define VPE_SC_FACTOR_RAV_MASK 0x03ff
384#define VPE_SC_FACTOR_RAV_SHIFT 0
385#define VPE_CHROMA_INTP_THR_MASK 0x03ff
386#define VPE_CHROMA_INTP_THR_SHIFT 12
387#define VPE_DELTA_CHROMA_THR_MASK 0x0f
388#define VPE_DELTA_CHROMA_THR_SHIFT 24
389
390#define VPE_SC_MP_SC17 0x0744
391#define VPE_EV_THR_MASK 0x03ff
392#define VPE_EV_THR_SHIFT 12
393#define VPE_DELTA_LUMA_THR_MASK 0x0f
394#define VPE_DELTA_LUMA_THR_SHIFT 24
395#define VPE_DELTA_EV_THR_MASK 0x0f
396#define VPE_DELTA_EV_THR_SHIFT 28
397
398#define VPE_SC_MP_SC18 0x0748
399#define VPE_HS_FACTOR_MASK 0x03ff
400#define VPE_HS_FACTOR_SHIFT 0
401#define VPE_CONF_DEFAULT_MASK 0x01ff
402#define VPE_CONF_DEFAULT_SHIFT 16
403
404#define VPE_SC_MP_SC19 0x074c
405#define VPE_HPF_COEFF0_MASK 0xff
406#define VPE_HPF_COEFF0_SHIFT 0
407#define VPE_HPF_COEFF1_MASK 0xff
408#define VPE_HPF_COEFF1_SHIFT 8
409#define VPE_HPF_COEFF2_MASK 0xff
410#define VPE_HPF_COEFF2_SHIFT 16
411#define VPE_HPF_COEFF3_MASK 0xff
412#define VPE_HPF_COEFF3_SHIFT 23
413
414#define VPE_SC_MP_SC20 0x0750
415#define VPE_HPF_COEFF4_MASK 0xff
416#define VPE_HPF_COEFF4_SHIFT 0
417#define VPE_HPF_COEFF5_MASK 0xff
418#define VPE_HPF_COEFF5_SHIFT 8
419#define VPE_HPF_NORM_SHIFT_MASK 0x07
420#define VPE_HPF_NORM_SHIFT_SHIFT 16
421#define VPE_NL_LIMIT_MASK 0x1ff
422#define VPE_NL_LIMIT_SHIFT 20
423
424#define VPE_SC_MP_SC21 0x0754
425#define VPE_NL_LO_THR_MASK 0x01ff
426#define VPE_NL_LO_THR_SHIFT 0
427#define VPE_NL_LO_SLOPE_MASK 0xff
428#define VPE_NL_LO_SLOPE_SHIFT 16
429
430#define VPE_SC_MP_SC22 0x0758
431#define VPE_NL_HI_THR_MASK 0x01ff
432#define VPE_NL_HI_THR_SHIFT 0
433#define VPE_NL_HI_SLOPE_SH_MASK 0x07
434#define VPE_NL_HI_SLOPE_SH_SHIFT 16
435
436#define VPE_SC_MP_SC23 0x075c
437#define VPE_GRADIENT_THR_MASK 0x07ff
438#define VPE_GRADIENT_THR_SHIFT 0
439#define VPE_GRADIENT_THR_RANGE_MASK 0x0f
440#define VPE_GRADIENT_THR_RANGE_SHIFT 12
441#define VPE_MIN_GY_THR_MASK 0xff
442#define VPE_MIN_GY_THR_SHIFT 16
443#define VPE_MIN_GY_THR_RANGE_MASK 0x0f
444#define VPE_MIN_GY_THR_RANGE_SHIFT 28
445
446#define VPE_SC_MP_SC24 0x0760
447#define VPE_ORG_H_MASK 0x07ff
448#define VPE_ORG_H_SHIFT 0
449#define VPE_ORG_W_MASK 0x07ff
450#define VPE_ORG_W_SHIFT 16
451
452#define VPE_SC_MP_SC25 0x0764
453#define VPE_OFF_H_MASK 0x07ff
454#define VPE_OFF_H_SHIFT 0
455#define VPE_OFF_W_MASK 0x07ff
456#define VPE_OFF_W_SHIFT 16
457
458/* VPE color space converter regs */ 309/* VPE color space converter regs */
459#define VPE_CSC_CSC00 0x5700 310#define VPE_CSC_CSC00 0x5700
460#define VPE_CSC_A0_MASK 0x1fff 311#define VPE_CSC_A0_MASK 0x1fff
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-27 22:28:13 -0400