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-rw-r--r--Documentation/devicetree/bindings/pci/pci-keystone.txt4
-rw-r--r--drivers/pci/host/pci-keystone.c21
2 files changed, 3 insertions, 22 deletions
diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
index de9c475b66f4..54eae2938174 100644
--- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
+++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
@@ -13,9 +13,7 @@ Required Properties:-
13 13
14compatibility: "ti,keystone-pcie" 14compatibility: "ti,keystone-pcie"
15reg: index 1 is the base address and length of DW application registers. 15reg: index 1 is the base address and length of DW application registers.
16 index 2 is the base address and length of PCI mode configuration 16 index 2 is the base address and length of PCI device ID register.
17 register.
18 index 3 is the base address and length of PCI device ID register.
19 17
20pcie_msi_intc : Interrupt controller device node for MSI IRQ chip 18pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
21 interrupt-cells: should be set to 1 19 interrupt-cells: should be set to 1
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
index c58a9eb60141..e69932ddd19c 100644
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -35,10 +35,6 @@
35#define MAX_MSI_HOST_IRQS 8 35#define MAX_MSI_HOST_IRQS 8
36#define MAX_LEGACY_HOST_IRQS 4 36#define MAX_LEGACY_HOST_IRQS 4
37 37
38/* RC mode settings masks */
39#define PCIE_RC_MODE BIT(2)
40#define PCIE_MODE_MASK (BIT(1) | BIT(2))
41
42/* DEV_STAT_CTRL */ 38/* DEV_STAT_CTRL */
43#define PCIE_CAP_BASE 0x70 39#define PCIE_CAP_BASE 0x70
44 40
@@ -355,7 +351,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
355 void __iomem *reg_p; 351 void __iomem *reg_p;
356 struct phy *phy; 352 struct phy *phy;
357 int ret = 0; 353 int ret = 0;
358 u32 val;
359 354
360 ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie), 355 ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
361 GFP_KERNEL); 356 GFP_KERNEL);
@@ -365,18 +360,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
365 } 360 }
366 pp = &ks_pcie->pp; 361 pp = &ks_pcie->pp;
367 362
368 /* index 2 is the devcfg register for RC mode settings */
369 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
370 reg_p = devm_ioremap_resource(dev, res);
371 if (IS_ERR(reg_p))
372 return PTR_ERR(reg_p);
373
374 /* enable RC mode in devcfg */
375 val = readl(reg_p);
376 val &= ~PCIE_MODE_MASK;
377 val |= PCIE_RC_MODE;
378 writel(val, reg_p);
379
380 /* initialize SerDes Phy if present */ 363 /* initialize SerDes Phy if present */
381 phy = devm_phy_get(dev, "pcie-phy"); 364 phy = devm_phy_get(dev, "pcie-phy");
382 if (!IS_ERR_OR_NULL(phy)) { 365 if (!IS_ERR_OR_NULL(phy)) {
@@ -385,8 +368,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
385 return ret; 368 return ret;
386 } 369 }
387 370
388 /* index 3 is to read PCI DEVICE_ID */ 371 /* index 2 is to read PCI DEVICE_ID */
389 res = platform_get_resource(pdev, IORESOURCE_MEM, 3); 372 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
390 reg_p = devm_ioremap_resource(dev, res); 373 reg_p = devm_ioremap_resource(dev, res);
391 if (IS_ERR(reg_p)) 374 if (IS_ERR(reg_p))
392 return PTR_ERR(reg_p); 375 return PTR_ERR(reg_p);