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-rw-r--r--sound/soc/fsl/Kconfig1
-rw-r--r--sound/soc/fsl/fsl_ssi.c241
-rw-r--r--sound/soc/fsl/fsl_ssi.h50
3 files changed, 158 insertions, 134 deletions
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 338a91642471..2d6281f1e1f4 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -4,6 +4,7 @@ config SND_SOC_FSL_SAI
4 select SND_SOC_GENERIC_DMAENGINE_PCM 4 select SND_SOC_GENERIC_DMAENGINE_PCM
5 5
6config SND_SOC_FSL_SSI 6config SND_SOC_FSL_SSI
7 select REGMAP_MMIO
7 tristate 8 tristate
8 9
9config SND_SOC_FSL_SPDIF 10config SND_SOC_FSL_SPDIF
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 9fe3a1068f67..8d58b50bfbee 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -53,25 +53,6 @@
53#include "fsl_ssi.h" 53#include "fsl_ssi.h"
54#include "imx-pcm.h" 54#include "imx-pcm.h"
55 55
56#ifdef PPC
57#define read_ssi(addr) in_be32(addr)
58#define write_ssi(val, addr) out_be32(addr, val)
59#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
60#else
61#define read_ssi(addr) readl(addr)
62#define write_ssi(val, addr) writel(val, addr)
63/*
64 * FIXME: Proper locking should be added at write_ssi_mask caller level
65 * to ensure this register read/modify/write sequence is race free.
66 */
67static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
68{
69 u32 val = readl(addr);
70 val = (val & ~clear) | set;
71 writel(val, addr);
72}
73#endif
74
75/** 56/**
76 * FSLSSI_I2S_RATES: sample rates supported by the I2S 57 * FSLSSI_I2S_RATES: sample rates supported by the I2S
77 * 58 *
@@ -131,6 +112,13 @@ struct fsl_ssi_rxtx_reg_val {
131 struct fsl_ssi_reg_val rx; 112 struct fsl_ssi_reg_val rx;
132 struct fsl_ssi_reg_val tx; 113 struct fsl_ssi_reg_val tx;
133}; 114};
115static const struct regmap_config fsl_ssi_regconfig = {
116 .max_register = CCSR_SSI_SACCDIS,
117 .reg_bits = 32,
118 .val_bits = 32,
119 .reg_stride = 4,
120 .val_format_endian = REGMAP_ENDIAN_NATIVE,
121};
134 122
135struct fsl_ssi_soc_data { 123struct fsl_ssi_soc_data {
136 bool imx; 124 bool imx;
@@ -141,7 +129,7 @@ struct fsl_ssi_soc_data {
141/** 129/**
142 * fsl_ssi_private: per-SSI private data 130 * fsl_ssi_private: per-SSI private data
143 * 131 *
144 * @ssi: Pointer to the memory area 132 * @reg: Pointer to the regmap registers
145 * @irq: IRQ of this SSI 133 * @irq: IRQ of this SSI
146 * @cpu_dai_drv: CPU DAI driver for this device 134 * @cpu_dai_drv: CPU DAI driver for this device
147 * 135 *
@@ -172,7 +160,7 @@ struct fsl_ssi_soc_data {
172 * @soc: SoC specifc data 160 * @soc: SoC specifc data
173 */ 161 */
174struct fsl_ssi_private { 162struct fsl_ssi_private {
175 struct ccsr_ssi __iomem *ssi; 163 struct regmap *regs;
176 unsigned int irq; 164 unsigned int irq;
177 struct snd_soc_dai_driver cpu_dai_drv; 165 struct snd_soc_dai_driver cpu_dai_drv;
178 166
@@ -285,7 +273,7 @@ static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
285static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 273static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
286{ 274{
287 struct fsl_ssi_private *ssi_private = dev_id; 275 struct fsl_ssi_private *ssi_private = dev_id;
288 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 276 struct regmap *regs = ssi_private->regs;
289 __be32 sisr; 277 __be32 sisr;
290 __be32 sisr2; 278 __be32 sisr2;
291 279
@@ -293,12 +281,12 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
293 were interrupted for. We mask it with the Interrupt Enable register 281 were interrupted for. We mask it with the Interrupt Enable register
294 so that we only check for events that we're interested in. 282 so that we only check for events that we're interested in.
295 */ 283 */
296 sisr = read_ssi(&ssi->sisr); 284 regmap_read(regs, CCSR_SSI_SISR, &sisr);
297 285
298 sisr2 = sisr & ssi_private->soc->sisr_write_mask; 286 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
299 /* Clear the bits that we set */ 287 /* Clear the bits that we set */
300 if (sisr2) 288 if (sisr2)
301 write_ssi(sisr2, &ssi->sisr); 289 regmap_write(regs, CCSR_SSI_SISR, sisr2);
302 290
303 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); 291 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
304 292
@@ -311,17 +299,26 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
311static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, 299static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
312 bool enable) 300 bool enable)
313{ 301{
314 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 302 struct regmap *regs = ssi_private->regs;
315 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; 303 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
316 304
317 if (enable) { 305 if (enable) {
318 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier); 306 regmap_update_bits(regs, CCSR_SSI_SIER,
319 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr); 307 vals->rx.sier | vals->tx.sier,
320 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr); 308 vals->rx.sier | vals->tx.sier);
309 regmap_update_bits(regs, CCSR_SSI_SRCR,
310 vals->rx.srcr | vals->tx.srcr,
311 vals->rx.srcr | vals->tx.srcr);
312 regmap_update_bits(regs, CCSR_SSI_STCR,
313 vals->rx.stcr | vals->tx.stcr,
314 vals->rx.stcr | vals->tx.stcr);
321 } else { 315 } else {
322 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0); 316 regmap_update_bits(regs, CCSR_SSI_SRCR,
323 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0); 317 vals->rx.srcr | vals->tx.srcr, 0);
324 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0); 318 regmap_update_bits(regs, CCSR_SSI_STCR,
319 vals->rx.stcr | vals->tx.stcr, 0);
320 regmap_update_bits(regs, CCSR_SSI_SIER,
321 vals->rx.sier | vals->tx.sier, 0);
325 } 322 }
326} 323}
327 324
@@ -352,13 +349,17 @@ static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
352static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, 349static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
353 struct fsl_ssi_reg_val *vals) 350 struct fsl_ssi_reg_val *vals)
354{ 351{
355 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 352 struct regmap *regs = ssi_private->regs;
356 struct fsl_ssi_reg_val *avals; 353 struct fsl_ssi_reg_val *avals;
357 u32 scr_val = read_ssi(&ssi->scr); 354 int nr_active_streams;
358 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + 355 u32 scr_val;
359 !!(scr_val & CCSR_SSI_SCR_RE);
360 int keep_active; 356 int keep_active;
361 357
358 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
359
360 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
361 !!(scr_val & CCSR_SSI_SCR_RE);
362
362 if (nr_active_streams - 1 > 0) 363 if (nr_active_streams - 1 > 0)
363 keep_active = 1; 364 keep_active = 1;
364 else 365 else
@@ -375,7 +376,7 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
375 if (!enable) { 376 if (!enable) {
376 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 377 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
377 keep_active); 378 keep_active);
378 write_ssi_mask(&ssi->scr, scr, 0); 379 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
379 } 380 }
380 381
381 /* 382 /*
@@ -396,9 +397,9 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
396 * (online configuration) 397 * (online configuration)
397 */ 398 */
398 if (enable) { 399 if (enable) {
399 write_ssi_mask(&ssi->sier, 0, vals->sier); 400 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
400 write_ssi_mask(&ssi->srcr, 0, vals->srcr); 401 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
401 write_ssi_mask(&ssi->stcr, 0, vals->stcr); 402 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
402 } else { 403 } else {
403 u32 sier; 404 u32 sier;
404 u32 srcr; 405 u32 srcr;
@@ -421,15 +422,15 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
421 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, 422 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
422 keep_active); 423 keep_active);
423 424
424 write_ssi_mask(&ssi->srcr, srcr, 0); 425 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
425 write_ssi_mask(&ssi->stcr, stcr, 0); 426 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
426 write_ssi_mask(&ssi->sier, sier, 0); 427 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
427 } 428 }
428 429
429config_done: 430config_done:
430 /* Enabling of subunits is done after configuration */ 431 /* Enabling of subunits is done after configuration */
431 if (enable) 432 if (enable)
432 write_ssi_mask(&ssi->scr, 0, vals->scr); 433 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
433} 434}
434 435
435 436
@@ -480,32 +481,33 @@ static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
480 481
481static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) 482static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
482{ 483{
483 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 484 struct regmap *regs = ssi_private->regs;
484 485
485 /* 486 /*
486 * Setup the clock control register 487 * Setup the clock control register
487 */ 488 */
488 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), 489 regmap_write(regs, CCSR_SSI_STCCR,
489 &ssi->stccr); 490 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
490 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), 491 regmap_write(regs, CCSR_SSI_SRCCR,
491 &ssi->srccr); 492 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
492 493
493 /* 494 /*
494 * Enable AC97 mode and startup the SSI 495 * Enable AC97 mode and startup the SSI
495 */ 496 */
496 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, 497 regmap_write(regs, CCSR_SSI_SACNT,
497 &ssi->sacnt); 498 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
498 write_ssi(0xff, &ssi->saccdis); 499 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
499 write_ssi(0x300, &ssi->saccen); 500 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
500 501
501 /* 502 /*
502 * Enable SSI, Transmit and Receive. AC97 has to communicate with the 503 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
503 * codec before a stream is started. 504 * codec before a stream is started.
504 */ 505 */
505 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | 506 regmap_update_bits(regs, CCSR_SSI_SCR,
506 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); 507 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
508 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
507 509
508 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); 510 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
509} 511}
510 512
511/** 513/**
@@ -549,7 +551,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
549 struct snd_pcm_hw_params *hw_params) 551 struct snd_pcm_hw_params *hw_params)
550{ 552{
551 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 553 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
552 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 554 struct regmap *regs = ssi_private->regs;
553 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; 555 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
554 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 556 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
555 unsigned long clkrate, baudrate, tmprate; 557 unsigned long clkrate, baudrate, tmprate;
@@ -626,9 +628,9 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
626 CCSR_SSI_SxCCR_PSR; 628 CCSR_SSI_SxCCR_PSR;
627 629
628 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) 630 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
629 write_ssi_mask(&ssi->stccr, mask, stccr); 631 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
630 else 632 else
631 write_ssi_mask(&ssi->srccr, mask, stccr); 633 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
632 634
633 if (!baudclk_is_used) { 635 if (!baudclk_is_used) {
634 ret = clk_set_rate(ssi_private->baudclk, baudrate); 636 ret = clk_set_rate(ssi_private->baudclk, baudrate);
@@ -668,13 +670,17 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
668 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) 670 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
669{ 671{
670 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 672 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
671 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 673 struct regmap *regs = ssi_private->regs;
672 unsigned int channels = params_channels(hw_params); 674 unsigned int channels = params_channels(hw_params);
673 unsigned int sample_size = 675 unsigned int sample_size =
674 snd_pcm_format_width(params_format(hw_params)); 676 snd_pcm_format_width(params_format(hw_params));
675 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 677 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
676 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
677 int ret; 678 int ret;
679 u32 scr_val;
680 int enabled;
681
682 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
683 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
678 684
679 /* 685 /*
680 * If we're in synchronous mode, and the SSI is already enabled, 686 * If we're in synchronous mode, and the SSI is already enabled,
@@ -711,12 +717,14 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
711 /* In synchronous mode, the SSI uses STCCR for capture */ 717 /* In synchronous mode, the SSI uses STCCR for capture */
712 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 718 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
713 ssi_private->cpu_dai_drv.symmetric_rates) 719 ssi_private->cpu_dai_drv.symmetric_rates)
714 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); 720 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
721 wl);
715 else 722 else
716 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); 723 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
724 wl);
717 725
718 if (!fsl_ssi_is_ac97(ssi_private)) 726 if (!fsl_ssi_is_ac97(ssi_private))
719 write_ssi_mask(&ssi->scr, 727 regmap_update_bits(regs, CCSR_SSI_SCR,
720 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, 728 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
721 channels == 1 ? 0 : ssi_private->i2s_mode); 729 channels == 1 ? 0 : ssi_private->i2s_mode);
722 730
@@ -742,7 +750,7 @@ static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
742static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private, 750static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
743 unsigned int fmt) 751 unsigned int fmt)
744{ 752{
745 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 753 struct regmap *regs = ssi_private->regs;
746 u32 strcr = 0, stcr, srcr, scr, mask; 754 u32 strcr = 0, stcr, srcr, scr, mask;
747 u8 wm; 755 u8 wm;
748 756
@@ -755,14 +763,17 @@ static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
755 763
756 fsl_ssi_setup_reg_vals(ssi_private); 764 fsl_ssi_setup_reg_vals(ssi_private);
757 765
758 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); 766 regmap_read(regs, CCSR_SSI_SCR, &scr);
767 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
759 scr |= CCSR_SSI_SCR_SYNC_TX_FS; 768 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
760 769
761 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | 770 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
762 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | 771 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
763 CCSR_SSI_STCR_TEFS; 772 CCSR_SSI_STCR_TEFS;
764 stcr = read_ssi(&ssi->stcr) & ~mask; 773 regmap_read(regs, CCSR_SSI_STCR, &stcr);
765 srcr = read_ssi(&ssi->srcr) & ~mask; 774 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
775 stcr &= ~mask;
776 srcr &= ~mask;
766 777
767 ssi_private->i2s_mode = CCSR_SSI_SCR_NET; 778 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
768 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 779 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -770,10 +781,12 @@ static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
770 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 781 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
771 case SND_SOC_DAIFMT_CBS_CFS: 782 case SND_SOC_DAIFMT_CBS_CFS:
772 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 783 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
773 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, 784 regmap_update_bits(regs, CCSR_SSI_STCCR,
774 CCSR_SSI_SxCCR_DC(2)); 785 CCSR_SSI_SxCCR_DC_MASK,
775 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, 786 CCSR_SSI_SxCCR_DC(2));
776 CCSR_SSI_SxCCR_DC(2)); 787 regmap_update_bits(regs, CCSR_SSI_SRCCR,
788 CCSR_SSI_SxCCR_DC_MASK,
789 CCSR_SSI_SxCCR_DC(2));
777 break; 790 break;
778 case SND_SOC_DAIFMT_CBM_CFM: 791 case SND_SOC_DAIFMT_CBM_CFM:
779 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 792 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
@@ -852,9 +865,9 @@ static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
852 scr |= CCSR_SSI_SCR_SYN; 865 scr |= CCSR_SSI_SCR_SYN;
853 } 866 }
854 867
855 write_ssi(stcr, &ssi->stcr); 868 regmap_write(regs, CCSR_SSI_STCR, stcr);
856 write_ssi(srcr, &ssi->srcr); 869 regmap_write(regs, CCSR_SSI_SRCR, srcr);
857 write_ssi(scr, &ssi->scr); 870 regmap_write(regs, CCSR_SSI_SCR, scr);
858 871
859 /* 872 /*
860 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't 873 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
@@ -872,16 +885,16 @@ static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
872 else 885 else
873 wm = ssi_private->fifo_depth; 886 wm = ssi_private->fifo_depth;
874 887
875 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | 888 regmap_write(regs, CCSR_SSI_SFCSR,
876 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), 889 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
877 &ssi->sfcsr); 890 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
878 891
879 if (ssi_private->use_dual_fifo) { 892 if (ssi_private->use_dual_fifo) {
880 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, 893 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
881 CCSR_SSI_SRCR_RFEN1); 894 CCSR_SSI_SRCR_RFEN1);
882 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, 895 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
883 CCSR_SSI_STCR_TFEN1); 896 CCSR_SSI_STCR_TFEN1);
884 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, 897 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
885 CCSR_SSI_SCR_TCH_EN); 898 CCSR_SSI_SCR_TCH_EN);
886 } 899 }
887 900
@@ -911,31 +924,34 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
911 u32 rx_mask, int slots, int slot_width) 924 u32 rx_mask, int slots, int slot_width)
912{ 925{
913 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 926 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
914 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 927 struct regmap *regs = ssi_private->regs;
915 u32 val; 928 u32 val;
916 929
917 /* The slot number should be >= 2 if using Network mode or I2S mode */ 930 /* The slot number should be >= 2 if using Network mode or I2S mode */
918 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); 931 regmap_read(regs, CCSR_SSI_SCR, &val);
932 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
919 if (val && slots < 2) { 933 if (val && slots < 2) {
920 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); 934 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
921 return -EINVAL; 935 return -EINVAL;
922 } 936 }
923 937
924 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, 938 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
925 CCSR_SSI_SxCCR_DC(slots)); 939 CCSR_SSI_SxCCR_DC(slots));
926 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, 940 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
927 CCSR_SSI_SxCCR_DC(slots)); 941 CCSR_SSI_SxCCR_DC(slots));
928 942
929 /* The register SxMSKs needs SSI to provide essential clock due to 943 /* The register SxMSKs needs SSI to provide essential clock due to
930 * hardware design. So we here temporarily enable SSI to set them. 944 * hardware design. So we here temporarily enable SSI to set them.
931 */ 945 */
932 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; 946 regmap_read(regs, CCSR_SSI_SCR, &val);
933 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); 947 val &= CCSR_SSI_SCR_SSIEN;
948 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
949 CCSR_SSI_SCR_SSIEN);
934 950
935 write_ssi(tx_mask, &ssi->stmsk); 951 regmap_write(regs, CCSR_SSI_STMSK, tx_mask);
936 write_ssi(rx_mask, &ssi->srmsk); 952 regmap_write(regs, CCSR_SSI_SRMSK, rx_mask);
937 953
938 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); 954 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
939 955
940 return 0; 956 return 0;
941} 957}
@@ -954,7 +970,7 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
954{ 970{
955 struct snd_soc_pcm_runtime *rtd = substream->private_data; 971 struct snd_soc_pcm_runtime *rtd = substream->private_data;
956 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); 972 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
957 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 973 struct regmap *regs = ssi_private->regs;
958 974
959 switch (cmd) { 975 switch (cmd) {
960 case SNDRV_PCM_TRIGGER_START: 976 case SNDRV_PCM_TRIGGER_START:
@@ -981,9 +997,9 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
981 997
982 if (fsl_ssi_is_ac97(ssi_private)) { 998 if (fsl_ssi_is_ac97(ssi_private)) {
983 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 999 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
984 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); 1000 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
985 else 1001 else
986 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); 1002 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
987 } 1003 }
988 1004
989 return 0; 1005 return 0;
@@ -1058,7 +1074,7 @@ static struct fsl_ssi_private *fsl_ac97_data;
1058static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1074static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1059 unsigned short val) 1075 unsigned short val)
1060{ 1076{
1061 struct ccsr_ssi *ssi = fsl_ac97_data->ssi; 1077 struct regmap *regs = fsl_ac97_data->regs;
1062 unsigned int lreg; 1078 unsigned int lreg;
1063 unsigned int lval; 1079 unsigned int lval;
1064 1080
@@ -1067,12 +1083,12 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1067 1083
1068 1084
1069 lreg = reg << 12; 1085 lreg = reg << 12;
1070 write_ssi(lreg, &ssi->sacadd); 1086 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1071 1087
1072 lval = val << 4; 1088 lval = val << 4;
1073 write_ssi(lval , &ssi->sacdat); 1089 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1074 1090
1075 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, 1091 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1076 CCSR_SSI_SACNT_WR); 1092 CCSR_SSI_SACNT_WR);
1077 udelay(100); 1093 udelay(100);
1078} 1094}
@@ -1080,19 +1096,21 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1080static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1096static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1081 unsigned short reg) 1097 unsigned short reg)
1082{ 1098{
1083 struct ccsr_ssi *ssi = fsl_ac97_data->ssi; 1099 struct regmap *regs = fsl_ac97_data->regs;
1084 1100
1085 unsigned short val = -1; 1101 unsigned short val = -1;
1102 u32 reg_val;
1086 unsigned int lreg; 1103 unsigned int lreg;
1087 1104
1088 lreg = (reg & 0x7f) << 12; 1105 lreg = (reg & 0x7f) << 12;
1089 write_ssi(lreg, &ssi->sacadd); 1106 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1090 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, 1107 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1091 CCSR_SSI_SACNT_RD); 1108 CCSR_SSI_SACNT_RD);
1092 1109
1093 udelay(100); 1110 udelay(100);
1094 1111
1095 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; 1112 regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
1113 val = (reg_val >> 4) & 0xffff;
1096 1114
1097 return val; 1115 return val;
1098} 1116}
@@ -1151,10 +1169,8 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev,
1151 */ 1169 */
1152 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; 1170 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1153 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; 1171 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1154 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + 1172 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1155 offsetof(struct ccsr_ssi, stx0); 1173 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1156 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys +
1157 offsetof(struct ccsr_ssi, srx0);
1158 1174
1159 ret = !of_property_read_u32_array(np, "dmas", dmas, 4); 1175 ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1160 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { 1176 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
@@ -1216,6 +1232,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1216 const char *p, *sprop; 1232 const char *p, *sprop;
1217 const uint32_t *iprop; 1233 const uint32_t *iprop;
1218 struct resource res; 1234 struct resource res;
1235 void __iomem *iomem;
1219 char name[64]; 1236 char name[64];
1220 1237
1221 /* SSIs that are not connected on the board should have a 1238 /* SSIs that are not connected on the board should have a
@@ -1270,12 +1287,20 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1270 dev_err(&pdev->dev, "could not determine device resources\n"); 1287 dev_err(&pdev->dev, "could not determine device resources\n");
1271 return ret; 1288 return ret;
1272 } 1289 }
1273 ssi_private->ssi = of_iomap(np, 0); 1290 ssi_private->ssi_phys = res.start;
1274 if (!ssi_private->ssi) { 1291
1292 iomem = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1293 if (!iomem) {
1275 dev_err(&pdev->dev, "could not map device resources\n"); 1294 dev_err(&pdev->dev, "could not map device resources\n");
1276 return -ENOMEM; 1295 return -ENOMEM;
1277 } 1296 }
1278 ssi_private->ssi_phys = res.start; 1297
1298 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1299 &fsl_ssi_regconfig);
1300 if (IS_ERR(ssi_private->regs)) {
1301 dev_err(&pdev->dev, "Failed to init register map\n");
1302 return PTR_ERR(ssi_private->regs);
1303 }
1279 1304
1280 ssi_private->irq = irq_of_parse_and_map(np, 0); 1305 ssi_private->irq = irq_of_parse_and_map(np, 0);
1281 if (!ssi_private->irq) { 1306 if (!ssi_private->irq) {
@@ -1301,7 +1326,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1301 dev_set_drvdata(&pdev->dev, ssi_private); 1326 dev_set_drvdata(&pdev->dev, ssi_private);
1302 1327
1303 if (ssi_private->soc->imx) { 1328 if (ssi_private->soc->imx) {
1304 ret = fsl_ssi_imx_probe(pdev, ssi_private, ssi_private->ssi); 1329 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1305 if (ret) 1330 if (ret)
1306 goto error_irqmap; 1331 goto error_irqmap;
1307 } 1332 }
diff --git a/sound/soc/fsl/fsl_ssi.h b/sound/soc/fsl/fsl_ssi.h
index 71c3e7e4340d..506510540d0a 100644
--- a/sound/soc/fsl/fsl_ssi.h
+++ b/sound/soc/fsl/fsl_ssi.h
@@ -12,32 +12,30 @@
12#ifndef _MPC8610_I2S_H 12#ifndef _MPC8610_I2S_H
13#define _MPC8610_I2S_H 13#define _MPC8610_I2S_H
14 14
15/* SSI Register Map */ 15/* SSI registers */
16struct ccsr_ssi { 16#define CCSR_SSI_STX0 0x00
17 __be32 stx0; /* 0x.0000 - SSI Transmit Data Register 0 */ 17#define CCSR_SSI_STX1 0x04
18 __be32 stx1; /* 0x.0004 - SSI Transmit Data Register 1 */ 18#define CCSR_SSI_SRX0 0x08
19 __be32 srx0; /* 0x.0008 - SSI Receive Data Register 0 */ 19#define CCSR_SSI_SRX1 0x0c
20 __be32 srx1; /* 0x.000C - SSI Receive Data Register 1 */ 20#define CCSR_SSI_SCR 0x10
21 __be32 scr; /* 0x.0010 - SSI Control Register */ 21#define CCSR_SSI_SISR 0x14
22 __be32 sisr; /* 0x.0014 - SSI Interrupt Status Register Mixed */ 22#define CCSR_SSI_SIER 0x18
23 __be32 sier; /* 0x.0018 - SSI Interrupt Enable Register */ 23#define CCSR_SSI_STCR 0x1c
24 __be32 stcr; /* 0x.001C - SSI Transmit Configuration Register */ 24#define CCSR_SSI_SRCR 0x20
25 __be32 srcr; /* 0x.0020 - SSI Receive Configuration Register */ 25#define CCSR_SSI_STCCR 0x24
26 __be32 stccr; /* 0x.0024 - SSI Transmit Clock Control Register */ 26#define CCSR_SSI_SRCCR 0x28
27 __be32 srccr; /* 0x.0028 - SSI Receive Clock Control Register */ 27#define CCSR_SSI_SFCSR 0x2c
28 __be32 sfcsr; /* 0x.002C - SSI FIFO Control/Status Register */ 28#define CCSR_SSI_STR 0x30
29 __be32 str; /* 0x.0030 - SSI Test Register */ 29#define CCSR_SSI_SOR 0x34
30 __be32 sor; /* 0x.0034 - SSI Option Register */ 30#define CCSR_SSI_SACNT 0x38
31 __be32 sacnt; /* 0x.0038 - SSI AC97 Control Register */ 31#define CCSR_SSI_SACADD 0x3c
32 __be32 sacadd; /* 0x.003C - SSI AC97 Command Address Register */ 32#define CCSR_SSI_SACDAT 0x40
33 __be32 sacdat; /* 0x.0040 - SSI AC97 Command Data Register */ 33#define CCSR_SSI_SATAG 0x44
34 __be32 satag; /* 0x.0044 - SSI AC97 Tag Register */ 34#define CCSR_SSI_STMSK 0x48
35 __be32 stmsk; /* 0x.0048 - SSI Transmit Time Slot Mask Register */ 35#define CCSR_SSI_SRMSK 0x4c
36 __be32 srmsk; /* 0x.004C - SSI Receive Time Slot Mask Register */ 36#define CCSR_SSI_SACCST 0x50
37 __be32 saccst; /* 0x.0050 - SSI AC97 Channel Status Register */ 37#define CCSR_SSI_SACCEN 0x54
38 __be32 saccen; /* 0x.0054 - SSI AC97 Channel Enable Register */ 38#define CCSR_SSI_SACCDIS 0x58
39 __be32 saccdis; /* 0x.0058 - SSI AC97 Channel Disable Register */
40};
41 39
42#define CCSR_SSI_SCR_SYNC_TX_FS 0x00001000 40#define CCSR_SSI_SCR_SYNC_TX_FS 0x00001000
43#define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800 41#define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 15:14:44 -0400