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-rw-r--r--drivers/net/ethernet/mellanox/mlx4/fw.c141
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/fw.h37
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/main.c71
3 files changed, 154 insertions, 95 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.c b/drivers/net/ethernet/mellanox/mlx4/fw.c
index 622bffaa9d78..073b3d1c8b91 100644
--- a/drivers/net/ethernet/mellanox/mlx4/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx4/fw.c
@@ -886,61 +886,10 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
886 if (field32 & (1 << 21)) 886 if (field32 & (1 << 21))
887 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 887 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
888 888
889 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 889 for (i = 1; i <= dev_cap->num_ports; i++) {
890 for (i = 1; i <= dev_cap->num_ports; ++i) { 890 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
891 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 891 if (err)
892 dev_cap->max_vl[i] = field >> 4; 892 goto out;
893 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
894 dev_cap->ib_mtu[i] = field >> 4;
895 dev_cap->max_port_width[i] = field & 0xf;
896 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
897 dev_cap->max_gids[i] = 1 << (field & 0xf);
898 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
899 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
900 }
901 } else {
902#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
903#define QUERY_PORT_MTU_OFFSET 0x01
904#define QUERY_PORT_ETH_MTU_OFFSET 0x02
905#define QUERY_PORT_WIDTH_OFFSET 0x06
906#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
907#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
908#define QUERY_PORT_MAX_VL_OFFSET 0x0b
909#define QUERY_PORT_MAC_OFFSET 0x10
910#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
911#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
912#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
913
914 for (i = 1; i <= dev_cap->num_ports; ++i) {
915 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
916 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
917 if (err)
918 goto out;
919
920 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
921 dev_cap->supported_port_types[i] = field & 3;
922 dev_cap->suggested_type[i] = (field >> 3) & 1;
923 dev_cap->default_sense[i] = (field >> 4) & 1;
924 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
925 dev_cap->ib_mtu[i] = field & 0xf;
926 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
927 dev_cap->max_port_width[i] = field & 0xf;
928 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
929 dev_cap->max_gids[i] = 1 << (field >> 4);
930 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
931 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
932 dev_cap->max_vl[i] = field & 0xf;
933 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
934 dev_cap->log_max_macs[i] = field & 0xf;
935 dev_cap->log_max_vlans[i] = field >> 4;
936 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
937 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
938 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
939 dev_cap->trans_type[i] = field32 >> 24;
940 dev_cap->vendor_oui[i] = field32 & 0xffffff;
941 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
942 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
943 }
944 } 893 }
945 894
946 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 895 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
@@ -977,8 +926,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
977 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 926 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
978 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 927 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
979 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 928 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
980 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], 929 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
981 dev_cap->max_port_width[1]); 930 dev_cap->port_cap[1].max_port_width);
982 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 931 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
983 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 932 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
984 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 933 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
@@ -995,6 +944,84 @@ out:
995 return err; 944 return err;
996} 945}
997 946
947int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
948{
949 struct mlx4_cmd_mailbox *mailbox;
950 u32 *outbox;
951 u8 field;
952 u32 field32;
953 int err;
954
955 mailbox = mlx4_alloc_cmd_mailbox(dev);
956 if (IS_ERR(mailbox))
957 return PTR_ERR(mailbox);
958 outbox = mailbox->buf;
959
960 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
961 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
962 MLX4_CMD_TIME_CLASS_A,
963 MLX4_CMD_NATIVE);
964
965 if (err)
966 goto out;
967
968 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
969 port_cap->max_vl = field >> 4;
970 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
971 port_cap->ib_mtu = field >> 4;
972 port_cap->max_port_width = field & 0xf;
973 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
974 port_cap->max_gids = 1 << (field & 0xf);
975 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
976 port_cap->max_pkeys = 1 << (field & 0xf);
977 } else {
978#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
979#define QUERY_PORT_MTU_OFFSET 0x01
980#define QUERY_PORT_ETH_MTU_OFFSET 0x02
981#define QUERY_PORT_WIDTH_OFFSET 0x06
982#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
983#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
984#define QUERY_PORT_MAX_VL_OFFSET 0x0b
985#define QUERY_PORT_MAC_OFFSET 0x10
986#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
987#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
988#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
989
990 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT,
991 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
992 if (err)
993 goto out;
994
995 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
996 port_cap->supported_port_types = field & 3;
997 port_cap->suggested_type = (field >> 3) & 1;
998 port_cap->default_sense = (field >> 4) & 1;
999 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1000 port_cap->ib_mtu = field & 0xf;
1001 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1002 port_cap->max_port_width = field & 0xf;
1003 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1004 port_cap->max_gids = 1 << (field >> 4);
1005 port_cap->max_pkeys = 1 << (field & 0xf);
1006 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1007 port_cap->max_vl = field & 0xf;
1008 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1009 port_cap->log_max_macs = field & 0xf;
1010 port_cap->log_max_vlans = field >> 4;
1011 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1012 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1013 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1014 port_cap->trans_type = field32 >> 24;
1015 port_cap->vendor_oui = field32 & 0xffffff;
1016 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1017 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1018 }
1019
1020out:
1021 mlx4_free_cmd_mailbox(dev, mailbox);
1022 return err;
1023}
1024
998#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1025#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
999#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1026#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1000#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1027#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.h b/drivers/net/ethernet/mellanox/mlx4/fw.h
index 0e910a452b02..744398b7ab5e 100644
--- a/drivers/net/ethernet/mellanox/mlx4/fw.h
+++ b/drivers/net/ethernet/mellanox/mlx4/fw.h
@@ -43,6 +43,25 @@ struct mlx4_mod_stat_cfg {
43 u8 log_pg_sz_m; 43 u8 log_pg_sz_m;
44}; 44};
45 45
46struct mlx4_port_cap {
47 u8 supported_port_types;
48 u8 suggested_type;
49 u8 default_sense;
50 u8 log_max_macs;
51 u8 log_max_vlans;
52 int ib_mtu;
53 int max_port_width;
54 int max_vl;
55 int max_gids;
56 int max_pkeys;
57 u64 def_mac;
58 u16 eth_mtu;
59 int trans_type;
60 int vendor_oui;
61 u16 wavelength;
62 u64 trans_code;
63};
64
46struct mlx4_dev_cap { 65struct mlx4_dev_cap {
47 int max_srq_sz; 66 int max_srq_sz;
48 int max_qp_sz; 67 int max_qp_sz;
@@ -67,17 +86,6 @@ struct mlx4_dev_cap {
67 int local_ca_ack_delay; 86 int local_ca_ack_delay;
68 int num_ports; 87 int num_ports;
69 u32 max_msg_sz; 88 u32 max_msg_sz;
70 int ib_mtu[MLX4_MAX_PORTS + 1];
71 int max_port_width[MLX4_MAX_PORTS + 1];
72 int max_vl[MLX4_MAX_PORTS + 1];
73 int max_gids[MLX4_MAX_PORTS + 1];
74 int max_pkeys[MLX4_MAX_PORTS + 1];
75 u64 def_mac[MLX4_MAX_PORTS + 1];
76 u16 eth_mtu[MLX4_MAX_PORTS + 1];
77 int trans_type[MLX4_MAX_PORTS + 1];
78 int vendor_oui[MLX4_MAX_PORTS + 1];
79 u16 wavelength[MLX4_MAX_PORTS + 1];
80 u64 trans_code[MLX4_MAX_PORTS + 1];
81 u16 stat_rate_support; 89 u16 stat_rate_support;
82 int fs_log_max_ucast_qp_range_size; 90 int fs_log_max_ucast_qp_range_size;
83 int fs_max_num_qp_per_entry; 91 int fs_max_num_qp_per_entry;
@@ -115,12 +123,8 @@ struct mlx4_dev_cap {
115 u64 max_icm_sz; 123 u64 max_icm_sz;
116 int max_gso_sz; 124 int max_gso_sz;
117 int max_rss_tbl_sz; 125 int max_rss_tbl_sz;
118 u8 supported_port_types[MLX4_MAX_PORTS + 1];
119 u8 suggested_type[MLX4_MAX_PORTS + 1];
120 u8 default_sense[MLX4_MAX_PORTS + 1];
121 u8 log_max_macs[MLX4_MAX_PORTS + 1];
122 u8 log_max_vlans[MLX4_MAX_PORTS + 1];
123 u32 max_counters; 126 u32 max_counters;
127 struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1];
124}; 128};
125 129
126struct mlx4_func_cap { 130struct mlx4_func_cap {
@@ -217,6 +221,7 @@ struct mlx4_set_ib_param {
217}; 221};
218 222
219int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap); 223int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
224int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap);
220int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 225int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
221 struct mlx4_func_cap *func_cap); 226 struct mlx4_func_cap *func_cap);
222int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 227int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c
index 3bfe90b95f96..6173b8072988 100644
--- a/drivers/net/ethernet/mellanox/mlx4/main.c
+++ b/drivers/net/ethernet/mellanox/mlx4/main.c
@@ -254,6 +254,46 @@ static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
254 } 254 }
255} 255}
256 256
257static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
258 struct mlx4_port_cap *port_cap)
259{
260 dev->caps.vl_cap[port] = port_cap->max_vl;
261 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
262 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
263 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
264 /* set gid and pkey table operating lengths by default
265 * to non-sriov values
266 */
267 dev->caps.gid_table_len[port] = port_cap->max_gids;
268 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
269 dev->caps.port_width_cap[port] = port_cap->max_port_width;
270 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
271 dev->caps.def_mac[port] = port_cap->def_mac;
272 dev->caps.supported_type[port] = port_cap->supported_port_types;
273 dev->caps.suggested_type[port] = port_cap->suggested_type;
274 dev->caps.default_sense[port] = port_cap->default_sense;
275 dev->caps.trans_type[port] = port_cap->trans_type;
276 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
277 dev->caps.wavelength[port] = port_cap->wavelength;
278 dev->caps.trans_code[port] = port_cap->trans_code;
279
280 return 0;
281}
282
283static int mlx4_dev_port(struct mlx4_dev *dev, int port,
284 struct mlx4_port_cap *port_cap)
285{
286 int err = 0;
287
288 err = mlx4_QUERY_PORT(dev, port, port_cap);
289
290 if (err)
291 mlx4_err(dev, "QUERY_PORT command failed.\n");
292
293 return err;
294}
295
296#define MLX4_A0_STEERING_TABLE_SIZE 256
257static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 297static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
258{ 298{
259 int err; 299 int err;
@@ -289,24 +329,11 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
289 dev->caps.num_sys_eqs : 329 dev->caps.num_sys_eqs :
290 MLX4_MAX_EQ_NUM; 330 MLX4_MAX_EQ_NUM;
291 for (i = 1; i <= dev->caps.num_ports; ++i) { 331 for (i = 1; i <= dev->caps.num_ports; ++i) {
292 dev->caps.vl_cap[i] = dev_cap->max_vl[i]; 332 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
293 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; 333 if (err) {
294 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; 334 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
295 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; 335 return err;
296 /* set gid and pkey table operating lengths by default 336 }
297 * to non-sriov values */
298 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
299 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
300 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
301 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
302 dev->caps.def_mac[i] = dev_cap->def_mac[i];
303 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
304 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
305 dev->caps.default_sense[i] = dev_cap->default_sense[i];
306 dev->caps.trans_type[i] = dev_cap->trans_type[i];
307 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
308 dev->caps.wavelength[i] = dev_cap->wavelength[i];
309 dev->caps.trans_code[i] = dev_cap->trans_code[i];
310 } 337 }
311 338
312 dev->caps.uar_page_size = PAGE_SIZE; 339 dev->caps.uar_page_size = PAGE_SIZE;
@@ -415,13 +442,13 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
415 dev->caps.possible_type[i] = dev->caps.port_type[i]; 442 dev->caps.possible_type[i] = dev->caps.port_type[i];
416 } 443 }
417 444
418 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { 445 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
419 dev->caps.log_num_macs = dev_cap->log_max_macs[i]; 446 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
420 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 447 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
421 i, 1 << dev->caps.log_num_macs); 448 i, 1 << dev->caps.log_num_macs);
422 } 449 }
423 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { 450 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
424 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; 451 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
425 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 452 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
426 i, 1 << dev->caps.log_num_vlans); 453 i, 1 << dev->caps.log_num_vlans);
427 } 454 }
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-25 18:09:03 -0400