diff options
-rw-r--r-- | drivers/video/omap2/dss/dss_features.c | 33 | ||||
-rw-r--r-- | drivers/video/omap2/dss/dss_features.h | 8 | ||||
-rw-r--r-- | drivers/video/omap2/dss/hdmi.c | 27 | ||||
-rw-r--r-- | drivers/video/omap2/dss/ti_hdmi.h | 41 | ||||
-rw-r--r-- | drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 223 | ||||
-rw-r--r-- | drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 14 |
6 files changed, 162 insertions, 184 deletions
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 2777eb6d603b..f8fd6dbacabc 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c | |||
@@ -789,39 +789,6 @@ static const struct omap_dss_features omap5_dss_features = { | |||
789 | .burst_size_unit = 16, | 789 | .burst_size_unit = 16, |
790 | }; | 790 | }; |
791 | 791 | ||
792 | #if defined(CONFIG_OMAP4_DSS_HDMI) | ||
793 | /* HDMI OMAP4 Functions*/ | ||
794 | static const struct ti_hdmi_ip_ops omap4_hdmi_functions = { | ||
795 | |||
796 | .video_configure = ti_hdmi_4xxx_basic_configure, | ||
797 | .read_edid = ti_hdmi_4xxx_read_edid, | ||
798 | .dump_core = ti_hdmi_4xxx_core_dump, | ||
799 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
800 | .audio_start = ti_hdmi_4xxx_audio_start, | ||
801 | .audio_stop = ti_hdmi_4xxx_audio_stop, | ||
802 | .audio_config = ti_hdmi_4xxx_audio_config, | ||
803 | .audio_get_dma_port = ti_hdmi_4xxx_audio_get_dma_port, | ||
804 | #endif | ||
805 | |||
806 | }; | ||
807 | |||
808 | void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data, | ||
809 | enum omapdss_version version) | ||
810 | { | ||
811 | switch (version) { | ||
812 | case OMAPDSS_VER_OMAP4430_ES1: | ||
813 | case OMAPDSS_VER_OMAP4430_ES2: | ||
814 | case OMAPDSS_VER_OMAP4: | ||
815 | ip_data->ops = &omap4_hdmi_functions; | ||
816 | break; | ||
817 | default: | ||
818 | ip_data->ops = NULL; | ||
819 | } | ||
820 | |||
821 | WARN_ON(ip_data->ops == NULL); | ||
822 | } | ||
823 | #endif | ||
824 | |||
825 | /* Functions returning values related to a DSS feature */ | 792 | /* Functions returning values related to a DSS feature */ |
826 | int dss_feat_get_num_mgrs(void) | 793 | int dss_feat_get_num_mgrs(void) |
827 | { | 794 | { |
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 489b9bec4a6d..10b0556e1352 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h | |||
@@ -20,10 +20,6 @@ | |||
20 | #ifndef __OMAP2_DSS_FEATURES_H | 20 | #ifndef __OMAP2_DSS_FEATURES_H |
21 | #define __OMAP2_DSS_FEATURES_H | 21 | #define __OMAP2_DSS_FEATURES_H |
22 | 22 | ||
23 | #if defined(CONFIG_OMAP4_DSS_HDMI) | ||
24 | #include "ti_hdmi.h" | ||
25 | #endif | ||
26 | |||
27 | #define MAX_DSS_MANAGERS 4 | 23 | #define MAX_DSS_MANAGERS 4 |
28 | #define MAX_DSS_OVERLAYS 4 | 24 | #define MAX_DSS_OVERLAYS 4 |
29 | #define MAX_DSS_LCD_MANAGERS 3 | 25 | #define MAX_DSS_LCD_MANAGERS 3 |
@@ -117,8 +113,4 @@ bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type); | |||
117 | bool dss_has_feature(enum dss_feat_id id); | 113 | bool dss_has_feature(enum dss_feat_id id); |
118 | void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); | 114 | void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); |
119 | void dss_features_init(enum omapdss_version version); | 115 | void dss_features_init(enum omapdss_version version); |
120 | #if defined(CONFIG_OMAP4_DSS_HDMI) | ||
121 | void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data, | ||
122 | enum omapdss_version version); | ||
123 | #endif | ||
124 | #endif | 116 | #endif |
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index f7e2ac6861b6..0e9ecd691c5c 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c | |||
@@ -37,12 +37,10 @@ | |||
37 | #include <video/omapdss.h> | 37 | #include <video/omapdss.h> |
38 | 38 | ||
39 | #include "ti_hdmi.h" | 39 | #include "ti_hdmi.h" |
40 | #include "ti_hdmi_4xxx_ip.h" | ||
40 | #include "dss.h" | 41 | #include "dss.h" |
41 | #include "dss_features.h" | 42 | #include "dss_features.h" |
42 | 43 | ||
43 | #define HDMI_CORE_SYS 0x400 | ||
44 | #define HDMI_CORE_AV 0x900 | ||
45 | |||
46 | /* HDMI EDID Length move this */ | 44 | /* HDMI EDID Length move this */ |
47 | #define HDMI_EDID_MAX_LENGTH 256 | 45 | #define HDMI_EDID_MAX_LENGTH 256 |
48 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 | 46 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 |
@@ -493,7 +491,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |||
493 | goto err_phy_enable; | 491 | goto err_phy_enable; |
494 | } | 492 | } |
495 | 493 | ||
496 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); | 494 | hdmi4_configure(&hdmi.ip_data.core, &hdmi.ip_data.wp, |
495 | &hdmi.ip_data.cfg); | ||
497 | 496 | ||
498 | /* bypass TV gamma table */ | 497 | /* bypass TV gamma table */ |
499 | dispc_enable_gamma_table(0); | 498 | dispc_enable_gamma_table(0); |
@@ -594,7 +593,7 @@ static void hdmi_dump_regs(struct seq_file *s) | |||
594 | hdmi_wp_dump(&hdmi.ip_data.wp, s); | 593 | hdmi_wp_dump(&hdmi.ip_data.wp, s); |
595 | hdmi_pll_dump(&hdmi.ip_data.pll, s); | 594 | hdmi_pll_dump(&hdmi.ip_data.pll, s); |
596 | hdmi_phy_dump(&hdmi.ip_data.phy, s); | 595 | hdmi_phy_dump(&hdmi.ip_data.phy, s); |
597 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); | 596 | hdmi4_core_dump(&hdmi.ip_data.core, s); |
598 | 597 | ||
599 | hdmi_runtime_put(); | 598 | hdmi_runtime_put(); |
600 | mutex_unlock(&hdmi.lock); | 599 | mutex_unlock(&hdmi.lock); |
@@ -609,7 +608,7 @@ static int read_edid(u8 *buf, int len) | |||
609 | r = hdmi_runtime_get(); | 608 | r = hdmi_runtime_get(); |
610 | BUG_ON(r); | 609 | BUG_ON(r); |
611 | 610 | ||
612 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); | 611 | r = hdmi4_read_edid(&hdmi.ip_data.core, buf, len); |
613 | 612 | ||
614 | hdmi_runtime_put(); | 613 | hdmi_runtime_put(); |
615 | mutex_unlock(&hdmi.lock); | 614 | mutex_unlock(&hdmi.lock); |
@@ -813,7 +812,6 @@ static bool hdmi_mode_has_audio(void) | |||
813 | else | 812 | else |
814 | return false; | 813 | return false; |
815 | } | 814 | } |
816 | |||
817 | #endif | 815 | #endif |
818 | 816 | ||
819 | static int hdmi_connect(struct omap_dss_device *dssdev, | 817 | static int hdmi_connect(struct omap_dss_device *dssdev, |
@@ -822,8 +820,6 @@ static int hdmi_connect(struct omap_dss_device *dssdev, | |||
822 | struct omap_overlay_manager *mgr; | 820 | struct omap_overlay_manager *mgr; |
823 | int r; | 821 | int r; |
824 | 822 | ||
825 | dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version()); | ||
826 | |||
827 | r = hdmi_init_regulator(); | 823 | r = hdmi_init_regulator(); |
828 | if (r) | 824 | if (r) |
829 | return r; | 825 | return r; |
@@ -914,12 +910,12 @@ static void hdmi_audio_disable(struct omap_dss_device *dssdev) | |||
914 | 910 | ||
915 | static int hdmi_audio_start(struct omap_dss_device *dssdev) | 911 | static int hdmi_audio_start(struct omap_dss_device *dssdev) |
916 | { | 912 | { |
917 | return hdmi.ip_data.ops->audio_start(&hdmi.ip_data); | 913 | return hdmi4_audio_start(&hdmi.ip_data.core, &hdmi.ip_data.wp); |
918 | } | 914 | } |
919 | 915 | ||
920 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) | 916 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) |
921 | { | 917 | { |
922 | hdmi.ip_data.ops->audio_stop(&hdmi.ip_data); | 918 | hdmi4_audio_stop(&hdmi.ip_data.core, &hdmi.ip_data.wp); |
923 | } | 919 | } |
924 | 920 | ||
925 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | 921 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) |
@@ -946,7 +942,7 @@ static int hdmi_audio_config(struct omap_dss_device *dssdev, | |||
946 | goto err; | 942 | goto err; |
947 | } | 943 | } |
948 | 944 | ||
949 | r = hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio); | 945 | r = hdmi4_audio_config(&hdmi.ip_data.core, &hdmi.ip_data.wp, audio); |
950 | if (r) | 946 | if (r) |
951 | goto err; | 947 | goto err; |
952 | 948 | ||
@@ -1053,6 +1049,10 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev) | |||
1053 | if (r) | 1049 | if (r) |
1054 | return r; | 1050 | return r; |
1055 | 1051 | ||
1052 | r = hdmi4_core_init(pdev, &hdmi.ip_data.core); | ||
1053 | if (r) | ||
1054 | return r; | ||
1055 | |||
1056 | r = hdmi_get_clocks(pdev); | 1056 | r = hdmi_get_clocks(pdev); |
1057 | if (r) { | 1057 | if (r) { |
1058 | DSSERR("can't get clocks\n"); | 1058 | DSSERR("can't get clocks\n"); |
@@ -1061,9 +1061,6 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev) | |||
1061 | 1061 | ||
1062 | pm_runtime_enable(&pdev->dev); | 1062 | pm_runtime_enable(&pdev->dev); |
1063 | 1063 | ||
1064 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; | ||
1065 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; | ||
1066 | |||
1067 | hdmi_init_output(pdev); | 1064 | hdmi_init_output(pdev); |
1068 | 1065 | ||
1069 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); | 1066 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h index 716bac450ef0..9eb9b321314d 100644 --- a/drivers/video/omap2/dss/ti_hdmi.h +++ b/drivers/video/omap2/dss/ti_hdmi.h | |||
@@ -145,27 +145,6 @@ struct hdmi_audio_dma { | |||
145 | u16 fifo_threshold; | 145 | u16 fifo_threshold; |
146 | }; | 146 | }; |
147 | 147 | ||
148 | struct ti_hdmi_ip_ops { | ||
149 | |||
150 | void (*video_configure)(struct hdmi_ip_data *ip_data); | ||
151 | |||
152 | int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len); | ||
153 | |||
154 | void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
155 | |||
156 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
157 | int (*audio_start)(struct hdmi_ip_data *ip_data); | ||
158 | |||
159 | void (*audio_stop)(struct hdmi_ip_data *ip_data); | ||
160 | |||
161 | int (*audio_config)(struct hdmi_ip_data *ip_data, | ||
162 | struct omap_dss_audio *audio); | ||
163 | |||
164 | int (*audio_get_dma_port)(u32 *offset, u32 *size); | ||
165 | #endif | ||
166 | |||
167 | }; | ||
168 | |||
169 | /* | 148 | /* |
170 | * Refer to section 8.2 in HDMI 1.3 specification for | 149 | * Refer to section 8.2 in HDMI 1.3 specification for |
171 | * details about infoframe databytes | 150 | * details about infoframe databytes |
@@ -223,17 +202,19 @@ struct hdmi_phy_data { | |||
223 | int irq; | 202 | int irq; |
224 | }; | 203 | }; |
225 | 204 | ||
205 | struct hdmi_core_data { | ||
206 | void __iomem *base; | ||
207 | |||
208 | struct hdmi_core_infoframe_avi avi_cfg; | ||
209 | }; | ||
210 | |||
226 | struct hdmi_ip_data { | 211 | struct hdmi_ip_data { |
227 | struct hdmi_wp_data wp; | 212 | struct hdmi_wp_data wp; |
228 | struct hdmi_pll_data pll; | 213 | struct hdmi_pll_data pll; |
229 | struct hdmi_phy_data phy; | 214 | struct hdmi_phy_data phy; |
215 | struct hdmi_core_data core; | ||
230 | 216 | ||
231 | unsigned long core_sys_offset; | ||
232 | unsigned long core_av_offset; | ||
233 | |||
234 | const struct ti_hdmi_ip_ops *ops; | ||
235 | struct hdmi_config cfg; | 217 | struct hdmi_config cfg; |
236 | struct hdmi_core_infoframe_avi avi_cfg; | ||
237 | 218 | ||
238 | /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */ | 219 | /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */ |
239 | struct mutex lock; | 220 | struct mutex lock; |
@@ -273,9 +254,6 @@ void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp); | |||
273 | void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); | 254 | void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); |
274 | int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); | 255 | int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); |
275 | 256 | ||
276 | int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len); | ||
277 | void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data); | ||
278 | void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
279 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | 257 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
280 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts); | 258 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts); |
281 | int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); | 259 | int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); |
@@ -284,10 +262,5 @@ void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, | |||
284 | struct hdmi_audio_format *aud_fmt); | 262 | struct hdmi_audio_format *aud_fmt); |
285 | void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, | 263 | void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, |
286 | struct hdmi_audio_dma *aud_dma); | 264 | struct hdmi_audio_dma *aud_dma); |
287 | int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data); | ||
288 | void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data); | ||
289 | int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | ||
290 | struct omap_dss_audio *audio); | ||
291 | int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size); | ||
292 | #endif | 265 | #endif |
293 | #endif | 266 | #endif |
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c index c705aa113aac..4ac9e0af7ca6 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
27 | #include <linux/mutex.h> | 27 | #include <linux/mutex.h> |
28 | #include <linux/delay.h> | 28 | #include <linux/delay.h> |
29 | #include <linux/platform_device.h> | ||
29 | #include <linux/string.h> | 30 | #include <linux/string.h> |
30 | #include <linux/seq_file.h> | 31 | #include <linux/seq_file.h> |
31 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | 32 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
@@ -37,6 +38,8 @@ | |||
37 | #include "dss.h" | 38 | #include "dss.h" |
38 | #include "dss_features.h" | 39 | #include "dss_features.h" |
39 | 40 | ||
41 | #define HDMI_CORE_AV 0x500 | ||
42 | |||
40 | static inline void hdmi_write_reg(void __iomem *base_addr, | 43 | static inline void hdmi_write_reg(void __iomem *base_addr, |
41 | const u16 idx, u32 val) | 44 | const u16 idx, u32 val) |
42 | { | 45 | { |
@@ -67,19 +70,14 @@ static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, | |||
67 | return val; | 70 | return val; |
68 | } | 71 | } |
69 | 72 | ||
70 | static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data) | 73 | static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) |
71 | { | ||
72 | return ip_data->wp.base + ip_data->core_av_offset; | ||
73 | } | ||
74 | |||
75 | static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data) | ||
76 | { | 74 | { |
77 | return ip_data->wp.base + ip_data->core_sys_offset; | 75 | return core->base + HDMI_CORE_AV; |
78 | } | 76 | } |
79 | 77 | ||
80 | static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data) | 78 | static int hdmi_core_ddc_init(struct hdmi_core_data *core) |
81 | { | 79 | { |
82 | void __iomem *base = hdmi_core_sys_base(ip_data); | 80 | void __iomem *base = core->base; |
83 | 81 | ||
84 | /* Turn on CLK for DDC */ | 82 | /* Turn on CLK for DDC */ |
85 | REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); | 83 | REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); |
@@ -119,10 +117,10 @@ static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data) | |||
119 | return 0; | 117 | return 0; |
120 | } | 118 | } |
121 | 119 | ||
122 | static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, | 120 | static int hdmi_core_ddc_edid(struct hdmi_core_data *core, |
123 | u8 *pedid, int ext) | 121 | u8 *pedid, int ext) |
124 | { | 122 | { |
125 | void __iomem *base = hdmi_core_sys_base(ip_data); | 123 | void __iomem *base = core->base; |
126 | u32 i; | 124 | u32 i; |
127 | char checksum; | 125 | char checksum; |
128 | u32 offset = 0; | 126 | u32 offset = 0; |
@@ -201,26 +199,25 @@ static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, | |||
201 | return 0; | 199 | return 0; |
202 | } | 200 | } |
203 | 201 | ||
204 | int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, | 202 | int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) |
205 | u8 *edid, int len) | ||
206 | { | 203 | { |
207 | int r, l; | 204 | int r, l; |
208 | 205 | ||
209 | if (len < 128) | 206 | if (len < 128) |
210 | return -EINVAL; | 207 | return -EINVAL; |
211 | 208 | ||
212 | r = hdmi_core_ddc_init(ip_data); | 209 | r = hdmi_core_ddc_init(core); |
213 | if (r) | 210 | if (r) |
214 | return r; | 211 | return r; |
215 | 212 | ||
216 | r = hdmi_core_ddc_edid(ip_data, edid, 0); | 213 | r = hdmi_core_ddc_edid(core, edid, 0); |
217 | if (r) | 214 | if (r) |
218 | return r; | 215 | return r; |
219 | 216 | ||
220 | l = 128; | 217 | l = 128; |
221 | 218 | ||
222 | if (len >= 128 * 2 && edid[0x7e] > 0) { | 219 | if (len >= 128 * 2 && edid[0x7e] > 0) { |
223 | r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1); | 220 | r = hdmi_core_ddc_edid(core, edid + 0x80, 1); |
224 | if (r) | 221 | if (r) |
225 | return r; | 222 | return r; |
226 | l += 128; | 223 | l += 128; |
@@ -273,30 +270,31 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |||
273 | repeat_cfg->generic_pkt_repeat = 0; | 270 | repeat_cfg->generic_pkt_repeat = 0; |
274 | } | 271 | } |
275 | 272 | ||
276 | static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data) | 273 | static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) |
277 | { | 274 | { |
278 | pr_debug("Enter hdmi_core_powerdown_disable\n"); | 275 | pr_debug("Enter hdmi_core_powerdown_disable\n"); |
279 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); | 276 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); |
280 | } | 277 | } |
281 | 278 | ||
282 | static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data) | 279 | static void hdmi_core_swreset_release(struct hdmi_core_data *core) |
283 | { | 280 | { |
284 | pr_debug("Enter hdmi_core_swreset_release\n"); | 281 | pr_debug("Enter hdmi_core_swreset_release\n"); |
285 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0); | 282 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); |
286 | } | 283 | } |
287 | 284 | ||
288 | static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data) | 285 | static void hdmi_core_swreset_assert(struct hdmi_core_data *core) |
289 | { | 286 | { |
290 | pr_debug("Enter hdmi_core_swreset_assert\n"); | 287 | pr_debug("Enter hdmi_core_swreset_assert\n"); |
291 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0); | 288 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); |
292 | } | 289 | } |
293 | 290 | ||
294 | /* HDMI_CORE_VIDEO_CONFIG */ | 291 | /* HDMI_CORE_VIDEO_CONFIG */ |
295 | static void hdmi_core_video_config(struct hdmi_ip_data *ip_data, | 292 | static void hdmi_core_video_config(struct hdmi_core_data *core, |
296 | struct hdmi_core_video_config *cfg) | 293 | struct hdmi_core_video_config *cfg) |
297 | { | 294 | { |
298 | u32 r = 0; | 295 | u32 r = 0; |
299 | void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); | 296 | void __iomem *core_sys_base = core->base; |
297 | void __iomem *core_av_base = hdmi_av_base(core); | ||
300 | 298 | ||
301 | /* sys_ctrl1 default configuration not tunable */ | 299 | /* sys_ctrl1 default configuration not tunable */ |
302 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); | 300 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); |
@@ -323,23 +321,23 @@ static void hdmi_core_video_config(struct hdmi_ip_data *ip_data, | |||
323 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); | 321 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); |
324 | 322 | ||
325 | /* HDMI_Ctrl */ | 323 | /* HDMI_Ctrl */ |
326 | r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL); | 324 | r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); |
327 | r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); | 325 | r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); |
328 | r = FLD_MOD(r, cfg->pkt_mode, 5, 3); | 326 | r = FLD_MOD(r, cfg->pkt_mode, 5, 3); |
329 | r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); | 327 | r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); |
330 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r); | 328 | hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r); |
331 | 329 | ||
332 | /* TMDS_CTRL */ | 330 | /* TMDS_CTRL */ |
333 | REG_FLD_MOD(core_sys_base, | 331 | REG_FLD_MOD(core_sys_base, |
334 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); | 332 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); |
335 | } | 333 | } |
336 | 334 | ||
337 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data) | 335 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) |
338 | { | 336 | { |
339 | u32 val; | 337 | u32 val; |
340 | char sum = 0, checksum = 0; | 338 | char sum = 0, checksum = 0; |
341 | void __iomem *av_base = hdmi_av_base(ip_data); | 339 | void __iomem *av_base = hdmi_av_base(core); |
342 | struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg; | 340 | struct hdmi_core_infoframe_avi info_avi = core->avi_cfg; |
343 | 341 | ||
344 | sum += 0x82 + 0x002 + 0x00D; | 342 | sum += 0x82 + 0x002 + 0x00D; |
345 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); | 343 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); |
@@ -410,64 +408,64 @@ static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data) | |||
410 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); | 408 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); |
411 | } | 409 | } |
412 | 410 | ||
413 | static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data, | 411 | static void hdmi_core_av_packet_config(struct hdmi_core_data *core, |
414 | struct hdmi_core_packet_enable_repeat repeat_cfg) | 412 | struct hdmi_core_packet_enable_repeat repeat_cfg) |
415 | { | 413 | { |
416 | /* enable/repeat the infoframe */ | 414 | /* enable/repeat the infoframe */ |
417 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1, | 415 | hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1, |
418 | (repeat_cfg.audio_pkt << 5) | | 416 | (repeat_cfg.audio_pkt << 5) | |
419 | (repeat_cfg.audio_pkt_repeat << 4) | | 417 | (repeat_cfg.audio_pkt_repeat << 4) | |
420 | (repeat_cfg.avi_infoframe << 1) | | 418 | (repeat_cfg.avi_infoframe << 1) | |
421 | (repeat_cfg.avi_infoframe_repeat)); | 419 | (repeat_cfg.avi_infoframe_repeat)); |
422 | 420 | ||
423 | /* enable/repeat the packet */ | 421 | /* enable/repeat the packet */ |
424 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2, | 422 | hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2, |
425 | (repeat_cfg.gen_cntrl_pkt << 3) | | 423 | (repeat_cfg.gen_cntrl_pkt << 3) | |
426 | (repeat_cfg.gen_cntrl_pkt_repeat << 2) | | 424 | (repeat_cfg.gen_cntrl_pkt_repeat << 2) | |
427 | (repeat_cfg.generic_pkt << 1) | | 425 | (repeat_cfg.generic_pkt << 1) | |
428 | (repeat_cfg.generic_pkt_repeat)); | 426 | (repeat_cfg.generic_pkt_repeat)); |
429 | } | 427 | } |
430 | 428 | ||
431 | void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data) | 429 | void hdmi4_configure(struct hdmi_core_data *core, |
430 | struct hdmi_wp_data *wp, struct hdmi_config *cfg) | ||
432 | { | 431 | { |
433 | /* HDMI */ | 432 | /* HDMI */ |
434 | struct omap_video_timings video_timing; | 433 | struct omap_video_timings video_timing; |
435 | struct hdmi_video_format video_format; | 434 | struct hdmi_video_format video_format; |
436 | /* HDMI core */ | 435 | /* HDMI core */ |
437 | struct hdmi_core_infoframe_avi *avi_cfg = &ip_data->avi_cfg; | 436 | struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg; |
438 | struct hdmi_core_video_config v_core_cfg; | 437 | struct hdmi_core_video_config v_core_cfg; |
439 | struct hdmi_core_packet_enable_repeat repeat_cfg; | 438 | struct hdmi_core_packet_enable_repeat repeat_cfg; |
440 | struct hdmi_config *cfg = &ip_data->cfg; | ||
441 | 439 | ||
442 | hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg); | 440 | hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg); |
443 | 441 | ||
444 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); | 442 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); |
445 | 443 | ||
446 | hdmi_wp_video_config_timing(&ip_data->wp, &video_timing); | 444 | hdmi_wp_video_config_timing(wp, &video_timing); |
447 | 445 | ||
448 | /* video config */ | 446 | /* video config */ |
449 | video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; | 447 | video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; |
450 | 448 | ||
451 | hdmi_wp_video_config_format(&ip_data->wp, &video_format); | 449 | hdmi_wp_video_config_format(wp, &video_format); |
452 | 450 | ||
453 | hdmi_wp_video_config_interface(&ip_data->wp, &video_timing); | 451 | hdmi_wp_video_config_interface(wp, &video_timing); |
454 | 452 | ||
455 | /* | 453 | /* |
456 | * configure core video part | 454 | * configure core video part |
457 | * set software reset in the core | 455 | * set software reset in the core |
458 | */ | 456 | */ |
459 | hdmi_core_swreset_assert(ip_data); | 457 | hdmi_core_swreset_assert(core); |
460 | 458 | ||
461 | /* power down off */ | 459 | /* power down off */ |
462 | hdmi_core_powerdown_disable(ip_data); | 460 | hdmi_core_powerdown_disable(core); |
463 | 461 | ||
464 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; | 462 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; |
465 | v_core_cfg.hdmi_dvi = cfg->cm.mode; | 463 | v_core_cfg.hdmi_dvi = cfg->cm.mode; |
466 | 464 | ||
467 | hdmi_core_video_config(ip_data, &v_core_cfg); | 465 | hdmi_core_video_config(core, &v_core_cfg); |
468 | 466 | ||
469 | /* release software reset in the core */ | 467 | /* release software reset in the core */ |
470 | hdmi_core_swreset_release(ip_data); | 468 | hdmi_core_swreset_release(core); |
471 | 469 | ||
472 | /* | 470 | /* |
473 | * configure packet | 471 | * configure packet |
@@ -492,7 +490,7 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data) | |||
492 | avi_cfg->db10_11_pixel_eofleft = 0; | 490 | avi_cfg->db10_11_pixel_eofleft = 0; |
493 | avi_cfg->db12_13_pixel_sofright = 0; | 491 | avi_cfg->db12_13_pixel_sofright = 0; |
494 | 492 | ||
495 | hdmi_core_aux_infoframe_avi_config(ip_data); | 493 | hdmi_core_aux_infoframe_avi_config(core); |
496 | 494 | ||
497 | /* enable/repeat the infoframe */ | 495 | /* enable/repeat the infoframe */ |
498 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; | 496 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; |
@@ -500,21 +498,21 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data) | |||
500 | /* wakeup */ | 498 | /* wakeup */ |
501 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; | 499 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; |
502 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; | 500 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; |
503 | hdmi_core_av_packet_config(ip_data, repeat_cfg); | 501 | hdmi_core_av_packet_config(core, repeat_cfg); |
504 | } | 502 | } |
505 | 503 | ||
506 | void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) | 504 | void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s) |
507 | { | 505 | { |
508 | int i; | 506 | int i; |
509 | 507 | ||
510 | #define CORE_REG(i, name) name(i) | 508 | #define CORE_REG(i, name) name(i) |
511 | #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ | 509 | #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ |
512 | hdmi_read_reg(hdmi_core_sys_base(ip_data), r)) | 510 | hdmi_read_reg(core->base, r)) |
513 | #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ | 511 | #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ |
514 | hdmi_read_reg(hdmi_av_base(ip_data), r)) | 512 | hdmi_read_reg(hdmi_av_base(core), r)) |
515 | #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ | 513 | #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ |
516 | (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ | 514 | (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ |
517 | hdmi_read_reg(hdmi_av_base(ip_data), CORE_REG(i, r))) | 515 | hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) |
518 | 516 | ||
519 | DUMPCORE(HDMI_CORE_SYS_VND_IDL); | 517 | DUMPCORE(HDMI_CORE_SYS_VND_IDL); |
520 | DUMPCORE(HDMI_CORE_SYS_DEV_IDL); | 518 | DUMPCORE(HDMI_CORE_SYS_DEV_IDL); |
@@ -672,11 +670,11 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) | |||
672 | } | 670 | } |
673 | 671 | ||
674 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | 672 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
675 | static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data, | 673 | static void hdmi_core_audio_config(struct hdmi_core_data *core, |
676 | struct hdmi_core_audio_config *cfg) | 674 | struct hdmi_core_audio_config *cfg) |
677 | { | 675 | { |
678 | u32 r; | 676 | u32 r; |
679 | void __iomem *av_base = hdmi_av_base(ip_data); | 677 | void __iomem *av_base = hdmi_av_base(core); |
680 | 678 | ||
681 | /* | 679 | /* |
682 | * Parameters for generation of Audio Clock Recovery packets | 680 | * Parameters for generation of Audio Clock Recovery packets |
@@ -771,11 +769,11 @@ static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data, | |||
771 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); | 769 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); |
772 | } | 770 | } |
773 | 771 | ||
774 | static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data, | 772 | static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, |
775 | struct snd_cea_861_aud_if *info_aud) | 773 | struct snd_cea_861_aud_if *info_aud) |
776 | { | 774 | { |
777 | u8 sum = 0, checksum = 0; | 775 | u8 sum = 0, checksum = 0; |
778 | void __iomem *av_base = hdmi_av_base(ip_data); | 776 | void __iomem *av_base = hdmi_av_base(core); |
779 | 777 | ||
780 | /* | 778 | /* |
781 | * Set audio info frame type, version and length as | 779 | * Set audio info frame type, version and length as |
@@ -821,20 +819,20 @@ static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data, | |||
821 | */ | 819 | */ |
822 | } | 820 | } |
823 | 821 | ||
824 | int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | 822 | int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
825 | struct omap_dss_audio *audio) | 823 | struct omap_dss_audio *audio) |
826 | { | 824 | { |
827 | struct hdmi_audio_format audio_format; | 825 | struct hdmi_audio_format audio_format; |
828 | struct hdmi_audio_dma audio_dma; | 826 | struct hdmi_audio_dma audio_dma; |
829 | struct hdmi_core_audio_config core; | 827 | struct hdmi_core_audio_config acore; |
830 | int err, n, cts, channel_count; | 828 | int err, n, cts, channel_count; |
831 | unsigned int fs_nr; | 829 | unsigned int fs_nr; |
832 | bool word_length_16b = false; | 830 | bool word_length_16b = false; |
833 | 831 | ||
834 | if (!audio || !audio->iec || !audio->cea || !ip_data) | 832 | if (!audio || !audio->iec || !audio->cea || !core) |
835 | return -EINVAL; | 833 | return -EINVAL; |
836 | 834 | ||
837 | core.iec60958_cfg = audio->iec; | 835 | acore.iec60958_cfg = audio->iec; |
838 | /* | 836 | /* |
839 | * In the IEC-60958 status word, check if the audio sample word length | 837 | * In the IEC-60958 status word, check if the audio sample word length |
840 | * is 16-bit as several optimizations can be performed in such case. | 838 | * is 16-bit as several optimizations can be performed in such case. |
@@ -845,22 +843,22 @@ int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | |||
845 | 843 | ||
846 | /* I2S configuration. See Phillips' specification */ | 844 | /* I2S configuration. See Phillips' specification */ |
847 | if (word_length_16b) | 845 | if (word_length_16b) |
848 | core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; | 846 | acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
849 | else | 847 | else |
850 | core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; | 848 | acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
851 | /* | 849 | /* |
852 | * The I2S input word length is twice the lenght given in the IEC-60958 | 850 | * The I2S input word length is twice the lenght given in the IEC-60958 |
853 | * status word. If the word size is greater than | 851 | * status word. If the word size is greater than |
854 | * 20 bits, increment by one. | 852 | * 20 bits, increment by one. |
855 | */ | 853 | */ |
856 | core.i2s_cfg.in_length_bits = audio->iec->status[4] | 854 | acore.i2s_cfg.in_length_bits = audio->iec->status[4] |
857 | & IEC958_AES4_CON_WORDLEN; | 855 | & IEC958_AES4_CON_WORDLEN; |
858 | if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) | 856 | if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) |
859 | core.i2s_cfg.in_length_bits++; | 857 | acore.i2s_cfg.in_length_bits++; |
860 | core.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; | 858 | acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; |
861 | core.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; | 859 | acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; |
862 | core.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; | 860 | acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; |
863 | core.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; | 861 | acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; |
864 | 862 | ||
865 | /* convert sample frequency to a number */ | 863 | /* convert sample frequency to a number */ |
866 | switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { | 864 | switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { |
@@ -892,20 +890,20 @@ int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | |||
892 | err = hdmi_compute_acr(fs_nr, &n, &cts); | 890 | err = hdmi_compute_acr(fs_nr, &n, &cts); |
893 | 891 | ||
894 | /* Audio clock regeneration settings */ | 892 | /* Audio clock regeneration settings */ |
895 | core.n = n; | 893 | acore.n = n; |
896 | core.cts = cts; | 894 | acore.cts = cts; |
897 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { | 895 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { |
898 | core.aud_par_busclk = 0; | 896 | acore.aud_par_busclk = 0; |
899 | core.cts_mode = HDMI_AUDIO_CTS_MODE_SW; | 897 | acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; |
900 | core.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); | 898 | acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); |
901 | } else { | 899 | } else { |
902 | core.aud_par_busclk = (((128 * 31) - 1) << 8); | 900 | acore.aud_par_busclk = (((128 * 31) - 1) << 8); |
903 | core.cts_mode = HDMI_AUDIO_CTS_MODE_HW; | 901 | acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; |
904 | core.use_mclk = true; | 902 | acore.use_mclk = true; |
905 | } | 903 | } |
906 | 904 | ||
907 | if (core.use_mclk) | 905 | if (acore.use_mclk) |
908 | core.mclk_mode = HDMI_AUDIO_MCLK_128FS; | 906 | acore.mclk_mode = HDMI_AUDIO_MCLK_128FS; |
909 | 907 | ||
910 | /* Audio channels settings */ | 908 | /* Audio channels settings */ |
911 | channel_count = (audio->cea->db1_ct_cc & | 909 | channel_count = (audio->cea->db1_ct_cc & |
@@ -943,25 +941,25 @@ int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | |||
943 | */ | 941 | */ |
944 | if (channel_count == 2) { | 942 | if (channel_count == 2) { |
945 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; | 943 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; |
946 | core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; | 944 | acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; |
947 | core.layout = HDMI_AUDIO_LAYOUT_2CH; | 945 | acore.layout = HDMI_AUDIO_LAYOUT_2CH; |
948 | } else { | 946 | } else { |
949 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; | 947 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; |
950 | core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | | 948 | acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | |
951 | HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | | 949 | HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | |
952 | HDMI_AUDIO_I2S_SD3_EN; | 950 | HDMI_AUDIO_I2S_SD3_EN; |
953 | core.layout = HDMI_AUDIO_LAYOUT_8CH; | 951 | acore.layout = HDMI_AUDIO_LAYOUT_8CH; |
954 | } | 952 | } |
955 | 953 | ||
956 | core.en_spdif = false; | 954 | acore.en_spdif = false; |
957 | /* use sample frequency from channel status word */ | 955 | /* use sample frequency from channel status word */ |
958 | core.fs_override = true; | 956 | acore.fs_override = true; |
959 | /* enable ACR packets */ | 957 | /* enable ACR packets */ |
960 | core.en_acr_pkt = true; | 958 | acore.en_acr_pkt = true; |
961 | /* disable direct streaming digital audio */ | 959 | /* disable direct streaming digital audio */ |
962 | core.en_dsd_audio = false; | 960 | acore.en_dsd_audio = false; |
963 | /* use parallel audio interface */ | 961 | /* use parallel audio interface */ |
964 | core.en_parallel_aud_input = true; | 962 | acore.en_parallel_aud_input = true; |
965 | 963 | ||
966 | /* DMA settings */ | 964 | /* DMA settings */ |
967 | if (word_length_16b) | 965 | if (word_length_16b) |
@@ -988,37 +986,37 @@ int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | |||
988 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; | 986 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; |
989 | 987 | ||
990 | /* configure DMA and audio FIFO format*/ | 988 | /* configure DMA and audio FIFO format*/ |
991 | hdmi_wp_audio_config_dma(&ip_data->wp, &audio_dma); | 989 | hdmi_wp_audio_config_dma(wp, &audio_dma); |
992 | hdmi_wp_audio_config_format(&ip_data->wp, &audio_format); | 990 | hdmi_wp_audio_config_format(wp, &audio_format); |
993 | 991 | ||
994 | /* configure the core*/ | 992 | /* configure the core*/ |
995 | ti_hdmi_4xxx_core_audio_config(ip_data, &core); | 993 | hdmi_core_audio_config(core, &acore); |
996 | 994 | ||
997 | /* configure CEA 861 audio infoframe*/ | 995 | /* configure CEA 861 audio infoframe*/ |
998 | ti_hdmi_4xxx_core_audio_infoframe_cfg(ip_data, audio->cea); | 996 | hdmi_core_audio_infoframe_cfg(core, audio->cea); |
999 | 997 | ||
1000 | return 0; | 998 | return 0; |
1001 | } | 999 | } |
1002 | 1000 | ||
1003 | int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data) | 1001 | int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) |
1004 | { | 1002 | { |
1005 | REG_FLD_MOD(hdmi_av_base(ip_data), | 1003 | REG_FLD_MOD(hdmi_av_base(core), |
1006 | HDMI_CORE_AV_AUD_MODE, true, 0, 0); | 1004 | HDMI_CORE_AV_AUD_MODE, true, 0, 0); |
1007 | 1005 | ||
1008 | hdmi_wp_audio_core_req_enable(&ip_data->wp, true); | 1006 | hdmi_wp_audio_core_req_enable(wp, true); |
1009 | 1007 | ||
1010 | return 0; | 1008 | return 0; |
1011 | } | 1009 | } |
1012 | 1010 | ||
1013 | void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data) | 1011 | void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) |
1014 | { | 1012 | { |
1015 | REG_FLD_MOD(hdmi_av_base(ip_data), | 1013 | REG_FLD_MOD(hdmi_av_base(core), |
1016 | HDMI_CORE_AV_AUD_MODE, false, 0, 0); | 1014 | HDMI_CORE_AV_AUD_MODE, false, 0, 0); |
1017 | 1015 | ||
1018 | hdmi_wp_audio_core_req_enable(&ip_data->wp, false); | 1016 | hdmi_wp_audio_core_req_enable(wp, false); |
1019 | } | 1017 | } |
1020 | 1018 | ||
1021 | int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size) | 1019 | int hdmi4_audio_get_dma_port(u32 *offset, u32 *size) |
1022 | { | 1020 | { |
1023 | if (!offset || !size) | 1021 | if (!offset || !size) |
1024 | return -EINVAL; | 1022 | return -EINVAL; |
@@ -1028,3 +1026,40 @@ int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size) | |||
1028 | } | 1026 | } |
1029 | 1027 | ||
1030 | #endif | 1028 | #endif |
1029 | |||
1030 | #define CORE_OFFSET 0x400 | ||
1031 | #define CORE_SIZE 0xc00 | ||
1032 | |||
1033 | int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) | ||
1034 | { | ||
1035 | struct resource *res; | ||
1036 | struct resource temp_res; | ||
1037 | |||
1038 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_core"); | ||
1039 | if (!res) { | ||
1040 | DSSDBG("can't get CORE mem resource by name\n"); | ||
1041 | /* | ||
1042 | * if hwmod/DT doesn't have the memory resource information | ||
1043 | * split into HDMI sub blocks by name, we try again by getting | ||
1044 | * the platform's first resource. this code will be removed when | ||
1045 | * the driver can get the mem resources by name | ||
1046 | */ | ||
1047 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1048 | if (!res) { | ||
1049 | DSSERR("can't get CORE mem resource\n"); | ||
1050 | return -EINVAL; | ||
1051 | } | ||
1052 | |||
1053 | temp_res.start = res->start + CORE_OFFSET; | ||
1054 | temp_res.end = temp_res.start + CORE_SIZE - 1; | ||
1055 | res = &temp_res; | ||
1056 | } | ||
1057 | |||
1058 | core->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | ||
1059 | if (!core->base) { | ||
1060 | DSSERR("can't ioremap CORE\n"); | ||
1061 | return -ENOMEM; | ||
1062 | } | ||
1063 | |||
1064 | return 0; | ||
1065 | } | ||
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h index dc49713a894b..b9bb30004703 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | |||
@@ -400,4 +400,18 @@ struct hdmi_core_audio_config { | |||
400 | bool en_spdif; | 400 | bool en_spdif; |
401 | }; | 401 | }; |
402 | 402 | ||
403 | int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len); | ||
404 | void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | ||
405 | struct hdmi_config *cfg); | ||
406 | void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s); | ||
407 | int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core); | ||
408 | |||
409 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
410 | int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp); | ||
411 | void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp); | ||
412 | int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | ||
413 | struct omap_dss_audio *audio); | ||
414 | int hdmi4_audio_get_dma_port(u32 *offset, u32 *size); | ||
415 | #endif | ||
416 | |||
403 | #endif | 417 | #endif |