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-rw-r--r--drivers/gpu/drm/i915/intel_pm.c25
1 files changed, 9 insertions, 16 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2573c6967559..0feeae845f12 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1310,24 +1310,17 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
1310 * latency value. 1310 * latency value.
1311 */ 1311 */
1312 1312
1313static void vlv_update_drain_latency(struct drm_device *dev) 1313static void vlv_update_drain_latency(struct drm_crtc *crtc)
1314{ 1314{
1315 struct drm_device *dev = crtc->dev;
1315 struct drm_i915_private *dev_priv = dev->dev_private; 1316 struct drm_i915_private *dev_priv = dev->dev_private;
1316 enum pipe pipe; 1317 enum pipe pipe = to_intel_crtc(crtc)->pipe;
1317 1318 int plane_prec, plane_dl;
1318 for_each_pipe(pipe) { 1319 int cursor_prec, cursor_dl;
1319 int plane_prec, plane_dl; 1320 int plane_prec_mult, cursor_prec_mult;
1320 int cursor_prec, cursor_dl;
1321 int plane_prec_mult, cursor_prec_mult;
1322 1321
1323 if (!vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl, 1322 if (vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl,
1324 &cursor_prec_mult, &cursor_dl)) 1323 &cursor_prec_mult, &cursor_dl)) {
1325 continue;
1326
1327 /*
1328 * FIXME CHV spec still lists 16 and 32 as the precision
1329 * values. Need to figure out if spec is outdated or what.
1330 */
1331 cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ? 1324 cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1332 DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32; 1325 DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32;
1333 plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ? 1326 plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
@@ -1352,7 +1345,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
1352 unsigned int enabled = 0; 1345 unsigned int enabled = 0;
1353 bool cxsr_enabled; 1346 bool cxsr_enabled;
1354 1347
1355 vlv_update_drain_latency(dev); 1348 vlv_update_drain_latency(crtc);
1356 1349
1357 if (g4x_compute_wm0(dev, PIPE_A, 1350 if (g4x_compute_wm0(dev, PIPE_A,
1358 &valleyview_wm_info, latency_ns, 1351 &valleyview_wm_info, latency_ns,