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-rw-r--r--arch/mips/alchemy/common/platform.c151
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h63
2 files changed, 123 insertions, 91 deletions
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 36489fb184a2..541fff24abe6 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -13,9 +13,10 @@
13 13
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/etherdevice.h> 15#include <linux/etherdevice.h>
16#include <linux/init.h>
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
17#include <linux/serial_8250.h> 18#include <linux/serial_8250.h>
18#include <linux/init.h> 19#include <linux/slab.h>
19 20
20#include <asm/mach-au1x00/au1xxx.h> 21#include <asm/mach-au1x00/au1xxx.h>
21#include <asm/mach-au1x00/au1xxx_dbdma.h> 22#include <asm/mach-au1x00/au1xxx_dbdma.h>
@@ -372,15 +373,16 @@ static struct platform_device pbdb_smbus_device = {
372#endif 373#endif
373 374
374/* Macro to help defining the Ethernet MAC resources */ 375/* Macro to help defining the Ethernet MAC resources */
376#define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */
375#define MAC_RES(_base, _enable, _irq) \ 377#define MAC_RES(_base, _enable, _irq) \
376 { \ 378 { \
377 .start = CPHYSADDR(_base), \ 379 .start = _base, \
378 .end = CPHYSADDR(_base + 0xffff), \ 380 .end = _base + 0xffff, \
379 .flags = IORESOURCE_MEM, \ 381 .flags = IORESOURCE_MEM, \
380 }, \ 382 }, \
381 { \ 383 { \
382 .start = CPHYSADDR(_enable), \ 384 .start = _enable, \
383 .end = CPHYSADDR(_enable + 0x3), \ 385 .end = _enable + 0x3, \
384 .flags = IORESOURCE_MEM, \ 386 .flags = IORESOURCE_MEM, \
385 }, \ 387 }, \
386 { \ 388 { \
@@ -389,19 +391,29 @@ static struct platform_device pbdb_smbus_device = {
389 .flags = IORESOURCE_IRQ \ 391 .flags = IORESOURCE_IRQ \
390 } 392 }
391 393
392static struct resource au1xxx_eth0_resources[] = { 394static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
393#if defined(CONFIG_SOC_AU1000) 395 [ALCHEMY_CPU_AU1000] = {
394 MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), 396 MAC_RES(AU1000_MAC0_PHYS_ADDR,
395#elif defined(CONFIG_SOC_AU1100) 397 AU1000_MACEN_PHYS_ADDR,
396 MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), 398 AU1000_MAC0_DMA_INT)
397#elif defined(CONFIG_SOC_AU1550) 399 },
398 MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), 400 [ALCHEMY_CPU_AU1500] = {
399#elif defined(CONFIG_SOC_AU1500) 401 MAC_RES(AU1500_MAC0_PHYS_ADDR,
400 MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), 402 AU1500_MACEN_PHYS_ADDR,
401#endif 403 AU1500_MAC0_DMA_INT)
404 },
405 [ALCHEMY_CPU_AU1100] = {
406 MAC_RES(AU1000_MAC0_PHYS_ADDR,
407 AU1000_MACEN_PHYS_ADDR,
408 AU1100_MAC0_DMA_INT)
409 },
410 [ALCHEMY_CPU_AU1550] = {
411 MAC_RES(AU1000_MAC0_PHYS_ADDR,
412 AU1000_MACEN_PHYS_ADDR,
413 AU1550_MAC0_DMA_INT)
414 },
402}; 415};
403 416
404
405static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { 417static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
406 .phy1_search_mac0 = 1, 418 .phy1_search_mac0 = 1,
407}; 419};
@@ -409,20 +421,26 @@ static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
409static struct platform_device au1xxx_eth0_device = { 421static struct platform_device au1xxx_eth0_device = {
410 .name = "au1000-eth", 422 .name = "au1000-eth",
411 .id = 0, 423 .id = 0,
412 .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), 424 .num_resources = MAC_RES_COUNT,
413 .resource = au1xxx_eth0_resources,
414 .dev.platform_data = &au1xxx_eth0_platform_data, 425 .dev.platform_data = &au1xxx_eth0_platform_data,
415}; 426};
416 427
417#ifndef CONFIG_SOC_AU1100 428static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
418static struct resource au1xxx_eth1_resources[] = { 429 [ALCHEMY_CPU_AU1000] = {
419#if defined(CONFIG_SOC_AU1000) 430 MAC_RES(AU1000_MAC1_PHYS_ADDR,
420 MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), 431 AU1000_MACEN_PHYS_ADDR + 4,
421#elif defined(CONFIG_SOC_AU1550) 432 AU1000_MAC1_DMA_INT)
422 MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), 433 },
423#elif defined(CONFIG_SOC_AU1500) 434 [ALCHEMY_CPU_AU1500] = {
424 MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), 435 MAC_RES(AU1500_MAC1_PHYS_ADDR,
425#endif 436 AU1500_MACEN_PHYS_ADDR + 4,
437 AU1500_MAC1_DMA_INT)
438 },
439 [ALCHEMY_CPU_AU1550] = {
440 MAC_RES(AU1000_MAC1_PHYS_ADDR,
441 AU1000_MACEN_PHYS_ADDR + 4,
442 AU1550_MAC1_DMA_INT)
443 },
426}; 444};
427 445
428static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { 446static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
@@ -432,11 +450,9 @@ static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
432static struct platform_device au1xxx_eth1_device = { 450static struct platform_device au1xxx_eth1_device = {
433 .name = "au1000-eth", 451 .name = "au1000-eth",
434 .id = 1, 452 .id = 1,
435 .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), 453 .num_resources = MAC_RES_COUNT,
436 .resource = au1xxx_eth1_resources,
437 .dev.platform_data = &au1xxx_eth1_platform_data, 454 .dev.platform_data = &au1xxx_eth1_platform_data,
438}; 455};
439#endif
440 456
441void __init au1xxx_override_eth_cfg(unsigned int port, 457void __init au1xxx_override_eth_cfg(unsigned int port,
442 struct au1000_eth_platform_data *eth_data) 458 struct au1000_eth_platform_data *eth_data)
@@ -447,11 +463,62 @@ void __init au1xxx_override_eth_cfg(unsigned int port,
447 if (port == 0) 463 if (port == 0)
448 memcpy(&au1xxx_eth0_platform_data, eth_data, 464 memcpy(&au1xxx_eth0_platform_data, eth_data,
449 sizeof(struct au1000_eth_platform_data)); 465 sizeof(struct au1000_eth_platform_data));
450#ifndef CONFIG_SOC_AU1100
451 else 466 else
452 memcpy(&au1xxx_eth1_platform_data, eth_data, 467 memcpy(&au1xxx_eth1_platform_data, eth_data,
453 sizeof(struct au1000_eth_platform_data)); 468 sizeof(struct au1000_eth_platform_data));
454#endif 469}
470
471static void __init alchemy_setup_macs(int ctype)
472{
473 int ret, i;
474 unsigned char ethaddr[6];
475 struct resource *macres;
476
477 /* Handle 1st MAC */
478 if (alchemy_get_macs(ctype) < 1)
479 return;
480
481 macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
482 if (!macres) {
483 printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
484 return;
485 }
486 memcpy(macres, au1xxx_eth0_resources[ctype],
487 sizeof(struct resource) * MAC_RES_COUNT);
488 au1xxx_eth0_device.resource = macres;
489
490 i = prom_get_ethernet_addr(ethaddr);
491 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
492 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
493
494 ret = platform_device_register(&au1xxx_eth0_device);
495 if (!ret)
496 printk(KERN_INFO "Alchemy: failed to register MAC0\n");
497
498
499 /* Handle 2nd MAC */
500 if (alchemy_get_macs(ctype) < 2)
501 return;
502
503 macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
504 if (!macres) {
505 printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
506 return;
507 }
508 memcpy(macres, au1xxx_eth1_resources[ctype],
509 sizeof(struct resource) * MAC_RES_COUNT);
510 au1xxx_eth1_device.resource = macres;
511
512 ethaddr[5] += 1; /* next addr for 2nd MAC */
513 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
514 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
515
516 /* Register second MAC if enabled in pinfunc */
517 if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) {
518 ret = platform_device_register(&au1xxx_eth1_device);
519 if (ret)
520 printk(KERN_INFO "Alchemy: failed to register MAC1\n");
521 }
455} 522}
456 523
457static struct platform_device *au1xxx_platform_devices[] __initdata = { 524static struct platform_device *au1xxx_platform_devices[] __initdata = {
@@ -472,33 +539,17 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
472#ifdef SMBUS_PSC_BASE 539#ifdef SMBUS_PSC_BASE
473 &pbdb_smbus_device, 540 &pbdb_smbus_device,
474#endif 541#endif
475 &au1xxx_eth0_device,
476}; 542};
477 543
478static int __init au1xxx_platform_init(void) 544static int __init au1xxx_platform_init(void)
479{ 545{
480 int err, i, ctype = alchemy_get_cputype(); 546 int err, ctype = alchemy_get_cputype();
481 unsigned char ethaddr[6];
482 547
483 alchemy_setup_uarts(ctype); 548 alchemy_setup_uarts(ctype);
484 549 alchemy_setup_macs(ctype);
485 /* use firmware-provided mac addr if available and necessary */
486 i = prom_get_ethernet_addr(ethaddr);
487 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
488 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
489 550
490 err = platform_add_devices(au1xxx_platform_devices, 551 err = platform_add_devices(au1xxx_platform_devices,
491 ARRAY_SIZE(au1xxx_platform_devices)); 552 ARRAY_SIZE(au1xxx_platform_devices));
492#ifndef CONFIG_SOC_AU1100
493 ethaddr[5] += 1; /* next addr for 2nd MAC */
494 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
495 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
496
497 /* Register second MAC if enabled in pinfunc */
498 if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
499 err = platform_device_register(&au1xxx_eth1_device);
500#endif
501
502 return err; 553 return err;
503} 554}
504 555
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index c4ffb209edf2..415d287c272b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -219,6 +219,20 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
219 wmb(); 219 wmb();
220} 220}
221 221
222/* return number of ethernet MACs on a given cputype */
223static inline int alchemy_get_macs(int type)
224{
225 switch (type) {
226 case ALCHEMY_CPU_AU1000:
227 case ALCHEMY_CPU_AU1500:
228 case ALCHEMY_CPU_AU1550:
229 return 2;
230 case ALCHEMY_CPU_AU1100:
231 return 1;
232 }
233 return 0;
234}
235
222/* arch/mips/au1000/common/clocks.c */ 236/* arch/mips/au1000/common/clocks.c */
223extern void set_au1x00_speed(unsigned int new_freq); 237extern void set_au1x00_speed(unsigned int new_freq);
224extern unsigned int get_au1x00_speed(void); 238extern unsigned int get_au1x00_speed(void);
@@ -673,6 +687,12 @@ enum soc_au1200_ints {
673 */ 687 */
674 688
675#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ 689#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
690#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
691#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
692#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
693#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
694#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
695#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
676#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ 696#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
677#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ 697#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
678#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ 698#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
@@ -680,6 +700,8 @@ enum soc_au1200_ints {
680#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ 700#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
681#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ 701#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
682#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ 702#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
703#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
704#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
683 705
684 706
685#ifdef CONFIG_SOC_AU1000 707#ifdef CONFIG_SOC_AU1000
@@ -697,11 +719,6 @@ enum soc_au1200_ints {
697#define USBH_PHYS_ADDR 0x10100000 719#define USBH_PHYS_ADDR 0x10100000
698#define USBD_PHYS_ADDR 0x10200000 720#define USBD_PHYS_ADDR 0x10200000
699#define IRDA_PHYS_ADDR 0x10300000 721#define IRDA_PHYS_ADDR 0x10300000
700#define MAC0_PHYS_ADDR 0x10500000
701#define MAC1_PHYS_ADDR 0x10510000
702#define MACEN_PHYS_ADDR 0x10520000
703#define MACDMA0_PHYS_ADDR 0x14004000
704#define MACDMA1_PHYS_ADDR 0x14004200
705#define I2S_PHYS_ADDR 0x11000000 722#define I2S_PHYS_ADDR 0x11000000
706#define SSI0_PHYS_ADDR 0x11600000 723#define SSI0_PHYS_ADDR 0x11600000
707#define SSI1_PHYS_ADDR 0x11680000 724#define SSI1_PHYS_ADDR 0x11680000
@@ -728,11 +745,6 @@ enum soc_au1200_ints {
728#define USBH_PHYS_ADDR 0x10100000 745#define USBH_PHYS_ADDR 0x10100000
729#define USBD_PHYS_ADDR 0x10200000 746#define USBD_PHYS_ADDR 0x10200000
730#define PCI_PHYS_ADDR 0x14005000 747#define PCI_PHYS_ADDR 0x14005000
731#define MAC0_PHYS_ADDR 0x11500000
732#define MAC1_PHYS_ADDR 0x11510000
733#define MACEN_PHYS_ADDR 0x11520000
734#define MACDMA0_PHYS_ADDR 0x14004000
735#define MACDMA1_PHYS_ADDR 0x14004200
736#define I2S_PHYS_ADDR 0x11000000 748#define I2S_PHYS_ADDR 0x11000000
737#define GPIO2_PHYS_ADDR 0x11700000 749#define GPIO2_PHYS_ADDR 0x11700000
738#define SYS_PHYS_ADDR 0x11900000 750#define SYS_PHYS_ADDR 0x11900000
@@ -764,10 +776,6 @@ enum soc_au1200_ints {
764#define USBH_PHYS_ADDR 0x10100000 776#define USBH_PHYS_ADDR 0x10100000
765#define USBD_PHYS_ADDR 0x10200000 777#define USBD_PHYS_ADDR 0x10200000
766#define IRDA_PHYS_ADDR 0x10300000 778#define IRDA_PHYS_ADDR 0x10300000
767#define MAC0_PHYS_ADDR 0x10500000
768#define MACEN_PHYS_ADDR 0x10520000
769#define MACDMA0_PHYS_ADDR 0x14004000
770#define MACDMA1_PHYS_ADDR 0x14004200
771#define I2S_PHYS_ADDR 0x11000000 779#define I2S_PHYS_ADDR 0x11000000
772#define SSI0_PHYS_ADDR 0x11600000 780#define SSI0_PHYS_ADDR 0x11600000
773#define SSI1_PHYS_ADDR 0x11680000 781#define SSI1_PHYS_ADDR 0x11680000
@@ -787,11 +795,6 @@ enum soc_au1200_ints {
787#define USBH_PHYS_ADDR 0x14020000 795#define USBH_PHYS_ADDR 0x14020000
788#define USBD_PHYS_ADDR 0x10200000 796#define USBD_PHYS_ADDR 0x10200000
789#define PCI_PHYS_ADDR 0x14005000 797#define PCI_PHYS_ADDR 0x14005000
790#define MAC0_PHYS_ADDR 0x10500000
791#define MAC1_PHYS_ADDR 0x10510000
792#define MACEN_PHYS_ADDR 0x10520000
793#define MACDMA0_PHYS_ADDR 0x14004000
794#define MACDMA1_PHYS_ADDR 0x14004200
795#define GPIO2_PHYS_ADDR 0x11700000 798#define GPIO2_PHYS_ADDR 0x11700000
796#define SYS_PHYS_ADDR 0x11900000 799#define SYS_PHYS_ADDR 0x11900000
797#define PE_PHYS_ADDR 0x14008000 800#define PE_PHYS_ADDR 0x14008000
@@ -870,12 +873,6 @@ enum soc_au1200_ints {
870#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 873#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
871#define USB_HOST_CONFIG 0xB017FFFC 874#define USB_HOST_CONFIG 0xB017FFFC
872#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT 875#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
873
874#define AU1000_ETH0_BASE 0xB0500000
875#define AU1000_ETH1_BASE 0xB0510000
876#define AU1000_MAC0_ENABLE 0xB0520000
877#define AU1000_MAC1_ENABLE 0xB0520004
878#define NUM_ETH_INTERFACES 2
879#endif /* CONFIG_SOC_AU1000 */ 876#endif /* CONFIG_SOC_AU1000 */
880 877
881/* Au1500 */ 878/* Au1500 */
@@ -887,12 +884,6 @@ enum soc_au1200_ints {
887#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 884#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
888#define USB_HOST_CONFIG 0xB017fffc 885#define USB_HOST_CONFIG 0xB017fffc
889#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT 886#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
890
891#define AU1500_ETH0_BASE 0xB1500000
892#define AU1500_ETH1_BASE 0xB1510000
893#define AU1500_MAC0_ENABLE 0xB1520000
894#define AU1500_MAC1_ENABLE 0xB1520004
895#define NUM_ETH_INTERFACES 2
896#endif /* CONFIG_SOC_AU1500 */ 887#endif /* CONFIG_SOC_AU1500 */
897 888
898/* Au1100 */ 889/* Au1100 */
@@ -904,10 +895,6 @@ enum soc_au1200_ints {
904#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 895#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
905#define USB_HOST_CONFIG 0xB017FFFC 896#define USB_HOST_CONFIG 0xB017FFFC
906#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT 897#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
907
908#define AU1100_ETH0_BASE 0xB0500000
909#define AU1100_MAC0_ENABLE 0xB0520000
910#define NUM_ETH_INTERFACES 1
911#endif /* CONFIG_SOC_AU1100 */ 898#endif /* CONFIG_SOC_AU1100 */
912 899
913#ifdef CONFIG_SOC_AU1550 900#ifdef CONFIG_SOC_AU1550
@@ -917,12 +904,6 @@ enum soc_au1200_ints {
917#define USB_OHCI_LEN 0x00060000 904#define USB_OHCI_LEN 0x00060000
918#define USB_HOST_CONFIG 0xB4027ffc 905#define USB_HOST_CONFIG 0xB4027ffc
919#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT 906#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
920
921#define AU1550_ETH0_BASE 0xB0500000
922#define AU1550_ETH1_BASE 0xB0510000
923#define AU1550_MAC0_ENABLE 0xB0520000
924#define AU1550_MAC1_ENABLE 0xB0520004
925#define NUM_ETH_INTERFACES 2
926#endif /* CONFIG_SOC_AU1550 */ 907#endif /* CONFIG_SOC_AU1550 */
927 908
928 909