3 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index 041d0526a288..03664b0e8fa4 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 4fbc757d9cff..8c79a9e70b83 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                /*
                 * The prefetch counters don't differentiate between the I
@@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 2b0fe30ec12e..63990c42fac9 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,

diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 041d0526a288..03664b0e8fa4 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c
@@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
106	},	106	},
107	[C(OP_WRITE)] = {	107	[C(OP_WRITE)] = {
108	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	108	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
109	[C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,	109	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
110	},	110	},
111	[C(OP_PREFETCH)] = {	111	[C(OP_PREFETCH)] = {
112	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	112	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
259	},	259	},
260	[C(OP_WRITE)] = {	260	[C(OP_WRITE)] = {
261	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	261	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
262	[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,	262	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
263	},	263	},
264	[C(OP_PREFETCH)] = {	264	[C(OP_PREFETCH)] = {
265	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	265	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,


diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 4fbc757d9cff..8c79a9e70b83 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c
@@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
157	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	157	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
158	},	158	},
159	[C(OP_WRITE)] = {	159	[C(OP_WRITE)] = {
160	[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,	160	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
161	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	161	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
162	},	162	},
163	[C(OP_PREFETCH)] = {	163	[C(OP_PREFETCH)] = {
164	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	164	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
282	},	282	},
283	[C(OP_WRITE)] = {	283	[C(OP_WRITE)] = {
284	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	284	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
285	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	285	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
286	},	286	},
287	[C(OP_PREFETCH)] = {	287	[C(OP_PREFETCH)] = {
288	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	288	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
399	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	399	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
400	},	400	},
401	[C(OP_WRITE)] = {	401	[C(OP_WRITE)] = {
402	[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,	402	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
403	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	403	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
404	},	404	},
405	/*	405	/*
406	* The prefetch counters don't differentiate between the I	406	* The prefetch counters don't differentiate between the I
@@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
527	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	527	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
528	},	528	},
529	[C(OP_WRITE)] = {	529	[C(OP_WRITE)] = {
530	[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,	530	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
531	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	531	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
532	},	532	},
533	[C(OP_PREFETCH)] = {	533	[C(OP_PREFETCH)] = {
534	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	534	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
651	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	651	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
652	},	652	},
653	[C(OP_WRITE)] = {	653	[C(OP_WRITE)] = {
654	[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,	654	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
655	[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,	655	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
656	},	656	},
657	[C(OP_PREFETCH)] = {	657	[C(OP_PREFETCH)] = {
658	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	658	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,


diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 2b0fe30ec12e..63990c42fac9 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c
@@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
83	},	83	},
84	[C(OP_WRITE)] = {	84	[C(OP_WRITE)] = {
85	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	85	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
86	[C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,	86	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
87	},	87	},
88	[C(OP_PREFETCH)] = {	88	[C(OP_PREFETCH)] = {
89	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,	89	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,