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-rw-r--r--drivers/ide/Kconfig34
-rw-r--r--drivers/ide/Makefile2
-rw-r--r--drivers/ide/cris/Makefile3
-rw-r--r--drivers/ide/cris/ide-cris.c1151
4 files changed, 1 insertions, 1189 deletions
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 3f9e10001e19..f702f9152ce6 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -862,40 +862,6 @@ config BLK_DEV_IDE_BAST
862 Say Y here if you want to support the onboard IDE channels on the 862 Say Y here if you want to support the onboard IDE channels on the
863 Simtec BAST or the Thorcom VR1000 863 Simtec BAST or the Thorcom VR1000
864 864
865config ETRAX_IDE
866 tristate "ETRAX IDE support"
867 depends on CRIS && BROKEN
868 select BLK_DEV_IDEDMA
869 help
870 Enables the ETRAX IDE driver.
871
872 You can't use parallel ports or SCSI ports at the same time.
873
874config ETRAX_IDE_DELAY
875 int "Delay for drives to regain consciousness"
876 depends on ETRAX_IDE && ETRAX_ARCH_V10
877 default 15
878 help
879 Number of seconds to wait for IDE drives to spin up after an IDE
880 reset.
881
882choice
883 prompt "IDE reset pin"
884 depends on ETRAX_IDE && ETRAX_ARCH_V10
885 default ETRAX_IDE_PB7_RESET
886
887config ETRAX_IDE_PB7_RESET
888 bool "Port_PB_Bit_7"
889 help
890 IDE reset on pin 7 on port B
891
892config ETRAX_IDE_G27_RESET
893 bool "Port_G_Bit_27"
894 help
895 IDE reset on pin 27 on port G
896
897endchoice
898
899config IDE_H8300 865config IDE_H8300
900 tristate "H8300 IDE support" 866 tristate "H8300 IDE support"
901 depends on H8300 867 depends on H8300
diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile
index 571544c37bb2..f94b679b611e 100644
--- a/drivers/ide/Makefile
+++ b/drivers/ide/Makefile
@@ -35,7 +35,7 @@ ifeq ($(CONFIG_BLK_DEV_CMD640), y)
35 obj-y += cmd640-core.o 35 obj-y += cmd640-core.o
36endif 36endif
37 37
38obj-$(CONFIG_BLK_DEV_IDE) += cris/ ppc/ 38obj-$(CONFIG_BLK_DEV_IDE) += ppc/
39obj-$(CONFIG_IDE_H8300) += h8300/ 39obj-$(CONFIG_IDE_H8300) += h8300/
40obj-$(CONFIG_IDE_GENERIC) += ide-generic.o 40obj-$(CONFIG_IDE_GENERIC) += ide-generic.o
41obj-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o 41obj-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o
diff --git a/drivers/ide/cris/Makefile b/drivers/ide/cris/Makefile
deleted file mode 100644
index 20b95960531f..000000000000
--- a/drivers/ide/cris/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
1EXTRA_CFLAGS += -Idrivers/ide
2
3obj-$(CONFIG_IDE_ETRAX) += ide-cris.o
diff --git a/drivers/ide/cris/ide-cris.c b/drivers/ide/cris/ide-cris.c
deleted file mode 100644
index 38b069c0057f..000000000000
--- a/drivers/ide/cris/ide-cris.c
+++ /dev/null
@@ -1,1151 +0,0 @@
1/*
2 * Etrax specific IDE functions, like init and PIO-mode setting etc.
3 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
4 * Copyright (c) 2000-2005 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (initial version)
7 * Mikael Starvik (crisv32 port)
8 */
9
10/* Regarding DMA:
11 *
12 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
13 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
14 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
15 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
16 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
17 */
18
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/timer.h>
22#include <linux/mm.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/blkdev.h>
26#include <linux/hdreg.h>
27#include <linux/ide.h>
28#include <linux/init.h>
29
30#include <asm/io.h>
31#include <asm/dma.h>
32
33/* number of DMA descriptors */
34#define MAX_DMA_DESCRS 64
35
36/* number of times to retry busy-flags when reading/writing IDE-registers
37 * this can't be too high because a hung harddisk might cause the watchdog
38 * to trigger (sometimes INB and OUTB are called with irq's disabled)
39 */
40
41#define IDE_REGISTER_TIMEOUT 300
42
43#define LOWDB(x)
44#define D(x)
45
46enum /* Transfer types */
47{
48 TYPE_PIO,
49 TYPE_DMA,
50 TYPE_UDMA
51};
52
53/* CRISv32 specifics */
54#ifdef CONFIG_ETRAX_ARCH_V32
55#include <asm/arch/hwregs/ata_defs.h>
56#include <asm/arch/hwregs/dma_defs.h>
57#include <asm/arch/hwregs/dma.h>
58#include <asm/arch/pinmux.h>
59
60#define ATA_UDMA2_CYC 2
61#define ATA_UDMA2_DVS 3
62#define ATA_UDMA1_CYC 2
63#define ATA_UDMA1_DVS 4
64#define ATA_UDMA0_CYC 4
65#define ATA_UDMA0_DVS 6
66#define ATA_DMA2_STROBE 7
67#define ATA_DMA2_HOLD 1
68#define ATA_DMA1_STROBE 8
69#define ATA_DMA1_HOLD 3
70#define ATA_DMA0_STROBE 25
71#define ATA_DMA0_HOLD 19
72#define ATA_PIO4_SETUP 3
73#define ATA_PIO4_STROBE 7
74#define ATA_PIO4_HOLD 1
75#define ATA_PIO3_SETUP 3
76#define ATA_PIO3_STROBE 9
77#define ATA_PIO3_HOLD 3
78#define ATA_PIO2_SETUP 3
79#define ATA_PIO2_STROBE 13
80#define ATA_PIO2_HOLD 5
81#define ATA_PIO1_SETUP 5
82#define ATA_PIO1_STROBE 23
83#define ATA_PIO1_HOLD 9
84#define ATA_PIO0_SETUP 9
85#define ATA_PIO0_STROBE 39
86#define ATA_PIO0_HOLD 9
87
88int
89cris_ide_ack_intr(ide_hwif_t* hwif)
90{
91 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
92 hwif->io_ports.data_addr);
93 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
94 return 1;
95}
96
97static inline int
98cris_ide_busy(void)
99{
100 reg_ata_rs_stat_data stat_data;
101 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
102 return stat_data.busy;
103}
104
105static inline int
106cris_ide_ready(void)
107{
108 return !cris_ide_busy();
109}
110
111static inline int
112cris_ide_data_available(unsigned short* data)
113{
114 reg_ata_rs_stat_data stat_data;
115 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
116 *data = stat_data.data;
117 return stat_data.dav;
118}
119
120static void
121cris_ide_write_command(unsigned long command)
122{
123 REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
124}
125
126static void
127cris_ide_set_speed(int type, int setup, int strobe, int hold)
128{
129 reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
130 reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
131
132 if (type == TYPE_PIO) {
133 ctrl0.pio_setup = setup;
134 ctrl0.pio_strb = strobe;
135 ctrl0.pio_hold = hold;
136 } else if (type == TYPE_DMA) {
137 ctrl0.dma_strb = strobe;
138 ctrl0.dma_hold = hold;
139 } else if (type == TYPE_UDMA) {
140 ctrl1.udma_tcyc = setup;
141 ctrl1.udma_tdvs = strobe;
142 }
143 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
144 REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
145}
146
147static unsigned long
148cris_ide_base_address(int bus)
149{
150 reg_ata_rw_ctrl2 ctrl2 = {0};
151 ctrl2.sel = bus;
152 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
153}
154
155static unsigned long
156cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
157{
158 reg_ata_rw_ctrl2 ctrl2 = {0};
159 ctrl2.addr = addr;
160 ctrl2.cs1 = cs1;
161 ctrl2.cs0 = cs0;
162 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
163}
164
165static __init void
166cris_ide_reset(unsigned val)
167{
168 reg_ata_rw_ctrl0 ctrl0 = {0};
169 ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
170 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
171}
172
173static __init void
174cris_ide_init(void)
175{
176 reg_ata_rw_ctrl0 ctrl0 = {0};
177 reg_ata_rw_intr_mask intr_mask = {0};
178
179 ctrl0.en = regk_ata_yes;
180 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
181
182 intr_mask.bus0 = regk_ata_yes;
183 intr_mask.bus1 = regk_ata_yes;
184 intr_mask.bus2 = regk_ata_yes;
185 intr_mask.bus3 = regk_ata_yes;
186
187 REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
188
189 crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
190 crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
191
192 crisv32_pinmux_alloc_fixed(pinmux_ata);
193 crisv32_pinmux_alloc_fixed(pinmux_ata0);
194 crisv32_pinmux_alloc_fixed(pinmux_ata1);
195 crisv32_pinmux_alloc_fixed(pinmux_ata2);
196 crisv32_pinmux_alloc_fixed(pinmux_ata3);
197
198 DMA_RESET(regi_dma2);
199 DMA_ENABLE(regi_dma2);
200 DMA_RESET(regi_dma3);
201 DMA_ENABLE(regi_dma3);
202
203 DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
204 DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
205}
206
207static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
208
209#define cris_dma_descr_type dma_descr_data
210#define cris_pio_read regk_ata_rd
211#define cris_ultra_mask 0x7
212#define MAX_DESCR_SIZE 0xffffffffUL
213
214static unsigned long
215cris_ide_get_reg(unsigned long reg)
216{
217 return (reg & 0x0e000000) >> 25;
218}
219
220static void
221cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
222{
223 d->buf = (char*)virt_to_phys(buf);
224 d->after = d->buf + len;
225 d->eol = last;
226}
227
228static void
229cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
230{
231 ide_hwif_t *hwif = drive->hwif;
232
233 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
234 hwif->io_ports.data_addr);
235 reg_ata_rw_trf_cnt trf_cnt = {0};
236
237 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
238 mycontext.saved_data_buf = d->buf;
239 /* start the dma channel */
240 DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
241
242 /* initiate a multi word dma read using PIO handshaking */
243 trf_cnt.cnt = len >> 1;
244 /* Due to a "feature" the transfer count has to be one extra word for UDMA. */
245 if (type == TYPE_UDMA)
246 trf_cnt.cnt++;
247 REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
248
249 ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
250 ctrl2.trf_mode = regk_ata_dma;
251 ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
252 type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
253 ctrl2.multi = regk_ata_yes;
254 ctrl2.dma_size = regk_ata_word;
255 REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
256}
257
258static void
259cris_ide_wait_dma(int dir)
260{
261 reg_dma_rw_stat status;
262 do
263 {
264 status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
265 } while(status.list_state != regk_dma_data_at_eol);
266}
267
268static int cris_dma_test_irq(ide_drive_t *drive)
269{
270 ide_hwif_t *hwif = drive->hwif;
271 int intr = REG_RD_INT(ata, regi_ata, r_intr);
272
273 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
274 hwif->io_ports.data_addr);
275
276 return intr & (1 << ctrl2.sel) ? 1 : 0;
277}
278
279static void cris_ide_initialize_dma(int dir)
280{
281}
282
283#else
284/* CRISv10 specifics */
285#include <asm/arch/svinto.h>
286#include <asm/arch/io_interface_mux.h>
287
288/* PIO timing (in R_ATA_CONFIG)
289 *
290 * _____________________________
291 * ADDRESS : ________/
292 *
293 * _______________
294 * DIOR : ____________/ \__________
295 *
296 * _______________
297 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
298 *
299 *
300 * DIOR is unbuffered while address and data is buffered.
301 * This creates two problems:
302 * 1. The DIOR pulse is to early (because it is unbuffered)
303 * 2. The rise time of DIOR is long
304 *
305 * There are at least three different plausible solutions
306 * 1. Use a pad capable of larger currents in Etrax
307 * 2. Use an external buffer
308 * 3. Make the strobe pulse longer
309 *
310 * Some of the strobe timings below are modified to compensate
311 * for this. This implies a slight performance decrease.
312 *
313 * THIS SHOULD NEVER BE CHANGED!
314 *
315 * TODO: Is this true for the latest LX boards still ?
316 */
317
318#define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */
319#define ATA_UDMA2_DVS 0
320#define ATA_UDMA1_CYC 0
321#define ATA_UDMA1_DVS 0
322#define ATA_UDMA0_CYC 0
323#define ATA_UDMA0_DVS 0
324#define ATA_DMA2_STROBE 4
325#define ATA_DMA2_HOLD 0
326#define ATA_DMA1_STROBE 4
327#define ATA_DMA1_HOLD 1
328#define ATA_DMA0_STROBE 12
329#define ATA_DMA0_HOLD 9
330#define ATA_PIO4_SETUP 1
331#define ATA_PIO4_STROBE 5
332#define ATA_PIO4_HOLD 0
333#define ATA_PIO3_SETUP 1
334#define ATA_PIO3_STROBE 5
335#define ATA_PIO3_HOLD 1
336#define ATA_PIO2_SETUP 1
337#define ATA_PIO2_STROBE 6
338#define ATA_PIO2_HOLD 2
339#define ATA_PIO1_SETUP 2
340#define ATA_PIO1_STROBE 11
341#define ATA_PIO1_HOLD 4
342#define ATA_PIO0_SETUP 4
343#define ATA_PIO0_STROBE 19
344#define ATA_PIO0_HOLD 4
345
346int
347cris_ide_ack_intr(ide_hwif_t* hwif)
348{
349 return 1;
350}
351
352static inline int
353cris_ide_busy(void)
354{
355 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
356}
357
358static inline int
359cris_ide_ready(void)
360{
361 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
362}
363
364static inline int
365cris_ide_data_available(unsigned short* data)
366{
367 unsigned long status = *R_ATA_STATUS_DATA;
368 *data = (unsigned short)status;
369 return status & IO_MASK(R_ATA_STATUS_DATA, dav);
370}
371
372static void
373cris_ide_write_command(unsigned long command)
374{
375 *R_ATA_CTRL_DATA = command;
376}
377
378static void
379cris_ide_set_speed(int type, int setup, int strobe, int hold)
380{
381 static int pio_setup = ATA_PIO4_SETUP;
382 static int pio_strobe = ATA_PIO4_STROBE;
383 static int pio_hold = ATA_PIO4_HOLD;
384 static int dma_strobe = ATA_DMA2_STROBE;
385 static int dma_hold = ATA_DMA2_HOLD;
386
387 if (type == TYPE_PIO) {
388 pio_setup = setup;
389 pio_strobe = strobe;
390 pio_hold = hold;
391 } else if (type == TYPE_DMA) {
392 dma_strobe = strobe;
393 dma_hold = hold;
394 }
395 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
396 IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
397 IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) |
398 IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) |
399 IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
400 IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) );
401}
402
403static unsigned long
404cris_ide_base_address(int bus)
405{
406 return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
407}
408
409static unsigned long
410cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
411{
412 return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
413 IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
414 IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
415}
416
417static __init void
418cris_ide_reset(unsigned val)
419{
420#ifdef CONFIG_ETRAX_IDE_G27_RESET
421 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
422#endif
423#ifdef CONFIG_ETRAX_IDE_PB7_RESET
424 port_pb_dir_shadow = port_pb_dir_shadow |
425 IO_STATE(R_PORT_PB_DIR, dir7, output);
426 *R_PORT_PB_DIR = port_pb_dir_shadow;
427 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
428#endif
429}
430
431static __init void
432cris_ide_init(void)
433{
434 volatile unsigned int dummy;
435
436 *R_ATA_CTRL_DATA = 0;
437 *R_ATA_TRANSFER_CNT = 0;
438 *R_ATA_CONFIG = 0;
439
440 if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
441 printk(KERN_CRIT "ide: Failed to get IO interface\n");
442 return;
443 } else if (cris_request_dma(ATA_TX_DMA_NBR,
444 "ETRAX100LX IDE TX",
445 DMA_VERBOSE_ON_ERROR,
446 dma_ata)) {
447 cris_free_io_interface(if_ata);
448 printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
449 return;
450 } else if (cris_request_dma(ATA_RX_DMA_NBR,
451 "ETRAX100LX IDE RX",
452 DMA_VERBOSE_ON_ERROR,
453 dma_ata)) {
454 cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
455 cris_free_io_interface(if_ata);
456 printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
457 return;
458 }
459
460 /* make a dummy read to set the ata controller in a proper state */
461 dummy = *R_ATA_STATUS_DATA;
462
463 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
464 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
465 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
466
467 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
468
469 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
470 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
471 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
472 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
473
474 /* reset the dma channels we will use */
475
476 RESET_DMA(ATA_TX_DMA_NBR);
477 RESET_DMA(ATA_RX_DMA_NBR);
478 WAIT_DMA(ATA_TX_DMA_NBR);
479 WAIT_DMA(ATA_RX_DMA_NBR);
480}
481
482#define cris_dma_descr_type etrax_dma_descr
483#define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
484#define cris_ultra_mask 0x0
485#define MAX_DESCR_SIZE 0x10000UL
486
487static unsigned long
488cris_ide_get_reg(unsigned long reg)
489{
490 return (reg & 0x0e000000) >> 25;
491}
492
493static void
494cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
495{
496 d->buf = virt_to_phys(buf);
497 d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
498 if (last)
499 d->ctrl |= d_eol;
500}
501
502static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
503{
504 unsigned long cmd;
505
506 if (dir) {
507 /* need to do this before RX DMA due to a chip bug
508 * it is enough to just flush the part of the cache that
509 * corresponds to the buffers we start, but since HD transfers
510 * usually are more than 8 kB, it is easier to optimize for the
511 * normal case and just flush the entire cache. its the only
512 * way to be sure! (OB movie quote)
513 */
514 flush_etrax_cache();
515 *R_DMA_CH3_FIRST = virt_to_phys(d);
516 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
517
518 } else {
519 *R_DMA_CH2_FIRST = virt_to_phys(d);
520 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
521 }
522
523 /* initiate a multi word dma read using DMA handshaking */
524
525 *R_ATA_TRANSFER_CNT =
526 IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
527
528 cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
529 cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
530 IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
531 *R_ATA_CTRL_DATA =
532 cmd |
533 IO_FIELD(R_ATA_CTRL_DATA, data,
534 drive->hwif->io_ports.data_addr) |
535 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
536 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
537 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
538}
539
540static void
541cris_ide_wait_dma(int dir)
542{
543 if (dir)
544 WAIT_DMA(ATA_RX_DMA_NBR);
545 else
546 WAIT_DMA(ATA_TX_DMA_NBR);
547}
548
549static int cris_dma_test_irq(ide_drive_t *drive)
550{
551 int intr = *R_IRQ_MASK0_RD;
552 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel,
553 drive->hwif->io_ports.data_addr);
554
555 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
556}
557
558
559static void cris_ide_initialize_dma(int dir)
560{
561 if (dir)
562 {
563 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
564 WAIT_DMA(ATA_RX_DMA_NBR);
565 }
566 else
567 {
568 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
569 WAIT_DMA(ATA_TX_DMA_NBR);
570 }
571}
572
573#endif
574
575void
576cris_ide_outw(unsigned short data, unsigned long reg) {
577 int timeleft;
578
579 LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
580
581 /* note the lack of handling any timeouts. we stop waiting, but we don't
582 * really notify anybody.
583 */
584
585 timeleft = IDE_REGISTER_TIMEOUT;
586 /* wait for busy flag */
587 do {
588 timeleft--;
589 } while(timeleft && cris_ide_busy());
590
591 /*
592 * Fall through at a timeout, so the ongoing command will be
593 * aborted by the write below, which is expected to be a dummy
594 * command to the command register. This happens when a faulty
595 * drive times out on a command. See comment on timeout in
596 * INB.
597 */
598 if(!timeleft)
599 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
600
601 cris_ide_write_command(reg|data); /* write data to the drive's register */
602
603 timeleft = IDE_REGISTER_TIMEOUT;
604 /* wait for transmitter ready */
605 do {
606 timeleft--;
607 } while(timeleft && !cris_ide_ready());
608}
609
610void
611cris_ide_outb(unsigned char data, unsigned long reg)
612{
613 cris_ide_outw(data, reg);
614}
615
616void
617cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
618{
619 cris_ide_outw(addr, port);
620}
621
622unsigned short
623cris_ide_inw(unsigned long reg) {
624 int timeleft;
625 unsigned short val;
626
627 timeleft = IDE_REGISTER_TIMEOUT;
628 /* wait for busy flag */
629 do {
630 timeleft--;
631 } while(timeleft && cris_ide_busy());
632
633 if(!timeleft) {
634 /*
635 * If we're asked to read the status register, like for
636 * example when a command does not complete for an
637 * extended time, but the ATA interface is stuck in a
638 * busy state at the *ETRAX* ATA interface level (as has
639 * happened repeatedly with at least one bad disk), then
640 * the best thing to do is to pretend that we read
641 * "busy" in the status register, so the IDE driver will
642 * time-out, abort the ongoing command and perform a
643 * reset sequence. Note that the subsequent OUT_BYTE
644 * call will also timeout on busy, but as long as the
645 * write is still performed, everything will be fine.
646 */
647 if (cris_ide_get_reg(reg) == 7)
648 return BUSY_STAT;
649 else
650 /* For other rare cases we assume 0 is good enough. */
651 return 0;
652 }
653
654 cris_ide_write_command(reg | cris_pio_read);
655
656 timeleft = IDE_REGISTER_TIMEOUT;
657 /* wait for available */
658 do {
659 timeleft--;
660 } while(timeleft && !cris_ide_data_available(&val));
661
662 if(!timeleft)
663 return 0;
664
665 LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
666
667 return val;
668}
669
670unsigned char
671cris_ide_inb(unsigned long reg)
672{
673 return (unsigned char)cris_ide_inw(reg);
674}
675
676static void cris_input_data(ide_drive_t *, struct request *, void *, unsigned);
677static void cris_output_data(ide_drive_t *, struct request *, void *, unsigned);
678
679static void cris_dma_host_set(ide_drive_t *drive, int on)
680{
681}
682
683static void cris_set_pio_mode(ide_drive_t *drive, const u8 pio)
684{
685 int setup, strobe, hold;
686
687 switch(pio)
688 {
689 case 0:
690 setup = ATA_PIO0_SETUP;
691 strobe = ATA_PIO0_STROBE;
692 hold = ATA_PIO0_HOLD;
693 break;
694 case 1:
695 setup = ATA_PIO1_SETUP;
696 strobe = ATA_PIO1_STROBE;
697 hold = ATA_PIO1_HOLD;
698 break;
699 case 2:
700 setup = ATA_PIO2_SETUP;
701 strobe = ATA_PIO2_STROBE;
702 hold = ATA_PIO2_HOLD;
703 break;
704 case 3:
705 setup = ATA_PIO3_SETUP;
706 strobe = ATA_PIO3_STROBE;
707 hold = ATA_PIO3_HOLD;
708 break;
709 case 4:
710 setup = ATA_PIO4_SETUP;
711 strobe = ATA_PIO4_STROBE;
712 hold = ATA_PIO4_HOLD;
713 break;
714 default:
715 return;
716 }
717
718 cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
719}
720
721static void cris_set_dma_mode(ide_drive_t *drive, const u8 speed)
722{
723 int cyc = 0, dvs = 0, strobe = 0, hold = 0;
724
725 switch(speed)
726 {
727 case XFER_UDMA_0:
728 cyc = ATA_UDMA0_CYC;
729 dvs = ATA_UDMA0_DVS;
730 break;
731 case XFER_UDMA_1:
732 cyc = ATA_UDMA1_CYC;
733 dvs = ATA_UDMA1_DVS;
734 break;
735 case XFER_UDMA_2:
736 cyc = ATA_UDMA2_CYC;
737 dvs = ATA_UDMA2_DVS;
738 break;
739 case XFER_MW_DMA_0:
740 strobe = ATA_DMA0_STROBE;
741 hold = ATA_DMA0_HOLD;
742 break;
743 case XFER_MW_DMA_1:
744 strobe = ATA_DMA1_STROBE;
745 hold = ATA_DMA1_HOLD;
746 break;
747 case XFER_MW_DMA_2:
748 strobe = ATA_DMA2_STROBE;
749 hold = ATA_DMA2_HOLD;
750 break;
751 }
752
753 if (speed >= XFER_UDMA_0)
754 cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
755 else
756 cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
757}
758
759static void __init cris_setup_ports(hw_regs_t *hw, unsigned long base)
760{
761 int i;
762
763 memset(hw, 0, sizeof(*hw));
764
765 for (i = 0; i <= 7; i++)
766 hw->io_ports_array[i] = base + cris_ide_reg_addr(i, 0, 1);
767
768 /*
769 * the IDE control register is at ATA address 6,
770 * with CS1 active instead of CS0
771 */
772 hw->io_ports.ctl_addr = base + cris_ide_reg_addr(6, 1, 0);
773
774 hw->irq = ide_default_irq(0);
775 hw->ack_intr = cris_ide_ack_intr;
776}
777
778static void cris_tf_load(ide_drive_t *drive, ide_task_t *task)
779{
780 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
781 struct ide_taskfile *tf = &task->tf;
782 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
783
784 if (task->tf_flags & IDE_TFLAG_FLAGGED)
785 HIHI = 0xFF;
786
787 ide_set_irq(drive, 1);
788
789 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
790 cris_ide_outw((tf->hob_data << 8) | tf->data,
791 io_ports->data_addr);
792
793 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
794 cris_ide_outb(tf->hob_feature, io_ports->feature_addr);
795 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
796 cris_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
797 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
798 cris_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
799 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
800 cris_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
801 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
802 cris_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
803
804 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
805 cris_ide_outb(tf->feature, io_ports->feature_addr);
806 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
807 cris_ide_outb(tf->nsect, io_ports->nsect_addr);
808 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
809 cris_ide_outb(tf->lbal, io_ports->lbal_addr);
810 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
811 cris_ide_outb(tf->lbam, io_ports->lbam_addr);
812 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
813 cris_ide_outb(tf->lbah, io_ports->lbah_addr);
814
815 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
816 cris_ide_outb((tf->device & HIHI) | drive->select.all,
817 io_ports->device_addr);
818}
819
820static void cris_tf_read(ide_drive_t *drive, ide_task_t *task)
821{
822 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
823 struct ide_taskfile *tf = &task->tf;
824
825 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
826 u16 data = cris_ide_inw(io_ports->data_addr);
827
828 tf->data = data & 0xff;
829 tf->hob_data = (data >> 8) & 0xff;
830 }
831
832 /* be sure we're looking at the low order bits */
833 cris_ide_outb(drive->ctl & ~0x80, io_ports->ctl_addr);
834
835 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
836 tf->nsect = cris_ide_inb(io_ports->nsect_addr);
837 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
838 tf->lbal = cris_ide_inb(io_ports->lbal_addr);
839 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
840 tf->lbam = cris_ide_inb(io_ports->lbam_addr);
841 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
842 tf->lbah = cris_ide_inb(io_ports->lbah_addr);
843 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
844 tf->device = cris_ide_inb(io_ports->device_addr);
845
846 if (task->tf_flags & IDE_TFLAG_LBA48) {
847 cris_ide_outb(drive->ctl | 0x80, io_ports->ctl_addr);
848
849 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
850 tf->hob_feature = cris_ide_inb(io_ports->feature_addr);
851 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
852 tf->hob_nsect = cris_ide_inb(io_ports->nsect_addr);
853 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
854 tf->hob_lbal = cris_ide_inb(io_ports->lbal_addr);
855 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
856 tf->hob_lbam = cris_ide_inb(io_ports->lbam_addr);
857 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
858 tf->hob_lbah = cris_ide_inb(io_ports->lbah_addr);
859 }
860}
861
862static const struct ide_port_ops cris_port_ops = {
863 .set_pio_mode = cris_set_pio_mode,
864 .set_dma_mode = cris_set_dma_mode,
865};
866
867static const struct ide_dma_ops cris_dma_ops;
868
869static const struct ide_port_info cris_port_info __initdata = {
870 .chipset = ide_etrax100,
871 .port_ops = &cris_port_ops,
872 .dma_ops = &cris_dma_ops,
873 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
874 IDE_HFLAG_NO_DMA, /* no SFF-style DMA */
875 .pio_mask = ATA_PIO4,
876 .udma_mask = cris_ultra_mask,
877 .mwdma_mask = ATA_MWDMA2,
878};
879
880static int __init init_e100_ide(void)
881{
882 hw_regs_t hw;
883 int h;
884 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
885
886 printk("ide: ETRAX FS built-in ATA DMA controller\n");
887
888 for (h = 0; h < 4; h++) {
889 ide_hwif_t *hwif = NULL;
890
891 cris_setup_ports(&hw, cris_ide_base_address(h));
892
893 hwif = ide_find_port();
894 if (hwif == NULL)
895 continue;
896 ide_init_port_data(hwif, hwif->index);
897 ide_init_port_hw(hwif, &hw);
898
899 hwif->tf_load = cris_tf_load;
900 hwif->tf_read = cris_tf_read;
901
902 hwif->input_data = cris_input_data;
903 hwif->output_data = cris_output_data;
904
905 hwif->OUTB = &cris_ide_outb;
906 hwif->OUTBSYNC = &cris_ide_outbsync;
907 hwif->INB = &cris_ide_inb;
908 hwif->cbl = ATA_CBL_PATA40;
909
910 idx[h] = hwif->index;
911 }
912
913 /* Reset pulse */
914 cris_ide_reset(0);
915 udelay(25);
916 cris_ide_reset(1);
917
918 cris_ide_init();
919
920 cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
921 cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
922 cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
923
924 ide_device_add(idx, &cris_port_info);
925
926 return 0;
927}
928
929static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
930
931/*
932 * This is used for most PIO data transfers *from* the IDE interface
933 *
934 * These routines will round up any request for an odd number of bytes,
935 * so if an odd bytecount is specified, be sure that there's at least one
936 * extra byte allocated for the buffer.
937 */
938static void cris_input_data(ide_drive_t *drive, struct request *rq,
939 void *buffer, unsigned int bytecount)
940{
941 D(printk("input_data, buffer 0x%x, count %d\n", buffer, bytecount));
942
943 if(bytecount & 1) {
944 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
945 bytecount++; /* to round off */
946 }
947
948 /* setup DMA and start transfer */
949
950 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
951 cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
952
953 /* wait for completion */
954 LED_DISK_READ(1);
955 cris_ide_wait_dma(1);
956 LED_DISK_READ(0);
957}
958
959/*
960 * This is used for most PIO data transfers *to* the IDE interface
961 */
962static void cris_output_data(ide_drive_t *drive, struct request *rq,
963 void *buffer, unsigned int bytecount)
964{
965 D(printk("output_data, buffer 0x%x, count %d\n", buffer, bytecount));
966
967 if(bytecount & 1) {
968 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
969 bytecount++;
970 }
971
972 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
973 cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
974
975 /* wait for completion */
976
977 LED_DISK_WRITE(1);
978 LED_DISK_READ(1);
979 cris_ide_wait_dma(0);
980 LED_DISK_WRITE(0);
981}
982
983/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
984static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
985static unsigned int ata_tot_size;
986
987/*
988 * cris_ide_build_dmatable() prepares a dma request.
989 * Returns 0 if all went okay, returns 1 otherwise.
990 */
991static int cris_ide_build_dmatable (ide_drive_t *drive)
992{
993 ide_hwif_t *hwif = drive->hwif;
994 struct scatterlist* sg;
995 struct request *rq = drive->hwif->hwgroup->rq;
996 unsigned long size, addr;
997 unsigned int count = 0;
998 int i = 0;
999
1000 sg = hwif->sg_table;
1001
1002 ata_tot_size = 0;
1003
1004 ide_map_sg(drive, rq);
1005 i = hwif->sg_nents;
1006
1007 while(i) {
1008 /*
1009 * Determine addr and size of next buffer area. We assume that
1010 * individual virtual buffers are always composed linearly in
1011 * physical memory. For example, we assume that any 8kB buffer
1012 * is always composed of two adjacent physical 4kB pages rather
1013 * than two possibly non-adjacent physical 4kB pages.
1014 */
1015 /* group sequential buffers into one large buffer */
1016 addr = sg_phys(sg);
1017 size = sg_dma_len(sg);
1018 while (--i) {
1019 sg = sg_next(sg);
1020 if ((addr + size) != sg_phys(sg))
1021 break;
1022 size += sg_dma_len(sg);
1023 }
1024
1025 /* did we run out of descriptors? */
1026
1027 if(count >= MAX_DMA_DESCRS) {
1028 printk("%s: too few DMA descriptors\n", drive->name);
1029 return 1;
1030 }
1031
1032 /* however, this case is more difficult - rw_trf_cnt cannot be more
1033 than 65536 words per transfer, so in that case we need to either
1034 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
1035 the descriptors, or
1036 2) simply do the request here, and get dma_intr to only ide_end_request on
1037 those blocks that were actually set-up for transfer.
1038 */
1039
1040 if(ata_tot_size + size > 131072) {
1041 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
1042 return 1;
1043 }
1044
1045 /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
1046 don't handle size > 131072 only one split is necessary */
1047
1048 if(size > MAX_DESCR_SIZE) {
1049 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
1050 count++;
1051 ata_tot_size += MAX_DESCR_SIZE;
1052 size -= MAX_DESCR_SIZE;
1053 addr += MAX_DESCR_SIZE;
1054 }
1055
1056 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
1057 count++;
1058 ata_tot_size += size;
1059 }
1060
1061 if (count) {
1062 /* return and say all is ok */
1063 return 0;
1064 }
1065
1066 printk("%s: empty DMA table?\n", drive->name);
1067 return 1; /* let the PIO routines handle this weirdness */
1068}
1069
1070/*
1071 * cris_dma_intr() is the handler for disk read/write DMA interrupts
1072 */
1073static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
1074{
1075 LED_DISK_READ(0);
1076 LED_DISK_WRITE(0);
1077
1078 return ide_dma_intr(drive);
1079}
1080
1081/*
1082 * Functions below initiates/aborts DMA read/write operations on a drive.
1083 *
1084 * The caller is assumed to have selected the drive and programmed the drive's
1085 * sector address using CHS or LBA. All that remains is to prepare for DMA
1086 * and then issue the actual read/write DMA/PIO command to the drive.
1087 *
1088 * For ATAPI devices, we just prepare for DMA and return. The caller should
1089 * then issue the packet command to the drive and call us again with
1090 * cris_dma_start afterwards.
1091 *
1092 * Returns 0 if all went well.
1093 * Returns 1 if DMA read/write could not be started, in which case
1094 * the caller should revert to PIO for the current request.
1095 */
1096
1097static int cris_dma_end(ide_drive_t *drive)
1098{
1099 drive->waiting_for_dma = 0;
1100 return 0;
1101}
1102
1103static int cris_dma_setup(ide_drive_t *drive)
1104{
1105 struct request *rq = drive->hwif->hwgroup->rq;
1106
1107 cris_ide_initialize_dma(!rq_data_dir(rq));
1108 if (cris_ide_build_dmatable (drive)) {
1109 ide_map_sg(drive, rq);
1110 return 1;
1111 }
1112
1113 drive->waiting_for_dma = 1;
1114 return 0;
1115}
1116
1117static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
1118{
1119 ide_execute_command(drive, command, &cris_dma_intr, WAIT_CMD, NULL);
1120}
1121
1122static void cris_dma_start(ide_drive_t *drive)
1123{
1124 struct request *rq = drive->hwif->hwgroup->rq;
1125 int writing = rq_data_dir(rq);
1126 int type = TYPE_DMA;
1127
1128 if (drive->current_speed >= XFER_UDMA_0)
1129 type = TYPE_UDMA;
1130
1131 cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
1132
1133 if (writing) {
1134 LED_DISK_WRITE(1);
1135 } else {
1136 LED_DISK_READ(1);
1137 }
1138}
1139
1140static const struct ide_dma_ops cris_dma_ops = {
1141 .dma_host_set = cris_dma_host_set,
1142 .dma_setup = cris_dma_setup,
1143 .dma_exec_cmd = cris_dma_exec_cmd,
1144 .dma_start = cris_dma_start,
1145 .dma_end = cris_dma_end,
1146 .dma_test_irq = cris_dma_test_irq,
1147};
1148
1149module_init(init_e100_ide);
1150
1151MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 14:22:25 -0400