diff options
-rw-r--r-- | Documentation/devicetree/bindings/clock/silabs,si5351.txt | 4 | ||||
-rw-r--r-- | drivers/clk/clk-si5351.c | 63 | ||||
-rw-r--r-- | drivers/clk/clk.c | 8 | ||||
-rw-r--r-- | drivers/clk/qcom/gcc-msm8916.c | 4 | ||||
-rw-r--r-- | drivers/clk/samsung/Makefile | 2 | ||||
-rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 1 | ||||
-rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 12 | ||||
-rw-r--r-- | include/linux/platform_data/si5351.h | 4 |
8 files changed, 66 insertions, 32 deletions
diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt index c40711e8e8f7..28b28309f535 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt | |||
@@ -17,7 +17,8 @@ Required properties: | |||
17 | - #clock-cells: from common clock binding; shall be set to 1. | 17 | - #clock-cells: from common clock binding; shall be set to 1. |
18 | - clocks: from common clock binding; list of parent clock | 18 | - clocks: from common clock binding; list of parent clock |
19 | handles, shall be xtal reference clock or xtal and clkin for | 19 | handles, shall be xtal reference clock or xtal and clkin for |
20 | si5351c only. | 20 | si5351c only. Corresponding clock input names are "xtal" and |
21 | "clkin" respectively. | ||
21 | - #address-cells: shall be set to 1. | 22 | - #address-cells: shall be set to 1. |
22 | - #size-cells: shall be set to 0. | 23 | - #size-cells: shall be set to 0. |
23 | 24 | ||
@@ -71,6 +72,7 @@ i2c-master-node { | |||
71 | 72 | ||
72 | /* connect xtal input to 25MHz reference */ | 73 | /* connect xtal input to 25MHz reference */ |
73 | clocks = <&ref25>; | 74 | clocks = <&ref25>; |
75 | clock-names = "xtal"; | ||
74 | 76 | ||
75 | /* connect xtal input as source of pll0 and pll1 */ | 77 | /* connect xtal input as source of pll0 and pll1 */ |
76 | silabs,pll-source = <0 0>, <1 0>; | 78 | silabs,pll-source = <0 0>, <1 0>; |
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 44ea107cfc67..30335d3b99af 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c | |||
@@ -1128,13 +1128,6 @@ static int si5351_dt_parse(struct i2c_client *client, | |||
1128 | if (!pdata) | 1128 | if (!pdata) |
1129 | return -ENOMEM; | 1129 | return -ENOMEM; |
1130 | 1130 | ||
1131 | pdata->clk_xtal = of_clk_get(np, 0); | ||
1132 | if (!IS_ERR(pdata->clk_xtal)) | ||
1133 | clk_put(pdata->clk_xtal); | ||
1134 | pdata->clk_clkin = of_clk_get(np, 1); | ||
1135 | if (!IS_ERR(pdata->clk_clkin)) | ||
1136 | clk_put(pdata->clk_clkin); | ||
1137 | |||
1138 | /* | 1131 | /* |
1139 | * property silabs,pll-source : <num src>, [<..>] | 1132 | * property silabs,pll-source : <num src>, [<..>] |
1140 | * allow to selectively set pll source | 1133 | * allow to selectively set pll source |
@@ -1328,8 +1321,22 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1328 | i2c_set_clientdata(client, drvdata); | 1321 | i2c_set_clientdata(client, drvdata); |
1329 | drvdata->client = client; | 1322 | drvdata->client = client; |
1330 | drvdata->variant = variant; | 1323 | drvdata->variant = variant; |
1331 | drvdata->pxtal = pdata->clk_xtal; | 1324 | drvdata->pxtal = devm_clk_get(&client->dev, "xtal"); |
1332 | drvdata->pclkin = pdata->clk_clkin; | 1325 | drvdata->pclkin = devm_clk_get(&client->dev, "clkin"); |
1326 | |||
1327 | if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER || | ||
1328 | PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER) | ||
1329 | return -EPROBE_DEFER; | ||
1330 | |||
1331 | /* | ||
1332 | * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL, | ||
1333 | * VARIANT_C can have CLKIN instead. | ||
1334 | */ | ||
1335 | if (IS_ERR(drvdata->pxtal) && | ||
1336 | (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) { | ||
1337 | dev_err(&client->dev, "missing parent clock\n"); | ||
1338 | return -EINVAL; | ||
1339 | } | ||
1333 | 1340 | ||
1334 | drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config); | 1341 | drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config); |
1335 | if (IS_ERR(drvdata->regmap)) { | 1342 | if (IS_ERR(drvdata->regmap)) { |
@@ -1393,6 +1400,11 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1393 | } | 1400 | } |
1394 | } | 1401 | } |
1395 | 1402 | ||
1403 | if (!IS_ERR(drvdata->pxtal)) | ||
1404 | clk_prepare_enable(drvdata->pxtal); | ||
1405 | if (!IS_ERR(drvdata->pclkin)) | ||
1406 | clk_prepare_enable(drvdata->pclkin); | ||
1407 | |||
1396 | /* register xtal input clock gate */ | 1408 | /* register xtal input clock gate */ |
1397 | memset(&init, 0, sizeof(init)); | 1409 | memset(&init, 0, sizeof(init)); |
1398 | init.name = si5351_input_names[0]; | 1410 | init.name = si5351_input_names[0]; |
@@ -1407,7 +1419,8 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1407 | clk = devm_clk_register(&client->dev, &drvdata->xtal); | 1419 | clk = devm_clk_register(&client->dev, &drvdata->xtal); |
1408 | if (IS_ERR(clk)) { | 1420 | if (IS_ERR(clk)) { |
1409 | dev_err(&client->dev, "unable to register %s\n", init.name); | 1421 | dev_err(&client->dev, "unable to register %s\n", init.name); |
1410 | return PTR_ERR(clk); | 1422 | ret = PTR_ERR(clk); |
1423 | goto err_clk; | ||
1411 | } | 1424 | } |
1412 | 1425 | ||
1413 | /* register clkin input clock gate */ | 1426 | /* register clkin input clock gate */ |
@@ -1425,7 +1438,8 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1425 | if (IS_ERR(clk)) { | 1438 | if (IS_ERR(clk)) { |
1426 | dev_err(&client->dev, "unable to register %s\n", | 1439 | dev_err(&client->dev, "unable to register %s\n", |
1427 | init.name); | 1440 | init.name); |
1428 | return PTR_ERR(clk); | 1441 | ret = PTR_ERR(clk); |
1442 | goto err_clk; | ||
1429 | } | 1443 | } |
1430 | } | 1444 | } |
1431 | 1445 | ||
@@ -1447,7 +1461,8 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1447 | clk = devm_clk_register(&client->dev, &drvdata->pll[0].hw); | 1461 | clk = devm_clk_register(&client->dev, &drvdata->pll[0].hw); |
1448 | if (IS_ERR(clk)) { | 1462 | if (IS_ERR(clk)) { |
1449 | dev_err(&client->dev, "unable to register %s\n", init.name); | 1463 | dev_err(&client->dev, "unable to register %s\n", init.name); |
1450 | return -EINVAL; | 1464 | ret = PTR_ERR(clk); |
1465 | goto err_clk; | ||
1451 | } | 1466 | } |
1452 | 1467 | ||
1453 | /* register PLLB or VXCO (Si5351B) */ | 1468 | /* register PLLB or VXCO (Si5351B) */ |
@@ -1471,7 +1486,8 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1471 | clk = devm_clk_register(&client->dev, &drvdata->pll[1].hw); | 1486 | clk = devm_clk_register(&client->dev, &drvdata->pll[1].hw); |
1472 | if (IS_ERR(clk)) { | 1487 | if (IS_ERR(clk)) { |
1473 | dev_err(&client->dev, "unable to register %s\n", init.name); | 1488 | dev_err(&client->dev, "unable to register %s\n", init.name); |
1474 | return -EINVAL; | 1489 | ret = PTR_ERR(clk); |
1490 | goto err_clk; | ||
1475 | } | 1491 | } |
1476 | 1492 | ||
1477 | /* register clk multisync and clk out divider */ | 1493 | /* register clk multisync and clk out divider */ |
@@ -1492,8 +1508,10 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1492 | num_clocks * sizeof(*drvdata->onecell.clks), GFP_KERNEL); | 1508 | num_clocks * sizeof(*drvdata->onecell.clks), GFP_KERNEL); |
1493 | 1509 | ||
1494 | if (WARN_ON(!drvdata->msynth || !drvdata->clkout || | 1510 | if (WARN_ON(!drvdata->msynth || !drvdata->clkout || |
1495 | !drvdata->onecell.clks)) | 1511 | !drvdata->onecell.clks)) { |
1496 | return -ENOMEM; | 1512 | ret = -ENOMEM; |
1513 | goto err_clk; | ||
1514 | } | ||
1497 | 1515 | ||
1498 | for (n = 0; n < num_clocks; n++) { | 1516 | for (n = 0; n < num_clocks; n++) { |
1499 | drvdata->msynth[n].num = n; | 1517 | drvdata->msynth[n].num = n; |
@@ -1511,7 +1529,8 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1511 | if (IS_ERR(clk)) { | 1529 | if (IS_ERR(clk)) { |
1512 | dev_err(&client->dev, "unable to register %s\n", | 1530 | dev_err(&client->dev, "unable to register %s\n", |
1513 | init.name); | 1531 | init.name); |
1514 | return -EINVAL; | 1532 | ret = PTR_ERR(clk); |
1533 | goto err_clk; | ||
1515 | } | 1534 | } |
1516 | } | 1535 | } |
1517 | 1536 | ||
@@ -1538,7 +1557,8 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1538 | if (IS_ERR(clk)) { | 1557 | if (IS_ERR(clk)) { |
1539 | dev_err(&client->dev, "unable to register %s\n", | 1558 | dev_err(&client->dev, "unable to register %s\n", |
1540 | init.name); | 1559 | init.name); |
1541 | return -EINVAL; | 1560 | ret = PTR_ERR(clk); |
1561 | goto err_clk; | ||
1542 | } | 1562 | } |
1543 | drvdata->onecell.clks[n] = clk; | 1563 | drvdata->onecell.clks[n] = clk; |
1544 | 1564 | ||
@@ -1557,10 +1577,17 @@ static int si5351_i2c_probe(struct i2c_client *client, | |||
1557 | &drvdata->onecell); | 1577 | &drvdata->onecell); |
1558 | if (ret) { | 1578 | if (ret) { |
1559 | dev_err(&client->dev, "unable to add clk provider\n"); | 1579 | dev_err(&client->dev, "unable to add clk provider\n"); |
1560 | return ret; | 1580 | goto err_clk; |
1561 | } | 1581 | } |
1562 | 1582 | ||
1563 | return 0; | 1583 | return 0; |
1584 | |||
1585 | err_clk: | ||
1586 | if (!IS_ERR(drvdata->pxtal)) | ||
1587 | clk_disable_unprepare(drvdata->pxtal); | ||
1588 | if (!IS_ERR(drvdata->pclkin)) | ||
1589 | clk_disable_unprepare(drvdata->pclkin); | ||
1590 | return ret; | ||
1564 | } | 1591 | } |
1565 | 1592 | ||
1566 | static const struct i2c_device_id si5351_i2c_ids[] = { | 1593 | static const struct i2c_device_id si5351_i2c_ids[] = { |
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 459ce9da13e0..5b0f41868b42 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c | |||
@@ -1475,8 +1475,10 @@ static struct clk_core *__clk_set_parent_before(struct clk_core *clk, | |||
1475 | */ | 1475 | */ |
1476 | if (clk->prepare_count) { | 1476 | if (clk->prepare_count) { |
1477 | clk_core_prepare(parent); | 1477 | clk_core_prepare(parent); |
1478 | flags = clk_enable_lock(); | ||
1478 | clk_core_enable(parent); | 1479 | clk_core_enable(parent); |
1479 | clk_core_enable(clk); | 1480 | clk_core_enable(clk); |
1481 | clk_enable_unlock(flags); | ||
1480 | } | 1482 | } |
1481 | 1483 | ||
1482 | /* update the clk tree topology */ | 1484 | /* update the clk tree topology */ |
@@ -1491,13 +1493,17 @@ static void __clk_set_parent_after(struct clk_core *core, | |||
1491 | struct clk_core *parent, | 1493 | struct clk_core *parent, |
1492 | struct clk_core *old_parent) | 1494 | struct clk_core *old_parent) |
1493 | { | 1495 | { |
1496 | unsigned long flags; | ||
1497 | |||
1494 | /* | 1498 | /* |
1495 | * Finish the migration of prepare state and undo the changes done | 1499 | * Finish the migration of prepare state and undo the changes done |
1496 | * for preventing a race with clk_enable(). | 1500 | * for preventing a race with clk_enable(). |
1497 | */ | 1501 | */ |
1498 | if (core->prepare_count) { | 1502 | if (core->prepare_count) { |
1503 | flags = clk_enable_lock(); | ||
1499 | clk_core_disable(core); | 1504 | clk_core_disable(core); |
1500 | clk_core_disable(old_parent); | 1505 | clk_core_disable(old_parent); |
1506 | clk_enable_unlock(flags); | ||
1501 | clk_core_unprepare(old_parent); | 1507 | clk_core_unprepare(old_parent); |
1502 | } | 1508 | } |
1503 | } | 1509 | } |
@@ -1525,8 +1531,10 @@ static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent, | |||
1525 | clk_enable_unlock(flags); | 1531 | clk_enable_unlock(flags); |
1526 | 1532 | ||
1527 | if (clk->prepare_count) { | 1533 | if (clk->prepare_count) { |
1534 | flags = clk_enable_lock(); | ||
1528 | clk_core_disable(clk); | 1535 | clk_core_disable(clk); |
1529 | clk_core_disable(parent); | 1536 | clk_core_disable(parent); |
1537 | clk_enable_unlock(flags); | ||
1530 | clk_core_unprepare(parent); | 1538 | clk_core_unprepare(parent); |
1531 | } | 1539 | } |
1532 | return ret; | 1540 | return ret; |
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index d3458474eb3a..c66f7bc2ae87 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c | |||
@@ -71,8 +71,8 @@ static const char *gcc_xo_gpll0_bimc[] = { | |||
71 | static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { | 71 | static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { |
72 | { P_XO, 0 }, | 72 | { P_XO, 0 }, |
73 | { P_GPLL0_AUX, 3 }, | 73 | { P_GPLL0_AUX, 3 }, |
74 | { P_GPLL2_AUX, 2 }, | ||
75 | { P_GPLL1, 1 }, | 74 | { P_GPLL1, 1 }, |
75 | { P_GPLL2_AUX, 2 }, | ||
76 | }; | 76 | }; |
77 | 77 | ||
78 | static const char *gcc_xo_gpll0a_gpll1_gpll2a[] = { | 78 | static const char *gcc_xo_gpll0a_gpll1_gpll2a[] = { |
@@ -1115,7 +1115,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { | |||
1115 | static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { | 1115 | static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { |
1116 | F(100000000, P_GPLL0, 8, 0, 0), | 1116 | F(100000000, P_GPLL0, 8, 0, 0), |
1117 | F(160000000, P_GPLL0, 5, 0, 0), | 1117 | F(160000000, P_GPLL0, 5, 0, 0), |
1118 | F(228570000, P_GPLL0, 5, 0, 0), | 1118 | F(228570000, P_GPLL0, 3.5, 0, 0), |
1119 | { } | 1119 | { } |
1120 | }; | 1120 | }; |
1121 | 1121 | ||
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 17e9af7fe81f..a17683b2cf27 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile | |||
@@ -10,7 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o | |||
10 | obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o | 10 | obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o |
11 | obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o | 11 | obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o |
12 | obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o | 12 | obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o |
13 | obj-$(CONFIG_ARCH_EXYNOS5433) += clk-exynos5433.o | 13 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos5433.o |
14 | obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o | 14 | obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o |
15 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o | 15 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o |
16 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o | 16 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o |
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 07d666cc6a29..bea4a173eef5 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c | |||
@@ -271,6 +271,7 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { | |||
271 | { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, | 271 | { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, |
272 | { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, | 272 | { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, |
273 | { .offset = SRC_MASK_ISP, .value = 0x11111000, }, | 273 | { .offset = SRC_MASK_ISP, .value = 0x11111000, }, |
274 | { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, | ||
274 | { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, | 275 | { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, |
275 | { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, | 276 | { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, |
276 | }; | 277 | }; |
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 387e3e39e635..9e04ae2bb4d7 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c | |||
@@ -748,7 +748,7 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = { | |||
748 | PLL_35XX_RATE(825000000U, 275, 4, 1), | 748 | PLL_35XX_RATE(825000000U, 275, 4, 1), |
749 | PLL_35XX_RATE(800000000U, 400, 6, 1), | 749 | PLL_35XX_RATE(800000000U, 400, 6, 1), |
750 | PLL_35XX_RATE(733000000U, 733, 12, 1), | 750 | PLL_35XX_RATE(733000000U, 733, 12, 1), |
751 | PLL_35XX_RATE(700000000U, 360, 6, 1), | 751 | PLL_35XX_RATE(700000000U, 175, 3, 1), |
752 | PLL_35XX_RATE(667000000U, 222, 4, 1), | 752 | PLL_35XX_RATE(667000000U, 222, 4, 1), |
753 | PLL_35XX_RATE(633000000U, 211, 4, 1), | 753 | PLL_35XX_RATE(633000000U, 211, 4, 1), |
754 | PLL_35XX_RATE(600000000U, 500, 5, 2), | 754 | PLL_35XX_RATE(600000000U, 500, 5, 2), |
@@ -760,14 +760,14 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = { | |||
760 | PLL_35XX_RATE(444000000U, 370, 5, 2), | 760 | PLL_35XX_RATE(444000000U, 370, 5, 2), |
761 | PLL_35XX_RATE(420000000U, 350, 5, 2), | 761 | PLL_35XX_RATE(420000000U, 350, 5, 2), |
762 | PLL_35XX_RATE(400000000U, 400, 6, 2), | 762 | PLL_35XX_RATE(400000000U, 400, 6, 2), |
763 | PLL_35XX_RATE(350000000U, 360, 6, 2), | 763 | PLL_35XX_RATE(350000000U, 350, 6, 2), |
764 | PLL_35XX_RATE(333000000U, 222, 4, 2), | 764 | PLL_35XX_RATE(333000000U, 222, 4, 2), |
765 | PLL_35XX_RATE(300000000U, 500, 5, 3), | 765 | PLL_35XX_RATE(300000000U, 500, 5, 3), |
766 | PLL_35XX_RATE(266000000U, 532, 6, 3), | 766 | PLL_35XX_RATE(266000000U, 532, 6, 3), |
767 | PLL_35XX_RATE(200000000U, 400, 6, 3), | 767 | PLL_35XX_RATE(200000000U, 400, 6, 3), |
768 | PLL_35XX_RATE(166000000U, 332, 6, 3), | 768 | PLL_35XX_RATE(166000000U, 332, 6, 3), |
769 | PLL_35XX_RATE(160000000U, 320, 6, 3), | 769 | PLL_35XX_RATE(160000000U, 320, 6, 3), |
770 | PLL_35XX_RATE(133000000U, 552, 6, 4), | 770 | PLL_35XX_RATE(133000000U, 532, 6, 4), |
771 | PLL_35XX_RATE(100000000U, 400, 6, 4), | 771 | PLL_35XX_RATE(100000000U, 400, 6, 4), |
772 | { /* sentinel */ } | 772 | { /* sentinel */ } |
773 | }; | 773 | }; |
@@ -1490,7 +1490,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = { | |||
1490 | 1490 | ||
1491 | /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ | 1491 | /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ |
1492 | GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", | 1492 | GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", |
1493 | ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), | 1493 | ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0), |
1494 | 1494 | ||
1495 | /* ENABLE_PCLK_MIF_SECURE_RTC */ | 1495 | /* ENABLE_PCLK_MIF_SECURE_RTC */ |
1496 | GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", | 1496 | GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", |
@@ -3665,7 +3665,7 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = { | |||
3665 | ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), | 3665 | ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), |
3666 | GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", | 3666 | GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", |
3667 | ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), | 3667 | ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), |
3668 | GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll", | 3668 | GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2", |
3669 | ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0), | 3669 | ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0), |
3670 | }; | 3670 | }; |
3671 | 3671 | ||
@@ -3927,7 +3927,7 @@ CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", | |||
3927 | #define ENABLE_PCLK_MSCL 0x0900 | 3927 | #define ENABLE_PCLK_MSCL 0x0900 |
3928 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 | 3928 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 |
3929 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 | 3929 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 |
3930 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x000c | 3930 | #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c |
3931 | #define ENABLE_SCLK_MSCL 0x0a00 | 3931 | #define ENABLE_SCLK_MSCL 0x0a00 |
3932 | #define ENABLE_IP_MSCL0 0x0b00 | 3932 | #define ENABLE_IP_MSCL0 0x0b00 |
3933 | #define ENABLE_IP_MSCL1 0x0b04 | 3933 | #define ENABLE_IP_MSCL1 0x0b04 |
diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index a947ab8b441a..533d9807e543 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h | |||
@@ -5,8 +5,6 @@ | |||
5 | #ifndef __LINUX_PLATFORM_DATA_SI5351_H__ | 5 | #ifndef __LINUX_PLATFORM_DATA_SI5351_H__ |
6 | #define __LINUX_PLATFORM_DATA_SI5351_H__ | 6 | #define __LINUX_PLATFORM_DATA_SI5351_H__ |
7 | 7 | ||
8 | struct clk; | ||
9 | |||
10 | /** | 8 | /** |
11 | * enum si5351_pll_src - Si5351 pll clock source | 9 | * enum si5351_pll_src - Si5351 pll clock source |
12 | * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config | 10 | * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config |
@@ -107,8 +105,6 @@ struct si5351_clkout_config { | |||
107 | * @clkout: array of clkout configuration | 105 | * @clkout: array of clkout configuration |
108 | */ | 106 | */ |
109 | struct si5351_platform_data { | 107 | struct si5351_platform_data { |
110 | struct clk *clk_xtal; | ||
111 | struct clk *clk_clkin; | ||
112 | enum si5351_pll_src pll_src[2]; | 108 | enum si5351_pll_src pll_src[2]; |
113 | struct si5351_clkout_config clkout[8]; | 109 | struct si5351_clkout_config clkout[8]; |
114 | }; | 110 | }; |