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-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-exynos4415.c1142
-rw-r--r--include/dt-bindings/clock/exynos4415.h360
3 files changed, 1503 insertions, 0 deletions
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc602e8a..d8535e6df1db 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o 5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o 6obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
7obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o 7obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
8obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
8obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o 9obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
9obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o 10obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
10obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o 11obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c
new file mode 100644
index 000000000000..c7208c7a3add
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4415.c
@@ -0,0 +1,1142 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos4415 SoC.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/platform_device.h>
18#include <linux/syscore_ops.h>
19
20#include <dt-bindings/clock/exynos4415.h>
21
22#include "clk.h"
23#include "clk-pll.h"
24
25#define SRC_LEFTBUS 0x4200
26#define DIV_LEFTBUS 0x4500
27#define GATE_IP_LEFTBUS 0x4800
28#define GATE_IP_IMAGE 0x4930
29#define SRC_RIGHTBUS 0x8200
30#define DIV_RIGHTBUS 0x8500
31#define GATE_IP_RIGHTBUS 0x8800
32#define GATE_IP_PERIR 0x8960
33#define EPLL_LOCK 0xc010
34#define G3D_PLL_LOCK 0xc020
35#define DISP_PLL_LOCK 0xc030
36#define ISP_PLL_LOCK 0xc040
37#define EPLL_CON0 0xc110
38#define EPLL_CON1 0xc114
39#define EPLL_CON2 0xc118
40#define G3D_PLL_CON0 0xc120
41#define G3D_PLL_CON1 0xc124
42#define G3D_PLL_CON2 0xc128
43#define ISP_PLL_CON0 0xc130
44#define ISP_PLL_CON1 0xc134
45#define ISP_PLL_CON2 0xc138
46#define DISP_PLL_CON0 0xc140
47#define DISP_PLL_CON1 0xc144
48#define DISP_PLL_CON2 0xc148
49#define SRC_TOP0 0xc210
50#define SRC_TOP1 0xc214
51#define SRC_CAM 0xc220
52#define SRC_TV 0xc224
53#define SRC_MFC 0xc228
54#define SRC_G3D 0xc22c
55#define SRC_LCD 0xc234
56#define SRC_ISP 0xc238
57#define SRC_MAUDIO 0xc23c
58#define SRC_FSYS 0xc240
59#define SRC_PERIL0 0xc250
60#define SRC_PERIL1 0xc254
61#define SRC_CAM1 0xc258
62#define SRC_TOP_ISP0 0xc25c
63#define SRC_TOP_ISP1 0xc260
64#define SRC_MASK_TOP 0xc310
65#define SRC_MASK_CAM 0xc320
66#define SRC_MASK_TV 0xc324
67#define SRC_MASK_LCD 0xc334
68#define SRC_MASK_ISP 0xc338
69#define SRC_MASK_MAUDIO 0xc33c
70#define SRC_MASK_FSYS 0xc340
71#define SRC_MASK_PERIL0 0xc350
72#define SRC_MASK_PERIL1 0xc354
73#define DIV_TOP 0xc510
74#define DIV_CAM 0xc520
75#define DIV_TV 0xc524
76#define DIV_MFC 0xc528
77#define DIV_G3D 0xc52c
78#define DIV_LCD 0xc534
79#define DIV_ISP 0xc538
80#define DIV_MAUDIO 0xc53c
81#define DIV_FSYS0 0xc540
82#define DIV_FSYS1 0xc544
83#define DIV_FSYS2 0xc548
84#define DIV_PERIL0 0xc550
85#define DIV_PERIL1 0xc554
86#define DIV_PERIL2 0xc558
87#define DIV_PERIL3 0xc55c
88#define DIV_PERIL4 0xc560
89#define DIV_PERIL5 0xc564
90#define DIV_CAM1 0xc568
91#define DIV_TOP_ISP1 0xc56c
92#define DIV_TOP_ISP0 0xc570
93#define CLKDIV2_RATIO 0xc580
94#define GATE_SCLK_CAM 0xc820
95#define GATE_SCLK_TV 0xc824
96#define GATE_SCLK_MFC 0xc828
97#define GATE_SCLK_G3D 0xc82c
98#define GATE_SCLK_LCD 0xc834
99#define GATE_SCLK_MAUDIO 0xc83c
100#define GATE_SCLK_FSYS 0xc840
101#define GATE_SCLK_PERIL 0xc850
102#define GATE_IP_CAM 0xc920
103#define GATE_IP_TV 0xc924
104#define GATE_IP_MFC 0xc928
105#define GATE_IP_G3D 0xc92c
106#define GATE_IP_LCD 0xc934
107#define GATE_IP_FSYS 0xc940
108#define GATE_IP_PERIL 0xc950
109#define GATE_BLOCK 0xc970
110#define APLL_LOCK 0x14000
111#define APLL_CON0 0x14100
112#define SRC_CPU 0x14200
113#define DIV_CPU0 0x14500
114#define DIV_CPU1 0x14504
115
116enum exynos4415_plls {
117 apll, epll, g3d_pll, isp_pll, disp_pll,
118 nr_plls,
119};
120
121/*
122 * Support for CMU save/restore across system suspends
123 */
124#ifdef CONFIG_PM_SLEEP
125static struct samsung_clk_reg_dump *exynos4415_clk_regs;
126static struct samsung_clk_provider *exynos4415_ctx;
127
128static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
129 SRC_LEFTBUS,
130 DIV_LEFTBUS,
131 GATE_IP_LEFTBUS,
132 GATE_IP_IMAGE,
133 SRC_RIGHTBUS,
134 DIV_RIGHTBUS,
135 GATE_IP_RIGHTBUS,
136 GATE_IP_PERIR,
137 EPLL_LOCK,
138 G3D_PLL_LOCK,
139 DISP_PLL_LOCK,
140 ISP_PLL_LOCK,
141 EPLL_CON0,
142 EPLL_CON1,
143 EPLL_CON2,
144 G3D_PLL_CON0,
145 G3D_PLL_CON1,
146 G3D_PLL_CON2,
147 ISP_PLL_CON0,
148 ISP_PLL_CON1,
149 ISP_PLL_CON2,
150 DISP_PLL_CON0,
151 DISP_PLL_CON1,
152 DISP_PLL_CON2,
153 SRC_TOP0,
154 SRC_TOP1,
155 SRC_CAM,
156 SRC_TV,
157 SRC_MFC,
158 SRC_G3D,
159 SRC_LCD,
160 SRC_ISP,
161 SRC_MAUDIO,
162 SRC_FSYS,
163 SRC_PERIL0,
164 SRC_PERIL1,
165 SRC_CAM1,
166 SRC_TOP_ISP0,
167 SRC_TOP_ISP1,
168 SRC_MASK_TOP,
169 SRC_MASK_CAM,
170 SRC_MASK_TV,
171 SRC_MASK_LCD,
172 SRC_MASK_ISP,
173 SRC_MASK_MAUDIO,
174 SRC_MASK_FSYS,
175 SRC_MASK_PERIL0,
176 SRC_MASK_PERIL1,
177 DIV_TOP,
178 DIV_CAM,
179 DIV_TV,
180 DIV_MFC,
181 DIV_G3D,
182 DIV_LCD,
183 DIV_ISP,
184 DIV_MAUDIO,
185 DIV_FSYS0,
186 DIV_FSYS1,
187 DIV_FSYS2,
188 DIV_PERIL0,
189 DIV_PERIL1,
190 DIV_PERIL2,
191 DIV_PERIL3,
192 DIV_PERIL4,
193 DIV_PERIL5,
194 DIV_CAM1,
195 DIV_TOP_ISP1,
196 DIV_TOP_ISP0,
197 CLKDIV2_RATIO,
198 GATE_SCLK_CAM,
199 GATE_SCLK_TV,
200 GATE_SCLK_MFC,
201 GATE_SCLK_G3D,
202 GATE_SCLK_LCD,
203 GATE_SCLK_MAUDIO,
204 GATE_SCLK_FSYS,
205 GATE_SCLK_PERIL,
206 GATE_IP_CAM,
207 GATE_IP_TV,
208 GATE_IP_MFC,
209 GATE_IP_G3D,
210 GATE_IP_LCD,
211 GATE_IP_FSYS,
212 GATE_IP_PERIL,
213 GATE_BLOCK,
214 APLL_LOCK,
215 APLL_CON0,
216 SRC_CPU,
217 DIV_CPU0,
218 DIV_CPU1,
219};
220
221static int exynos4415_clk_suspend(void)
222{
223 samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
224 ARRAY_SIZE(exynos4415_cmu_clk_regs));
225
226 return 0;
227}
228
229static void exynos4415_clk_resume(void)
230{
231 samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
232 ARRAY_SIZE(exynos4415_cmu_clk_regs));
233}
234
235static struct syscore_ops exynos4415_clk_syscore_ops = {
236 .suspend = exynos4415_clk_suspend,
237 .resume = exynos4415_clk_resume,
238};
239
240static void exynos4415_clk_sleep_init(void)
241{
242 exynos4415_clk_regs =
243 samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
244 ARRAY_SIZE(exynos4415_cmu_clk_regs));
245 if (!exynos4415_clk_regs) {
246 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
247 return;
248 }
249
250 register_syscore_ops(&exynos4415_clk_syscore_ops);
251}
252#else
253static inline void exynos4415_clk_sleep_init(void) { }
254#endif
255
256/* list of all parent clock list */
257PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
258
259PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
260PNAME(mout_g3d_pll_p) = { "fin_pll", "fout_g3d_pll", };
261PNAME(mout_isp_pll_p) = { "fin_pll", "fout_isp_pll", };
262PNAME(mout_disp_pll_p) = { "fin_pll", "fout_disp_pll", };
263
264PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
265PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
266PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
267PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
268
269PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
270PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_g3d_pll", };
271
272PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
273PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
274
275PNAME(mout_aclk_266_p) = { "mout_mpll_user_t", "mout_g3d_pll", };
276
277PNAME(group_epll_g3dpll_p) = { "mout_epll", "mout_g3d_pll" };
278PNAME(group_sclk_p) = { "xxti", "xusbxti",
279 "none", "mout_isp_pll",
280 "none", "none", "div_mpll_pre",
281 "mout_epll", "mout_g3d_pll", };
282PNAME(group_spdif_p) = { "mout_audio0", "mout_audio1",
283 "mout_audio2", "spdif_extclk", };
284PNAME(group_sclk_audio2_p) = { "audiocdclk2", "none",
285 "none", "mout_isp_pll",
286 "mout_disp_pll", "xusbxti",
287 "div_mpll_pre", "mout_epll",
288 "mout_g3d_pll", };
289PNAME(group_sclk_audio1_p) = { "audiocdclk1", "none",
290 "none", "mout_isp_pll",
291 "mout_disp_pll", "xusbxti",
292 "div_mpll_pre", "mout_epll",
293 "mout_g3d_pll", };
294PNAME(group_sclk_audio0_p) = { "audiocdclk0", "none",
295 "none", "mout_isp_pll",
296 "mout_disp_pll", "xusbxti",
297 "div_mpll_pre", "mout_epll",
298 "mout_g3d_pll", };
299PNAME(group_fimc_lclk_p) = { "xxti", "xusbxti",
300 "none", "mout_isp_pll",
301 "none", "mout_disp_pll",
302 "mout_mpll_user_t", "mout_epll",
303 "mout_g3d_pll", };
304PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
305 "m_bitclkhsdiv4_4l", "mout_isp_pll",
306 "mout_disp_pll", "sclk_hdmiphy",
307 "div_mpll_pre", "mout_epll",
308 "mout_g3d_pll", };
309PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy" };
310PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
311PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
312PNAME(mout_jpeg_p) = { "mout_jpeg_0", "mout_jpeg_1" };
313PNAME(mout_jpeg1_p) = { "mout_epll", "mout_g3d_pll" };
314PNAME(group_aclk_isp0_300_p) = { "mout_isp_pll", "div_mpll_pre" };
315PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" };
316PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
317PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
318PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" };
319
320static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = {
321 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
322 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
323};
324
325static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = {
326 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
327};
328
329static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {
330 /*
331 * NOTE: Following table is sorted by register address in ascending
332 * order and then bitfield shift in descending order, as it is done
333 * in the User's Manual. When adding new entries, please make sure
334 * that the order is preserved, to avoid merge conflicts and make
335 * further work with defined data easier.
336 */
337
338 /* SRC_LEFTBUS */
339 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
340 SRC_LEFTBUS, 4, 1),
341 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
342
343 /* SRC_RIGHTBUS */
344 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
345 SRC_RIGHTBUS, 4, 1),
346 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
347
348 /* SRC_TOP0 */
349 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
350 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_mout_mpll_user_t_p,
351 SRC_TOP0, 24, 1),
352 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_mout_mpll_user_t_p,
353 SRC_TOP0, 20, 1),
354 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_mout_mpll_user_t_p,
355 SRC_TOP0, 16, 1),
356 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p,
357 SRC_TOP0, 12, 1),
358 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
359 SRC_TOP0, 8, 1),
360 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_TOP0, 4, 1),
361 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
362
363 /* SRC_TOP1 */
364 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p,
365 SRC_TOP1, 28, 1),
366 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
367 SRC_TOP1, 16, 1),
368 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p,
369 SRC_TOP1, 12, 1),
370 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp",
371 group_mout_mpll_user_t_p, SRC_TOP1, 8, 1),
372 MUX(CLK_MOUT_G3D_PLLSRC, "mout_g3d_pllsrc", mout_g3d_pllsrc_p,
373 SRC_TOP1, 0, 1),
374
375 /* SRC_CAM */
376 MUX(CLK_MOUT_CSIS1, "mout_csis1", group_fimc_lclk_p, SRC_CAM, 28, 4),
377 MUX(CLK_MOUT_CSIS0, "mout_csis0", group_fimc_lclk_p, SRC_CAM, 24, 4),
378 MUX(CLK_MOUT_CAM1, "mout_cam1", group_fimc_lclk_p, SRC_CAM, 20, 4),
379 MUX(CLK_MOUT_FIMC3_LCLK, "mout_fimc3_lclk", group_fimc_lclk_p, SRC_CAM,
380 12, 4),
381 MUX(CLK_MOUT_FIMC2_LCLK, "mout_fimc2_lclk", group_fimc_lclk_p, SRC_CAM,
382 8, 4),
383 MUX(CLK_MOUT_FIMC1_LCLK, "mout_fimc1_lclk", group_fimc_lclk_p, SRC_CAM,
384 4, 4),
385 MUX(CLK_MOUT_FIMC0_LCLK, "mout_fimc0_lclk", group_fimc_lclk_p, SRC_CAM,
386 0, 4),
387
388 /* SRC_TV */
389 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
390
391 /* SRC_MFC */
392 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
393 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_g3dpll_p, SRC_MFC, 4, 1),
394 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_mout_mpll_user_t_p, SRC_MFC, 0,
395 1),
396
397 /* SRC_G3D */
398 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
399 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_g3dpll_p, SRC_G3D, 4, 1),
400 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_mout_mpll_user_t_p, SRC_G3D, 0,
401 1),
402
403 /* SRC_LCD */
404 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_fimc_lclk_p, SRC_LCD, 12, 4),
405 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
406
407 /* SRC_ISP */
408 MUX(CLK_MOUT_TSADC_ISP, "mout_tsadc_isp", group_fimc_lclk_p, SRC_ISP,
409 16, 4),
410 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_fimc_lclk_p, SRC_ISP,
411 12, 4),
412 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_fimc_lclk_p, SRC_ISP,
413 8, 4),
414 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_fimc_lclk_p, SRC_ISP,
415 4, 4),
416 MUX(CLK_MOUT_PWM_ISP, "mout_pwm_isp", group_fimc_lclk_p, SRC_ISP,
417 0, 4),
418
419 /* SRC_MAUDIO */
420 MUX(CLK_MOUT_AUDIO0, "mout_audio0", group_sclk_audio0_p, SRC_MAUDIO,
421 0, 4),
422
423 /* SRC_FSYS */
424 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
425 MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
426 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
427 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
428
429 /* SRC_PERIL0 */
430 MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
431 MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
432 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
433 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
434
435 /* SRC_PERIL1 */
436 MUX(CLK_MOUT_SPI2, "mout_spi2", group_sclk_p, SRC_PERIL1, 24, 4),
437 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
438 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
439 MUX(CLK_MOUT_SPDIF, "mout_spdif", group_spdif_p, SRC_PERIL1, 8, 4),
440 MUX(CLK_MOUT_AUDIO2, "mout_audio2", group_sclk_audio2_p, SRC_PERIL1,
441 4, 4),
442 MUX(CLK_MOUT_AUDIO1, "mout_audio1", group_sclk_audio1_p, SRC_PERIL1,
443 0, 4),
444
445 /* SRC_CPU */
446 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
447 SRC_CPU, 24, 1),
448 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
449 MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
450 CLK_MUX_READ_ONLY),
451 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
452 CLK_SET_RATE_PARENT, 0),
453
454 /* SRC_CAM1 */
455 MUX(CLK_MOUT_PXLASYNC_CSIS1_FIMC, "mout_pxlasync_csis1",
456 group_fimc_lclk_p, SRC_CAM1, 20, 1),
457 MUX(CLK_MOUT_PXLASYNC_CSIS0_FIMC, "mout_pxlasync_csis0",
458 group_fimc_lclk_p, SRC_CAM1, 16, 1),
459 MUX(CLK_MOUT_JPEG, "mout_jpeg", mout_jpeg_p, SRC_CAM1, 8, 1),
460 MUX(CLK_MOUT_JPEG1, "mout_jpeg_1", mout_jpeg1_p, SRC_CAM1, 4, 1),
461 MUX(CLK_MOUT_JPEG0, "mout_jpeg_0", group_mout_mpll_user_t_p, SRC_CAM1,
462 0, 1),
463
464 /* SRC_TOP_ISP0 */
465 MUX(CLK_MOUT_ACLK_ISP0_300, "mout_aclk_isp0_300",
466 group_aclk_isp0_300_p, SRC_TOP_ISP0, 8, 1),
467 MUX(CLK_MOUT_ACLK_ISP0_400, "mout_aclk_isp0_400_user",
468 group_aclk_isp0_400_user_p, SRC_TOP_ISP0, 4, 1),
469 MUX(CLK_MOUT_ACLK_ISP0_300_USER, "mout_aclk_isp0_300_user",
470 group_aclk_isp0_300_user_p, SRC_TOP_ISP0, 0, 1),
471
472 /* SRC_TOP_ISP1 */
473 MUX(CLK_MOUT_ACLK_ISP1_300, "mout_aclk_isp1_300",
474 group_aclk_isp0_300_p, SRC_TOP_ISP1, 4, 1),
475 MUX(CLK_MOUT_ACLK_ISP1_300_USER, "mout_aclk_isp1_300_user",
476 group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
477};
478
479static struct samsung_div_clock exynos4415_div_clks[] __initdata = {
480 /*
481 * NOTE: Following table is sorted by register address in ascending
482 * order and then bitfield shift in descending order, as it is done
483 * in the User's Manual. When adding new entries, please make sure
484 * that the order is preserved, to avoid merge conflicts and make
485 * further work with defined data easier.
486 */
487
488 /* DIV_LEFTBUS */
489 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
490 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
491
492 /* DIV_RIGHTBUS */
493 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
494 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
495
496 /* DIV_TOP */
497 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
498 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
499 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
500 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
501 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
502 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
503 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
504
505 /* DIV_CAM */
506 DIV(CLK_DIV_CSIS1, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
507 DIV(CLK_DIV_CSIS0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
508 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
509 DIV(CLK_DIV_FIMC3_LCLK, "div_fimc3_lclk", "mout_fimc3_lclk", DIV_CAM,
510 12, 4),
511 DIV(CLK_DIV_FIMC2_LCLK, "div_fimc2_lclk", "mout_fimc2_lclk", DIV_CAM,
512 8, 4),
513 DIV(CLK_DIV_FIMC1_LCLK, "div_fimc1_lclk", "mout_fimc1_lclk", DIV_CAM,
514 4, 4),
515 DIV(CLK_DIV_FIMC0_LCLK, "div_fimc0_lclk", "mout_fimc0_lclk", DIV_CAM,
516 0, 4),
517
518 /* DIV_TV */
519 DIV(CLK_DIV_TV_BLK, "div_tv_blk", "mout_g3d_pll", DIV_TV, 0, 4),
520
521 /* DIV_MFC */
522 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
523
524 /* DIV_G3D */
525 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
526
527 /* DIV_LCD */
528 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
529 CLK_SET_RATE_PARENT, 0),
530 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
531 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
532
533 /* DIV_ISP */
534 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
535 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
536 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
537 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
538 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
539 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
540 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
541 DIV(CLK_DIV_PWM_ISP, "div_pwm_isp", "mout_pwm_isp", DIV_ISP, 0, 4),
542
543 /* DIV_MAUDIO */
544 DIV(CLK_DIV_PCM0, "div_pcm0", "div_audio0", DIV_MAUDIO, 4, 8),
545 DIV(CLK_DIV_AUDIO0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
546
547 /* DIV_FSYS0 */
548 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
549 CLK_SET_RATE_PARENT, 0),
550 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
551
552 /* DIV_FSYS1 */
553 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
554 CLK_SET_RATE_PARENT, 0),
555 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
556 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
557 CLK_SET_RATE_PARENT, 0),
558 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
559
560 /* DIV_FSYS2 */
561 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
562 CLK_SET_RATE_PARENT, 0),
563 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4,
564 CLK_SET_RATE_PARENT, 0),
565
566 /* DIV_PERIL0 */
567 DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
568 DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
569 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
570 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
571
572 /* DIV_PERIL1 */
573 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
574 CLK_SET_RATE_PARENT, 0),
575 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
576 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
577 CLK_SET_RATE_PARENT, 0),
578 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
579
580 /* DIV_PERIL2 */
581 DIV_F(CLK_DIV_SPI2_PRE, "div_spi2_pre", "div_spi2", DIV_PERIL2, 8, 8,
582 CLK_SET_RATE_PARENT, 0),
583 DIV(CLK_DIV_SPI2, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
584
585 /* DIV_PERIL4 */
586 DIV(CLK_DIV_PCM2, "div_pcm2", "div_audio2", DIV_PERIL4, 20, 8),
587 DIV(CLK_DIV_AUDIO2, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
588 DIV(CLK_DIV_PCM1, "div_pcm1", "div_audio1", DIV_PERIL4, 20, 8),
589 DIV(CLK_DIV_AUDIO1, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
590
591 /* DIV_PERIL5 */
592 DIV(CLK_DIV_I2S1, "div_i2s1", "div_audio1", DIV_PERIL5, 0, 6),
593
594 /* DIV_CAM1 */
595 DIV(CLK_DIV_PXLASYNC_CSIS1_FIMC, "div_pxlasync_csis1_fimc",
596 "mout_pxlasync_csis1", DIV_CAM1, 24, 4),
597 DIV(CLK_DIV_PXLASYNC_CSIS0_FIMC, "div_pxlasync_csis0_fimc",
598 "mout_pxlasync_csis0", DIV_CAM1, 20, 4),
599 DIV(CLK_DIV_JPEG, "div_jpeg", "mout_jpeg", DIV_CAM1, 0, 4),
600
601 /* DIV_CPU0 */
602 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
603 DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
604 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
605 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
606 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
607 DIV(CLK_DIV_PERIPH, "div_periph", "div_core2", DIV_CPU0, 12, 3),
608 DIV(CLK_DIV_COREM1, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
609 DIV(CLK_DIV_COREM0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
610 DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
611 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
612
613 /* DIV_CPU1 */
614 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
615 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
616};
617
618static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = {
619 /*
620 * NOTE: Following table is sorted by register address in ascending
621 * order and then bitfield shift in descending order, as it is done
622 * in the User's Manual. When adding new entries, please make sure
623 * that the order is preserved, to avoid merge conflicts and make
624 * further work with defined data easier.
625 */
626
627 /* GATE_IP_LEFTBUS */
628 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
629 CLK_IGNORE_UNUSED, 0),
630 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
631 CLK_IGNORE_UNUSED, 0),
632 GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
633 CLK_IGNORE_UNUSED, 0),
634 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
635 CLK_IGNORE_UNUSED, 0),
636 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
637 CLK_IGNORE_UNUSED, 0),
638
639 /* GATE_IP_IMAGE */
640 GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
641 9, 0, 0),
642 GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
643 8, 0, 0),
644 GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
645 7, 0, 0),
646 GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
647 5, 0, 0),
648 GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
649 4, 0, 0),
650 GATE(CLK_MDMA2, "mdma2", "div_aclk_100", GATE_IP_IMAGE, 2, 0, 0),
651 GATE(CLK_ROTATOR, "rotator", "div_aclk_100", GATE_IP_IMAGE, 1, 0, 0),
652
653 /* GATE_IP_RIGHTBUS */
654 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
655 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
656 GATE(CLK_ASYNC_MAUDIOX, "async_maudiox", "div_aclk_100",
657 GATE_IP_RIGHTBUS, 7, CLK_IGNORE_UNUSED, 0),
658 GATE(CLK_ASYNC_MFCR, "async_mfcr", "div_aclk_100",
659 GATE_IP_RIGHTBUS, 6, CLK_IGNORE_UNUSED, 0),
660 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
661 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
662 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
663 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
664 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100",
665 GATE_IP_RIGHTBUS, 2, CLK_IGNORE_UNUSED, 0),
666 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
667 GATE_IP_RIGHTBUS, 1, CLK_IGNORE_UNUSED, 0),
668 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100",
669 GATE_IP_RIGHTBUS, 0, CLK_IGNORE_UNUSED, 0),
670
671 /* GATE_IP_PERIR */
672 GATE(CLK_ANTIRBK_APBIF, "antirbk_apbif", "div_aclk_100",
673 GATE_IP_PERIR, 24, CLK_IGNORE_UNUSED, 0),
674 GATE(CLK_EFUSE_WRITER_APBIF, "efuse_writer_apbif", "div_aclk_100",
675 GATE_IP_PERIR, 23, CLK_IGNORE_UNUSED, 0),
676 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
677 CLK_IGNORE_UNUSED, 0),
678 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
679 CLK_IGNORE_UNUSED, 0),
680 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
681 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
682 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
683 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
684 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
685 CLK_IGNORE_UNUSED, 0),
686 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
687 GATE_IP_PERIR, 17, 0, 0),
688 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
689 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
690 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
691 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
692 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
693 CLK_IGNORE_UNUSED, 0),
694 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk_100", GATE_IP_PERIR, 11,
695 CLK_IGNORE_UNUSED, 0),
696 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
697 CLK_IGNORE_UNUSED, 0),
698 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
699 CLK_IGNORE_UNUSED, 0),
700 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
701 CLK_IGNORE_UNUSED, 0),
702 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
703 CLK_IGNORE_UNUSED, 0),
704 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
705 CLK_IGNORE_UNUSED, 0),
706 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
707 CLK_IGNORE_UNUSED, 0),
708 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
709 CLK_IGNORE_UNUSED, 0),
710 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
711 CLK_IGNORE_UNUSED, 0),
712 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
713 CLK_IGNORE_UNUSED, 0),
714 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
715 CLK_IGNORE_UNUSED, 0),
716 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
717 CLK_IGNORE_UNUSED, 0),
718
719 /* GATE_SCLK_CAM - non-completed */
720 GATE(CLK_SCLK_PXLAYSNC_CSIS1_FIMC, "sclk_pxlasync_csis1_fimc",
721 "div_pxlasync_csis1_fimc", GATE_SCLK_CAM, 11,
722 CLK_SET_RATE_PARENT, 0),
723 GATE(CLK_SCLK_PXLAYSNC_CSIS0_FIMC, "sclk_pxlasync_csis0_fimc",
724 "div_pxlasync_csis0_fimc", GATE_SCLK_CAM,
725 10, CLK_SET_RATE_PARENT, 0),
726 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
727 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
728 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1",
729 GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
730 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0",
731 GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
732 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
733 GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
734 GATE(CLK_SCLK_FIMC3_LCLK, "sclk_fimc3_lclk", "div_fimc3_lclk",
735 GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
736 GATE(CLK_SCLK_FIMC2_LCLK, "sclk_fimc2_lclk", "div_fimc2_lclk",
737 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
738 GATE(CLK_SCLK_FIMC1_LCLK, "sclk_fimc1_lclk", "div_fimc1_lclk",
739 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
740 GATE(CLK_SCLK_FIMC0_LCLK, "sclk_fimc0_lclk", "div_fimc0_lclk",
741 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
742
743 /* GATE_SCLK_TV */
744 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "div_tv_blk",
745 GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
746 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
747 GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
748 GATE(CLK_SCLK_MIXER, "sclk_mixer", "div_tv_blk",
749 GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
750
751 /* GATE_SCLK_MFC */
752 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
753 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
754
755 /* GATE_SCLK_G3D */
756 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
757 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
758
759 /* GATE_SCLK_LCD */
760 GATE(CLK_SCLK_MIPIDPHY4L, "sclk_mipidphy4l", "div_mipi0",
761 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
762 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
763 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
764 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_fimd0",
765 GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
766 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
767 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
768
769 /* GATE_SCLK_MAUDIO */
770 GATE(CLK_SCLK_PCM0, "sclk_pcm0", "div_pcm0",
771 GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
772 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
773 GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
774
775 /* GATE_SCLK_FSYS */
776 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
777 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
778 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
779 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
780 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
781 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
782 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
783 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
784 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
785 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
786
787 /* GATE_SCLK_PERIL */
788 GATE(CLK_SCLK_I2S, "sclk_i2s1", "div_i2s1",
789 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
790 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "div_pcm2",
791 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
792 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "div_pcm1",
793 GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
794 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
795 GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
796 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
797 GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
798 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
799 GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
800 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi2_pre",
801 GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
802 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
803 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
804 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
805 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
806 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
807 GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
808 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
809 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
810 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
811 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
812 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
813 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
814
815 /* GATE_IP_CAM */
816 GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
817 22, CLK_IGNORE_UNUSED, 0),
818 GATE(CLK_FIMC_LITE2, "fimc_lite2", "div_aclk_160", GATE_IP_CAM,
819 20, CLK_IGNORE_UNUSED, 0),
820 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_aclk_160", GATE_IP_CAM,
821 18, CLK_IGNORE_UNUSED, 0),
822 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
823 17, CLK_IGNORE_UNUSED, 0),
824 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_aclk_160", GATE_IP_CAM,
825 16, CLK_IGNORE_UNUSED, 0),
826 GATE(CLK_SMMUJPEG, "smmujpeg", "div_aclk_160", GATE_IP_CAM, 11, 0, 0),
827 GATE(CLK_SMMUFIMC3, "smmufimc3", "div_aclk_160", GATE_IP_CAM, 10, 0, 0),
828 GATE(CLK_SMMUFIMC2, "smmufimc2", "div_aclk_160", GATE_IP_CAM, 9, 0, 0),
829 GATE(CLK_SMMUFIMC1, "smmufimc1", "div_aclk_160", GATE_IP_CAM, 8, 0, 0),
830 GATE(CLK_SMMUFIMC0, "smmufimc0", "div_aclk_160", GATE_IP_CAM, 7, 0, 0),
831 GATE(CLK_JPEG, "jpeg", "div_aclk_160", GATE_IP_CAM, 6, 0, 0),
832 GATE(CLK_CSIS1, "csis1", "div_aclk_160", GATE_IP_CAM, 5, 0, 0),
833 GATE(CLK_CSIS0, "csis0", "div_aclk_160", GATE_IP_CAM, 4, 0, 0),
834 GATE(CLK_FIMC3, "fimc3", "div_aclk_160", GATE_IP_CAM, 3, 0, 0),
835 GATE(CLK_FIMC2, "fimc2", "div_aclk_160", GATE_IP_CAM, 2, 0, 0),
836 GATE(CLK_FIMC1, "fimc1", "div_aclk_160", GATE_IP_CAM, 1, 0, 0),
837 GATE(CLK_FIMC0, "fimc0", "div_aclk_160", GATE_IP_CAM, 0, 0, 0),
838
839 /* GATE_IP_TV */
840 GATE(CLK_PPMUTV, "ppmutv", "div_aclk_100", GATE_IP_TV, 5, 0, 0),
841 GATE(CLK_SMMUTV, "smmutv", "div_aclk_100", GATE_IP_TV, 4, 0, 0),
842 GATE(CLK_HDMI, "hdmi", "div_aclk_100", GATE_IP_TV, 3, 0, 0),
843 GATE(CLK_MIXER, "mixer", "div_aclk_100", GATE_IP_TV, 1, 0, 0),
844 GATE(CLK_VP, "vp", "div_aclk_100", GATE_IP_TV, 0, 0, 0),
845
846 /* GATE_IP_MFC */
847 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "div_aclk_200", GATE_IP_MFC, 4,
848 CLK_IGNORE_UNUSED, 0),
849 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
850 CLK_IGNORE_UNUSED, 0),
851 GATE(CLK_SMMUMFC_R, "smmumfc_r", "div_aclk_200", GATE_IP_MFC, 2, 0, 0),
852 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
853 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
854
855 /* GATE_IP_G3D */
856 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
857 CLK_IGNORE_UNUSED, 0),
858 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
859
860 /* GATE_IP_LCD */
861 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
862 CLK_IGNORE_UNUSED, 0),
863 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
864 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
865 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
866 GATE(CLK_MIE0, "mie0", "div_aclk_160", GATE_IP_LCD, 1, 0, 0),
867 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
868
869 /* GATE_IP_FSYS */
870 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
871 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
872 CLK_IGNORE_UNUSED, 0),
873 GATE(CLK_NFCON, "nfcon", "div_aclk_200", GATE_IP_FSYS, 16, 0, 0),
874 GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13,
875 0, 0),
876 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
877 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
878 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
879 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
880 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
881 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
882 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
883
884 /* GATE_IP_PERIL */
885 GATE(CLK_SPDIF, "spdif", "div_aclk_100", GATE_IP_PERIL, 26, 0, 0),
886 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
887 GATE(CLK_PCM2, "pcm2", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
888 GATE(CLK_PCM1, "pcm1", "div_aclk_100", GATE_IP_PERIL, 22, 0, 0),
889 GATE(CLK_I2S1, "i2s1", "div_aclk_100", GATE_IP_PERIL, 20, 0, 0),
890 GATE(CLK_SPI2, "spi2", "div_aclk_100", GATE_IP_PERIL, 18, 0, 0),
891 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
892 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
893 GATE(CLK_I2CHDMI, "i2chdmi", "div_aclk_100", GATE_IP_PERIL, 14, 0, 0),
894 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
895 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
896 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
897 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
898 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
899 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
900 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
901 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
902 GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
903 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
904 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
905 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
906};
907
908/*
909 * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
910 */
911static struct samsung_pll_rate_table exynos4415_pll_rates[] = {
912 PLL_35XX_RATE(1600000000, 400, 3, 1),
913 PLL_35XX_RATE(1500000000, 250, 2, 1),
914 PLL_35XX_RATE(1400000000, 175, 3, 0),
915 PLL_35XX_RATE(1300000000, 325, 3, 1),
916 PLL_35XX_RATE(1200000000, 400, 4, 1),
917 PLL_35XX_RATE(1100000000, 275, 3, 1),
918 PLL_35XX_RATE(1066000000, 533, 6, 1),
919 PLL_35XX_RATE(1000000000, 250, 3, 1),
920 PLL_35XX_RATE(960000000, 320, 4, 1),
921 PLL_35XX_RATE(900000000, 300, 4, 1),
922 PLL_35XX_RATE(850000000, 425, 6, 1),
923 PLL_35XX_RATE(800000000, 200, 3, 1),
924 PLL_35XX_RATE(700000000, 175, 3, 1),
925 PLL_35XX_RATE(667000000, 667, 12, 1),
926 PLL_35XX_RATE(600000000, 400, 4, 2),
927 PLL_35XX_RATE(550000000, 275, 3, 2),
928 PLL_35XX_RATE(533000000, 533, 6, 2),
929 PLL_35XX_RATE(520000000, 260, 3, 2),
930 PLL_35XX_RATE(500000000, 250, 3, 2),
931 PLL_35XX_RATE(440000000, 220, 3, 2),
932 PLL_35XX_RATE(400000000, 200, 3, 2),
933 PLL_35XX_RATE(350000000, 175, 3, 2),
934 PLL_35XX_RATE(300000000, 300, 3, 3),
935 PLL_35XX_RATE(266000000, 266, 3, 3),
936 PLL_35XX_RATE(200000000, 200, 3, 3),
937 PLL_35XX_RATE(160000000, 160, 3, 3),
938 PLL_35XX_RATE(100000000, 200, 3, 4),
939 { /* sentinel */ }
940};
941
942/* EPLL */
943static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
944 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
945 PLL_36XX_RATE(288000000, 96, 2, 2, 0),
946 PLL_36XX_RATE(192000000, 128, 2, 3, 0),
947 PLL_36XX_RATE(144000000, 96, 2, 3, 0),
948 PLL_36XX_RATE(96000000, 128, 2, 4, 0),
949 PLL_36XX_RATE(84000000, 112, 2, 4, 0),
950 PLL_36XX_RATE(80750011, 107, 2, 4, 43691),
951 PLL_36XX_RATE(73728004, 98, 2, 4, 19923),
952 PLL_36XX_RATE(67987602, 271, 3, 5, 62285),
953 PLL_36XX_RATE(65911004, 175, 2, 5, 49982),
954 PLL_36XX_RATE(50000000, 200, 3, 5, 0),
955 PLL_36XX_RATE(49152003, 131, 2, 5, 4719),
956 PLL_36XX_RATE(48000000, 128, 2, 5, 0),
957 PLL_36XX_RATE(45250000, 181, 3, 5, 0),
958 { /* sentinel */ }
959};
960
961static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = {
962 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
963 APLL_LOCK, APLL_CON0, NULL),
964 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
965 EPLL_LOCK, EPLL_CON0, NULL),
966 [g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll",
967 "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL),
968 [isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
969 ISP_PLL_LOCK, ISP_PLL_CON0, NULL),
970 [disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
971 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL),
972};
973
974static void __init exynos4415_cmu_init(struct device_node *np)
975{
976 void __iomem *reg_base;
977
978 reg_base = of_iomap(np, 0);
979 if (!reg_base)
980 panic("%s: failed to map registers\n", __func__);
981
982 exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
983 if (!exynos4415_ctx)
984 panic("%s: unable to allocate context.\n", __func__);
985
986 exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
987 exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
988 exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
989 exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
990 exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
991
992 samsung_clk_register_fixed_factor(exynos4415_ctx,
993 exynos4415_fixed_factor_clks,
994 ARRAY_SIZE(exynos4415_fixed_factor_clks));
995 samsung_clk_register_fixed_rate(exynos4415_ctx,
996 exynos4415_fixed_rate_clks,
997 ARRAY_SIZE(exynos4415_fixed_rate_clks));
998
999 samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
1000 ARRAY_SIZE(exynos4415_plls), reg_base);
1001 samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
1002 ARRAY_SIZE(exynos4415_mux_clks));
1003 samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
1004 ARRAY_SIZE(exynos4415_div_clks));
1005 samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
1006 ARRAY_SIZE(exynos4415_gate_clks));
1007
1008 exynos4415_clk_sleep_init();
1009
1010 samsung_clk_of_add_provider(np, exynos4415_ctx);
1011}
1012CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
1013
1014/*
1015 * CMU DMC
1016 */
1017
1018#define MPLL_LOCK 0x008
1019#define MPLL_CON0 0x108
1020#define MPLL_CON1 0x10c
1021#define MPLL_CON2 0x110
1022#define BPLL_LOCK 0x118
1023#define BPLL_CON0 0x218
1024#define BPLL_CON1 0x21c
1025#define BPLL_CON2 0x220
1026#define SRC_DMC 0x300
1027#define DIV_DMC1 0x504
1028
1029enum exynos4415_dmc_plls {
1030 mpll, bpll,
1031 nr_dmc_plls,
1032};
1033
1034#ifdef CONFIG_PM_SLEEP
1035static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
1036static struct samsung_clk_provider *exynos4415_dmc_ctx;
1037
1038static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
1039 MPLL_LOCK,
1040 MPLL_CON0,
1041 MPLL_CON1,
1042 MPLL_CON2,
1043 BPLL_LOCK,
1044 BPLL_CON0,
1045 BPLL_CON1,
1046 BPLL_CON2,
1047 SRC_DMC,
1048 DIV_DMC1,
1049};
1050
1051static int exynos4415_dmc_clk_suspend(void)
1052{
1053 samsung_clk_save(exynos4415_dmc_ctx->reg_base,
1054 exynos4415_dmc_clk_regs,
1055 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1056 return 0;
1057}
1058
1059static void exynos4415_dmc_clk_resume(void)
1060{
1061 samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
1062 exynos4415_dmc_clk_regs,
1063 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1064}
1065
1066static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
1067 .suspend = exynos4415_dmc_clk_suspend,
1068 .resume = exynos4415_dmc_clk_resume,
1069};
1070
1071static void exynos4415_dmc_clk_sleep_init(void)
1072{
1073 exynos4415_dmc_clk_regs =
1074 samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
1075 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1076 if (!exynos4415_dmc_clk_regs) {
1077 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
1078 return;
1079 }
1080
1081 register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
1082}
1083#else
1084static inline void exynos4415_dmc_clk_sleep_init(void) { }
1085#endif /* CONFIG_PM_SLEEP */
1086
1087PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
1088PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
1089PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
1090
1091static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = {
1092 MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
1093 MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
1094 MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
1095 MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
1096};
1097
1098static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
1099 DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
1100 DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
1101 DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
1102 DIV_DMC1, 19, 2),
1103 DIV(CLK_DMC_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
1104 DIV(CLK_DMC_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
1105 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
1106};
1107
1108static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = {
1109 [mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
1110 MPLL_LOCK, MPLL_CON0, NULL),
1111 [bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
1112 BPLL_LOCK, BPLL_CON0, NULL),
1113};
1114
1115static void __init exynos4415_cmu_dmc_init(struct device_node *np)
1116{
1117 void __iomem *reg_base;
1118
1119 reg_base = of_iomap(np, 0);
1120 if (!reg_base)
1121 panic("%s: failed to map registers\n", __func__);
1122
1123 exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
1124 if (!exynos4415_dmc_ctx)
1125 panic("%s: unable to allocate context.\n", __func__);
1126
1127 exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
1128 exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
1129
1130 samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
1131 ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
1132 samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
1133 ARRAY_SIZE(exynos4415_dmc_mux_clks));
1134 samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
1135 ARRAY_SIZE(exynos4415_dmc_div_clks));
1136
1137 exynos4415_dmc_clk_sleep_init();
1138
1139 samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
1140}
1141CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
1142 exynos4415_cmu_dmc_init);
diff --git a/include/dt-bindings/clock/exynos4415.h b/include/dt-bindings/clock/exynos4415.h
new file mode 100644
index 000000000000..7eed55100721
--- /dev/null
+++ b/include/dt-bindings/clock/exynos4415.h
@@ -0,0 +1,360 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Samsung Exynos4415 clock controllers.
10 */
11
12#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
13#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
14
15/*
16 * Let each exported clock get a unique index, which is used on DT-enabled
17 * platforms to lookup the clock from a clock specifier. These indices are
18 * therefore considered an ABI and so must not be changed. This implies
19 * that new clocks should be added either in free spaces between clock groups
20 * or at the end.
21 */
22
23/*
24 * Main CMU
25 */
26
27#define CLK_OSCSEL 1
28#define CLK_FIN_PLL 2
29#define CLK_FOUT_APLL 3
30#define CLK_FOUT_MPLL 4
31#define CLK_FOUT_EPLL 5
32#define CLK_FOUT_G3D_PLL 6
33#define CLK_FOUT_ISP_PLL 7
34#define CLK_FOUT_DISP_PLL 8
35
36/* Muxes */
37#define CLK_MOUT_MPLL_USER_L 16
38#define CLK_MOUT_GDL 17
39#define CLK_MOUT_MPLL_USER_R 18
40#define CLK_MOUT_GDR 19
41#define CLK_MOUT_EBI 20
42#define CLK_MOUT_ACLK_200 21
43#define CLK_MOUT_ACLK_160 22
44#define CLK_MOUT_ACLK_100 23
45#define CLK_MOUT_ACLK_266 24
46#define CLK_MOUT_G3D_PLL 25
47#define CLK_MOUT_EPLL 26
48#define CLK_MOUT_EBI_1 27
49#define CLK_MOUT_ISP_PLL 28
50#define CLK_MOUT_DISP_PLL 29
51#define CLK_MOUT_MPLL_USER_T 30
52#define CLK_MOUT_ACLK_400_MCUISP 31
53#define CLK_MOUT_G3D_PLLSRC 32
54#define CLK_MOUT_CSIS1 33
55#define CLK_MOUT_CSIS0 34
56#define CLK_MOUT_CAM1 35
57#define CLK_MOUT_FIMC3_LCLK 36
58#define CLK_MOUT_FIMC2_LCLK 37
59#define CLK_MOUT_FIMC1_LCLK 38
60#define CLK_MOUT_FIMC0_LCLK 39
61#define CLK_MOUT_MFC 40
62#define CLK_MOUT_MFC_1 41
63#define CLK_MOUT_MFC_0 42
64#define CLK_MOUT_G3D 43
65#define CLK_MOUT_G3D_1 44
66#define CLK_MOUT_G3D_0 45
67#define CLK_MOUT_MIPI0 46
68#define CLK_MOUT_FIMD0 47
69#define CLK_MOUT_TSADC_ISP 48
70#define CLK_MOUT_UART_ISP 49
71#define CLK_MOUT_SPI1_ISP 50
72#define CLK_MOUT_SPI0_ISP 51
73#define CLK_MOUT_PWM_ISP 52
74#define CLK_MOUT_AUDIO0 53
75#define CLK_MOUT_TSADC 54
76#define CLK_MOUT_MMC2 55
77#define CLK_MOUT_MMC1 56
78#define CLK_MOUT_MMC0 57
79#define CLK_MOUT_UART3 58
80#define CLK_MOUT_UART2 59
81#define CLK_MOUT_UART1 60
82#define CLK_MOUT_UART0 61
83#define CLK_MOUT_SPI2 62
84#define CLK_MOUT_SPI1 63
85#define CLK_MOUT_SPI0 64
86#define CLK_MOUT_SPDIF 65
87#define CLK_MOUT_AUDIO2 66
88#define CLK_MOUT_AUDIO1 67
89#define CLK_MOUT_MPLL_USER_C 68
90#define CLK_MOUT_HPM 69
91#define CLK_MOUT_CORE 70
92#define CLK_MOUT_APLL 71
93#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72
94#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73
95#define CLK_MOUT_JPEG 74
96#define CLK_MOUT_JPEG1 75
97#define CLK_MOUT_JPEG0 76
98#define CLK_MOUT_ACLK_ISP0_300 77
99#define CLK_MOUT_ACLK_ISP0_400 78
100#define CLK_MOUT_ACLK_ISP0_300_USER 79
101#define CLK_MOUT_ACLK_ISP1_300 80
102#define CLK_MOUT_ACLK_ISP1_300_USER 81
103#define CLK_MOUT_HDMI 82
104
105/* Dividers */
106#define CLK_DIV_GPL 90
107#define CLK_DIV_GDL 91
108#define CLK_DIV_GPR 92
109#define CLK_DIV_GDR 93
110#define CLK_DIV_ACLK_400_MCUISP 94
111#define CLK_DIV_EBI 95
112#define CLK_DIV_ACLK_200 96
113#define CLK_DIV_ACLK_160 97
114#define CLK_DIV_ACLK_100 98
115#define CLK_DIV_ACLK_266 99
116#define CLK_DIV_CSIS1 100
117#define CLK_DIV_CSIS0 101
118#define CLK_DIV_CAM1 102
119#define CLK_DIV_FIMC3_LCLK 103
120#define CLK_DIV_FIMC2_LCLK 104
121#define CLK_DIV_FIMC1_LCLK 105
122#define CLK_DIV_FIMC0_LCLK 106
123#define CLK_DIV_TV_BLK 107
124#define CLK_DIV_MFC 108
125#define CLK_DIV_G3D 109
126#define CLK_DIV_MIPI0_PRE 110
127#define CLK_DIV_MIPI0 111
128#define CLK_DIV_FIMD0 112
129#define CLK_DIV_UART_ISP 113
130#define CLK_DIV_SPI1_ISP_PRE 114
131#define CLK_DIV_SPI1_ISP 115
132#define CLK_DIV_SPI0_ISP_PRE 116
133#define CLK_DIV_SPI0_ISP 117
134#define CLK_DIV_PWM_ISP 118
135#define CLK_DIV_PCM0 119
136#define CLK_DIV_AUDIO0 120
137#define CLK_DIV_TSADC_PRE 121
138#define CLK_DIV_TSADC 122
139#define CLK_DIV_MMC1_PRE 123
140#define CLK_DIV_MMC1 124
141#define CLK_DIV_MMC0_PRE 125
142#define CLK_DIV_MMC0 126
143#define CLK_DIV_MMC2_PRE 127
144#define CLK_DIV_MMC2 128
145#define CLK_DIV_UART3 129
146#define CLK_DIV_UART2 130
147#define CLK_DIV_UART1 131
148#define CLK_DIV_UART0 132
149#define CLK_DIV_SPI1_PRE 133
150#define CLK_DIV_SPI1 134
151#define CLK_DIV_SPI0_PRE 135
152#define CLK_DIV_SPI0 136
153#define CLK_DIV_SPI2_PRE 137
154#define CLK_DIV_SPI2 138
155#define CLK_DIV_PCM2 139
156#define CLK_DIV_AUDIO2 140
157#define CLK_DIV_PCM1 141
158#define CLK_DIV_AUDIO1 142
159#define CLK_DIV_I2S1 143
160#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144
161#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145
162#define CLK_DIV_JPEG 146
163#define CLK_DIV_CORE2 147
164#define CLK_DIV_APLL 148
165#define CLK_DIV_PCLK_DBG 149
166#define CLK_DIV_ATB 150
167#define CLK_DIV_PERIPH 151
168#define CLK_DIV_COREM1 152
169#define CLK_DIV_COREM0 153
170#define CLK_DIV_CORE 154
171#define CLK_DIV_HPM 155
172#define CLK_DIV_COPY 156
173
174/* Gates */
175#define CLK_ASYNC_G3D 180
176#define CLK_ASYNC_MFCL 181
177#define CLK_ASYNC_TVX 182
178#define CLK_PPMULEFT 183
179#define CLK_GPIO_LEFT 184
180#define CLK_PPMUIMAGE 185
181#define CLK_QEMDMA2 186
182#define CLK_QEROTATOR 187
183#define CLK_SMMUMDMA2 188
184#define CLK_SMMUROTATOR 189
185#define CLK_MDMA2 190
186#define CLK_ROTATOR 191
187#define CLK_ASYNC_ISPMX 192
188#define CLK_ASYNC_MAUDIOX 193
189#define CLK_ASYNC_MFCR 194
190#define CLK_ASYNC_FSYSD 195
191#define CLK_ASYNC_LCD0X 196
192#define CLK_ASYNC_CAMX 197
193#define CLK_PPMURIGHT 198
194#define CLK_GPIO_RIGHT 199
195#define CLK_ANTIRBK_APBIF 200
196#define CLK_EFUSE_WRITER_APBIF 201
197#define CLK_MONOCNT 202
198#define CLK_TZPC6 203
199#define CLK_PROVISIONKEY1 204
200#define CLK_PROVISIONKEY0 205
201#define CLK_CMU_ISPPART 206
202#define CLK_TMU_APBIF 207
203#define CLK_KEYIF 208
204#define CLK_RTC 209
205#define CLK_WDT 210
206#define CLK_MCT 211
207#define CLK_SECKEY 212
208#define CLK_HDMI_CEC 213
209#define CLK_TZPC5 214
210#define CLK_TZPC4 215
211#define CLK_TZPC3 216
212#define CLK_TZPC2 217
213#define CLK_TZPC1 218
214#define CLK_TZPC0 219
215#define CLK_CMU_COREPART 220
216#define CLK_CMU_TOPPART 221
217#define CLK_PMU_APBIF 222
218#define CLK_SYSREG 223
219#define CLK_CHIP_ID 224
220#define CLK_SMMUFIMC_LITE2 225
221#define CLK_FIMC_LITE2 226
222#define CLK_PIXELASYNCM1 227
223#define CLK_PIXELASYNCM0 228
224#define CLK_PPMUCAMIF 229
225#define CLK_SMMUJPEG 230
226#define CLK_SMMUFIMC3 231
227#define CLK_SMMUFIMC2 232
228#define CLK_SMMUFIMC1 233
229#define CLK_SMMUFIMC0 234
230#define CLK_JPEG 235
231#define CLK_CSIS1 236
232#define CLK_CSIS0 237
233#define CLK_FIMC3 238
234#define CLK_FIMC2 239
235#define CLK_FIMC1 240
236#define CLK_FIMC0 241
237#define CLK_PPMUTV 242
238#define CLK_SMMUTV 243
239#define CLK_HDMI 244
240#define CLK_MIXER 245
241#define CLK_VP 246
242#define CLK_PPMUMFC_R 247
243#define CLK_PPMUMFC_L 248
244#define CLK_SMMUMFC_R 249
245#define CLK_SMMUMFC_L 250
246#define CLK_MFC 251
247#define CLK_PPMUG3D 252
248#define CLK_G3D 253
249#define CLK_PPMULCD0 254
250#define CLK_SMMUFIMD0 255
251#define CLK_DSIM0 256
252#define CLK_SMIES 257
253#define CLK_MIE0 258
254#define CLK_FIMD0 259
255#define CLK_TSADC 260
256#define CLK_PPMUFILE 261
257#define CLK_NFCON 262
258#define CLK_USBDEVICE 263
259#define CLK_USBHOST 264
260#define CLK_SROMC 265
261#define CLK_SDMMC2 266
262#define CLK_SDMMC1 267
263#define CLK_SDMMC0 268
264#define CLK_PDMA1 269
265#define CLK_PDMA0 270
266#define CLK_SPDIF 271
267#define CLK_PWM 272
268#define CLK_PCM2 273
269#define CLK_PCM1 274
270#define CLK_I2S1 275
271#define CLK_SPI2 276
272#define CLK_SPI1 277
273#define CLK_SPI0 278
274#define CLK_I2CHDMI 279
275#define CLK_I2C7 280
276#define CLK_I2C6 281
277#define CLK_I2C5 282
278#define CLK_I2C4 283
279#define CLK_I2C3 284
280#define CLK_I2C2 285
281#define CLK_I2C1 286
282#define CLK_I2C0 287
283#define CLK_UART3 288
284#define CLK_UART2 289
285#define CLK_UART1 290
286#define CLK_UART0 291
287
288/* Special clocks */
289#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330
290#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331
291#define CLK_SCLK_JPEG 332
292#define CLK_SCLK_CSIS1 333
293#define CLK_SCLK_CSIS0 334
294#define CLK_SCLK_CAM1 335
295#define CLK_SCLK_FIMC3_LCLK 336
296#define CLK_SCLK_FIMC2_LCLK 337
297#define CLK_SCLK_FIMC1_LCLK 338
298#define CLK_SCLK_FIMC0_LCLK 339
299#define CLK_SCLK_PIXEL 340
300#define CLK_SCLK_HDMI 341
301#define CLK_SCLK_MIXER 342
302#define CLK_SCLK_MFC 343
303#define CLK_SCLK_G3D 344
304#define CLK_SCLK_MIPIDPHY4L 345
305#define CLK_SCLK_MIPI0 346
306#define CLK_SCLK_MDNIE0 347
307#define CLK_SCLK_FIMD0 348
308#define CLK_SCLK_PCM0 349
309#define CLK_SCLK_AUDIO0 350
310#define CLK_SCLK_TSADC 351
311#define CLK_SCLK_EBI 352
312#define CLK_SCLK_MMC2 353
313#define CLK_SCLK_MMC1 354
314#define CLK_SCLK_MMC0 355
315#define CLK_SCLK_I2S 356
316#define CLK_SCLK_PCM2 357
317#define CLK_SCLK_PCM1 358
318#define CLK_SCLK_AUDIO2 359
319#define CLK_SCLK_AUDIO1 360
320#define CLK_SCLK_SPDIF 361
321#define CLK_SCLK_SPI2 362
322#define CLK_SCLK_SPI1 363
323#define CLK_SCLK_SPI0 364
324#define CLK_SCLK_UART3 365
325#define CLK_SCLK_UART2 366
326#define CLK_SCLK_UART1 367
327#define CLK_SCLK_UART0 368
328#define CLK_SCLK_HDMIPHY 369
329
330/*
331 * Total number of clocks of main CMU.
332 * NOTE: Must be equal to last clock ID increased by one.
333 */
334#define CLK_NR_CLKS 370
335
336/*
337 * CMU DMC
338 */
339#define CLK_DMC_FOUT_MPLL 1
340#define CLK_DMC_FOUT_BPLL 2
341
342#define CLK_DMC_MOUT_MPLL 3
343#define CLK_DMC_MOUT_BPLL 4
344#define CLK_DMC_MOUT_DPHY 5
345#define CLK_DMC_MOUT_DMC_BUS 6
346
347#define CLK_DMC_DIV_DMC 7
348#define CLK_DMC_DIV_DPHY 8
349#define CLK_DMC_DIV_DMC_PRE 9
350#define CLK_DMC_DIV_DMCP 10
351#define CLK_DMC_DIV_DMCD 11
352#define CLK_DMC_DIV_MPLL_PRE 12
353
354/*
355 * Total number of clocks of CMU_DMC.
356 * NOTE: Must be equal to highest clock ID increased by one.
357 */
358#define NR_CLKS_DMC 13
359
360#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 18:53:59 -0400