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-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/am33xx-restart.c12
-rw-r--r--arch/arm/mach-omap2/clock.c3
-rw-r--r--arch/arm/mach-omap2/cm.h18
-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h2
-rw-r--r--arch/arm/mach-omap2/cm1_54xx.h2
-rw-r--r--arch/arm/mach-omap2/cm1_7xx.h2
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h2
-rw-r--r--arch/arm/mach-omap2/cm2_54xx.h2
-rw-r--r--arch/arm/mach-omap2/cm2_7xx.h2
-rw-r--r--arch/arm/mach-omap2/cm2xxx.c17
-rw-r--r--arch/arm/mach-omap2/cm2xxx.h10
-rw-r--r--arch/arm/mach-omap2/cm33xx.c61
-rw-r--r--arch/arm/mach-omap2/cm33xx.h37
-rw-r--r--arch/arm/mach-omap2/cm3xxx.c19
-rw-r--r--arch/arm/mach-omap2/cm3xxx.h12
-rw-r--r--arch/arm/mach-omap2/cm44xx.c49
-rw-r--r--arch/arm/mach-omap2/cm44xx.h3
-rw-r--r--arch/arm/mach-omap2/cm_44xx_54xx.h36
-rw-r--r--arch/arm/mach-omap2/cm_common.c82
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c80
-rw-r--r--arch/arm/mach-omap2/cminst44xx.h43
-rw-r--r--arch/arm/mach-omap2/io.c11
-rw-r--r--arch/arm/mach-omap2/omap2-restart.c5
-rw-r--r--arch/arm/mach-omap2/omap3-restart.c7
-rw-r--r--arch/arm/mach-omap2/omap4-restart.c6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c248
-rw-r--r--arch/arm/mach-omap2/prm.h16
-rw-r--r--arch/arm/mach-omap2/prm2xxx.c6
-rw-r--r--arch/arm/mach-omap2/prm2xxx.h1
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c19
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h9
-rw-r--r--arch/arm/mach-omap2/prm33xx.c64
-rw-r--r--arch/arm/mach-omap2/prm33xx.h11
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c32
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h16
-rw-r--r--arch/arm/mach-omap2/prm44xx.c36
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h19
-rw-r--r--arch/arm/mach-omap2/prm_common.c99
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c10
-rw-r--r--arch/arm/mach-omap2/prminst44xx.h5
41 files changed, 530 insertions, 586 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d9e94122073e..3b653b3ac268 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -113,7 +113,7 @@ obj-y += prm_common.o cm_common.o
113obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o 113obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
114obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o 114obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
115obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o 115obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
116omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ 116omap-prcm-4-5-common = cminst44xx.o prm44xx.o \
117 prcm_mpu44xx.o prminst44xx.o \ 117 prcm_mpu44xx.o prminst44xx.o \
118 vc44xx_data.o vp44xx_data.o 118 vc44xx_data.o vp44xx_data.o
119obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) 119obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index c88d8df753c2..5bace6a45ffb 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -9,8 +9,7 @@
9#include <linux/reboot.h> 9#include <linux/reboot.h>
10 10
11#include "common.h" 11#include "common.h"
12#include "prm-regbits-33xx.h" 12#include "prm.h"
13#include "prm33xx.h"
14 13
15/** 14/**
16 * am3xx_restart - trigger a software restart of the SoC 15 * am3xx_restart - trigger a software restart of the SoC
@@ -24,12 +23,5 @@ void am33xx_restart(enum reboot_mode mode, const char *cmd)
24{ 23{
25 /* TODO: Handle mode and cmd if necessary */ 24 /* TODO: Handle mode and cmd if necessary */
26 25
27 am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK, 26 omap_prm_reset_system();
28 AM33XX_RST_GLOBAL_WARM_SW_MASK,
29 AM33XX_PRM_DEVICE_MOD,
30 AM33XX_PRM_RSTCTRL_OFFSET);
31
32 /* OCP barrier */
33 (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
34 AM33XX_PRM_RSTCTRL_OFFSET);
35} 27}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c2b239857cc4..6ad5b4dbd33e 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -171,7 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
171 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), 171 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
172 idlest_val, __clk_get_name(clk->hw.clk)); 172 idlest_val, __clk_get_name(clk->hw.clk));
173 } else { 173 } else {
174 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 174 omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
175 idlest_bit);
175 }; 176 };
176} 177}
177 178
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 93473f9a551c..6222e87a79b6 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -45,17 +45,29 @@ extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
45 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations 45 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
46 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl 46 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
47 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl 47 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
48 * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
49 * @module_enable: ptr to the SoC CM-specific module_enable impl
50 * @module_disable: ptr to the SoC CM-specific module_disable impl
48 */ 51 */
49struct cm_ll_data { 52struct cm_ll_data {
50 int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst, 53 int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
51 u8 *idlest_reg_id); 54 u8 *idlest_reg_id);
52 int (*wait_module_ready)(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); 55 int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
56 u8 idlest_shift);
57 int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg,
58 u8 idlest_shift);
59 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
60 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
53}; 61};
54 62
55extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, 63extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
56 u8 *idlest_reg_id); 64 u8 *idlest_reg_id);
57extern int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); 65int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
58 66 u8 idlest_shift);
67int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
68 u8 idlest_shift);
69int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
70int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
59extern int cm_register(struct cm_ll_data *cld); 71extern int cm_register(struct cm_ll_data *cld);
60extern int cm_unregister(struct cm_ll_data *cld); 72extern int cm_unregister(struct cm_ll_data *cld);
61 73
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 5ae8fe39d6ee..a5949927b661 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,8 +25,6 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 26#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
27 27
28#include "cm_44xx_54xx.h"
29
30/* CM1 base address */ 28/* CM1 base address */
31#define OMAP4430_CM1_BASE 0x4a004000 29#define OMAP4430_CM1_BASE 0x4a004000
32 30
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
index 90b3348e6672..fd245dfa7391 100644
--- a/arch/arm/mach-omap2/cm1_54xx.h
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -22,8 +22,6 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H 23#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
24 24
25#include "cm_44xx_54xx.h"
26
27/* CM1 base address */ 25/* CM1 base address */
28#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 26#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
29 27
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
index ca6fa1febaac..2f1c09eea021 100644
--- a/arch/arm/mach-omap2/cm1_7xx.h
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -23,8 +23,6 @@
23#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H 23#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
24#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H 24#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
25 25
26#include "cm_44xx_54xx.h"
27
28/* CM1 base address */ 26/* CM1 base address */
29#define DRA7XX_CM_CORE_AON_BASE 0x4a005000 27#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
30 28
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index ee5136d7cdda..7521abf3d830 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,8 +25,6 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 26#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
27 27
28#include "cm_44xx_54xx.h"
29
30/* CM2 base address */ 28/* CM2 base address */
31#define OMAP4430_CM2_BASE 0x4a008000 29#define OMAP4430_CM2_BASE 0x4a008000
32 30
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
index 2683231b299b..ff4040c196d8 100644
--- a/arch/arm/mach-omap2/cm2_54xx.h
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -21,8 +21,6 @@
21#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 21#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 22#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
23 23
24#include "cm_44xx_54xx.h"
25
26/* CM2 base address */ 24/* CM2 base address */
27#define OMAP54XX_CM_CORE_BASE 0x4a008000 25#define OMAP54XX_CM_CORE_BASE 0x4a008000
28 26
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index e966e3a3c931..ce63fdb68056 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -22,8 +22,6 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H 23#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
24 24
25#include "cm_44xx_54xx.h"
26
27/* CM2 base address */ 25/* CM2 base address */
28#define DRA7XX_CM_CORE_BASE 0x4a008000 26#define DRA7XX_CM_CORE_BASE 0x4a008000
29 27
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 8be6ea50c092..a96d901b1d5d 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -53,7 +53,7 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)
53 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); 53 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
54} 54}
55 55
56bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) 56static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
57{ 57{
58 u32 v; 58 u32 v;
59 59
@@ -64,12 +64,12 @@ bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
64 return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; 64 return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
65} 65}
66 66
67void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) 67static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
68{ 68{
69 _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask); 69 _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
70} 70}
71 71
72void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) 72static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
73{ 73{
74 _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask); 74 _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
75} 75}
@@ -150,7 +150,7 @@ static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit)
150 v |= m; 150 v |= m;
151 omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); 151 omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
152 152
153 omap2xxx_cm_wait_module_ready(PLL_MOD, 1, status_bit); 153 omap2xxx_cm_wait_module_ready(0, PLL_MOD, 1, status_bit);
154 154
155 /* 155 /*
156 * REVISIT: Should we return an error code if 156 * REVISIT: Should we return an error code if
@@ -204,8 +204,9 @@ void omap2xxx_cm_apll96_disable(void)
204 * XXX This function is only needed until absolute register addresses are 204 * XXX This function is only needed until absolute register addresses are
205 * removed from the OMAP struct clk records. 205 * removed from the OMAP struct clk records.
206 */ 206 */
207int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, 207static int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
208 u8 *idlest_reg_id) 208 s16 *prcm_inst,
209 u8 *idlest_reg_id)
209{ 210{
210 unsigned long offs; 211 unsigned long offs;
211 u8 idlest_offs; 212 u8 idlest_offs;
@@ -238,6 +239,7 @@ int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
238 239
239/** 240/**
240 * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby 241 * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
242 * @part: PRCM partition, ignored for OMAP2
241 * @prcm_mod: PRCM module offset 243 * @prcm_mod: PRCM module offset
242 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) 244 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
243 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check 245 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
@@ -246,7 +248,8 @@ int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
246 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon 248 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
247 * success or -EBUSY if the module doesn't enable in time. 249 * success or -EBUSY if the module doesn't enable in time.
248 */ 250 */
249int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) 251int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
252 u8 idlest_shift)
250{ 253{
251 int ena = 0, i = 0; 254 int ena = 0, i = 0;
252 u8 cm_idlest_reg; 255 u8 cm_idlest_reg;
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 891d81c3c8f4..c89502b168ae 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -46,9 +46,6 @@
46 46
47#ifndef __ASSEMBLER__ 47#ifndef __ASSEMBLER__
48 48
49extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
50extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
51
52extern void omap2xxx_cm_set_dpll_disable_autoidle(void); 49extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
53extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); 50extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
54 51
@@ -57,11 +54,8 @@ extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
57extern void omap2xxx_cm_set_apll96_disable_autoidle(void); 54extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
58extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); 55extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
59 56
60extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask); 57int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
61extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, 58 u8 idlest_shift);
62 u8 idlest_shift);
63extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
64 s16 *prcm_inst, u8 *idlest_reg_id);
65extern int omap2xxx_cm_fclks_active(void); 59extern int omap2xxx_cm_fclks_active(void);
66extern int omap2xxx_cm_mpu_retention_allowed(void); 60extern int omap2xxx_cm_mpu_retention_allowed(void);
67extern u32 omap2xxx_cm_get_core_clk_src(void); 61extern u32 omap2xxx_cm_get_core_clk_src(void);
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index b3f99e93def0..b9ad463a368a 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -96,13 +96,12 @@ static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
96/** 96/**
97 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 97 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
98 * @inst: CM instance register offset (*_INST macro) 98 * @inst: CM instance register offset (*_INST macro)
99 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
100 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 99 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
101 * 100 *
102 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 101 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
103 * bit 0. 102 * bit 0.
104 */ 103 */
105static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs) 104static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs)
106{ 105{
107 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); 106 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
108 v &= AM33XX_IDLEST_MASK; 107 v &= AM33XX_IDLEST_MASK;
@@ -113,17 +112,16 @@ static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
113/** 112/**
114 * _is_module_ready - can module registers be accessed without causing an abort? 113 * _is_module_ready - can module registers be accessed without causing an abort?
115 * @inst: CM instance register offset (*_INST macro) 114 * @inst: CM instance register offset (*_INST macro)
116 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
117 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 115 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
118 * 116 *
119 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 117 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
120 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 118 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
121 */ 119 */
122static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) 120static bool _is_module_ready(u16 inst, u16 clkctrl_offs)
123{ 121{
124 u32 v; 122 u32 v;
125 123
126 v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs); 124 v = _clkctrl_idlest(inst, clkctrl_offs);
127 125
128 return (v == CLKCTRL_IDLEST_FUNCTIONAL || 126 return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
129 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 127 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
@@ -158,7 +156,7 @@ static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
158 * Returns true if the clockdomain referred to by (@inst, @cdoffs) 156 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
159 * is in hardware-supervised idle mode, or 0 otherwise. 157 * is in hardware-supervised idle mode, or 0 otherwise.
160 */ 158 */
161bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs) 159static bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
162{ 160{
163 u32 v; 161 u32 v;
164 162
@@ -177,7 +175,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
177 * Put a clockdomain referred to by (@inst, @cdoffs) into 175 * Put a clockdomain referred to by (@inst, @cdoffs) into
178 * hardware-supervised idle mode. No return value. 176 * hardware-supervised idle mode. No return value.
179 */ 177 */
180void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs) 178static void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
181{ 179{
182 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); 180 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
183} 181}
@@ -191,7 +189,7 @@ void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
191 * software-supervised idle mode, i.e., controlled manually by the 189 * software-supervised idle mode, i.e., controlled manually by the
192 * Linux OMAP clockdomain code. No return value. 190 * Linux OMAP clockdomain code. No return value.
193 */ 191 */
194void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs) 192static void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
195{ 193{
196 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); 194 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
197} 195}
@@ -204,7 +202,7 @@ void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
204 * Put a clockdomain referred to by (@inst, @cdoffs) into idle 202 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
205 * No return value. 203 * No return value.
206 */ 204 */
207void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs) 205static void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
208{ 206{
209 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); 207 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
210} 208}
@@ -217,7 +215,7 @@ void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
217 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, 215 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
218 * waking it up. No return value. 216 * waking it up. No return value.
219 */ 217 */
220void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs) 218static void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
221{ 219{
222 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); 220 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
223} 221}
@@ -228,20 +226,22 @@ void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
228 226
229/** 227/**
230 * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state 228 * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
229 * @part: PRCM partition, ignored for AM33xx
231 * @inst: CM instance register offset (*_INST macro) 230 * @inst: CM instance register offset (*_INST macro)
232 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
233 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 231 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
232 * @bit_shift: bit shift for the register, ignored for AM33xx
234 * 233 *
235 * Wait for the module IDLEST to be functional. If the idle state is in any 234 * Wait for the module IDLEST to be functional. If the idle state is in any
236 * the non functional state (trans, idle or disabled), module and thus the 235 * the non functional state (trans, idle or disabled), module and thus the
237 * sysconfig cannot be accessed and will probably lead to an "imprecise 236 * sysconfig cannot be accessed and will probably lead to an "imprecise
238 * external abort" 237 * external abort"
239 */ 238 */
240int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) 239static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
240 u8 bit_shift)
241{ 241{
242 int i = 0; 242 int i = 0;
243 243
244 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), 244 omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
245 MAX_MODULE_READY_TIME, i); 245 MAX_MODULE_READY_TIME, i);
246 246
247 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 247 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
@@ -250,22 +250,24 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
250/** 250/**
251 * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled' 251 * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
252 * state 252 * state
253 * @part: CM partition, ignored for AM33xx
253 * @inst: CM instance register offset (*_INST macro) 254 * @inst: CM instance register offset (*_INST macro)
254 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
255 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 255 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
256 * @bit_shift: bit shift for the register, ignored for AM33xx
256 * 257 *
257 * Wait for the module IDLEST to be disabled. Some PRCM transition, 258 * Wait for the module IDLEST to be disabled. Some PRCM transition,
258 * like reset assertion or parent clock de-activation must wait the 259 * like reset assertion or parent clock de-activation must wait the
259 * module to be fully disabled. 260 * module to be fully disabled.
260 */ 261 */
261int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs) 262static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
263 u8 bit_shift)
262{ 264{
263 int i = 0; 265 int i = 0;
264 266
265 if (!clkctrl_offs) 267 if (!clkctrl_offs)
266 return 0; 268 return 0;
267 269
268 omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) == 270 omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
269 CLKCTRL_IDLEST_DISABLED), 271 CLKCTRL_IDLEST_DISABLED),
270 MAX_MODULE_READY_TIME, i); 272 MAX_MODULE_READY_TIME, i);
271 273
@@ -275,13 +277,14 @@ int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
275/** 277/**
276 * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL 278 * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
277 * @mode: Module mode (SW or HW) 279 * @mode: Module mode (SW or HW)
280 * @part: CM partition, ignored for AM33xx
278 * @inst: CM instance register offset (*_INST macro) 281 * @inst: CM instance register offset (*_INST macro)
279 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
280 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 282 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
281 * 283 *
282 * No return value. 284 * No return value.
283 */ 285 */
284void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) 286static void am33xx_cm_module_enable(u8 mode, u8 part, u16 inst,
287 u16 clkctrl_offs)
285{ 288{
286 u32 v; 289 u32 v;
287 290
@@ -293,13 +296,13 @@ void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
293 296
294/** 297/**
295 * am33xx_cm_module_disable - Disable the module inside CLKCTRL 298 * am33xx_cm_module_disable - Disable the module inside CLKCTRL
299 * @part: CM partition, ignored for AM33xx
296 * @inst: CM instance register offset (*_INST macro) 300 * @inst: CM instance register offset (*_INST macro)
297 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
298 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 301 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
299 * 302 *
300 * No return value. 303 * No return value.
301 */ 304 */
302void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) 305static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
303{ 306{
304 u32 v; 307 u32 v;
305 308
@@ -362,3 +365,21 @@ struct clkdm_ops am33xx_clkdm_operations = {
362 .clkdm_clk_enable = am33xx_clkdm_clk_enable, 365 .clkdm_clk_enable = am33xx_clkdm_clk_enable,
363 .clkdm_clk_disable = am33xx_clkdm_clk_disable, 366 .clkdm_clk_disable = am33xx_clkdm_clk_disable,
364}; 367};
368
369static struct cm_ll_data am33xx_cm_ll_data = {
370 .wait_module_ready = &am33xx_cm_wait_module_ready,
371 .wait_module_idle = &am33xx_cm_wait_module_idle,
372 .module_enable = &am33xx_cm_module_enable,
373 .module_disable = &am33xx_cm_module_disable,
374};
375
376int __init am33xx_cm_init(void)
377{
378 return cm_register(&am33xx_cm_ll_data);
379}
380
381static void __exit am33xx_cm_exit(void)
382{
383 cm_unregister(&am33xx_cm_ll_data);
384}
385__exitcall(am33xx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index bd2441790779..046b4b2bc9d9 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -374,41 +374,6 @@
374 374
375 375
376#ifndef __ASSEMBLER__ 376#ifndef __ASSEMBLER__
377bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs); 377int am33xx_cm_init(void);
378void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
379void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
380void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
381void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
382
383#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
384extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
385 u16 clkctrl_offs);
386extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
387 u16 clkctrl_offs);
388extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
389 u16 clkctrl_offs);
390extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
391 u16 clkctrl_offs);
392#else
393static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
394 u16 clkctrl_offs)
395{
396 return 0;
397}
398static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
399 u16 clkctrl_offs)
400{
401}
402static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
403 u16 clkctrl_offs)
404{
405}
406static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
407 u16 clkctrl_offs)
408{
409 return 0;
410}
411#endif
412
413#endif /* ASSEMBLER */ 378#endif /* ASSEMBLER */
414#endif 379#endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 129a4e7f6ef5..ebead8f035f9 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -42,7 +42,7 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)
42 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); 42 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
43} 43}
44 44
45bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) 45static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
46{ 46{
47 u32 v; 47 u32 v;
48 48
@@ -53,22 +53,22 @@ bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
53 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; 53 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
54} 54}
55 55
56void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) 56static void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
57{ 57{
58 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask); 58 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
59} 59}
60 60
61void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) 61static void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
62{ 62{
63 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask); 63 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
64} 64}
65 65
66void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask) 66static void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
67{ 67{
68 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask); 68 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
69} 69}
70 70
71void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) 71static void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
72{ 72{
73 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); 73 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
74} 74}
@@ -79,6 +79,7 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
79 79
80/** 80/**
81 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby 81 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
82 * @part: PRCM partition, ignored for OMAP3
82 * @prcm_mod: PRCM module offset 83 * @prcm_mod: PRCM module offset
83 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) 84 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
84 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check 85 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
@@ -87,7 +88,8 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
87 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon 88 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
88 * success or -EBUSY if the module doesn't enable in time. 89 * success or -EBUSY if the module doesn't enable in time.
89 */ 90 */
90int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) 91static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
92 u8 idlest_shift)
91{ 93{
92 int ena = 0, i = 0; 94 int ena = 0, i = 0;
93 u8 cm_idlest_reg; 95 u8 cm_idlest_reg;
@@ -116,8 +118,9 @@ int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
116 * XXX This function is only needed until absolute register addresses are 118 * XXX This function is only needed until absolute register addresses are
117 * removed from the OMAP struct clk records. 119 * removed from the OMAP struct clk records.
118 */ 120 */
119int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, 121static int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
120 u8 *idlest_reg_id) 122 s16 *prcm_inst,
123 u8 *idlest_reg_id)
121{ 124{
122 unsigned long offs; 125 unsigned long offs;
123 u8 idlest_offs; 126 u8 idlest_offs;
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 7a16b5598127..734a8581c0c4 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -68,18 +68,6 @@
68 68
69#ifndef __ASSEMBLER__ 69#ifndef __ASSEMBLER__
70 70
71extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
72extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
73extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
74extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
75
76extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
77extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
78 u8 idlest_shift);
79
80extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
81 s16 *prcm_inst, u8 *idlest_reg_id);
82
83extern void omap3_cm_save_context(void); 71extern void omap3_cm_save_context(void);
84extern void omap3_cm_restore_context(void); 72extern void omap3_cm_restore_context(void);
85extern void omap3_cm_save_scratchpad_contents(u32 *ptr); 73extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
deleted file mode 100644
index fe5cc7bae489..000000000000
--- a/arch/arm/mach-omap2/cm44xx.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * OMAP4 CM1, CM2 module low-level functions
3 *
4 * Copyright (C) 2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * These functions are intended to be used only by the cminst44xx.c file.
12 * XXX Perhaps we should just move them there and make them static.
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
21#include "cm.h"
22#include "cm1_44xx.h"
23#include "cm2_44xx.h"
24
25/* CM1 hardware module low-level functions */
26
27/* Read a register in CM1 */
28u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
29{
30 return readl_relaxed(cm_base + inst + reg);
31}
32
33/* Write into a register in CM1 */
34void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
35{
36 writel_relaxed(val, cm_base + inst + reg);
37}
38
39/* Read a register in CM2 */
40u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
41{
42 return readl_relaxed(cm2_base + inst + reg);
43}
44
45/* Write into a register in CM2 */
46void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
47{
48 writel_relaxed(val, cm2_base + inst + reg);
49}
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 3380beeace6e..728d06a4af19 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,4 +23,7 @@
23#define OMAP4_CM_CLKSTCTRL 0x0000 23#define OMAP4_CM_CLKSTCTRL 0x0000
24#define OMAP4_CM_STATICDEP 0x0004 24#define OMAP4_CM_STATICDEP 0x0004
25 25
26void omap_cm_base_init(void);
27int omap4_cm_init(void);
28
26#endif 29#endif
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
deleted file mode 100644
index cbb211690321..000000000000
--- a/arch/arm/mach-omap2/cm_44xx_54xx.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
25
26/* CM1 Function prototypes */
27extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
28extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
29extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
30
31/* CM2 Function prototypes */
32extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
33extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
34extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
35
36#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8f6c4710877e..8fe02fcedc48 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -72,9 +72,10 @@ int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
72} 72}
73 73
74/** 74/**
75 * cm_wait_module_ready - wait for a module to leave idle or standby 75 * omap_cm_wait_module_ready - wait for a module to leave idle or standby
76 * @part: PRCM partition
76 * @prcm_mod: PRCM module offset 77 * @prcm_mod: PRCM module offset
77 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) 78 * @idlest_reg: CM_IDLESTx register
78 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check 79 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
79 * 80 *
80 * Wait for the PRCM to indicate that the module identified by 81 * Wait for the PRCM to indicate that the module identified by
@@ -83,7 +84,8 @@ int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
83 * no per-SoC wait_module_ready() function pointer has been registered 84 * no per-SoC wait_module_ready() function pointer has been registered
84 * or if the idlest register is unknown on the SoC. 85 * or if the idlest register is unknown on the SoC.
85 */ 86 */
86int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) 87int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
88 u8 idlest_shift)
87{ 89{
88 if (!cm_ll_data->wait_module_ready) { 90 if (!cm_ll_data->wait_module_ready) {
89 WARN_ONCE(1, "cm: %s: no low-level function defined\n", 91 WARN_ONCE(1, "cm: %s: no low-level function defined\n",
@@ -91,7 +93,79 @@ int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
91 return -EINVAL; 93 return -EINVAL;
92 } 94 }
93 95
94 return cm_ll_data->wait_module_ready(prcm_mod, idlest_id, idlest_shift); 96 return cm_ll_data->wait_module_ready(part, prcm_mod, idlest_reg,
97 idlest_shift);
98}
99
100/**
101 * omap_cm_wait_module_idle - wait for a module to enter idle or standby
102 * @part: PRCM partition
103 * @prcm_mod: PRCM module offset
104 * @idlest_reg: CM_IDLESTx register
105 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
106 *
107 * Wait for the PRCM to indicate that the module identified by
108 * (@prcm_mod, @idlest_id, @idlest_shift) is no longer clocked. Return
109 * 0 upon success, -EBUSY if the module doesn't enable in time, or
110 * -EINVAL if no per-SoC wait_module_idle() function pointer has been
111 * registered or if the idlest register is unknown on the SoC.
112 */
113int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
114 u8 idlest_shift)
115{
116 if (!cm_ll_data->wait_module_idle) {
117 WARN_ONCE(1, "cm: %s: no low-level function defined\n",
118 __func__);
119 return -EINVAL;
120 }
121
122 return cm_ll_data->wait_module_idle(part, prcm_mod, idlest_reg,
123 idlest_shift);
124}
125
126/**
127 * omap_cm_module_enable - enable a module
128 * @mode: target mode for the module
129 * @part: PRCM partition
130 * @inst: PRCM instance
131 * @clkctrl_offs: CM_CLKCTRL register offset for the module
132 *
133 * Enables clocks for a module identified by (@part, @inst, @clkctrl_offs)
134 * making its IO space accessible. Return 0 upon success, -EINVAL if no
135 * per-SoC module_enable() function pointer has been registered.
136 */
137int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs)
138{
139 if (!cm_ll_data->module_enable) {
140 WARN_ONCE(1, "cm: %s: no low-level function defined\n",
141 __func__);
142 return -EINVAL;
143 }
144
145 cm_ll_data->module_enable(mode, part, inst, clkctrl_offs);
146 return 0;
147}
148
149/**
150 * omap_cm_module_disable - disable a module
151 * @part: PRCM partition
152 * @inst: PRCM instance
153 * @clkctrl_offs: CM_CLKCTRL register offset for the module
154 *
155 * Disables clocks for a module identified by (@part, @inst, @clkctrl_offs)
156 * makings its IO space inaccessible. Return 0 upon success, -EINVAL if
157 * no per-SoC module_disable() function pointer has been registered.
158 */
159int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
160{
161 if (!cm_ll_data->module_disable) {
162 WARN_ONCE(1, "cm: %s: no low-level function defined\n",
163 __func__);
164 return -EINVAL;
165 }
166
167 cm_ll_data->module_disable(part, inst, clkctrl_offs);
168 return 0;
95} 169}
96 170
97/** 171/**
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 12aca56942c0..95a8cff66aff 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -26,7 +26,6 @@
26#include "cm1_44xx.h" 26#include "cm1_44xx.h"
27#include "cm2_44xx.h" 27#include "cm2_44xx.h"
28#include "cm44xx.h" 28#include "cm44xx.h"
29#include "cminst44xx.h"
30#include "cm-regbits-34xx.h" 29#include "cm-regbits-34xx.h"
31#include "prcm44xx.h" 30#include "prcm44xx.h"
32#include "prm44xx.h" 31#include "prm44xx.h"
@@ -74,17 +73,18 @@ void omap_cm_base_init(void)
74 73
75/* Private functions */ 74/* Private functions */
76 75
76static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
77
77/** 78/**
78 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 79 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
79 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 80 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
80 * @inst: CM instance register offset (*_INST macro) 81 * @inst: CM instance register offset (*_INST macro)
81 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
82 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 82 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
83 * 83 *
84 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 84 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
85 * bit 0. 85 * bit 0.
86 */ 86 */
87static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 87static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs)
88{ 88{
89 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 89 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
90 v &= OMAP4430_IDLEST_MASK; 90 v &= OMAP4430_IDLEST_MASK;
@@ -96,26 +96,23 @@ static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
96 * _is_module_ready - can module registers be accessed without causing an abort? 96 * _is_module_ready - can module registers be accessed without causing an abort?
97 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 97 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
98 * @inst: CM instance register offset (*_INST macro) 98 * @inst: CM instance register offset (*_INST macro)
99 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
100 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 99 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
101 * 100 *
102 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 101 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
103 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 102 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
104 */ 103 */
105static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 104static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs)
106{ 105{
107 u32 v; 106 u32 v;
108 107
109 v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs); 108 v = _clkctrl_idlest(part, inst, clkctrl_offs);
110 109
111 return (v == CLKCTRL_IDLEST_FUNCTIONAL || 110 return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
112 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 111 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
113} 112}
114 113
115/* Public functions */
116
117/* Read a register in a CM instance */ 114/* Read a register in a CM instance */
118u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) 115static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
119{ 116{
120 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 117 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
121 part == OMAP4430_INVALID_PRCM_PARTITION || 118 part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -124,7 +121,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
124} 121}
125 122
126/* Write into a register in a CM instance */ 123/* Write into a register in a CM instance */
127void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) 124static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
128{ 125{
129 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 126 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
130 part == OMAP4430_INVALID_PRCM_PARTITION || 127 part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -133,8 +130,8 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
133} 130}
134 131
135/* Read-modify-write a register in CM1. Caller must lock */ 132/* Read-modify-write a register in CM1. Caller must lock */
136u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, 133static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
137 s16 idx) 134 s16 idx)
138{ 135{
139 u32 v; 136 u32 v;
140 137
@@ -146,17 +143,18 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
146 return v; 143 return v;
147} 144}
148 145
149u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 146static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
150{ 147{
151 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 148 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
152} 149}
153 150
154u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 151static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
152 s16 idx)
155{ 153{
156 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 154 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
157} 155}
158 156
159u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 157static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
160{ 158{
161 u32 v; 159 u32 v;
162 160
@@ -200,7 +198,7 @@ static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
200 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 198 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
201 * is in hardware-supervised idle mode, or 0 otherwise. 199 * is in hardware-supervised idle mode, or 0 otherwise.
202 */ 200 */
203bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) 201static bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
204{ 202{
205 u32 v; 203 u32 v;
206 204
@@ -220,7 +218,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
220 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 218 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
221 * hardware-supervised idle mode. No return value. 219 * hardware-supervised idle mode. No return value.
222 */ 220 */
223void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) 221static void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
224{ 222{
225 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 223 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
226} 224}
@@ -235,7 +233,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
235 * software-supervised idle mode, i.e., controlled manually by the 233 * software-supervised idle mode, i.e., controlled manually by the
236 * Linux OMAP clockdomain code. No return value. 234 * Linux OMAP clockdomain code. No return value.
237 */ 235 */
238void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) 236static void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
239{ 237{
240 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 238 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
241} 239}
@@ -249,7 +247,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
249 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 247 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
250 * waking it up. No return value. 248 * waking it up. No return value.
251 */ 249 */
252void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) 250static void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
253{ 251{
254 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 252 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
255} 253}
@@ -258,7 +256,7 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
258 * 256 *
259 */ 257 */
260 258
261void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) 259static void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
262{ 260{
263 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 261 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
264} 262}
@@ -267,23 +265,23 @@ void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
267 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 265 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
268 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 266 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
269 * @inst: CM instance register offset (*_INST macro) 267 * @inst: CM instance register offset (*_INST macro)
270 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
271 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 268 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
269 * @bit_shift: bit shift for the register, ignored for OMAP4+
272 * 270 *
273 * Wait for the module IDLEST to be functional. If the idle state is in any 271 * Wait for the module IDLEST to be functional. If the idle state is in any
274 * the non functional state (trans, idle or disabled), module and thus the 272 * the non functional state (trans, idle or disabled), module and thus the
275 * sysconfig cannot be accessed and will probably lead to an "imprecise 273 * sysconfig cannot be accessed and will probably lead to an "imprecise
276 * external abort" 274 * external abort"
277 */ 275 */
278int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, 276static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
279 u16 clkctrl_offs) 277 u8 bit_shift)
280{ 278{
281 int i = 0; 279 int i = 0;
282 280
283 if (!clkctrl_offs) 281 if (!clkctrl_offs)
284 return 0; 282 return 0;
285 283
286 omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs), 284 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
287 MAX_MODULE_READY_TIME, i); 285 MAX_MODULE_READY_TIME, i);
288 286
289 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 287 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
@@ -294,21 +292,22 @@ int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
294 * state 292 * state
295 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 293 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
296 * @inst: CM instance register offset (*_INST macro) 294 * @inst: CM instance register offset (*_INST macro)
297 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
298 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 295 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
296 * @bit_shift: Bit shift for the register, ignored for OMAP4+
299 * 297 *
300 * Wait for the module IDLEST to be disabled. Some PRCM transition, 298 * Wait for the module IDLEST to be disabled. Some PRCM transition,
301 * like reset assertion or parent clock de-activation must wait the 299 * like reset assertion or parent clock de-activation must wait the
302 * module to be fully disabled. 300 * module to be fully disabled.
303 */ 301 */
304int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) 302static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
303 u8 bit_shift)
305{ 304{
306 int i = 0; 305 int i = 0;
307 306
308 if (!clkctrl_offs) 307 if (!clkctrl_offs)
309 return 0; 308 return 0;
310 309
311 omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) == 310 omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) ==
312 CLKCTRL_IDLEST_DISABLED), 311 CLKCTRL_IDLEST_DISABLED),
313 MAX_MODULE_DISABLE_TIME, i); 312 MAX_MODULE_DISABLE_TIME, i);
314 313
@@ -320,13 +319,12 @@ int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_off
320 * @mode: Module mode (SW or HW) 319 * @mode: Module mode (SW or HW)
321 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 320 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
322 * @inst: CM instance register offset (*_INST macro) 321 * @inst: CM instance register offset (*_INST macro)
323 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
324 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 322 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
325 * 323 *
326 * No return value. 324 * No return value.
327 */ 325 */
328void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, 326static void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
329 u16 clkctrl_offs) 327 u16 clkctrl_offs)
330{ 328{
331 u32 v; 329 u32 v;
332 330
@@ -340,13 +338,11 @@ void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
340 * omap4_cminst_module_disable - Disable the module inside CLKCTRL 338 * omap4_cminst_module_disable - Disable the module inside CLKCTRL
341 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 339 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
342 * @inst: CM instance register offset (*_INST macro) 340 * @inst: CM instance register offset (*_INST macro)
343 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
344 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 341 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
345 * 342 *
346 * No return value. 343 * No return value.
347 */ 344 */
348void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, 345static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
349 u16 clkctrl_offs)
350{ 346{
351 u32 v; 347 u32 v;
352 348
@@ -510,3 +506,21 @@ struct clkdm_ops am43xx_clkdm_operations = {
510 .clkdm_clk_enable = omap4_clkdm_clk_enable, 506 .clkdm_clk_enable = omap4_clkdm_clk_enable,
511 .clkdm_clk_disable = omap4_clkdm_clk_disable, 507 .clkdm_clk_disable = omap4_clkdm_clk_disable,
512}; 508};
509
510static struct cm_ll_data omap4xxx_cm_ll_data = {
511 .wait_module_ready = &omap4_cminst_wait_module_ready,
512 .wait_module_idle = &omap4_cminst_wait_module_idle,
513 .module_enable = &omap4_cminst_module_enable,
514 .module_disable = &omap4_cminst_module_disable,
515};
516
517int __init omap4_cm_init(void)
518{
519 return cm_register(&omap4xxx_cm_ll_data);
520}
521
522static void __exit omap4_cm_exit(void)
523{
524 cm_unregister(&omap4xxx_cm_ll_data);
525}
526__exitcall(omap4_cm_exit);
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
deleted file mode 100644
index 7f56ea444bc4..000000000000
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * OMAP4 Clock Management (CM) function prototypes
3 *
4 * Copyright (C) 2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
12#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
13
14bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
15void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
16void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
17void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
18void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
19extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
20extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
21 u16 clkctrl_offs);
22extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
23 u16 clkctrl_offs);
24extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
25 u16 clkctrl_offs);
26/*
27 * In an ideal world, we would not export these low-level functions,
28 * but this will probably take some time to fix properly
29 */
30u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
31void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx);
32u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
33 u16 inst, s16 idx);
34u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst,
35 s16 idx);
36u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
37 s16 idx);
38extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
39 u32 mask);
40
41extern void omap_cm_base_init(void);
42
43#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 03cbb16898a3..4fc838354e31 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -45,13 +45,15 @@
45#include "sram.h" 45#include "sram.h"
46#include "cm2xxx.h" 46#include "cm2xxx.h"
47#include "cm3xxx.h" 47#include "cm3xxx.h"
48#include "cm33xx.h"
49#include "cm44xx.h"
48#include "prm.h" 50#include "prm.h"
49#include "cm.h" 51#include "cm.h"
50#include "prcm_mpu44xx.h" 52#include "prcm_mpu44xx.h"
51#include "prminst44xx.h" 53#include "prminst44xx.h"
52#include "cminst44xx.h"
53#include "prm2xxx.h" 54#include "prm2xxx.h"
54#include "prm3xxx.h" 55#include "prm3xxx.h"
56#include "prm33xx.h"
55#include "prm44xx.h" 57#include "prm44xx.h"
56#include "opp2xxx.h" 58#include "opp2xxx.h"
57 59
@@ -565,6 +567,8 @@ void __init am33xx_init_early(void)
565 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); 567 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
566 omap3xxx_check_revision(); 568 omap3xxx_check_revision();
567 am33xx_check_features(); 569 am33xx_check_features();
570 am33xx_prm_init();
571 am33xx_cm_init();
568 am33xx_powerdomains_init(); 572 am33xx_powerdomains_init();
569 am33xx_clockdomains_init(); 573 am33xx_clockdomains_init();
570 am33xx_hwmod_init(); 574 am33xx_hwmod_init();
@@ -591,6 +595,8 @@ void __init am43xx_init_early(void)
591 omap_cm_base_init(); 595 omap_cm_base_init();
592 omap3xxx_check_revision(); 596 omap3xxx_check_revision();
593 am33xx_check_features(); 597 am33xx_check_features();
598 omap44xx_prm_init();
599 omap4_cm_init();
594 am43xx_powerdomains_init(); 600 am43xx_powerdomains_init();
595 am43xx_clockdomains_init(); 601 am43xx_clockdomains_init();
596 am43xx_hwmod_init(); 602 am43xx_hwmod_init();
@@ -620,6 +626,7 @@ void __init omap4430_init_early(void)
620 omap_cm_base_init(); 626 omap_cm_base_init();
621 omap4xxx_check_revision(); 627 omap4xxx_check_revision();
622 omap4xxx_check_features(); 628 omap4xxx_check_features();
629 omap4_cm_init();
623 omap4_pm_init_early(); 630 omap4_pm_init_early();
624 omap44xx_prm_init(); 631 omap44xx_prm_init();
625 omap44xx_voltagedomains_init(); 632 omap44xx_voltagedomains_init();
@@ -655,6 +662,7 @@ void __init omap5_init_early(void)
655 omap_cm_base_init(); 662 omap_cm_base_init();
656 omap44xx_prm_init(); 663 omap44xx_prm_init();
657 omap5xxx_check_revision(); 664 omap5xxx_check_revision();
665 omap4_cm_init();
658 omap54xx_voltagedomains_init(); 666 omap54xx_voltagedomains_init();
659 omap54xx_powerdomains_init(); 667 omap54xx_powerdomains_init();
660 omap54xx_clockdomains_init(); 668 omap54xx_clockdomains_init();
@@ -686,6 +694,7 @@ void __init dra7xx_init_early(void)
686 omap_cm_base_init(); 694 omap_cm_base_init();
687 omap44xx_prm_init(); 695 omap44xx_prm_init();
688 dra7xxx_check_revision(); 696 dra7xxx_check_revision();
697 omap4_cm_init();
689 dra7xx_powerdomains_init(); 698 dra7xx_powerdomains_init();
690 dra7xx_clockdomains_init(); 699 dra7xx_clockdomains_init();
691 dra7xx_hwmod_init(); 700 dra7xx_hwmod_init();
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 68423e26399d..d937b2e4040b 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -15,7 +15,7 @@
15 15
16#include "soc.h" 16#include "soc.h"
17#include "common.h" 17#include "common.h"
18#include "prm2xxx.h" 18#include "prm.h"
19 19
20/* 20/*
21 * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set 21 * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set
@@ -40,8 +40,7 @@ void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
40 40
41 /* XXX Should save the cmd argument for use after the reboot */ 41 /* XXX Should save the cmd argument for use after the reboot */
42 42
43 omap2xxx_prm_dpll_reset(); /* never returns */ 43 omap_prm_reset_system();
44 while (1);
45} 44}
46 45
47/** 46/**
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 5de2a0c2979d..103a49f68bcb 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -14,10 +14,8 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/reboot.h> 15#include <linux/reboot.h>
16 16
17#include "iomap.h"
18#include "common.h"
19#include "control.h" 17#include "control.h"
20#include "prm3xxx.h" 18#include "prm.h"
21 19
22/* Global address base setup code */ 20/* Global address base setup code */
23 21
@@ -32,6 +30,5 @@
32void omap3xxx_restart(enum reboot_mode mode, const char *cmd) 30void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
33{ 31{
34 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); 32 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
35 omap3xxx_prm_dpll3_reset(); /* never returns */ 33 omap_prm_reset_system();
36 while (1);
37} 34}
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
index 41dfd7da8170..a99e7f7fb5be 100644
--- a/arch/arm/mach-omap2/omap4-restart.c
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -9,7 +9,7 @@
9 9
10#include <linux/types.h> 10#include <linux/types.h>
11#include <linux/reboot.h> 11#include <linux/reboot.h>
12#include "prminst44xx.h" 12#include "prm.h"
13 13
14/** 14/**
15 * omap44xx_restart - trigger a software restart of the SoC 15 * omap44xx_restart - trigger a software restart of the SoC
@@ -22,7 +22,5 @@
22void omap44xx_restart(enum reboot_mode mode, const char *cmd) 22void omap44xx_restart(enum reboot_mode mode, const char *cmd)
23{ 23{
24 /* XXX Should save 'cmd' into scratchpad for use after reboot */ 24 /* XXX Should save 'cmd' into scratchpad for use after reboot */
25 omap4_prminst_global_warm_sw_reset(); /* never returns */ 25 omap_prm_reset_system();
26 while (1)
27 ;
28} 26}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index acae6d5d1151..ee5f38df477d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -153,7 +153,6 @@
153#include "powerdomain.h" 153#include "powerdomain.h"
154#include "cm2xxx.h" 154#include "cm2xxx.h"
155#include "cm3xxx.h" 155#include "cm3xxx.h"
156#include "cminst44xx.h"
157#include "cm33xx.h" 156#include "cm33xx.h"
158#include "prm.h" 157#include "prm.h"
159#include "prm3xxx.h" 158#include "prm3xxx.h"
@@ -979,31 +978,9 @@ static void _omap4_enable_module(struct omap_hwmod *oh)
979 pr_debug("omap_hwmod: %s: %s: %d\n", 978 pr_debug("omap_hwmod: %s: %s: %d\n",
980 oh->name, __func__, oh->prcm.omap4.modulemode); 979 oh->name, __func__, oh->prcm.omap4.modulemode);
981 980
982 omap4_cminst_module_enable(oh->prcm.omap4.modulemode, 981 omap_cm_module_enable(oh->prcm.omap4.modulemode,
983 oh->clkdm->prcm_partition, 982 oh->clkdm->prcm_partition,
984 oh->clkdm->cm_inst, 983 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs);
985 oh->clkdm->clkdm_offs,
986 oh->prcm.omap4.clkctrl_offs);
987}
988
989/**
990 * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX
991 * @oh: struct omap_hwmod *
992 *
993 * Enables the PRCM module mode related to the hwmod @oh.
994 * No return value.
995 */
996static void _am33xx_enable_module(struct omap_hwmod *oh)
997{
998 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
999 return;
1000
1001 pr_debug("omap_hwmod: %s: %s: %d\n",
1002 oh->name, __func__, oh->prcm.omap4.modulemode);
1003
1004 am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst,
1005 oh->clkdm->clkdm_offs,
1006 oh->prcm.omap4.clkctrl_offs);
1007} 984}
1008 985
1009/** 986/**
@@ -1026,35 +1003,9 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
1026 if (oh->flags & HWMOD_NO_IDLEST) 1003 if (oh->flags & HWMOD_NO_IDLEST)
1027 return 0; 1004 return 0;
1028 1005
1029 return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, 1006 return omap_cm_wait_module_idle(oh->clkdm->prcm_partition,
1030 oh->clkdm->cm_inst, 1007 oh->clkdm->cm_inst,
1031 oh->clkdm->clkdm_offs, 1008 oh->prcm.omap4.clkctrl_offs, 0);
1032 oh->prcm.omap4.clkctrl_offs);
1033}
1034
1035/**
1036 * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX
1037 * @oh: struct omap_hwmod *
1038 *
1039 * Wait for a module @oh to enter slave idle. Returns 0 if the module
1040 * does not have an IDLEST bit or if the module successfully enters
1041 * slave idle; otherwise, pass along the return value of the
1042 * appropriate *_cm*_wait_module_idle() function.
1043 */
1044static int _am33xx_wait_target_disable(struct omap_hwmod *oh)
1045{
1046 if (!oh)
1047 return -EINVAL;
1048
1049 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1050 return 0;
1051
1052 if (oh->flags & HWMOD_NO_IDLEST)
1053 return 0;
1054
1055 return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst,
1056 oh->clkdm->clkdm_offs,
1057 oh->prcm.omap4.clkctrl_offs);
1058} 1009}
1059 1010
1060/** 1011/**
@@ -1859,10 +1810,8 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
1859 1810
1860 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); 1811 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
1861 1812
1862 omap4_cminst_module_disable(oh->clkdm->prcm_partition, 1813 omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst,
1863 oh->clkdm->cm_inst, 1814 oh->prcm.omap4.clkctrl_offs);
1864 oh->clkdm->clkdm_offs,
1865 oh->prcm.omap4.clkctrl_offs);
1866 1815
1867 v = _omap4_wait_target_disable(oh); 1816 v = _omap4_wait_target_disable(oh);
1868 if (v) 1817 if (v)
@@ -1873,36 +1822,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
1873} 1822}
1874 1823
1875/** 1824/**
1876 * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX
1877 * @oh: struct omap_hwmod *
1878 *
1879 * Disable the PRCM module mode related to the hwmod @oh.
1880 * Return EINVAL if the modulemode is not supported and 0 in case of success.
1881 */
1882static int _am33xx_disable_module(struct omap_hwmod *oh)
1883{
1884 int v;
1885
1886 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
1887 return -EINVAL;
1888
1889 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
1890
1891 if (_are_any_hardreset_lines_asserted(oh))
1892 return 0;
1893
1894 am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs,
1895 oh->prcm.omap4.clkctrl_offs);
1896
1897 v = _am33xx_wait_target_disable(oh);
1898 if (v)
1899 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
1900 oh->name);
1901
1902 return 0;
1903}
1904
1905/**
1906 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit 1825 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
1907 * @oh: struct omap_hwmod * 1826 * @oh: struct omap_hwmod *
1908 * 1827 *
@@ -2065,10 +1984,7 @@ static void _reconfigure_io_chain(void)
2065 1984
2066 spin_lock_irqsave(&io_chain_lock, flags); 1985 spin_lock_irqsave(&io_chain_lock, flags);
2067 1986
2068 if (cpu_is_omap34xx()) 1987 omap_prm_reconfigure_io_chain();
2069 omap3xxx_prm_reconfigure_io_chain();
2070 else if (cpu_is_omap44xx())
2071 omap44xx_prm_reconfigure_io_chain();
2072 1988
2073 spin_unlock_irqrestore(&io_chain_lock, flags); 1989 spin_unlock_irqrestore(&io_chain_lock, flags);
2074} 1990}
@@ -2925,7 +2841,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
2925/* Static functions intended only for use in soc_ops field function pointers */ 2841/* Static functions intended only for use in soc_ops field function pointers */
2926 2842
2927/** 2843/**
2928 * _omap2xxx_wait_target_ready - wait for a module to leave slave idle 2844 * _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle
2929 * @oh: struct omap_hwmod * 2845 * @oh: struct omap_hwmod *
2930 * 2846 *
2931 * Wait for a module @oh to leave slave idle. Returns 0 if the module 2847 * Wait for a module @oh to leave slave idle. Returns 0 if the module
@@ -2933,7 +2849,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
2933 * slave idle; otherwise, pass along the return value of the 2849 * slave idle; otherwise, pass along the return value of the
2934 * appropriate *_cm*_wait_module_ready() function. 2850 * appropriate *_cm*_wait_module_ready() function.
2935 */ 2851 */
2936static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh) 2852static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh)
2937{ 2853{
2938 if (!oh) 2854 if (!oh)
2939 return -EINVAL; 2855 return -EINVAL;
@@ -2946,36 +2862,9 @@ static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh)
2946 2862
2947 /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ 2863 /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
2948 2864
2949 return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, 2865 return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs,
2950 oh->prcm.omap2.idlest_reg_id, 2866 oh->prcm.omap2.idlest_reg_id,
2951 oh->prcm.omap2.idlest_idle_bit); 2867 oh->prcm.omap2.idlest_idle_bit);
2952}
2953
2954/**
2955 * _omap3xxx_wait_target_ready - wait for a module to leave slave idle
2956 * @oh: struct omap_hwmod *
2957 *
2958 * Wait for a module @oh to leave slave idle. Returns 0 if the module
2959 * does not have an IDLEST bit or if the module successfully leaves
2960 * slave idle; otherwise, pass along the return value of the
2961 * appropriate *_cm*_wait_module_ready() function.
2962 */
2963static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh)
2964{
2965 if (!oh)
2966 return -EINVAL;
2967
2968 if (oh->flags & HWMOD_NO_IDLEST)
2969 return 0;
2970
2971 if (!_find_mpu_rt_port(oh))
2972 return 0;
2973
2974 /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
2975
2976 return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
2977 oh->prcm.omap2.idlest_reg_id,
2978 oh->prcm.omap2.idlest_idle_bit);
2979} 2868}
2980 2869
2981/** 2870/**
@@ -3000,37 +2889,9 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh)
3000 2889
3001 /* XXX check module SIDLEMODE, hardreset status */ 2890 /* XXX check module SIDLEMODE, hardreset status */
3002 2891
3003 return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, 2892 return omap_cm_wait_module_ready(oh->clkdm->prcm_partition,
3004 oh->clkdm->cm_inst, 2893 oh->clkdm->cm_inst,
3005 oh->clkdm->clkdm_offs, 2894 oh->prcm.omap4.clkctrl_offs, 0);
3006 oh->prcm.omap4.clkctrl_offs);
3007}
3008
3009/**
3010 * _am33xx_wait_target_ready - wait for a module to leave slave idle
3011 * @oh: struct omap_hwmod *
3012 *
3013 * Wait for a module @oh to leave slave idle. Returns 0 if the module
3014 * does not have an IDLEST bit or if the module successfully leaves
3015 * slave idle; otherwise, pass along the return value of the
3016 * appropriate *_cm*_wait_module_ready() function.
3017 */
3018static int _am33xx_wait_target_ready(struct omap_hwmod *oh)
3019{
3020 if (!oh || !oh->clkdm)
3021 return -EINVAL;
3022
3023 if (oh->flags & HWMOD_NO_IDLEST)
3024 return 0;
3025
3026 if (!_find_mpu_rt_port(oh))
3027 return 0;
3028
3029 /* XXX check module SIDLEMODE, hardreset status */
3030
3031 return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst,
3032 oh->clkdm->clkdm_offs,
3033 oh->prcm.omap4.clkctrl_offs);
3034} 2895}
3035 2896
3036/** 2897/**
@@ -3047,8 +2908,8 @@ static int _am33xx_wait_target_ready(struct omap_hwmod *oh)
3047static int _omap2_assert_hardreset(struct omap_hwmod *oh, 2908static int _omap2_assert_hardreset(struct omap_hwmod *oh,
3048 struct omap_hwmod_rst_info *ohri) 2909 struct omap_hwmod_rst_info *ohri)
3049{ 2910{
3050 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, 2911 return omap_prm_assert_hardreset(ohri->rst_shift, 0,
3051 ohri->rst_shift); 2912 oh->prcm.omap2.module_offs, 0);
3052} 2913}
3053 2914
3054/** 2915/**
@@ -3065,9 +2926,8 @@ static int _omap2_assert_hardreset(struct omap_hwmod *oh,
3065static int _omap2_deassert_hardreset(struct omap_hwmod *oh, 2926static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
3066 struct omap_hwmod_rst_info *ohri) 2927 struct omap_hwmod_rst_info *ohri)
3067{ 2928{
3068 return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, 2929 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
3069 ohri->rst_shift, 2930 oh->prcm.omap2.module_offs, 0, 0);
3070 ohri->st_shift);
3071} 2931}
3072 2932
3073/** 2933/**
@@ -3085,8 +2945,8 @@ static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
3085static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, 2945static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
3086 struct omap_hwmod_rst_info *ohri) 2946 struct omap_hwmod_rst_info *ohri)
3087{ 2947{
3088 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, 2948 return omap_prm_is_hardreset_asserted(ohri->st_shift, 0,
3089 ohri->st_shift); 2949 oh->prcm.omap2.module_offs, 0);
3090} 2950}
3091 2951
3092/** 2952/**
@@ -3107,10 +2967,10 @@ static int _omap4_assert_hardreset(struct omap_hwmod *oh,
3107 if (!oh->clkdm) 2967 if (!oh->clkdm)
3108 return -EINVAL; 2968 return -EINVAL;
3109 2969
3110 return omap4_prminst_assert_hardreset(ohri->rst_shift, 2970 return omap_prm_assert_hardreset(ohri->rst_shift,
3111 oh->clkdm->pwrdm.ptr->prcm_partition, 2971 oh->clkdm->pwrdm.ptr->prcm_partition,
3112 oh->clkdm->pwrdm.ptr->prcm_offs, 2972 oh->clkdm->pwrdm.ptr->prcm_offs,
3113 oh->prcm.omap4.rstctrl_offs); 2973 oh->prcm.omap4.rstctrl_offs);
3114} 2974}
3115 2975
3116/** 2976/**
@@ -3134,10 +2994,10 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
3134 if (ohri->st_shift) 2994 if (ohri->st_shift)
3135 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", 2995 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
3136 oh->name, ohri->name); 2996 oh->name, ohri->name);
3137 return omap4_prminst_deassert_hardreset(ohri->rst_shift, 2997 return omap_prm_deassert_hardreset(ohri->rst_shift, 0,
3138 oh->clkdm->pwrdm.ptr->prcm_partition, 2998 oh->clkdm->pwrdm.ptr->prcm_partition,
3139 oh->clkdm->pwrdm.ptr->prcm_offs, 2999 oh->clkdm->pwrdm.ptr->prcm_offs,
3140 oh->prcm.omap4.rstctrl_offs); 3000 oh->prcm.omap4.rstctrl_offs, 0);
3141} 3001}
3142 3002
3143/** 3003/**
@@ -3158,10 +3018,11 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
3158 if (!oh->clkdm) 3018 if (!oh->clkdm)
3159 return -EINVAL; 3019 return -EINVAL;
3160 3020
3161 return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, 3021 return omap_prm_is_hardreset_asserted(ohri->rst_shift,
3162 oh->clkdm->pwrdm.ptr->prcm_partition, 3022 oh->clkdm->pwrdm.ptr->
3163 oh->clkdm->pwrdm.ptr->prcm_offs, 3023 prcm_partition,
3164 oh->prcm.omap4.rstctrl_offs); 3024 oh->clkdm->pwrdm.ptr->prcm_offs,
3025 oh->prcm.omap4.rstctrl_offs);
3165} 3026}
3166 3027
3167/** 3028/**
@@ -3180,9 +3041,9 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
3180 struct omap_hwmod_rst_info *ohri) 3041 struct omap_hwmod_rst_info *ohri)
3181 3042
3182{ 3043{
3183 return am33xx_prm_assert_hardreset(ohri->rst_shift, 3044 return omap_prm_assert_hardreset(ohri->rst_shift, 0,
3184 oh->clkdm->pwrdm.ptr->prcm_offs, 3045 oh->clkdm->pwrdm.ptr->prcm_offs,
3185 oh->prcm.omap4.rstctrl_offs); 3046 oh->prcm.omap4.rstctrl_offs);
3186} 3047}
3187 3048
3188/** 3049/**
@@ -3200,11 +3061,10 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
3200static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, 3061static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
3201 struct omap_hwmod_rst_info *ohri) 3062 struct omap_hwmod_rst_info *ohri)
3202{ 3063{
3203 return am33xx_prm_deassert_hardreset(ohri->rst_shift, 3064 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
3204 ohri->st_shift, 3065 oh->clkdm->pwrdm.ptr->prcm_offs,
3205 oh->clkdm->pwrdm.ptr->prcm_offs, 3066 oh->prcm.omap4.rstctrl_offs,
3206 oh->prcm.omap4.rstctrl_offs, 3067 oh->prcm.omap4.rstst_offs);
3207 oh->prcm.omap4.rstst_offs);
3208} 3068}
3209 3069
3210/** 3070/**
@@ -3222,9 +3082,9 @@ static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
3222static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, 3082static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
3223 struct omap_hwmod_rst_info *ohri) 3083 struct omap_hwmod_rst_info *ohri)
3224{ 3084{
3225 return am33xx_prm_is_hardreset_asserted(ohri->rst_shift, 3085 return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0,
3226 oh->clkdm->pwrdm.ptr->prcm_offs, 3086 oh->clkdm->pwrdm.ptr->prcm_offs,
3227 oh->prcm.omap4.rstctrl_offs); 3087 oh->prcm.omap4.rstctrl_offs);
3228} 3088}
3229 3089
3230/* Public functions */ 3090/* Public functions */
@@ -4232,12 +4092,12 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
4232void __init omap_hwmod_init(void) 4092void __init omap_hwmod_init(void)
4233{ 4093{
4234 if (cpu_is_omap24xx()) { 4094 if (cpu_is_omap24xx()) {
4235 soc_ops.wait_target_ready = _omap2xxx_wait_target_ready; 4095 soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
4236 soc_ops.assert_hardreset = _omap2_assert_hardreset; 4096 soc_ops.assert_hardreset = _omap2_assert_hardreset;
4237 soc_ops.deassert_hardreset = _omap2_deassert_hardreset; 4097 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
4238 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; 4098 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
4239 } else if (cpu_is_omap34xx()) { 4099 } else if (cpu_is_omap34xx()) {
4240 soc_ops.wait_target_ready = _omap3xxx_wait_target_ready; 4100 soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
4241 soc_ops.assert_hardreset = _omap2_assert_hardreset; 4101 soc_ops.assert_hardreset = _omap2_assert_hardreset;
4242 soc_ops.deassert_hardreset = _omap2_deassert_hardreset; 4102 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
4243 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; 4103 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
@@ -4256,14 +4116,14 @@ void __init omap_hwmod_init(void)
4256 soc_ops.enable_module = _omap4_enable_module; 4116 soc_ops.enable_module = _omap4_enable_module;
4257 soc_ops.disable_module = _omap4_disable_module; 4117 soc_ops.disable_module = _omap4_disable_module;
4258 soc_ops.wait_target_ready = _omap4_wait_target_ready; 4118 soc_ops.wait_target_ready = _omap4_wait_target_ready;
4259 soc_ops.assert_hardreset = _am33xx_assert_hardreset; 4119 soc_ops.assert_hardreset = _omap4_assert_hardreset;
4260 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; 4120 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
4261 soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; 4121 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
4262 soc_ops.init_clkdm = _init_clkdm; 4122 soc_ops.init_clkdm = _init_clkdm;
4263 } else if (soc_is_am33xx()) { 4123 } else if (soc_is_am33xx()) {
4264 soc_ops.enable_module = _am33xx_enable_module; 4124 soc_ops.enable_module = _omap4_enable_module;
4265 soc_ops.disable_module = _am33xx_disable_module; 4125 soc_ops.disable_module = _omap4_disable_module;
4266 soc_ops.wait_target_ready = _am33xx_wait_target_ready; 4126 soc_ops.wait_target_ready = _omap4_wait_target_ready;
4267 soc_ops.assert_hardreset = _am33xx_assert_hardreset; 4127 soc_ops.assert_hardreset = _am33xx_assert_hardreset;
4268 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; 4128 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
4269 soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; 4129 soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 48480d557b61..77752e49d8d4 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -29,6 +29,7 @@ int of_prcm_init(void);
29 * PRM_HAS_VOLTAGE: has voltage domains 29 * PRM_HAS_VOLTAGE: has voltage domains
30 */ 30 */
31#define PRM_HAS_IO_WAKEUP (1 << 0) 31#define PRM_HAS_IO_WAKEUP (1 << 0)
32#define PRM_HAS_VOLTAGE (1 << 1)
32 33
33/* 34/*
34 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP 35 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -127,6 +128,8 @@ struct prm_reset_src_map {
127 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn 128 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
128 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn 129 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
129 * @late_init: ptr to the late init function 130 * @late_init: ptr to the late init function
131 * @assert_hardreset: ptr to the SoC PRM hardreset assert impl
132 * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl
130 * 133 *
131 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are 134 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
132 * deprecated. 135 * deprecated.
@@ -136,14 +139,27 @@ struct prm_ll_data {
136 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx); 139 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
137 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx); 140 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
138 int (*late_init)(void); 141 int (*late_init)(void);
142 int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset);
143 int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
144 u16 offset, u16 st_offset);
145 int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
146 u16 offset);
147 void (*reset_system)(void);
139}; 148};
140 149
141extern int prm_register(struct prm_ll_data *pld); 150extern int prm_register(struct prm_ll_data *pld);
142extern int prm_unregister(struct prm_ll_data *pld); 151extern int prm_unregister(struct prm_ll_data *pld);
143 152
153int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
154int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
155 u16 offset, u16 st_offset);
156int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
144extern u32 prm_read_reset_sources(void); 157extern u32 prm_read_reset_sources(void);
145extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx); 158extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
146extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx); 159extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
160void omap_prm_reset_system(void);
161
162void omap_prm_reconfigure_io_chain(void);
147 163
148#endif 164#endif
149 165
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 86958050547a..af0f15278fc2 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -106,7 +106,7 @@ static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
106 * Set the DPLL reset bit, which should reboot the SoC. This is the 106 * Set the DPLL reset bit, which should reboot the SoC. This is the
107 * recommended way to restart the SoC. No return value. 107 * recommended way to restart the SoC. No return value.
108 */ 108 */
109void omap2xxx_prm_dpll_reset(void) 109static void omap2xxx_prm_dpll_reset(void)
110{ 110{
111 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD, 111 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
112 OMAP2_RM_RSTCTRL); 112 OMAP2_RM_RSTCTRL);
@@ -212,6 +212,10 @@ struct pwrdm_ops omap2_pwrdm_operations = {
212 212
213static struct prm_ll_data omap2xxx_prm_ll_data = { 213static struct prm_ll_data omap2xxx_prm_ll_data = {
214 .read_reset_sources = &omap2xxx_prm_read_reset_sources, 214 .read_reset_sources = &omap2xxx_prm_read_reset_sources,
215 .assert_hardreset = &omap2_prm_assert_hardreset,
216 .deassert_hardreset = &omap2_prm_deassert_hardreset,
217 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
218 .reset_system = &omap2xxx_prm_dpll_reset,
215}; 219};
216 220
217int __init omap2xxx_prm_init(void) 221int __init omap2xxx_prm_init(void)
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index d73414139292..1d51643062f7 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -124,7 +124,6 @@
124extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); 124extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
125extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); 125extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
126 126
127extern void omap2xxx_prm_dpll_reset(void);
128void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); 127void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
129 128
130extern int __init omap2xxx_prm_init(void); 129extern int __init omap2xxx_prm_init(void);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index c13b4e293ffa..cc3341f263cd 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -24,14 +24,16 @@
24/** 24/**
25 * omap2_prm_is_hardreset_asserted - read the HW reset line state of 25 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
26 * submodules contained in the hwmod module 26 * submodules contained in the hwmod module
27 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
28 * @shift: register bit shift corresponding to the reset line to check 27 * @shift: register bit shift corresponding to the reset line to check
28 * @part: PRM partition, ignored for OMAP2
29 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
30 * @offset: register offset, ignored for OMAP2
29 * 31 *
30 * Returns 1 if the (sub)module hardreset line is currently asserted, 32 * Returns 1 if the (sub)module hardreset line is currently asserted,
31 * 0 if the (sub)module hardreset line is not currently asserted, or 33 * 0 if the (sub)module hardreset line is not currently asserted, or
32 * -EINVAL if called while running on a non-OMAP2/3 chip. 34 * -EINVAL if called while running on a non-OMAP2/3 chip.
33 */ 35 */
34int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) 36int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
35{ 37{
36 return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, 38 return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
37 (1 << shift)); 39 (1 << shift));
@@ -39,8 +41,10 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
39 41
40/** 42/**
41 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule 43 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
42 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
43 * @shift: register bit shift corresponding to the reset line to assert 44 * @shift: register bit shift corresponding to the reset line to assert
45 * @part: PRM partition, ignored for OMAP2
46 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
47 * @offset: register offset, ignored for OMAP2
44 * 48 *
45 * Some IPs like dsp or iva contain processors that require an HW 49 * Some IPs like dsp or iva contain processors that require an HW
46 * reset line to be asserted / deasserted in order to fully enable the 50 * reset line to be asserted / deasserted in order to fully enable the
@@ -49,7 +53,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
49 * place the submodule into reset. Returns 0 upon success or -EINVAL 53 * place the submodule into reset. Returns 0 upon success or -EINVAL
50 * upon an argument error. 54 * upon an argument error.
51 */ 55 */
52int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) 56int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
53{ 57{
54 u32 mask; 58 u32 mask;
55 59
@@ -64,6 +68,10 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
64 * @prm_mod: PRM submodule base (e.g. CORE_MOD) 68 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
65 * @rst_shift: register bit shift corresponding to the reset line to deassert 69 * @rst_shift: register bit shift corresponding to the reset line to deassert
66 * @st_shift: register bit shift for the status of the deasserted submodule 70 * @st_shift: register bit shift for the status of the deasserted submodule
71 * @part: PRM partition, not used for OMAP2
72 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
73 * @rst_offset: reset register offset, not used for OMAP2
74 * @st_offset: reset status register offset, not used for OMAP2
67 * 75 *
68 * Some IPs like dsp or iva contain processors that require an HW 76 * Some IPs like dsp or iva contain processors that require an HW
69 * reset line to be asserted / deasserted in order to fully enable the 77 * reset line to be asserted / deasserted in order to fully enable the
@@ -74,7 +82,8 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
74 * -EINVAL upon an argument error, -EEXIST if the submodule was already out 82 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
75 * of reset, or -EBUSY if the submodule did not exit reset promptly. 83 * of reset, or -EBUSY if the submodule did not exit reset promptly.
76 */ 84 */
77int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) 85int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
86 s16 prm_mod, u16 rst_offset, u16 st_offset)
78{ 87{
79 u32 rst, st; 88 u32 rst, st;
80 int c; 89 int c;
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 1a3a96392b97..f57e29b0e041 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -100,9 +100,12 @@ static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
100} 100}
101 101
102/* These omap2_ PRM functions apply to both OMAP2 and 3 */ 102/* These omap2_ PRM functions apply to both OMAP2 and 3 */
103extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); 103int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
104extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); 104int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
105extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); 105 u16 offset);
106int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
107 s16 prm_mod, u16 reset_offset,
108 u16 st_offset);
106 109
107extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); 110extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
108extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm); 111extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 62709cd2f9c5..02f628601b09 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -23,20 +23,24 @@
23#include "prm33xx.h" 23#include "prm33xx.h"
24#include "prm-regbits-33xx.h" 24#include "prm-regbits-33xx.h"
25 25
26#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000
27
28#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
29
26/* Read a register in a PRM instance */ 30/* Read a register in a PRM instance */
27u32 am33xx_prm_read_reg(s16 inst, u16 idx) 31static u32 am33xx_prm_read_reg(s16 inst, u16 idx)
28{ 32{
29 return readl_relaxed(prm_base + inst + idx); 33 return readl_relaxed(prm_base + inst + idx);
30} 34}
31 35
32/* Write into a register in a PRM instance */ 36/* Write into a register in a PRM instance */
33void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) 37static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
34{ 38{
35 writel_relaxed(val, prm_base + inst + idx); 39 writel_relaxed(val, prm_base + inst + idx);
36} 40}
37 41
38/* Read-modify-write a register in PRM. Caller must lock */ 42/* Read-modify-write a register in PRM. Caller must lock */
39u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) 43static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
40{ 44{
41 u32 v; 45 u32 v;
42 46
@@ -52,6 +56,7 @@ u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
52 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of 56 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
53 * submodules contained in the hwmod module 57 * submodules contained in the hwmod module
54 * @shift: register bit shift corresponding to the reset line to check 58 * @shift: register bit shift corresponding to the reset line to check
59 * @part: PRM partition, ignored for AM33xx
55 * @inst: CM instance register offset (*_INST macro) 60 * @inst: CM instance register offset (*_INST macro)
56 * @rstctrl_offs: RM_RSTCTRL register address offset for this module 61 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
57 * 62 *
@@ -59,7 +64,8 @@ u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
59 * 0 if the (sub)module hardreset line is not currently asserted, or 64 * 0 if the (sub)module hardreset line is not currently asserted, or
60 * -EINVAL upon parameter error. 65 * -EINVAL upon parameter error.
61 */ 66 */
62int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs) 67static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
68 u16 rstctrl_offs)
63{ 69{
64 u32 v; 70 u32 v;
65 71
@@ -73,6 +79,7 @@ int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
73/** 79/**
74 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule 80 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
75 * @shift: register bit shift corresponding to the reset line to assert 81 * @shift: register bit shift corresponding to the reset line to assert
82 * @part: CM partition, ignored for AM33xx
76 * @inst: CM instance register offset (*_INST macro) 83 * @inst: CM instance register offset (*_INST macro)
77 * @rstctrl_reg: RM_RSTCTRL register address for this module 84 * @rstctrl_reg: RM_RSTCTRL register address for this module
78 * 85 *
@@ -83,7 +90,8 @@ int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
83 * place the submodule into reset. Returns 0 upon success or -EINVAL 90 * place the submodule into reset. Returns 0 upon success or -EINVAL
84 * upon an argument error. 91 * upon an argument error.
85 */ 92 */
86int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs) 93static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst,
94 u16 rstctrl_offs)
87{ 95{
88 u32 mask = 1 << shift; 96 u32 mask = 1 << shift;
89 97
@@ -96,6 +104,8 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
96 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and 104 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
97 * wait 105 * wait
98 * @shift: register bit shift corresponding to the reset line to deassert 106 * @shift: register bit shift corresponding to the reset line to deassert
107 * @st_shift: reset status register bit shift corresponding to the reset line
108 * @part: PRM partition, not used for AM33xx
99 * @inst: CM instance register offset (*_INST macro) 109 * @inst: CM instance register offset (*_INST macro)
100 * @rstctrl_reg: RM_RSTCTRL register address for this module 110 * @rstctrl_reg: RM_RSTCTRL register address for this module
101 * @rstst_reg: RM_RSTST register address for this module 111 * @rstst_reg: RM_RSTST register address for this module
@@ -109,14 +119,15 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
109 * -EINVAL upon an argument error, -EEXIST if the submodule was already out 119 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
110 * of reset, or -EBUSY if the submodule did not exit reset promptly. 120 * of reset, or -EBUSY if the submodule did not exit reset promptly.
111 */ 121 */
112int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst, 122static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
113 u16 rstctrl_offs, u16 rstst_offs) 123 s16 inst, u16 rstctrl_offs,
124 u16 rstst_offs)
114{ 125{
115 int c; 126 int c;
116 u32 mask = 1 << st_shift; 127 u32 mask = 1 << st_shift;
117 128
118 /* Check the current status to avoid de-asserting the line twice */ 129 /* Check the current status to avoid de-asserting the line twice */
119 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0) 130 if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0)
120 return -EEXIST; 131 return -EEXIST;
121 132
122 /* Clear the reset status by writing 1 to the status bit */ 133 /* Clear the reset status by writing 1 to the status bit */
@@ -128,7 +139,7 @@ int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
128 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); 139 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
129 140
130 /* wait the status to be set */ 141 /* wait the status to be set */
131 omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst, 142 omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst,
132 rstst_offs), 143 rstst_offs),
133 MAX_MODULE_HARDRESET_WAIT, c); 144 MAX_MODULE_HARDRESET_WAIT, c);
134 145
@@ -325,6 +336,23 @@ static int am33xx_check_vcvp(void)
325 return 0; 336 return 0;
326} 337}
327 338
339/**
340 * am33xx_prm_global_warm_sw_reset - reboot the device via warm reset
341 *
342 * Immediately reboots the device through warm reset.
343 */
344static void am33xx_prm_global_warm_sw_reset(void)
345{
346 am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK,
347 AM33XX_RST_GLOBAL_WARM_SW_MASK,
348 AM33XX_PRM_DEVICE_MOD,
349 AM33XX_PRM_RSTCTRL_OFFSET);
350
351 /* OCP barrier */
352 (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
353 AM33XX_PRM_RSTCTRL_OFFSET);
354}
355
328struct pwrdm_ops am33xx_pwrdm_operations = { 356struct pwrdm_ops am33xx_pwrdm_operations = {
329 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, 357 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
330 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, 358 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
@@ -342,3 +370,21 @@ struct pwrdm_ops am33xx_pwrdm_operations = {
342 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, 370 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
343 .pwrdm_has_voltdm = am33xx_check_vcvp, 371 .pwrdm_has_voltdm = am33xx_check_vcvp,
344}; 372};
373
374static struct prm_ll_data am33xx_prm_ll_data = {
375 .assert_hardreset = am33xx_prm_assert_hardreset,
376 .deassert_hardreset = am33xx_prm_deassert_hardreset,
377 .is_hardreset_asserted = am33xx_prm_is_hardreset_asserted,
378 .reset_system = am33xx_prm_global_warm_sw_reset,
379};
380
381int __init am33xx_prm_init(void)
382{
383 return prm_register(&am33xx_prm_ll_data);
384}
385
386static void __exit am33xx_prm_exit(void)
387{
388 prm_unregister(&am33xx_prm_ll_data);
389}
390__exitcall(am33xx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 9b9918dfb119..98ac41f271da 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -118,14 +118,7 @@
118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) 118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
119 119
120#ifndef __ASSEMBLER__ 120#ifndef __ASSEMBLER__
121extern u32 am33xx_prm_read_reg(s16 inst, u16 idx); 121int am33xx_prm_init(void);
122extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx); 122
123extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
124extern void am33xx_prm_global_warm_sw_reset(void);
125extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
126 u16 rstctrl_offs);
127extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
128extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
129 u16 rstctrl_offs, u16 rstst_offs);
130#endif /* ASSEMBLER */ 123#endif /* ASSEMBLER */
131#endif 124#endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index ff08da385a2d..c5e00c6714b1 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -30,6 +30,11 @@
30#include "cm3xxx.h" 30#include "cm3xxx.h"
31#include "cm-regbits-34xx.h" 31#include "cm-regbits-34xx.h"
32 32
33static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
34static void omap3xxx_prm_ocp_barrier(void);
35static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
36static void omap3xxx_prm_restore_irqen(u32 *saved_mask);
37
33static const struct omap_prcm_irq omap3_prcm_irqs[] = { 38static const struct omap_prcm_irq omap3_prcm_irqs[] = {
34 OMAP_PRCM_IRQ("wkup", 0, 0), 39 OMAP_PRCM_IRQ("wkup", 0, 0),
35 OMAP_PRCM_IRQ("io", 9, 1), 40 OMAP_PRCM_IRQ("io", 9, 1),
@@ -131,7 +136,7 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
131 * recommended way to restart the SoC, considering Errata i520. No 136 * recommended way to restart the SoC, considering Errata i520. No
132 * return value. 137 * return value.
133 */ 138 */
134void omap3xxx_prm_dpll3_reset(void) 139static void omap3xxx_prm_dpll3_reset(void)
135{ 140{
136 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD, 141 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD,
137 OMAP2_RM_RSTCTRL); 142 OMAP2_RM_RSTCTRL);
@@ -147,7 +152,7 @@ void omap3xxx_prm_dpll3_reset(void)
147 * MPU IRQs, and store the result into the u32 pointed to by @events. 152 * MPU IRQs, and store the result into the u32 pointed to by @events.
148 * No return value. 153 * No return value.
149 */ 154 */
150void omap3xxx_prm_read_pending_irqs(unsigned long *events) 155static void omap3xxx_prm_read_pending_irqs(unsigned long *events)
151{ 156{
152 u32 mask, st; 157 u32 mask, st;
153 158
@@ -166,7 +171,7 @@ void omap3xxx_prm_read_pending_irqs(unsigned long *events)
166 * block, to avoid race conditions after acknowledging or clearing IRQ 171 * block, to avoid race conditions after acknowledging or clearing IRQ
167 * bits. No return value. 172 * bits. No return value.
168 */ 173 */
169void omap3xxx_prm_ocp_barrier(void) 174static void omap3xxx_prm_ocp_barrier(void)
170{ 175{
171 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); 176 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
172} 177}
@@ -182,7 +187,7 @@ void omap3xxx_prm_ocp_barrier(void)
182 * returning; otherwise, spurious interrupts might occur. No return 187 * returning; otherwise, spurious interrupts might occur. No return
183 * value. 188 * value.
184 */ 189 */
185void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask) 190static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
186{ 191{
187 saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD, 192 saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
188 OMAP3_PRM_IRQENABLE_MPU_OFFSET); 193 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
@@ -202,7 +207,7 @@ void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
202 * barrier should be needed here; any pending PRM interrupts will fire 207 * barrier should be needed here; any pending PRM interrupts will fire
203 * once the writes reach the PRM. No return value. 208 * once the writes reach the PRM. No return value.
204 */ 209 */
205void omap3xxx_prm_restore_irqen(u32 *saved_mask) 210static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
206{ 211{
207 omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD, 212 omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
208 OMAP3_PRM_IRQENABLE_MPU_OFFSET); 213 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
@@ -375,7 +380,7 @@ void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
375 * The ST_IO_CHAIN bit does not exist in 3430 before es3.1. The only 380 * The ST_IO_CHAIN bit does not exist in 3430 before es3.1. The only
376 * thing we can do is toggle EN_IO bit for earlier omaps. 381 * thing we can do is toggle EN_IO bit for earlier omaps.
377 */ 382 */
378void omap3430_pre_es3_1_reconfigure_io_chain(void) 383static void omap3430_pre_es3_1_reconfigure_io_chain(void)
379{ 384{
380 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 385 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
381 PM_WKEN); 386 PM_WKEN);
@@ -393,7 +398,7 @@ void omap3430_pre_es3_1_reconfigure_io_chain(void)
393 * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No 398 * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No
394 * return value. These registers are only available in 3430 es3.1 and later. 399 * return value. These registers are only available in 3430 es3.1 and later.
395 */ 400 */
396void omap3_prm_reconfigure_io_chain(void) 401static void omap3_prm_reconfigure_io_chain(void)
397{ 402{
398 int i = 0; 403 int i = 0;
399 404
@@ -416,15 +421,6 @@ void omap3_prm_reconfigure_io_chain(void)
416} 421}
417 422
418/** 423/**
419 * omap3xxx_prm_reconfigure_io_chain - reconfigure I/O chain
420 */
421void omap3xxx_prm_reconfigure_io_chain(void)
422{
423 if (omap3_prcm_irq_setup.reconfigure_io_chain)
424 omap3_prcm_irq_setup.reconfigure_io_chain();
425}
426
427/**
428 * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches 424 * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
429 * 425 *
430 * Activates the I/O wakeup event latches and allows events logged by 426 * Activates the I/O wakeup event latches and allows events logged by
@@ -664,6 +660,10 @@ static int omap3xxx_prm_late_init(void);
664static struct prm_ll_data omap3xxx_prm_ll_data = { 660static struct prm_ll_data omap3xxx_prm_ll_data = {
665 .read_reset_sources = &omap3xxx_prm_read_reset_sources, 661 .read_reset_sources = &omap3xxx_prm_read_reset_sources,
666 .late_init = &omap3xxx_prm_late_init, 662 .late_init = &omap3xxx_prm_late_init,
663 .assert_hardreset = &omap2_prm_assert_hardreset,
664 .deassert_hardreset = &omap2_prm_deassert_hardreset,
665 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
666 .reset_system = &omap3xxx_prm_dpll3_reset,
667}; 667};
668 668
669int __init omap3xxx_prm_init(void) 669int __init omap3xxx_prm_init(void)
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index bc37d42a8704..cfde3f4a03cc 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -144,22 +144,6 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
144extern void omap3_prm_vcvp_write(u32 val, u8 offset); 144extern void omap3_prm_vcvp_write(u32 val, u8 offset);
145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
146 146
147#ifdef CONFIG_ARCH_OMAP3
148void omap3xxx_prm_reconfigure_io_chain(void);
149#else
150static inline void omap3xxx_prm_reconfigure_io_chain(void)
151{
152}
153#endif
154
155/* PRM interrupt-related functions */
156extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
157extern void omap3xxx_prm_ocp_barrier(void);
158extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
159extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
160
161extern void omap3xxx_prm_dpll3_reset(void);
162
163extern int __init omap3xxx_prm_init(void); 147extern int __init omap3xxx_prm_init(void);
164extern u32 omap3xxx_prm_get_reset_sources(void); 148extern u32 omap3xxx_prm_get_reset_sources(void);
165int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits); 149int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 0958d070d3db..cc170fb81ff7 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -32,6 +32,12 @@
32 32
33/* Static data */ 33/* Static data */
34 34
35static void omap44xx_prm_read_pending_irqs(unsigned long *events);
36static void omap44xx_prm_ocp_barrier(void);
37static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
38static void omap44xx_prm_restore_irqen(u32 *saved_mask);
39static void omap44xx_prm_reconfigure_io_chain(void);
40
35static const struct omap_prcm_irq omap4_prcm_irqs[] = { 41static const struct omap_prcm_irq omap4_prcm_irqs[] = {
36 OMAP_PRCM_IRQ("io", 9, 1), 42 OMAP_PRCM_IRQ("io", 9, 1),
37}; 43};
@@ -80,19 +86,19 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
80/* PRM low-level functions */ 86/* PRM low-level functions */
81 87
82/* Read a register in a CM/PRM instance in the PRM module */ 88/* Read a register in a CM/PRM instance in the PRM module */
83u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) 89static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
84{ 90{
85 return readl_relaxed(prm_base + inst + reg); 91 return readl_relaxed(prm_base + inst + reg);
86} 92}
87 93
88/* Write into a register in a CM/PRM instance in the PRM module */ 94/* Write into a register in a CM/PRM instance in the PRM module */
89void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) 95static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
90{ 96{
91 writel_relaxed(val, prm_base + inst + reg); 97 writel_relaxed(val, prm_base + inst + reg);
92} 98}
93 99
94/* Read-modify-write a register in a PRM module. Caller must lock */ 100/* Read-modify-write a register in a PRM module. Caller must lock */
95u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) 101static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
96{ 102{
97 u32 v; 103 u32 v;
98 104
@@ -207,7 +213,7 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
207 * MPU IRQs, and store the result into the two u32s pointed to by @events. 213 * MPU IRQs, and store the result into the two u32s pointed to by @events.
208 * No return value. 214 * No return value.
209 */ 215 */
210void omap44xx_prm_read_pending_irqs(unsigned long *events) 216static void omap44xx_prm_read_pending_irqs(unsigned long *events)
211{ 217{
212 events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, 218 events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
213 OMAP4_PRM_IRQSTATUS_MPU_OFFSET); 219 OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
@@ -224,7 +230,7 @@ void omap44xx_prm_read_pending_irqs(unsigned long *events)
224 * block, to avoid race conditions after acknowledging or clearing IRQ 230 * block, to avoid race conditions after acknowledging or clearing IRQ
225 * bits. No return value. 231 * bits. No return value.
226 */ 232 */
227void omap44xx_prm_ocp_barrier(void) 233static void omap44xx_prm_ocp_barrier(void)
228{ 234{
229 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 235 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
230 OMAP4_REVISION_PRM_OFFSET); 236 OMAP4_REVISION_PRM_OFFSET);
@@ -241,7 +247,7 @@ void omap44xx_prm_ocp_barrier(void)
241 * interrupts reaches the PRM before returning; otherwise, spurious 247 * interrupts reaches the PRM before returning; otherwise, spurious
242 * interrupts might occur. No return value. 248 * interrupts might occur. No return value.
243 */ 249 */
244void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) 250static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
245{ 251{
246 saved_mask[0] = 252 saved_mask[0] =
247 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 253 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
@@ -270,7 +276,7 @@ void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
270 * No OCP barrier should be needed here; any pending PRM interrupts will fire 276 * No OCP barrier should be needed here; any pending PRM interrupts will fire
271 * once the writes reach the PRM. No return value. 277 * once the writes reach the PRM. No return value.
272 */ 278 */
273void omap44xx_prm_restore_irqen(u32 *saved_mask) 279static void omap44xx_prm_restore_irqen(u32 *saved_mask)
274{ 280{
275 omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST, 281 omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
276 OMAP4_PRM_IRQENABLE_MPU_OFFSET); 282 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
@@ -287,7 +293,7 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
287 * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted. 293 * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
288 * No return value. XXX Are the final two steps necessary? 294 * No return value. XXX Are the final two steps necessary?
289 */ 295 */
290void omap44xx_prm_reconfigure_io_chain(void) 296static void omap44xx_prm_reconfigure_io_chain(void)
291{ 297{
292 int i = 0; 298 int i = 0;
293 s32 inst = omap4_prmst_get_prm_dev_inst(); 299 s32 inst = omap4_prmst_get_prm_dev_inst();
@@ -652,11 +658,10 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
652 658
653static int omap4_check_vcvp(void) 659static int omap4_check_vcvp(void)
654{ 660{
655 /* No VC/VP on dra7xx devices */ 661 if (prm_features & PRM_HAS_VOLTAGE)
656 if (soc_is_dra7xx()) 662 return 1;
657 return 0;
658 663
659 return 1; 664 return 0;
660} 665}
661 666
662struct pwrdm_ops omap4_pwrdm_operations = { 667struct pwrdm_ops omap4_pwrdm_operations = {
@@ -689,6 +694,10 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
689 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, 694 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
690 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, 695 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
691 .late_init = &omap44xx_prm_late_init, 696 .late_init = &omap44xx_prm_late_init,
697 .assert_hardreset = omap4_prminst_assert_hardreset,
698 .deassert_hardreset = omap4_prminst_deassert_hardreset,
699 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
700 .reset_system = omap4_prminst_global_warm_sw_reset,
692}; 701};
693 702
694int __init omap44xx_prm_init(void) 703int __init omap44xx_prm_init(void)
@@ -696,6 +705,9 @@ int __init omap44xx_prm_init(void)
696 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) 705 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
697 prm_features |= PRM_HAS_IO_WAKEUP; 706 prm_features |= PRM_HAS_IO_WAKEUP;
698 707
708 if (!soc_is_dra7xx())
709 prm_features |= PRM_HAS_VOLTAGE;
710
699 return prm_register(&omap44xx_prm_ll_data); 711 return prm_register(&omap44xx_prm_ll_data);
700} 712}
701 713
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 8d95aa543ef5..f7512515fde5 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -26,10 +26,6 @@
26/* Function prototypes */ 26/* Function prototypes */
27#ifndef __ASSEMBLER__ 27#ifndef __ASSEMBLER__
28 28
29extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
30extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
31extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
32
33/* OMAP4/OMAP5-specific VP functions */ 29/* OMAP4/OMAP5-specific VP functions */
34u32 omap4_prm_vp_check_txdone(u8 vp_id); 30u32 omap4_prm_vp_check_txdone(u8 vp_id);
35void omap4_prm_vp_clear_txdone(u8 vp_id); 31void omap4_prm_vp_clear_txdone(u8 vp_id);
@@ -42,21 +38,6 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
42extern void omap4_prm_vcvp_write(u32 val, u8 offset); 38extern void omap4_prm_vcvp_write(u32 val, u8 offset);
43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 39extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
44 40
45#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
46 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
47void omap44xx_prm_reconfigure_io_chain(void);
48#else
49static inline void omap44xx_prm_reconfigure_io_chain(void)
50{
51}
52#endif
53
54/* PRM interrupt-related functions */
55extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
56extern void omap44xx_prm_ocp_barrier(void);
57extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
58extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
59
60extern int __init omap44xx_prm_init(void); 41extern int __init omap44xx_prm_init(void);
61extern u32 omap44xx_prm_get_reset_sources(void); 42extern u32 omap44xx_prm_get_reset_sources(void);
62 43
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index ee2b5222eac0..779940cb6e56 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -423,6 +423,105 @@ void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
423} 423}
424 424
425/** 425/**
426 * omap_prm_assert_hardreset - assert hardreset for an IP block
427 * @shift: register bit shift corresponding to the reset line
428 * @part: PRM partition
429 * @prm_mod: PRM submodule base or instance offset
430 * @offset: register offset
431 *
432 * Asserts a hardware reset line for an IP block.
433 */
434int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
435{
436 if (!prm_ll_data->assert_hardreset) {
437 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
438 __func__);
439 return -EINVAL;
440 }
441
442 return prm_ll_data->assert_hardreset(shift, part, prm_mod, offset);
443}
444
445/**
446 * omap_prm_deassert_hardreset - deassert hardreset for an IP block
447 * @shift: register bit shift corresponding to the reset line
448 * @st_shift: reset status bit shift corresponding to the reset line
449 * @part: PRM partition
450 * @prm_mod: PRM submodule base or instance offset
451 * @offset: register offset
452 * @st_offset: status register offset
453 *
454 * Deasserts a hardware reset line for an IP block.
455 */
456int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
457 u16 offset, u16 st_offset)
458{
459 if (!prm_ll_data->deassert_hardreset) {
460 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
461 __func__);
462 return -EINVAL;
463 }
464
465 return prm_ll_data->deassert_hardreset(shift, st_shift, part, prm_mod,
466 offset, st_offset);
467}
468
469/**
470 * omap_prm_is_hardreset_asserted - check the hardreset status for an IP block
471 * @shift: register bit shift corresponding to the reset line
472 * @part: PRM partition
473 * @prm_mod: PRM submodule base or instance offset
474 * @offset: register offset
475 *
476 * Checks if a hardware reset line for an IP block is enabled or not.
477 */
478int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
479{
480 if (!prm_ll_data->is_hardreset_asserted) {
481 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
482 __func__);
483 return -EINVAL;
484 }
485
486 return prm_ll_data->is_hardreset_asserted(shift, part, prm_mod, offset);
487}
488
489/**
490 * omap_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
491 *
492 * Clear any previously-latched I/O wakeup events and ensure that the
493 * I/O wakeup gates are aligned with the current mux settings.
494 * Calls SoC specific I/O chain reconfigure function if available,
495 * otherwise does nothing.
496 */
497void omap_prm_reconfigure_io_chain(void)
498{
499 if (!prcm_irq_setup || !prcm_irq_setup->reconfigure_io_chain)
500 return;
501
502 prcm_irq_setup->reconfigure_io_chain();
503}
504
505/**
506 * omap_prm_reset_system - trigger global SW reset
507 *
508 * Triggers SoC specific global warm reset to reboot the device.
509 */
510void omap_prm_reset_system(void)
511{
512 if (!prm_ll_data->reset_system) {
513 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
514 __func__);
515 return;
516 }
517
518 prm_ll_data->reset_system();
519
520 while (1)
521 cpu_relax();
522}
523
524/**
426 * prm_register - register per-SoC low-level data with the PRM 525 * prm_register - register per-SoC low-level data with the PRM
427 * @pld: low-level per-SoC OMAP PRM data & function pointers to register 526 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
428 * 527 *
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 225e0258d76d..8adf7b1a1dce 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -148,8 +148,12 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
148/** 148/**
149 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and 149 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
150 * wait 150 * wait
151 * @rstctrl_reg: RM_RSTCTRL register address for this module
152 * @shift: register bit shift corresponding to the reset line to deassert 151 * @shift: register bit shift corresponding to the reset line to deassert
152 * @st_shift: status bit offset, not used for OMAP4+
153 * @part: PRM partition
154 * @inst: PRM instance offset
155 * @rstctrl_offs: reset register offset
156 * @st_offs: reset status register offset, not used for OMAP4+
153 * 157 *
154 * Some IPs like dsp, ipu or iva contain processors that require an HW 158 * Some IPs like dsp, ipu or iva contain processors that require an HW
155 * reset line to be asserted / deasserted in order to fully enable the 159 * reset line to be asserted / deasserted in order to fully enable the
@@ -160,8 +164,8 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
160 * -EINVAL upon an argument error, -EEXIST if the submodule was already out 164 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
161 * of reset, or -EBUSY if the submodule did not exit reset promptly. 165 * of reset, or -EBUSY if the submodule did not exit reset promptly.
162 */ 166 */
163int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst, 167int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
164 u16 rstctrl_offs) 168 u16 rstctrl_offs, u16 st_offs)
165{ 169{
166 int c; 170 int c;
167 u32 mask = 1 << shift; 171 u32 mask = 1 << shift;
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index 583aa3774571..fb1c9d7a2f9d 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -30,8 +30,9 @@ extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
30 u16 rstctrl_offs); 30 u16 rstctrl_offs);
31extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst, 31extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
32 u16 rstctrl_offs); 32 u16 rstctrl_offs);
33extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst, 33int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
34 u16 rstctrl_offs); 34 s16 inst, u16 rstctrl_offs,
35 u16 rstst_offs);
35 36
36extern void omap_prm_base_init(void); 37extern void omap_prm_base_init(void);
37 38
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-27 07:28:45 -0400