2 files changed, 11 insertions, 1 deletions

diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 9ec0b39f9ddc..28cdbd9f399c 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -548,6 +548,9 @@
 #define L1CSR1_ICFI     0x00000002      /* Instr Cache Flash Invalidate */
 #define L1CSR1_ICE      0x00000001      /* Instr Cache Enable */
 
+/* Bit definitions for L1CSR2. */
+#define L1CSR2_DCWS     0x40000000      /* Data Cache write shadow */
+
 /* Bit definitions for L2CSR0. */
 #define L2CSR0_L2E      0x80000000      /* L2 Cache Enable */
 #define L2CSR0_L2PE     0x40000000      /* L2 Cache Parity/ECC Enable */
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f19d9777d3c1..4e5908264d1a 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -457,7 +457,14 @@ int machine_check_e500mc(struct pt_regs *regs)
 
         if (reason & MCSR_DCPERR_MC) {
                 printk("Data Cache Parity Error\n");
-                recoverable = 0;
+
+                /*
+                 * In write shadow mode we auto-recover from the error, but it
+                 * may still get logged and cause a machine check.  We should
+                 * only treat the non-write shadow case as non-recoverable.
+                 */
+                if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
+                        recoverable = 0;
         }
 
         if (reason & MCSR_L2MMU_MHIT) {