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-rw-r--r--drivers/gpu/drm/i915/i915_irq.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b31e7ca614bf..5c3baa0ec049 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2574,7 +2574,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
2574{ 2574{
2575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2576 u32 enable_mask; 2576 u32 enable_mask;
2577 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; 2577 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2578 PIPE_CRC_DONE_ENABLE;
2578 unsigned long irqflags; 2579 unsigned long irqflags;
2579 2580
2580 enable_mask = I915_DISPLAY_PORT_INTERRUPT; 2581 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
@@ -2697,6 +2698,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
2697static int i8xx_irq_postinstall(struct drm_device *dev) 2698static int i8xx_irq_postinstall(struct drm_device *dev)
2698{ 2699{
2699 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2700 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2701 unsigned long irqflags;
2700 2702
2701 I915_WRITE16(EMR, 2703 I915_WRITE16(EMR,
2702 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 2704 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -2717,6 +2719,13 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
2717 I915_USER_INTERRUPT); 2719 I915_USER_INTERRUPT);
2718 POSTING_READ16(IER); 2720 POSTING_READ16(IER);
2719 2721
2722 /* Interrupt setup is already guaranteed to be single-threaded, this is
2723 * just to make the assert_spin_locked check happy. */
2724 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2725 i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
2726 i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
2727 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2728
2720 return 0; 2729 return 0;
2721} 2730}
2722 2731
@@ -2857,6 +2866,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
2857{ 2866{
2858 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2867 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2859 u32 enable_mask; 2868 u32 enable_mask;
2869 unsigned long irqflags;
2860 2870
2861 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 2871 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2862 2872
@@ -2892,6 +2902,13 @@ static int i915_irq_postinstall(struct drm_device *dev)
2892 2902
2893 i915_enable_asle_pipestat(dev); 2903 i915_enable_asle_pipestat(dev);
2894 2904
2905 /* Interrupt setup is already guaranteed to be single-threaded, this is
2906 * just to make the assert_spin_locked check happy. */
2907 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2908 i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
2909 i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
2910 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2911
2895 return 0; 2912 return 0;
2896} 2913}
2897 2914
@@ -3105,6 +3122,8 @@ static int i965_irq_postinstall(struct drm_device *dev)
3105 * just to make the assert_spin_locked check happy. */ 3122 * just to make the assert_spin_locked check happy. */
3106 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3123 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3107 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); 3124 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
3125 i915_enable_pipestat(dev_priv, 0, PIPE_CRC_DONE_ENABLE);
3126 i915_enable_pipestat(dev_priv, 1, PIPE_CRC_DONE_ENABLE);
3108 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3127 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3109 3128
3110 /* 3129 /*