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-rw-r--r--drivers/spi/Kconfig10
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-bcm2835.c10
-rw-r--r--drivers/spi/spi-bcm63xx-hsspi.c475
-rw-r--r--drivers/spi/spi-bcm63xx.c46
-rw-r--r--drivers/spi/spi-bitbang-txrx.h2
-rw-r--r--drivers/spi/spi-clps711x.c23
-rw-r--r--drivers/spi/spi-coldfire-qspi.c53
-rw-r--r--drivers/spi/spi-davinci.c49
-rw-r--r--drivers/spi/spi-dw-mmio.c74
-rw-r--r--drivers/spi/spi-dw-pci.c45
-rw-r--r--drivers/spi/spi-dw.c26
-rw-r--r--drivers/spi/spi-dw.h5
-rw-r--r--drivers/spi/spi-falcon.c12
-rw-r--r--drivers/spi/spi-fsl-dspi.c3
-rw-r--r--drivers/spi/spi-mxs.c9
-rw-r--r--drivers/spi/spi-rspi.c356
-rw-r--r--drivers/spi/spi-sc18is602.c16
-rw-r--r--drivers/spi/spi-sh.c3
-rw-r--r--drivers/spi/spi-sirf.c7
-rw-r--r--drivers/spi/spi-topcliff-pch.c6
21 files changed, 771 insertions, 460 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index eb1f1ef5fa2e..94964af1428d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -118,6 +118,13 @@ config SPI_BCM63XX
118 help 118 help
119 Enable support for the SPI controller on the Broadcom BCM63xx SoCs. 119 Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
120 120
121config SPI_BCM63XX_HSSPI
122 tristate "Broadcom BCM63XX HS SPI controller driver"
123 depends on BCM63XX || COMPILE_TEST
124 help
125 This enables support for the High Speed SPI controller present on
126 newer Broadcom BCM63XX SoCs.
127
121config SPI_BITBANG 128config SPI_BITBANG
122 tristate "Utilities for Bitbanging SPI masters" 129 tristate "Utilities for Bitbanging SPI masters"
123 help 130 help
@@ -159,7 +166,6 @@ config SPI_DAVINCI
159 tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller" 166 tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller"
160 depends on ARCH_DAVINCI || ARCH_KEYSTONE 167 depends on ARCH_DAVINCI || ARCH_KEYSTONE
161 select SPI_BITBANG 168 select SPI_BITBANG
162 select TI_EDMA
163 help 169 help
164 SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules. 170 SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
165 171
@@ -370,7 +376,7 @@ config SPI_PXA2XX_PCI
370 376
371config SPI_RSPI 377config SPI_RSPI
372 tristate "Renesas RSPI controller" 378 tristate "Renesas RSPI controller"
373 depends on (SUPERH || ARCH_SHMOBILE) && SH_DMAE_BASE 379 depends on (SUPERH && SH_DMAE_BASE) || ARCH_SHMOBILE
374 help 380 help
375 SPI driver for Renesas RSPI blocks. 381 SPI driver for Renesas RSPI blocks.
376 382
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ab8d8644af0e..95af48d2d360 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o 16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o 17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
18obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o 18obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
19obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
19obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o 20obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
20obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o 21obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o
21obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o 22obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 9025edd7dc45..8a89dd1f2654 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -347,8 +347,8 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
347 347
348 clk_prepare_enable(bs->clk); 348 clk_prepare_enable(bs->clk);
349 349
350 err = request_irq(bs->irq, bcm2835_spi_interrupt, 0, 350 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
351 dev_name(&pdev->dev), master); 351 dev_name(&pdev->dev), master);
352 if (err) { 352 if (err) {
353 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 353 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
354 goto out_clk_disable; 354 goto out_clk_disable;
@@ -361,13 +361,11 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
361 err = devm_spi_register_master(&pdev->dev, master); 361 err = devm_spi_register_master(&pdev->dev, master);
362 if (err) { 362 if (err) {
363 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 363 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
364 goto out_free_irq; 364 goto out_clk_disable;
365 } 365 }
366 366
367 return 0; 367 return 0;
368 368
369out_free_irq:
370 free_irq(bs->irq, master);
371out_clk_disable: 369out_clk_disable:
372 clk_disable_unprepare(bs->clk); 370 clk_disable_unprepare(bs->clk);
373out_master_put: 371out_master_put:
@@ -380,8 +378,6 @@ static int bcm2835_spi_remove(struct platform_device *pdev)
380 struct spi_master *master = platform_get_drvdata(pdev); 378 struct spi_master *master = platform_get_drvdata(pdev);
381 struct bcm2835_spi *bs = spi_master_get_devdata(master); 379 struct bcm2835_spi *bs = spi_master_get_devdata(master);
382 380
383 free_irq(bs->irq, master);
384
385 /* Clear FIFOs, and disable the HW block */ 381 /* Clear FIFOs, and disable the HW block */
386 bcm2835_wr(bs, BCM2835_SPI_CS, 382 bcm2835_wr(bs, BCM2835_SPI_CS,
387 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 383 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c
new file mode 100644
index 000000000000..b528f9fc8bc0
--- /dev/null
+++ b/drivers/spi/spi-bcm63xx-hsspi.c
@@ -0,0 +1,475 @@
1/*
2 * Broadcom BCM63XX High Speed SPI Controller driver
3 *
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21#include <linux/workqueue.h>
22#include <linux/mutex.h>
23
24#define HSSPI_GLOBAL_CTRL_REG 0x0
25#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
26#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
27#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
28#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
29#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
30#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
31#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
32
33#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
34
35#define HSSPI_INT_STATUS_REG 0x8
36#define HSSPI_INT_STATUS_MASKED_REG 0xc
37#define HSSPI_INT_MASK_REG 0x10
38
39#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
40#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
41#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
42#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
43#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
44
45#define HSSPI_INT_CLEAR_ALL 0xff001f1f
46
47#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
48#define PINGPONG_CMD_COMMAND_MASK 0xf
49#define PINGPONG_COMMAND_NOOP 0
50#define PINGPONG_COMMAND_START_NOW 1
51#define PINGPONG_COMMAND_START_TRIGGER 2
52#define PINGPONG_COMMAND_HALT 3
53#define PINGPONG_COMMAND_FLUSH 4
54#define PINGPONG_CMD_PROFILE_SHIFT 8
55#define PINGPONG_CMD_SS_SHIFT 12
56
57#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
58
59#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
60#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
61#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
62#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
63
64#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
65#define SIGNAL_CTRL_LATCH_RISING BIT(12)
66#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
67#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
68
69#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
70#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
71#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
72#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
73#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
74#define MODE_CTRL_MODE_3WIRE BIT(20)
75#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
76
77#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
78
79
80#define HSSPI_OP_CODE_SHIFT 13
81#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
82#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
83#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
84#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
85#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
86
87#define HSSPI_BUFFER_LEN 512
88#define HSSPI_OPCODE_LEN 2
89
90#define HSSPI_MAX_PREPEND_LEN 15
91
92#define HSSPI_MAX_SYNC_CLOCK 30000000
93
94#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
95
96struct bcm63xx_hsspi {
97 struct completion done;
98 struct mutex bus_mutex;
99
100 struct platform_device *pdev;
101 struct clk *clk;
102 void __iomem *regs;
103 u8 __iomem *fifo;
104
105 u32 speed_hz;
106 u8 cs_polarity;
107};
108
109static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs,
110 bool active)
111{
112 u32 reg;
113
114 mutex_lock(&bs->bus_mutex);
115 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
116
117 reg &= ~BIT(cs);
118 if (active == !(bs->cs_polarity & BIT(cs)))
119 reg |= BIT(cs);
120
121 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
122 mutex_unlock(&bs->bus_mutex);
123}
124
125static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
126 struct spi_device *spi, int hz)
127{
128 unsigned profile = spi->chip_select;
129 u32 reg;
130
131 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
132 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
133 bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
134
135 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
136 if (hz > HSSPI_MAX_SYNC_CLOCK)
137 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
138 else
139 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
140 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
141
142 mutex_lock(&bs->bus_mutex);
143 /* setup clock polarity */
144 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
145 reg &= ~GLOBAL_CTRL_CLK_POLARITY;
146 if (spi->mode & SPI_CPOL)
147 reg |= GLOBAL_CTRL_CLK_POLARITY;
148 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
149 mutex_unlock(&bs->bus_mutex);
150}
151
152static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
153{
154 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
155 unsigned chip_select = spi->chip_select;
156 u16 opcode = 0;
157 int pending = t->len;
158 int step_size = HSSPI_BUFFER_LEN;
159 const u8 *tx = t->tx_buf;
160 u8 *rx = t->rx_buf;
161
162 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
163 bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
164
165 if (tx && rx)
166 opcode = HSSPI_OP_READ_WRITE;
167 else if (tx)
168 opcode = HSSPI_OP_WRITE;
169 else if (rx)
170 opcode = HSSPI_OP_READ;
171
172 if (opcode != HSSPI_OP_READ)
173 step_size -= HSSPI_OPCODE_LEN;
174
175 __raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
176 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
177 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
178 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
179
180 while (pending > 0) {
181 int curr_step = min_t(int, step_size, pending);
182
183 init_completion(&bs->done);
184 if (tx) {
185 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
186 tx += curr_step;
187 }
188
189 __raw_writew(opcode | curr_step, bs->fifo);
190
191 /* enable interrupt */
192 __raw_writel(HSSPI_PINGx_CMD_DONE(0),
193 bs->regs + HSSPI_INT_MASK_REG);
194
195 /* start the transfer */
196 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
197 chip_select << PINGPONG_CMD_PROFILE_SHIFT |
198 PINGPONG_COMMAND_START_NOW,
199 bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
200
201 if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
202 dev_err(&bs->pdev->dev, "transfer timed out!\n");
203 return -ETIMEDOUT;
204 }
205
206 if (rx) {
207 memcpy_fromio(rx, bs->fifo, curr_step);
208 rx += curr_step;
209 }
210
211 pending -= curr_step;
212 }
213
214 return 0;
215}
216
217static int bcm63xx_hsspi_setup(struct spi_device *spi)
218{
219 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
220 u32 reg;
221
222 reg = __raw_readl(bs->regs +
223 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
224 reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
225 if (spi->mode & SPI_CPHA)
226 reg |= SIGNAL_CTRL_LAUNCH_RISING;
227 else
228 reg |= SIGNAL_CTRL_LATCH_RISING;
229 __raw_writel(reg, bs->regs +
230 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
231
232 mutex_lock(&bs->bus_mutex);
233 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
234
235 /* only change actual polarities if there is no transfer */
236 if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
237 if (spi->mode & SPI_CS_HIGH)
238 reg |= BIT(spi->chip_select);
239 else
240 reg &= ~BIT(spi->chip_select);
241 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
242 }
243
244 if (spi->mode & SPI_CS_HIGH)
245 bs->cs_polarity |= BIT(spi->chip_select);
246 else
247 bs->cs_polarity &= ~BIT(spi->chip_select);
248
249 mutex_unlock(&bs->bus_mutex);
250
251 return 0;
252}
253
254static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
255 struct spi_message *msg)
256{
257 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
258 struct spi_transfer *t;
259 struct spi_device *spi = msg->spi;
260 int status = -EINVAL;
261 int dummy_cs;
262 u32 reg;
263
264 /* This controller does not support keeping CS active during idle.
265 * To work around this, we use the following ugly hack:
266 *
267 * a. Invert the target chip select's polarity so it will be active.
268 * b. Select a "dummy" chip select to use as the hardware target.
269 * c. Invert the dummy chip select's polarity so it will be inactive
270 * during the actual transfers.
271 * d. Tell the hardware to send to the dummy chip select. Thanks to
272 * the multiplexed nature of SPI the actual target will receive
273 * the transfer and we see its response.
274 *
275 * e. At the end restore the polarities again to their default values.
276 */
277
278 dummy_cs = !spi->chip_select;
279 bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
280
281 list_for_each_entry(t, &msg->transfers, transfer_list) {
282 status = bcm63xx_hsspi_do_txrx(spi, t);
283 if (status)
284 break;
285
286 msg->actual_length += t->len;
287
288 if (t->delay_usecs)
289 udelay(t->delay_usecs);
290
291 if (t->cs_change)
292 bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
293 }
294
295 mutex_lock(&bs->bus_mutex);
296 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
297 reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
298 reg |= bs->cs_polarity;
299 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
300 mutex_unlock(&bs->bus_mutex);
301
302 msg->status = status;
303 spi_finalize_current_message(master);
304
305 return 0;
306}
307
308static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
309{
310 struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
311
312 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
313 return IRQ_NONE;
314
315 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
316 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
317
318 complete(&bs->done);
319
320 return IRQ_HANDLED;
321}
322
323static int bcm63xx_hsspi_probe(struct platform_device *pdev)
324{
325 struct spi_master *master;
326 struct bcm63xx_hsspi *bs;
327 struct resource *res_mem;
328 void __iomem *regs;
329 struct device *dev = &pdev->dev;
330 struct clk *clk;
331 int irq, ret;
332 u32 reg, rate;
333
334 irq = platform_get_irq(pdev, 0);
335 if (irq < 0) {
336 dev_err(dev, "no irq\n");
337 return -ENXIO;
338 }
339
340 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341 regs = devm_ioremap_resource(dev, res_mem);
342 if (IS_ERR(regs))
343 return PTR_ERR(regs);
344
345 clk = devm_clk_get(dev, "hsspi");
346
347 if (IS_ERR(clk))
348 return PTR_ERR(clk);
349
350 rate = clk_get_rate(clk);
351 if (!rate)
352 return -EINVAL;
353
354 ret = clk_prepare_enable(clk);
355 if (ret)
356 return ret;
357
358 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
359 if (!master) {
360 ret = -ENOMEM;
361 goto out_disable_clk;
362 }
363
364 bs = spi_master_get_devdata(master);
365 bs->pdev = pdev;
366 bs->clk = clk;
367 bs->regs = regs;
368 bs->speed_hz = rate;
369 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
370
371 mutex_init(&bs->bus_mutex);
372
373 master->bus_num = HSSPI_BUS_NUM;
374 master->num_chipselect = 8;
375 master->setup = bcm63xx_hsspi_setup;
376 master->transfer_one_message = bcm63xx_hsspi_transfer_one;
377 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
378 master->bits_per_word_mask = SPI_BPW_MASK(8);
379 master->auto_runtime_pm = true;
380
381 platform_set_drvdata(pdev, master);
382
383 /* Initialize the hardware */
384 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
385
386 /* clean up any pending interrupts */
387 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
388
389 /* read out default CS polarities */
390 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
391 bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
392 __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
393 bs->regs + HSSPI_GLOBAL_CTRL_REG);
394
395 ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
396 pdev->name, bs);
397
398 if (ret)
399 goto out_put_master;
400
401 /* register and we are done */
402 ret = devm_spi_register_master(dev, master);
403 if (ret)
404 goto out_put_master;
405
406 return 0;
407
408out_put_master:
409 spi_master_put(master);
410out_disable_clk:
411 clk_disable_unprepare(clk);
412 return ret;
413}
414
415
416static int bcm63xx_hsspi_remove(struct platform_device *pdev)
417{
418 struct spi_master *master = platform_get_drvdata(pdev);
419 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
420
421 /* reset the hardware and block queue progress */
422 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
423 clk_disable_unprepare(bs->clk);
424
425 return 0;
426}
427
428#ifdef CONFIG_PM_SLEEP
429static int bcm63xx_hsspi_suspend(struct device *dev)
430{
431 struct spi_master *master = dev_get_drvdata(dev);
432 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
433
434 spi_master_suspend(master);
435 clk_disable_unprepare(bs->clk);
436
437 return 0;
438}
439
440static int bcm63xx_hsspi_resume(struct device *dev)
441{
442 struct spi_master *master = dev_get_drvdata(dev);
443 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
444 int ret;
445
446 ret = clk_prepare_enable(bs->clk);
447 if (ret)
448 return ret;
449
450 spi_master_resume(master);
451
452 return 0;
453}
454#endif
455
456static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = {
457 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_hsspi_suspend, bcm63xx_hsspi_resume)
458};
459
460static struct platform_driver bcm63xx_hsspi_driver = {
461 .driver = {
462 .name = "bcm63xx-hsspi",
463 .owner = THIS_MODULE,
464 .pm = &bcm63xx_hsspi_pm_ops,
465 },
466 .probe = bcm63xx_hsspi_probe,
467 .remove = bcm63xx_hsspi_remove,
468};
469
470module_platform_driver(bcm63xx_hsspi_driver);
471
472MODULE_ALIAS("platform:bcm63xx_hsspi");
473MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
474MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
475MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index dceb7b216f46..77286aef2adf 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -203,13 +203,7 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
203 if (!timeout) 203 if (!timeout)
204 return -ETIMEDOUT; 204 return -ETIMEDOUT;
205 205
206 /* read out all data */ 206 if (!do_rx)
207 rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
208
209 if (do_rx && rx_tail != len)
210 return -EIO;
211
212 if (!rx_tail)
213 return 0; 207 return 0;
214 208
215 len = 0; 209 len = 0;
@@ -343,22 +337,19 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
343 irq = platform_get_irq(pdev, 0); 337 irq = platform_get_irq(pdev, 0);
344 if (irq < 0) { 338 if (irq < 0) {
345 dev_err(dev, "no irq\n"); 339 dev_err(dev, "no irq\n");
346 ret = -ENXIO; 340 return -ENXIO;
347 goto out;
348 } 341 }
349 342
350 clk = clk_get(dev, "spi"); 343 clk = devm_clk_get(dev, "spi");
351 if (IS_ERR(clk)) { 344 if (IS_ERR(clk)) {
352 dev_err(dev, "no clock for device\n"); 345 dev_err(dev, "no clock for device\n");
353 ret = PTR_ERR(clk); 346 return PTR_ERR(clk);
354 goto out;
355 } 347 }
356 348
357 master = spi_alloc_master(dev, sizeof(*bs)); 349 master = spi_alloc_master(dev, sizeof(*bs));
358 if (!master) { 350 if (!master) {
359 dev_err(dev, "out of memory\n"); 351 dev_err(dev, "out of memory\n");
360 ret = -ENOMEM; 352 return -ENOMEM;
361 goto out_clk;
362 } 353 }
363 354
364 bs = spi_master_get_devdata(master); 355 bs = spi_master_get_devdata(master);
@@ -406,7 +397,10 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
406 } 397 }
407 398
408 /* Initialize hardware */ 399 /* Initialize hardware */
409 clk_prepare_enable(bs->clk); 400 ret = clk_prepare_enable(bs->clk);
401 if (ret)
402 goto out_err;
403
410 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 404 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
411 405
412 /* register and we are done */ 406 /* register and we are done */
@@ -425,9 +419,6 @@ out_clk_disable:
425 clk_disable_unprepare(clk); 419 clk_disable_unprepare(clk);
426out_err: 420out_err:
427 spi_master_put(master); 421 spi_master_put(master);
428out_clk:
429 clk_put(clk);
430out:
431 return ret; 422 return ret;
432} 423}
433 424
@@ -441,12 +432,11 @@ static int bcm63xx_spi_remove(struct platform_device *pdev)
441 432
442 /* HW shutdown */ 433 /* HW shutdown */
443 clk_disable_unprepare(bs->clk); 434 clk_disable_unprepare(bs->clk);
444 clk_put(bs->clk);
445 435
446 return 0; 436 return 0;
447} 437}
448 438
449#ifdef CONFIG_PM 439#ifdef CONFIG_PM_SLEEP
450static int bcm63xx_spi_suspend(struct device *dev) 440static int bcm63xx_spi_suspend(struct device *dev)
451{ 441{
452 struct spi_master *master = dev_get_drvdata(dev); 442 struct spi_master *master = dev_get_drvdata(dev);
@@ -463,29 +453,27 @@ static int bcm63xx_spi_resume(struct device *dev)
463{ 453{
464 struct spi_master *master = dev_get_drvdata(dev); 454 struct spi_master *master = dev_get_drvdata(dev);
465 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 455 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
456 int ret;
466 457
467 clk_prepare_enable(bs->clk); 458 ret = clk_prepare_enable(bs->clk);
459 if (ret)
460 return ret;
468 461
469 spi_master_resume(master); 462 spi_master_resume(master);
470 463
471 return 0; 464 return 0;
472} 465}
466#endif
473 467
474static const struct dev_pm_ops bcm63xx_spi_pm_ops = { 468static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
475 .suspend = bcm63xx_spi_suspend, 469 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
476 .resume = bcm63xx_spi_resume,
477}; 470};
478 471
479#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
480#else
481#define BCM63XX_SPI_PM_OPS NULL
482#endif
483
484static struct platform_driver bcm63xx_spi_driver = { 472static struct platform_driver bcm63xx_spi_driver = {
485 .driver = { 473 .driver = {
486 .name = "bcm63xx-spi", 474 .name = "bcm63xx-spi",
487 .owner = THIS_MODULE, 475 .owner = THIS_MODULE,
488 .pm = BCM63XX_SPI_PM_OPS, 476 .pm = &bcm63xx_spi_pm_ops,
489 }, 477 },
490 .probe = bcm63xx_spi_probe, 478 .probe = bcm63xx_spi_probe,
491 .remove = bcm63xx_spi_remove, 479 .remove = bcm63xx_spi_remove,
diff --git a/drivers/spi/spi-bitbang-txrx.h b/drivers/spi/spi-bitbang-txrx.h
index c16bf853c3eb..c616e41521be 100644
--- a/drivers/spi/spi-bitbang-txrx.h
+++ b/drivers/spi/spi-bitbang-txrx.h
@@ -38,7 +38,7 @@
38 * 38 *
39 * Since this is software, the timings may not be exactly what your board's 39 * Since this is software, the timings may not be exactly what your board's
40 * chips need ... there may be several reasons you'd need to tweak timings 40 * chips need ... there may be several reasons you'd need to tweak timings
41 * in these routines, not just make to make it faster or slower to match a 41 * in these routines, not just to make it faster or slower to match a
42 * particular CPU clock rate. 42 * particular CPU clock rate.
43 */ 43 */
44 44
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index 6f03d7e6435d..374ba4a48a9e 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * CLPS711X SPI bus driver 2 * CLPS711X SPI bus driver
3 * 3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 4 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -198,7 +198,7 @@ static int spi_clps711x_probe(struct platform_device *pdev)
198 ret = -EINVAL; 198 ret = -EINVAL;
199 goto err_out; 199 goto err_out;
200 } 200 }
201 if (gpio_request(hw->chipselect[i], DRIVER_NAME)) { 201 if (devm_gpio_request(&pdev->dev, hw->chipselect[i], NULL)) {
202 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i); 202 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
203 ret = -EINVAL; 203 ret = -EINVAL;
204 goto err_out; 204 goto err_out;
@@ -240,38 +240,21 @@ static int spi_clps711x_probe(struct platform_device *pdev)
240 dev_err(&pdev->dev, "Failed to register master\n"); 240 dev_err(&pdev->dev, "Failed to register master\n");
241 241
242err_out: 242err_out:
243 while (--i >= 0)
244 if (gpio_is_valid(hw->chipselect[i]))
245 gpio_free(hw->chipselect[i]);
246
247 spi_master_put(master); 243 spi_master_put(master);
248 244
249 return ret; 245 return ret;
250} 246}
251 247
252static int spi_clps711x_remove(struct platform_device *pdev)
253{
254 int i;
255 struct spi_master *master = platform_get_drvdata(pdev);
256 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
257
258 for (i = 0; i < master->num_chipselect; i++)
259 if (gpio_is_valid(hw->chipselect[i]))
260 gpio_free(hw->chipselect[i]);
261
262 return 0;
263}
264
265static struct platform_driver clps711x_spi_driver = { 248static struct platform_driver clps711x_spi_driver = {
266 .driver = { 249 .driver = {
267 .name = DRIVER_NAME, 250 .name = DRIVER_NAME,
268 .owner = THIS_MODULE, 251 .owner = THIS_MODULE,
269 }, 252 },
270 .probe = spi_clps711x_probe, 253 .probe = spi_clps711x_probe,
271 .remove = spi_clps711x_remove,
272}; 254};
273module_platform_driver(clps711x_spi_driver); 255module_platform_driver(clps711x_spi_driver);
274 256
275MODULE_LICENSE("GPL"); 257MODULE_LICENSE("GPL");
276MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 258MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
277MODULE_DESCRIPTION("CLPS711X SPI bus driver"); 259MODULE_DESCRIPTION("CLPS711X SPI bus driver");
260MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c
index cc5b75d10c38..cabed8f9119e 100644
--- a/drivers/spi/spi-coldfire-qspi.c
+++ b/drivers/spi/spi-coldfire-qspi.c
@@ -397,44 +397,31 @@ static int mcfqspi_probe(struct platform_device *pdev)
397 mcfqspi = spi_master_get_devdata(master); 397 mcfqspi = spi_master_get_devdata(master);
398 398
399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
400 if (!res) { 400 mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
401 dev_dbg(&pdev->dev, "platform_get_resource failed\n"); 401 if (IS_ERR(mcfqspi->iobase)) {
402 status = -ENXIO; 402 status = PTR_ERR(mcfqspi->iobase);
403 goto fail0; 403 goto fail0;
404 } 404 }
405 405
406 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
407 dev_dbg(&pdev->dev, "request_mem_region failed\n");
408 status = -EBUSY;
409 goto fail0;
410 }
411
412 mcfqspi->iobase = ioremap(res->start, resource_size(res));
413 if (!mcfqspi->iobase) {
414 dev_dbg(&pdev->dev, "ioremap failed\n");
415 status = -ENOMEM;
416 goto fail1;
417 }
418
419 mcfqspi->irq = platform_get_irq(pdev, 0); 406 mcfqspi->irq = platform_get_irq(pdev, 0);
420 if (mcfqspi->irq < 0) { 407 if (mcfqspi->irq < 0) {
421 dev_dbg(&pdev->dev, "platform_get_irq failed\n"); 408 dev_dbg(&pdev->dev, "platform_get_irq failed\n");
422 status = -ENXIO; 409 status = -ENXIO;
423 goto fail2; 410 goto fail0;
424 } 411 }
425 412
426 status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, 0, 413 status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
427 pdev->name, mcfqspi); 414 0, pdev->name, mcfqspi);
428 if (status) { 415 if (status) {
429 dev_dbg(&pdev->dev, "request_irq failed\n"); 416 dev_dbg(&pdev->dev, "request_irq failed\n");
430 goto fail2; 417 goto fail0;
431 } 418 }
432 419
433 mcfqspi->clk = clk_get(&pdev->dev, "qspi_clk"); 420 mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
434 if (IS_ERR(mcfqspi->clk)) { 421 if (IS_ERR(mcfqspi->clk)) {
435 dev_dbg(&pdev->dev, "clk_get failed\n"); 422 dev_dbg(&pdev->dev, "clk_get failed\n");
436 status = PTR_ERR(mcfqspi->clk); 423 status = PTR_ERR(mcfqspi->clk);
437 goto fail3; 424 goto fail0;
438 } 425 }
439 clk_enable(mcfqspi->clk); 426 clk_enable(mcfqspi->clk);
440 427
@@ -445,7 +432,7 @@ static int mcfqspi_probe(struct platform_device *pdev)
445 status = mcfqspi_cs_setup(mcfqspi); 432 status = mcfqspi_cs_setup(mcfqspi);
446 if (status) { 433 if (status) {
447 dev_dbg(&pdev->dev, "error initializing cs_control\n"); 434 dev_dbg(&pdev->dev, "error initializing cs_control\n");
448 goto fail4; 435 goto fail1;
449 } 436 }
450 437
451 init_waitqueue_head(&mcfqspi->waitq); 438 init_waitqueue_head(&mcfqspi->waitq);
@@ -459,10 +446,10 @@ static int mcfqspi_probe(struct platform_device *pdev)
459 446
460 platform_set_drvdata(pdev, master); 447 platform_set_drvdata(pdev, master);
461 448
462 status = spi_register_master(master); 449 status = devm_spi_register_master(&pdev->dev, master);
463 if (status) { 450 if (status) {
464 dev_dbg(&pdev->dev, "spi_register_master failed\n"); 451 dev_dbg(&pdev->dev, "spi_register_master failed\n");
465 goto fail5; 452 goto fail2;
466 } 453 }
467 pm_runtime_enable(mcfqspi->dev); 454 pm_runtime_enable(mcfqspi->dev);
468 455
@@ -470,17 +457,10 @@ static int mcfqspi_probe(struct platform_device *pdev)
470 457
471 return 0; 458 return 0;
472 459
473fail5:
474 mcfqspi_cs_teardown(mcfqspi);
475fail4:
476 clk_disable(mcfqspi->clk);
477 clk_put(mcfqspi->clk);
478fail3:
479 free_irq(mcfqspi->irq, mcfqspi);
480fail2: 460fail2:
481 iounmap(mcfqspi->iobase); 461 mcfqspi_cs_teardown(mcfqspi);
482fail1: 462fail1:
483 release_mem_region(res->start, resource_size(res)); 463 clk_disable(mcfqspi->clk);
484fail0: 464fail0:
485 spi_master_put(master); 465 spi_master_put(master);
486 466
@@ -501,11 +481,6 @@ static int mcfqspi_remove(struct platform_device *pdev)
501 481
502 mcfqspi_cs_teardown(mcfqspi); 482 mcfqspi_cs_teardown(mcfqspi);
503 clk_disable(mcfqspi->clk); 483 clk_disable(mcfqspi->clk);
504 clk_put(mcfqspi->clk);
505 free_irq(mcfqspi->irq, mcfqspi);
506 iounmap(mcfqspi->iobase);
507 release_mem_region(res->start, resource_size(res));
508 spi_unregister_master(master);
509 484
510 return 0; 485 return 0;
511} 486}
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 50b2d88c8190..5e7389faa2a0 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -396,10 +396,6 @@ static int davinci_spi_setup(struct spi_device *spi)
396 dspi = spi_master_get_devdata(spi->master); 396 dspi = spi_master_get_devdata(spi->master);
397 pdata = &dspi->pdata; 397 pdata = &dspi->pdata;
398 398
399 /* if bits per word length is zero then set it default 8 */
400 if (!spi->bits_per_word)
401 spi->bits_per_word = 8;
402
403 if (!(spi->mode & SPI_NO_CS)) { 399 if (!(spi->mode & SPI_NO_CS)) {
404 if ((pdata->chip_sel == NULL) || 400 if ((pdata->chip_sel == NULL) ||
405 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) 401 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
@@ -853,7 +849,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
853 struct spi_master *master; 849 struct spi_master *master;
854 struct davinci_spi *dspi; 850 struct davinci_spi *dspi;
855 struct davinci_spi_platform_data *pdata; 851 struct davinci_spi_platform_data *pdata;
856 struct resource *r, *mem; 852 struct resource *r;
857 resource_size_t dma_rx_chan = SPI_NO_RESOURCE; 853 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
858 resource_size_t dma_tx_chan = SPI_NO_RESOURCE; 854 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
859 int i = 0, ret = 0; 855 int i = 0, ret = 0;
@@ -894,39 +890,33 @@ static int davinci_spi_probe(struct platform_device *pdev)
894 890
895 dspi->pbase = r->start; 891 dspi->pbase = r->start;
896 892
897 mem = request_mem_region(r->start, resource_size(r), pdev->name); 893 dspi->base = devm_ioremap_resource(&pdev->dev, r);
898 if (mem == NULL) { 894 if (IS_ERR(dspi->base)) {
899 ret = -EBUSY; 895 ret = PTR_ERR(dspi->base);
900 goto free_master; 896 goto free_master;
901 } 897 }
902 898
903 dspi->base = ioremap(r->start, resource_size(r));
904 if (dspi->base == NULL) {
905 ret = -ENOMEM;
906 goto release_region;
907 }
908
909 dspi->irq = platform_get_irq(pdev, 0); 899 dspi->irq = platform_get_irq(pdev, 0);
910 if (dspi->irq <= 0) { 900 if (dspi->irq <= 0) {
911 ret = -EINVAL; 901 ret = -EINVAL;
912 goto unmap_io; 902 goto free_master;
913 } 903 }
914 904
915 ret = request_threaded_irq(dspi->irq, davinci_spi_irq, dummy_thread_fn, 905 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
916 0, dev_name(&pdev->dev), dspi); 906 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
917 if (ret) 907 if (ret)
918 goto unmap_io; 908 goto free_master;
919 909
920 dspi->bitbang.master = master; 910 dspi->bitbang.master = master;
921 if (dspi->bitbang.master == NULL) { 911 if (dspi->bitbang.master == NULL) {
922 ret = -ENODEV; 912 ret = -ENODEV;
923 goto irq_free; 913 goto free_master;
924 } 914 }
925 915
926 dspi->clk = clk_get(&pdev->dev, NULL); 916 dspi->clk = devm_clk_get(&pdev->dev, NULL);
927 if (IS_ERR(dspi->clk)) { 917 if (IS_ERR(dspi->clk)) {
928 ret = -ENODEV; 918 ret = -ENODEV;
929 goto irq_free; 919 goto free_master;
930 } 920 }
931 clk_prepare_enable(dspi->clk); 921 clk_prepare_enable(dspi->clk);
932 922
@@ -963,8 +953,8 @@ static int davinci_spi_probe(struct platform_device *pdev)
963 goto free_clk; 953 goto free_clk;
964 954
965 dev_info(&pdev->dev, "DMA: supported\n"); 955 dev_info(&pdev->dev, "DMA: supported\n");
966 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, " 956 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, "
967 "event queue: %d\n", dma_rx_chan, dma_tx_chan, 957 "event queue: %d\n", &dma_rx_chan, &dma_tx_chan,
968 pdata->dma_event_q); 958 pdata->dma_event_q);
969 } 959 }
970 960
@@ -1015,13 +1005,6 @@ free_dma:
1015 dma_release_channel(dspi->dma_tx); 1005 dma_release_channel(dspi->dma_tx);
1016free_clk: 1006free_clk:
1017 clk_disable_unprepare(dspi->clk); 1007 clk_disable_unprepare(dspi->clk);
1018 clk_put(dspi->clk);
1019irq_free:
1020 free_irq(dspi->irq, dspi);
1021unmap_io:
1022 iounmap(dspi->base);
1023release_region:
1024 release_mem_region(dspi->pbase, resource_size(r));
1025free_master: 1008free_master:
1026 spi_master_put(master); 1009 spi_master_put(master);
1027err: 1010err:
@@ -1041,7 +1024,6 @@ static int davinci_spi_remove(struct platform_device *pdev)
1041{ 1024{
1042 struct davinci_spi *dspi; 1025 struct davinci_spi *dspi;
1043 struct spi_master *master; 1026 struct spi_master *master;
1044 struct resource *r;
1045 1027
1046 master = platform_get_drvdata(pdev); 1028 master = platform_get_drvdata(pdev);
1047 dspi = spi_master_get_devdata(master); 1029 dspi = spi_master_get_devdata(master);
@@ -1049,11 +1031,6 @@ static int davinci_spi_remove(struct platform_device *pdev)
1049 spi_bitbang_stop(&dspi->bitbang); 1031 spi_bitbang_stop(&dspi->bitbang);
1050 1032
1051 clk_disable_unprepare(dspi->clk); 1033 clk_disable_unprepare(dspi->clk);
1052 clk_put(dspi->clk);
1053 free_irq(dspi->irq, dspi);
1054 iounmap(dspi->base);
1055 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1056 release_mem_region(dspi->pbase, resource_size(r));
1057 spi_master_put(master); 1034 spi_master_put(master);
1058 1035
1059 return 0; 1036 return 0;
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 168c620947f4..9af56cdf1540 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -30,14 +30,13 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
30{ 30{
31 struct dw_spi_mmio *dwsmmio; 31 struct dw_spi_mmio *dwsmmio;
32 struct dw_spi *dws; 32 struct dw_spi *dws;
33 struct resource *mem, *ioarea; 33 struct resource *mem;
34 int ret; 34 int ret;
35 35
36 dwsmmio = kzalloc(sizeof(struct dw_spi_mmio), GFP_KERNEL); 36 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
37 if (!dwsmmio) { 37 GFP_KERNEL);
38 ret = -ENOMEM; 38 if (!dwsmmio)
39 goto err_end; 39 return -ENOMEM;
40 }
41 40
42 dws = &dwsmmio->dws; 41 dws = &dwsmmio->dws;
43 42
@@ -45,80 +44,51 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
45 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 44 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
46 if (!mem) { 45 if (!mem) {
47 dev_err(&pdev->dev, "no mem resource?\n"); 46 dev_err(&pdev->dev, "no mem resource?\n");
48 ret = -EINVAL; 47 return -EINVAL;
49 goto err_kfree;
50 } 48 }
51 49
52 ioarea = request_mem_region(mem->start, resource_size(mem), 50 dws->regs = devm_ioremap_resource(&pdev->dev, mem);
53 pdev->name); 51 if (IS_ERR(dws->regs)) {
54 if (!ioarea) { 52 dev_err(&pdev->dev, "SPI region map failed\n");
55 dev_err(&pdev->dev, "SPI region already claimed\n"); 53 return PTR_ERR(dws->regs);
56 ret = -EBUSY;
57 goto err_kfree;
58 }
59
60 dws->regs = ioremap_nocache(mem->start, resource_size(mem));
61 if (!dws->regs) {
62 dev_err(&pdev->dev, "SPI region already mapped\n");
63 ret = -ENOMEM;
64 goto err_release_reg;
65 } 54 }
66 55
67 dws->irq = platform_get_irq(pdev, 0); 56 dws->irq = platform_get_irq(pdev, 0);
68 if (dws->irq < 0) { 57 if (dws->irq < 0) {
69 dev_err(&pdev->dev, "no irq resource?\n"); 58 dev_err(&pdev->dev, "no irq resource?\n");
70 ret = dws->irq; /* -ENXIO */ 59 return dws->irq; /* -ENXIO */
71 goto err_unmap;
72 } 60 }
73 61
74 dwsmmio->clk = clk_get(&pdev->dev, NULL); 62 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
75 if (IS_ERR(dwsmmio->clk)) { 63 if (IS_ERR(dwsmmio->clk))
76 ret = PTR_ERR(dwsmmio->clk); 64 return PTR_ERR(dwsmmio->clk);
77 goto err_unmap; 65 ret = clk_prepare_enable(dwsmmio->clk);
78 } 66 if (ret)
79 clk_enable(dwsmmio->clk); 67 return ret;
80 68
81 dws->parent_dev = &pdev->dev;
82 dws->bus_num = 0; 69 dws->bus_num = 0;
83 dws->num_cs = 4; 70 dws->num_cs = 4;
84 dws->max_freq = clk_get_rate(dwsmmio->clk); 71 dws->max_freq = clk_get_rate(dwsmmio->clk);
85 72
86 ret = dw_spi_add_host(dws); 73 ret = dw_spi_add_host(&pdev->dev, dws);
87 if (ret) 74 if (ret)
88 goto err_clk; 75 goto out;
89 76
90 platform_set_drvdata(pdev, dwsmmio); 77 platform_set_drvdata(pdev, dwsmmio);
91 return 0; 78 return 0;
92 79
93err_clk: 80out:
94 clk_disable(dwsmmio->clk); 81 clk_disable_unprepare(dwsmmio->clk);
95 clk_put(dwsmmio->clk);
96 dwsmmio->clk = NULL;
97err_unmap:
98 iounmap(dws->regs);
99err_release_reg:
100 release_mem_region(mem->start, resource_size(mem));
101err_kfree:
102 kfree(dwsmmio);
103err_end:
104 return ret; 82 return ret;
105} 83}
106 84
107static int dw_spi_mmio_remove(struct platform_device *pdev) 85static int dw_spi_mmio_remove(struct platform_device *pdev)
108{ 86{
109 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); 87 struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
110 struct resource *mem;
111
112 clk_disable(dwsmmio->clk);
113 clk_put(dwsmmio->clk);
114 dwsmmio->clk = NULL;
115 88
89 clk_disable_unprepare(dwsmmio->clk);
116 dw_spi_remove_host(&dwsmmio->dws); 90 dw_spi_remove_host(&dwsmmio->dws);
117 iounmap(dwsmmio->dws.regs);
118 kfree(dwsmmio);
119 91
120 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
121 release_mem_region(mem->start, resource_size(mem));
122 return 0; 92 return 0;
123} 93}
124 94
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
index 66fa9955ea14..d4603efbd9bf 100644
--- a/drivers/spi/spi-dw-pci.c
+++ b/drivers/spi/spi-dw-pci.c
@@ -43,35 +43,25 @@ static int spi_pci_probe(struct pci_dev *pdev,
43 dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n", 43 dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
44 pdev->vendor, pdev->device); 44 pdev->vendor, pdev->device);
45 45
46 ret = pci_enable_device(pdev); 46 ret = pcim_enable_device(pdev);
47 if (ret) 47 if (ret)
48 return ret; 48 return ret;
49 49
50 dwpci = kzalloc(sizeof(struct dw_spi_pci), GFP_KERNEL); 50 dwpci = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_pci),
51 if (!dwpci) { 51 GFP_KERNEL);
52 ret = -ENOMEM; 52 if (!dwpci)
53 goto err_disable; 53 return -ENOMEM;
54 }
55 54
56 dwpci->pdev = pdev; 55 dwpci->pdev = pdev;
57 dws = &dwpci->dws; 56 dws = &dwpci->dws;
58 57
59 /* Get basic io resource and map it */ 58 /* Get basic io resource and map it */
60 dws->paddr = pci_resource_start(pdev, pci_bar); 59 dws->paddr = pci_resource_start(pdev, pci_bar);
61 dws->iolen = pci_resource_len(pdev, pci_bar);
62 60
63 ret = pci_request_region(pdev, pci_bar, dev_name(&pdev->dev)); 61 ret = pcim_iomap_regions(pdev, 1, dev_name(&pdev->dev));
64 if (ret) 62 if (ret)
65 goto err_kfree; 63 return ret;
66
67 dws->regs = ioremap_nocache((unsigned long)dws->paddr,
68 pci_resource_len(pdev, pci_bar));
69 if (!dws->regs) {
70 ret = -ENOMEM;
71 goto err_release_reg;
72 }
73 64
74 dws->parent_dev = &pdev->dev;
75 dws->bus_num = 0; 65 dws->bus_num = 0;
76 dws->num_cs = 4; 66 dws->num_cs = 4;
77 dws->irq = pdev->irq; 67 dws->irq = pdev->irq;
@@ -83,26 +73,17 @@ static int spi_pci_probe(struct pci_dev *pdev,
83 if (pdev->device == 0x0800) { 73 if (pdev->device == 0x0800) {
84 ret = dw_spi_mid_init(dws); 74 ret = dw_spi_mid_init(dws);
85 if (ret) 75 if (ret)
86 goto err_unmap; 76 return ret;
87 } 77 }
88 78
89 ret = dw_spi_add_host(dws); 79 ret = dw_spi_add_host(&pdev->dev, dws);
90 if (ret) 80 if (ret)
91 goto err_unmap; 81 return ret;
92 82
93 /* PCI hook and SPI hook use the same drv data */ 83 /* PCI hook and SPI hook use the same drv data */
94 pci_set_drvdata(pdev, dwpci); 84 pci_set_drvdata(pdev, dwpci);
95 return 0;
96 85
97err_unmap: 86 return 0;
98 iounmap(dws->regs);
99err_release_reg:
100 pci_release_region(pdev, pci_bar);
101err_kfree:
102 kfree(dwpci);
103err_disable:
104 pci_disable_device(pdev);
105 return ret;
106} 87}
107 88
108static void spi_pci_remove(struct pci_dev *pdev) 89static void spi_pci_remove(struct pci_dev *pdev)
@@ -110,10 +91,6 @@ static void spi_pci_remove(struct pci_dev *pdev)
110 struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); 91 struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
111 92
112 dw_spi_remove_host(&dwpci->dws); 93 dw_spi_remove_host(&dwpci->dws);
113 iounmap(dwpci->dws.regs);
114 pci_release_region(pdev, 0);
115 kfree(dwpci);
116 pci_disable_device(pdev);
117} 94}
118 95
119#ifdef CONFIG_PM 96#ifdef CONFIG_PM
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index b897c4adb39d..bf98d63d92b3 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -427,7 +427,6 @@ static void pump_transfers(unsigned long data)
427 dws->tx_end = dws->tx + transfer->len; 427 dws->tx_end = dws->tx + transfer->len;
428 dws->rx = transfer->rx_buf; 428 dws->rx = transfer->rx_buf;
429 dws->rx_end = dws->rx + transfer->len; 429 dws->rx_end = dws->rx + transfer->len;
430 dws->cs_change = transfer->cs_change;
431 dws->len = dws->cur_transfer->len; 430 dws->len = dws->cur_transfer->len;
432 if (chip != dws->prev_chip) 431 if (chip != dws->prev_chip)
433 cs_change = 1; 432 cs_change = 1;
@@ -620,9 +619,11 @@ static int dw_spi_setup(struct spi_device *spi)
620 /* Only alloc on first setup */ 619 /* Only alloc on first setup */
621 chip = spi_get_ctldata(spi); 620 chip = spi_get_ctldata(spi);
622 if (!chip) { 621 if (!chip) {
623 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 622 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
623 GFP_KERNEL);
624 if (!chip) 624 if (!chip)
625 return -ENOMEM; 625 return -ENOMEM;
626 spi_set_ctldata(spi, chip);
626 } 627 }
627 628
628 /* 629 /*
@@ -667,7 +668,6 @@ static int dw_spi_setup(struct spi_device *spi)
667 | (spi->mode << SPI_MODE_OFFSET) 668 | (spi->mode << SPI_MODE_OFFSET)
668 | (chip->tmode << SPI_TMOD_OFFSET); 669 | (chip->tmode << SPI_TMOD_OFFSET);
669 670
670 spi_set_ctldata(spi, chip);
671 return 0; 671 return 0;
672} 672}
673 673
@@ -776,18 +776,16 @@ static void spi_hw_init(struct dw_spi *dws)
776 } 776 }
777} 777}
778 778
779int dw_spi_add_host(struct dw_spi *dws) 779int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
780{ 780{
781 struct spi_master *master; 781 struct spi_master *master;
782 int ret; 782 int ret;
783 783
784 BUG_ON(dws == NULL); 784 BUG_ON(dws == NULL);
785 785
786 master = spi_alloc_master(dws->parent_dev, 0); 786 master = spi_alloc_master(dev, 0);
787 if (!master) { 787 if (!master)
788 ret = -ENOMEM; 788 return -ENOMEM;
789 goto exit;
790 }
791 789
792 dws->master = master; 790 dws->master = master;
793 dws->type = SSI_MOTO_SPI; 791 dws->type = SSI_MOTO_SPI;
@@ -797,7 +795,7 @@ int dw_spi_add_host(struct dw_spi *dws)
797 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", 795 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
798 dws->bus_num); 796 dws->bus_num);
799 797
800 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, 798 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
801 dws->name, dws); 799 dws->name, dws);
802 if (ret < 0) { 800 if (ret < 0) {
803 dev_err(&master->dev, "can not get IRQ\n"); 801 dev_err(&master->dev, "can not get IRQ\n");
@@ -836,7 +834,7 @@ int dw_spi_add_host(struct dw_spi *dws)
836 } 834 }
837 835
838 spi_master_set_devdata(master, dws); 836 spi_master_set_devdata(master, dws);
839 ret = spi_register_master(master); 837 ret = devm_spi_register_master(dev, master);
840 if (ret) { 838 if (ret) {
841 dev_err(&master->dev, "problem registering spi master\n"); 839 dev_err(&master->dev, "problem registering spi master\n");
842 goto err_queue_alloc; 840 goto err_queue_alloc;
@@ -851,10 +849,8 @@ err_queue_alloc:
851 dws->dma_ops->dma_exit(dws); 849 dws->dma_ops->dma_exit(dws);
852err_diable_hw: 850err_diable_hw:
853 spi_enable_chip(dws, 0); 851 spi_enable_chip(dws, 0);
854 free_irq(dws->irq, dws);
855err_free_master: 852err_free_master:
856 spi_master_put(master); 853 spi_master_put(master);
857exit:
858 return ret; 854 return ret;
859} 855}
860EXPORT_SYMBOL_GPL(dw_spi_add_host); 856EXPORT_SYMBOL_GPL(dw_spi_add_host);
@@ -878,10 +874,6 @@ void dw_spi_remove_host(struct dw_spi *dws)
878 spi_enable_chip(dws, 0); 874 spi_enable_chip(dws, 0);
879 /* Disable clk */ 875 /* Disable clk */
880 spi_set_clk(dws, 0); 876 spi_set_clk(dws, 0);
881 free_irq(dws->irq, dws);
882
883 /* Disconnect from the SPI framework */
884 spi_unregister_master(dws->master);
885} 877}
886EXPORT_SYMBOL_GPL(dw_spi_remove_host); 878EXPORT_SYMBOL_GPL(dw_spi_remove_host);
887 879
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 9c57c078031e..587643dae11e 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -92,13 +92,11 @@ struct dw_spi_dma_ops {
92struct dw_spi { 92struct dw_spi {
93 struct spi_master *master; 93 struct spi_master *master;
94 struct spi_device *cur_dev; 94 struct spi_device *cur_dev;
95 struct device *parent_dev;
96 enum dw_ssi_type type; 95 enum dw_ssi_type type;
97 char name[16]; 96 char name[16];
98 97
99 void __iomem *regs; 98 void __iomem *regs;
100 unsigned long paddr; 99 unsigned long paddr;
101 u32 iolen;
102 int irq; 100 int irq;
103 u32 fifo_len; /* depth of the FIFO buffer */ 101 u32 fifo_len; /* depth of the FIFO buffer */
104 u32 max_freq; /* max bus freq supported */ 102 u32 max_freq; /* max bus freq supported */
@@ -135,7 +133,6 @@ struct dw_spi {
135 u8 n_bytes; /* current is a 1/2 bytes op */ 133 u8 n_bytes; /* current is a 1/2 bytes op */
136 u8 max_bits_per_word; /* maxim is 16b */ 134 u8 max_bits_per_word; /* maxim is 16b */
137 u32 dma_width; 135 u32 dma_width;
138 int cs_change;
139 irqreturn_t (*transfer_handler)(struct dw_spi *dws); 136 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
140 void (*cs_control)(u32 command); 137 void (*cs_control)(u32 command);
141 138
@@ -231,7 +228,7 @@ struct dw_spi_chip {
231 void (*cs_control)(u32 command); 228 void (*cs_control)(u32 command);
232}; 229};
233 230
234extern int dw_spi_add_host(struct dw_spi *dws); 231extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
235extern void dw_spi_remove_host(struct dw_spi *dws); 232extern void dw_spi_remove_host(struct dw_spi *dws);
236extern int dw_spi_suspend_host(struct dw_spi *dws); 233extern int dw_spi_suspend_host(struct dw_spi *dws);
237extern int dw_spi_resume_host(struct dw_spi *dws); 234extern int dw_spi_resume_host(struct dw_spi *dws);
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index c7a74f0ef892..dd5bd468e962 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -433,21 +433,12 @@ static int falcon_sflash_probe(struct platform_device *pdev)
433 433
434 platform_set_drvdata(pdev, priv); 434 platform_set_drvdata(pdev, priv);
435 435
436 ret = spi_register_master(master); 436 ret = devm_spi_register_master(&pdev->dev, master);
437 if (ret) 437 if (ret)
438 spi_master_put(master); 438 spi_master_put(master);
439 return ret; 439 return ret;
440} 440}
441 441
442static int falcon_sflash_remove(struct platform_device *pdev)
443{
444 struct falcon_sflash *priv = platform_get_drvdata(pdev);
445
446 spi_unregister_master(priv->master);
447
448 return 0;
449}
450
451static const struct of_device_id falcon_sflash_match[] = { 442static const struct of_device_id falcon_sflash_match[] = {
452 { .compatible = "lantiq,sflash-falcon" }, 443 { .compatible = "lantiq,sflash-falcon" },
453 {}, 444 {},
@@ -456,7 +447,6 @@ MODULE_DEVICE_TABLE(of, falcon_sflash_match);
456 447
457static struct platform_driver falcon_sflash_driver = { 448static struct platform_driver falcon_sflash_driver = {
458 .probe = falcon_sflash_probe, 449 .probe = falcon_sflash_probe,
459 .remove = falcon_sflash_remove,
460 .driver = { 450 .driver = {
461 .name = DRV_NAME, 451 .name = DRV_NAME,
462 .owner = THIS_MODULE, 452 .owner = THIS_MODULE,
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index a37f15665a60..ec79f726672a 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -375,9 +375,6 @@ static int dspi_setup(struct spi_device *spi)
375 if (!spi->max_speed_hz) 375 if (!spi->max_speed_hz)
376 return -EINVAL; 376 return -EINVAL;
377 377
378 if (!spi->bits_per_word)
379 spi->bits_per_word = 8;
380
381 return dspi_setup_transfer(spi, NULL); 378 return dspi_setup_transfer(spi, NULL);
382} 379}
383 380
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 3adebfa22e3d..79e5aa2250c8 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -111,14 +111,6 @@ static int mxs_spi_setup_transfer(struct spi_device *dev,
111 return 0; 111 return 0;
112} 112}
113 113
114static int mxs_spi_setup(struct spi_device *dev)
115{
116 if (!dev->bits_per_word)
117 dev->bits_per_word = 8;
118
119 return 0;
120}
121
122static u32 mxs_spi_cs_to_reg(unsigned cs) 114static u32 mxs_spi_cs_to_reg(unsigned cs)
123{ 115{
124 u32 select = 0; 116 u32 select = 0;
@@ -502,7 +494,6 @@ static int mxs_spi_probe(struct platform_device *pdev)
502 return -ENOMEM; 494 return -ENOMEM;
503 495
504 master->transfer_one_message = mxs_spi_transfer_one; 496 master->transfer_one_message = mxs_spi_transfer_one;
505 master->setup = mxs_spi_setup;
506 master->bits_per_word_mask = SPI_BPW_MASK(8); 497 master->bits_per_word_mask = SPI_BPW_MASK(8);
507 master->mode_bits = SPI_CPOL | SPI_CPHA; 498 master->mode_bits = SPI_CPOL | SPI_CPHA;
508 master->num_chipselect = 3; 499 master->num_chipselect = 3;
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 9e829cee7357..d1e89bb352d8 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -37,117 +37,145 @@
37#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h> 38#include <linux/spi/rspi.h>
39 39
40#define RSPI_SPCR 0x00 40#define RSPI_SPCR 0x00 /* Control Register */
41#define RSPI_SSLP 0x01 41#define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
42#define RSPI_SPPCR 0x02 42#define RSPI_SPPCR 0x02 /* Pin Control Register */
43#define RSPI_SPSR 0x03 43#define RSPI_SPSR 0x03 /* Status Register */
44#define RSPI_SPDR 0x04 44#define RSPI_SPDR 0x04 /* Data Register */
45#define RSPI_SPSCR 0x08 45#define RSPI_SPSCR 0x08 /* Sequence Control Register */
46#define RSPI_SPSSR 0x09 46#define RSPI_SPSSR 0x09 /* Sequence Status Register */
47#define RSPI_SPBR 0x0a 47#define RSPI_SPBR 0x0a /* Bit Rate Register */
48#define RSPI_SPDCR 0x0b 48#define RSPI_SPDCR 0x0b /* Data Control Register */
49#define RSPI_SPCKD 0x0c 49#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d 50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e 51#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f 52#define RSPI_SPCR2 0x0f /* Control Register 2 */
53#define RSPI_SPCMD0 0x10 53#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 54#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 55#define RSPI_SPCMD2 0x14 /* Command Register 2 */
56#define RSPI_SPCMD3 0x16 56#define RSPI_SPCMD3 0x16 /* Command Register 3 */
57#define RSPI_SPCMD4 0x18 57#define RSPI_SPCMD4 0x18 /* Command Register 4 */
58#define RSPI_SPCMD5 0x1a 58#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c 59#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e 60#define RSPI_SPCMD7 0x1e /* Command Register 7 */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
61 63
62/*qspi only */ 64/*qspi only */
63#define QSPI_SPBFCR 0x18 65#define QSPI_SPBFCR 0x18 /* Buffer Control Register */
64#define QSPI_SPBDCR 0x1a 66#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
65#define QSPI_SPBMUL0 0x1c 67#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
66#define QSPI_SPBMUL1 0x20 68#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
67#define QSPI_SPBMUL2 0x24 69#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
68#define QSPI_SPBMUL3 0x28 70#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
69 71
70/* SPCR */ 72/* SPCR - Control Register */
71#define SPCR_SPRIE 0x80 73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
72#define SPCR_SPE 0x40 74#define SPCR_SPE 0x40 /* Function Enable */
73#define SPCR_SPTIE 0x20 75#define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
74#define SPCR_SPEIE 0x10 76#define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
75#define SPCR_MSTR 0x08 77#define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
76#define SPCR_MODFEN 0x04 78#define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
77#define SPCR_TXMD 0x02 79/* RSPI on SH only */
78#define SPCR_SPMS 0x01 80#define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
79 81#define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
80/* SSLP */ 82/* QSPI on R-Car M2 only */
81#define SSLP_SSL1P 0x02 83#define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
82#define SSLP_SSL0P 0x01 84#define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
83 85
84/* SPPCR */ 86/* SSLP - Slave Select Polarity Register */
85#define SPPCR_MOIFE 0x20 87#define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
86#define SPPCR_MOIFV 0x10 88#define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
89
90/* SPPCR - Pin Control Register */
91#define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
92#define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
87#define SPPCR_SPOM 0x04 93#define SPPCR_SPOM 0x04
88#define SPPCR_SPLP2 0x02 94#define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
89#define SPPCR_SPLP 0x01 95#define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
90 96
91/* SPSR */ 97#define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
92#define SPSR_SPRF 0x80 98#define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
93#define SPSR_SPTEF 0x20 99
94#define SPSR_PERF 0x08 100/* SPSR - Status Register */
95#define SPSR_MODF 0x04 101#define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
96#define SPSR_IDLNF 0x02 102#define SPSR_TEND 0x40 /* Transmit End */
97#define SPSR_OVRF 0x01 103#define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
98 104#define SPSR_PERF 0x08 /* Parity Error Flag */
99/* SPSCR */ 105#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
100#define SPSCR_SPSLN_MASK 0x07 106#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
101 107#define SPSR_OVRF 0x01 /* Overrun Error Flag */
102/* SPSSR */ 108
103#define SPSSR_SPECM_MASK 0x70 109/* SPSCR - Sequence Control Register */
104#define SPSSR_SPCP_MASK 0x07 110#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
105 111
106/* SPDCR */ 112/* SPSSR - Sequence Status Register */
107#define SPDCR_SPLW 0x20 113#define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
108#define SPDCR_SPRDTD 0x10 114#define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
115
116/* SPDCR - Data Control Register */
117#define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
118#define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
119#define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
120#define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
121#define SPDCR_SPLWORD SPDCR_SPLW1
122#define SPDCR_SPLBYTE SPDCR_SPLW0
123#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
124#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */
109#define SPDCR_SLSEL1 0x08 125#define SPDCR_SLSEL1 0x08
110#define SPDCR_SLSEL0 0x04 126#define SPDCR_SLSEL0 0x04
111#define SPDCR_SLSEL_MASK 0x0c 127#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */
112#define SPDCR_SPFC1 0x02 128#define SPDCR_SPFC1 0x02
113#define SPDCR_SPFC0 0x01 129#define SPDCR_SPFC0 0x01
130#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */
114 131
115/* SPCKD */ 132/* SPCKD - Clock Delay Register */
116#define SPCKD_SCKDL_MASK 0x07 133#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
117 134
118/* SSLND */ 135/* SSLND - Slave Select Negation Delay Register */
119#define SSLND_SLNDL_MASK 0x07 136#define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
120 137
121/* SPND */ 138/* SPND - Next-Access Delay Register */
122#define SPND_SPNDL_MASK 0x07 139#define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
123 140
124/* SPCR2 */ 141/* SPCR2 - Control Register 2 */
125#define SPCR2_PTE 0x08 142#define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
126#define SPCR2_SPIE 0x04 143#define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
127#define SPCR2_SPOE 0x02 144#define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
128#define SPCR2_SPPE 0x01 145#define SPCR2_SPPE 0x01 /* Parity Enable */
129 146
130/* SPCMDn */ 147/* SPCMDn - Command Registers */
131#define SPCMD_SCKDEN 0x8000 148#define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
132#define SPCMD_SLNDEN 0x4000 149#define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
133#define SPCMD_SPNDEN 0x2000 150#define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
134#define SPCMD_LSBF 0x1000 151#define SPCMD_LSBF 0x1000 /* LSB First */
135#define SPCMD_SPB_MASK 0x0f00 152#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
136#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 153#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
137#define SPCMD_SPB_8BIT 0x0000 /* qspi only */ 154#define SPCMD_SPB_8BIT 0x0000 /* qspi only */
138#define SPCMD_SPB_16BIT 0x0100 155#define SPCMD_SPB_16BIT 0x0100
139#define SPCMD_SPB_20BIT 0x0000 156#define SPCMD_SPB_20BIT 0x0000
140#define SPCMD_SPB_24BIT 0x0100 157#define SPCMD_SPB_24BIT 0x0100
141#define SPCMD_SPB_32BIT 0x0200 158#define SPCMD_SPB_32BIT 0x0200
142#define SPCMD_SSLKP 0x0080 159#define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
143#define SPCMD_SSLA_MASK 0x0030 160#define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
144#define SPCMD_BRDV_MASK 0x000c 161#define SPCMD_SPIMOD1 0x0040
145#define SPCMD_CPOL 0x0002 162#define SPCMD_SPIMOD0 0x0020
146#define SPCMD_CPHA 0x0001 163#define SPCMD_SPIMOD_SINGLE 0
147 164#define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
148/* SPBFCR */ 165#define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
149#define SPBFCR_TXRST 0x80 /* qspi only */ 166#define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
150#define SPBFCR_RXRST 0x40 /* qspi only */ 167#define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
168#define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
169#define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
170#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
171
172/* SPBFCR - Buffer Control Register */
173#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */
174#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */
175#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
176#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
177
178#define DUMMY_DATA 0x00
151 179
152struct rspi_data { 180struct rspi_data {
153 void __iomem *addr; 181 void __iomem *addr;
@@ -158,7 +186,8 @@ struct rspi_data {
158 wait_queue_head_t wait; 186 wait_queue_head_t wait;
159 spinlock_t lock; 187 spinlock_t lock;
160 struct clk *clk; 188 struct clk *clk;
161 unsigned char spsr; 189 u8 spsr;
190 u16 spcmd;
162 const struct spi_ops *ops; 191 const struct spi_ops *ops;
163 192
164 /* for dmaengine */ 193 /* for dmaengine */
@@ -170,34 +199,35 @@ struct rspi_data {
170 unsigned dma_callbacked:1; 199 unsigned dma_callbacked:1;
171}; 200};
172 201
173static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset) 202static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
174{ 203{
175 iowrite8(data, rspi->addr + offset); 204 iowrite8(data, rspi->addr + offset);
176} 205}
177 206
178static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset) 207static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
179{ 208{
180 iowrite16(data, rspi->addr + offset); 209 iowrite16(data, rspi->addr + offset);
181} 210}
182 211
183static void rspi_write32(struct rspi_data *rspi, u32 data, u16 offset) 212static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
184{ 213{
185 iowrite32(data, rspi->addr + offset); 214 iowrite32(data, rspi->addr + offset);
186} 215}
187 216
188static u8 rspi_read8(struct rspi_data *rspi, u16 offset) 217static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
189{ 218{
190 return ioread8(rspi->addr + offset); 219 return ioread8(rspi->addr + offset);
191} 220}
192 221
193static u16 rspi_read16(struct rspi_data *rspi, u16 offset) 222static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
194{ 223{
195 return ioread16(rspi->addr + offset); 224 return ioread16(rspi->addr + offset);
196} 225}
197 226
198/* optional functions */ 227/* optional functions */
199struct spi_ops { 228struct spi_ops {
200 int (*set_config_register)(struct rspi_data *rspi, int access_size); 229 int (*set_config_register)(const struct rspi_data *rspi,
230 int access_size);
201 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg, 231 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg,
202 struct spi_transfer *t); 232 struct spi_transfer *t);
203 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg, 233 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
@@ -208,7 +238,8 @@ struct spi_ops {
208/* 238/*
209 * functions for RSPI 239 * functions for RSPI
210 */ 240 */
211static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 241static int rspi_set_config_register(const struct rspi_data *rspi,
242 int access_size)
212{ 243{
213 int spbr; 244 int spbr;
214 245
@@ -231,7 +262,7 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
231 rspi_write8(rspi, 0x00, RSPI_SPCR2); 262 rspi_write8(rspi, 0x00, RSPI_SPCR2);
232 263
233 /* Sets SPCMD */ 264 /* Sets SPCMD */
234 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP, 265 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd,
235 RSPI_SPCMD0); 266 RSPI_SPCMD0);
236 267
237 /* Sets RSPI mode */ 268 /* Sets RSPI mode */
@@ -243,7 +274,8 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
243/* 274/*
244 * functions for QSPI 275 * functions for QSPI
245 */ 276 */
246static int qspi_set_config_register(struct rspi_data *rspi, int access_size) 277static int qspi_set_config_register(const struct rspi_data *rspi,
278 int access_size)
247{ 279{
248 u16 spcmd; 280 u16 spcmd;
249 int spbr; 281 int spbr;
@@ -268,10 +300,10 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
268 spcmd = SPCMD_SPB_8BIT; 300 spcmd = SPCMD_SPB_8BIT;
269 else if (access_size == 16) 301 else if (access_size == 16)
270 spcmd = SPCMD_SPB_16BIT; 302 spcmd = SPCMD_SPB_16BIT;
271 else if (access_size == 32) 303 else
272 spcmd = SPCMD_SPB_32BIT; 304 spcmd = SPCMD_SPB_32BIT;
273 305
274 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SSLKP | SPCMD_SPNDEN; 306 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN;
275 307
276 /* Resets transfer data length */ 308 /* Resets transfer data length */
277 rspi_write32(rspi, 0, QSPI_SPBMUL0); 309 rspi_write32(rspi, 0, QSPI_SPBMUL0);
@@ -292,12 +324,12 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
292 324
293#define set_config_register(spi, n) spi->ops->set_config_register(spi, n) 325#define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
294 326
295static void rspi_enable_irq(struct rspi_data *rspi, u8 enable) 327static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
296{ 328{
297 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 329 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
298} 330}
299 331
300static void rspi_disable_irq(struct rspi_data *rspi, u8 disable) 332static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
301{ 333{
302 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 334 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
303} 335}
@@ -316,12 +348,12 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
316 return 0; 348 return 0;
317} 349}
318 350
319static void rspi_assert_ssl(struct rspi_data *rspi) 351static void rspi_assert_ssl(const struct rspi_data *rspi)
320{ 352{
321 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 353 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
322} 354}
323 355
324static void rspi_negate_ssl(struct rspi_data *rspi) 356static void rspi_negate_ssl(const struct rspi_data *rspi)
325{ 357{
326 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 358 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
327} 359}
@@ -330,9 +362,7 @@ static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
330 struct spi_transfer *t) 362 struct spi_transfer *t)
331{ 363{
332 int remain = t->len; 364 int remain = t->len;
333 u8 *data; 365 const u8 *data = t->tx_buf;
334
335 data = (u8 *)t->tx_buf;
336 while (remain > 0) { 366 while (remain > 0) {
337 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, 367 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
338 RSPI_SPCR); 368 RSPI_SPCR);
@@ -348,7 +378,7 @@ static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
348 remain--; 378 remain--;
349 } 379 }
350 380
351 /* Waiting for the last transmition */ 381 /* Waiting for the last transmission */
352 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 382 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
353 383
354 return 0; 384 return 0;
@@ -358,12 +388,11 @@ static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
358 struct spi_transfer *t) 388 struct spi_transfer *t)
359{ 389{
360 int remain = t->len; 390 int remain = t->len;
361 u8 *data; 391 const u8 *data = t->tx_buf;
362 392
363 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR); 393 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
364 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 394 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
365 395
366 data = (u8 *)t->tx_buf;
367 while (remain > 0) { 396 while (remain > 0) {
368 397
369 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 398 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
@@ -383,7 +412,7 @@ static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
383 remain--; 412 remain--;
384 } 413 }
385 414
386 /* Waiting for the last transmition */ 415 /* Waiting for the last transmission */
387 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 416 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
388 417
389 return 0; 418 return 0;
@@ -399,8 +428,8 @@ static void rspi_dma_complete(void *arg)
399 wake_up_interruptible(&rspi->wait); 428 wake_up_interruptible(&rspi->wait);
400} 429}
401 430
402static int rspi_dma_map_sg(struct scatterlist *sg, void *buf, unsigned len, 431static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf,
403 struct dma_chan *chan, 432 unsigned len, struct dma_chan *chan,
404 enum dma_transfer_direction dir) 433 enum dma_transfer_direction dir)
405{ 434{
406 sg_init_table(sg, 1); 435 sg_init_table(sg, 1);
@@ -440,12 +469,13 @@ static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len)
440static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) 469static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
441{ 470{
442 struct scatterlist sg; 471 struct scatterlist sg;
443 void *buf = NULL; 472 const void *buf = NULL;
444 struct dma_async_tx_descriptor *desc; 473 struct dma_async_tx_descriptor *desc;
445 unsigned len; 474 unsigned len;
446 int ret = 0; 475 int ret = 0;
447 476
448 if (rspi->dma_width_16bit) { 477 if (rspi->dma_width_16bit) {
478 void *tmp;
449 /* 479 /*
450 * If DMAC bus width is 16-bit, the driver allocates a dummy 480 * If DMAC bus width is 16-bit, the driver allocates a dummy
451 * buffer. And, the driver converts original data into the 481 * buffer. And, the driver converts original data into the
@@ -454,13 +484,14 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
454 * DMAC data: 1st byte, dummy, 2nd byte, dummy ... 484 * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
455 */ 485 */
456 len = t->len * 2; 486 len = t->len * 2;
457 buf = kmalloc(len, GFP_KERNEL); 487 tmp = kmalloc(len, GFP_KERNEL);
458 if (!buf) 488 if (!tmp)
459 return -ENOMEM; 489 return -ENOMEM;
460 rspi_memory_to_8bit(buf, t->tx_buf, t->len); 490 rspi_memory_to_8bit(tmp, t->tx_buf, t->len);
491 buf = tmp;
461 } else { 492 } else {
462 len = t->len; 493 len = t->len;
463 buf = (void *)t->tx_buf; 494 buf = t->tx_buf;
464 } 495 }
465 496
466 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { 497 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) {
@@ -508,9 +539,9 @@ end_nomap:
508 return ret; 539 return ret;
509} 540}
510 541
511static void rspi_receive_init(struct rspi_data *rspi) 542static void rspi_receive_init(const struct rspi_data *rspi)
512{ 543{
513 unsigned char spsr; 544 u8 spsr;
514 545
515 spsr = rspi_read8(rspi, RSPI_SPSR); 546 spsr = rspi_read8(rspi, RSPI_SPSR);
516 if (spsr & SPSR_SPRF) 547 if (spsr & SPSR_SPRF)
@@ -528,7 +559,7 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
528 559
529 rspi_receive_init(rspi); 560 rspi_receive_init(rspi);
530 561
531 data = (u8 *)t->rx_buf; 562 data = t->rx_buf;
532 while (remain > 0) { 563 while (remain > 0) {
533 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, 564 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
534 RSPI_SPCR); 565 RSPI_SPCR);
@@ -539,7 +570,7 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
539 return -ETIMEDOUT; 570 return -ETIMEDOUT;
540 } 571 }
541 /* dummy write for generate clock */ 572 /* dummy write for generate clock */
542 rspi_write16(rspi, 0x00, RSPI_SPDR); 573 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
543 574
544 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { 575 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
545 dev_err(&rspi->master->dev, 576 dev_err(&rspi->master->dev,
@@ -556,9 +587,9 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
556 return 0; 587 return 0;
557} 588}
558 589
559static void qspi_receive_init(struct rspi_data *rspi) 590static void qspi_receive_init(const struct rspi_data *rspi)
560{ 591{
561 unsigned char spsr; 592 u8 spsr;
562 593
563 spsr = rspi_read8(rspi, RSPI_SPSR); 594 spsr = rspi_read8(rspi, RSPI_SPSR);
564 if (spsr & SPSR_SPRF) 595 if (spsr & SPSR_SPRF)
@@ -575,7 +606,7 @@ static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
575 606
576 qspi_receive_init(rspi); 607 qspi_receive_init(rspi);
577 608
578 data = (u8 *)t->rx_buf; 609 data = t->rx_buf;
579 while (remain > 0) { 610 while (remain > 0) {
580 611
581 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 612 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
@@ -584,7 +615,7 @@ static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
584 return -ETIMEDOUT; 615 return -ETIMEDOUT;
585 } 616 }
586 /* dummy write for generate clock */ 617 /* dummy write for generate clock */
587 rspi_write8(rspi, 0x00, RSPI_SPDR); 618 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
588 619
589 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { 620 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
590 dev_err(&rspi->master->dev, 621 dev_err(&rspi->master->dev,
@@ -704,7 +735,7 @@ end_nomap:
704 return ret; 735 return ret;
705} 736}
706 737
707static int rspi_is_dma(struct rspi_data *rspi, struct spi_transfer *t) 738static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
708{ 739{
709 if (t->tx_buf && rspi->chan_tx) 740 if (t->tx_buf && rspi->chan_tx)
710 return 1; 741 return 1;
@@ -771,10 +802,14 @@ static int rspi_setup(struct spi_device *spi)
771{ 802{
772 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 803 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
773 804
774 if (!spi->bits_per_word)
775 spi->bits_per_word = 8;
776 rspi->max_speed_hz = spi->max_speed_hz; 805 rspi->max_speed_hz = spi->max_speed_hz;
777 806
807 rspi->spcmd = SPCMD_SSLKP;
808 if (spi->mode & SPI_CPOL)
809 rspi->spcmd |= SPCMD_CPOL;
810 if (spi->mode & SPI_CPHA)
811 rspi->spcmd |= SPCMD_CPHA;
812
778 set_config_register(rspi, 8); 813 set_config_register(rspi, 8);
779 814
780 return 0; 815 return 0;
@@ -802,10 +837,10 @@ static void rspi_cleanup(struct spi_device *spi)
802 837
803static irqreturn_t rspi_irq(int irq, void *_sr) 838static irqreturn_t rspi_irq(int irq, void *_sr)
804{ 839{
805 struct rspi_data *rspi = (struct rspi_data *)_sr; 840 struct rspi_data *rspi = _sr;
806 unsigned long spsr; 841 u8 spsr;
807 irqreturn_t ret = IRQ_NONE; 842 irqreturn_t ret = IRQ_NONE;
808 unsigned char disable_irq = 0; 843 u8 disable_irq = 0;
809 844
810 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 845 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
811 if (spsr & SPSR_SPRF) 846 if (spsr & SPSR_SPRF)
@@ -825,7 +860,7 @@ static irqreturn_t rspi_irq(int irq, void *_sr)
825static int rspi_request_dma(struct rspi_data *rspi, 860static int rspi_request_dma(struct rspi_data *rspi,
826 struct platform_device *pdev) 861 struct platform_device *pdev)
827{ 862{
828 struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); 863 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
829 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 864 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 dma_cap_mask_t mask; 865 dma_cap_mask_t mask;
831 struct dma_slave_config cfg; 866 struct dma_slave_config cfg;
@@ -887,11 +922,8 @@ static int rspi_remove(struct platform_device *pdev)
887{ 922{
888 struct rspi_data *rspi = platform_get_drvdata(pdev); 923 struct rspi_data *rspi = platform_get_drvdata(pdev);
889 924
890 spi_unregister_master(rspi->master);
891 rspi_release_dma(rspi); 925 rspi_release_dma(rspi);
892 free_irq(platform_get_irq(pdev, 0), rspi); 926 clk_disable(rspi->clk);
893 clk_put(rspi->clk);
894 iounmap(rspi->addr);
895 927
896 return 0; 928 return 0;
897} 929}
@@ -903,7 +935,7 @@ static int rspi_probe(struct platform_device *pdev)
903 struct rspi_data *rspi; 935 struct rspi_data *rspi;
904 int ret, irq; 936 int ret, irq;
905 char clk_name[16]; 937 char clk_name[16];
906 struct rspi_plat_data *rspi_pd = pdev->dev.platform_data; 938 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
907 const struct spi_ops *ops; 939 const struct spi_ops *ops;
908 const struct platform_device_id *id_entry = pdev->id_entry; 940 const struct platform_device_id *id_entry = pdev->id_entry;
909 941
@@ -913,12 +945,6 @@ static int rspi_probe(struct platform_device *pdev)
913 dev_err(&pdev->dev, "there is no set_config_register\n"); 945 dev_err(&pdev->dev, "there is no set_config_register\n");
914 return -ENODEV; 946 return -ENODEV;
915 } 947 }
916 /* get base addr */
917 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918 if (unlikely(res == NULL)) {
919 dev_err(&pdev->dev, "invalid resource\n");
920 return -EINVAL;
921 }
922 948
923 irq = platform_get_irq(pdev, 0); 949 irq = platform_get_irq(pdev, 0);
924 if (irq < 0) { 950 if (irq < 0) {
@@ -936,19 +962,20 @@ static int rspi_probe(struct platform_device *pdev)
936 platform_set_drvdata(pdev, rspi); 962 platform_set_drvdata(pdev, rspi);
937 rspi->ops = ops; 963 rspi->ops = ops;
938 rspi->master = master; 964 rspi->master = master;
939 rspi->addr = ioremap(res->start, resource_size(res)); 965
940 if (rspi->addr == NULL) { 966 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941 dev_err(&pdev->dev, "ioremap error.\n"); 967 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
942 ret = -ENOMEM; 968 if (IS_ERR(rspi->addr)) {
969 ret = PTR_ERR(rspi->addr);
943 goto error1; 970 goto error1;
944 } 971 }
945 972
946 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); 973 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id);
947 rspi->clk = clk_get(&pdev->dev, clk_name); 974 rspi->clk = devm_clk_get(&pdev->dev, clk_name);
948 if (IS_ERR(rspi->clk)) { 975 if (IS_ERR(rspi->clk)) {
949 dev_err(&pdev->dev, "cannot get clock\n"); 976 dev_err(&pdev->dev, "cannot get clock\n");
950 ret = PTR_ERR(rspi->clk); 977 ret = PTR_ERR(rspi->clk);
951 goto error2; 978 goto error1;
952 } 979 }
953 clk_enable(rspi->clk); 980 clk_enable(rspi->clk);
954 981
@@ -965,37 +992,36 @@ static int rspi_probe(struct platform_device *pdev)
965 master->setup = rspi_setup; 992 master->setup = rspi_setup;
966 master->transfer = rspi_transfer; 993 master->transfer = rspi_transfer;
967 master->cleanup = rspi_cleanup; 994 master->cleanup = rspi_cleanup;
995 master->mode_bits = SPI_CPHA | SPI_CPOL;
968 996
969 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi); 997 ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0,
998 dev_name(&pdev->dev), rspi);
970 if (ret < 0) { 999 if (ret < 0) {
971 dev_err(&pdev->dev, "request_irq error\n"); 1000 dev_err(&pdev->dev, "request_irq error\n");
972 goto error3; 1001 goto error2;
973 } 1002 }
974 1003
975 rspi->irq = irq; 1004 rspi->irq = irq;
976 ret = rspi_request_dma(rspi, pdev); 1005 ret = rspi_request_dma(rspi, pdev);
977 if (ret < 0) { 1006 if (ret < 0) {
978 dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 1007 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
979 goto error4; 1008 goto error3;
980 } 1009 }
981 1010
982 ret = spi_register_master(master); 1011 ret = devm_spi_register_master(&pdev->dev, master);
983 if (ret < 0) { 1012 if (ret < 0) {
984 dev_err(&pdev->dev, "spi_register_master error.\n"); 1013 dev_err(&pdev->dev, "spi_register_master error.\n");
985 goto error4; 1014 goto error3;
986 } 1015 }
987 1016
988 dev_info(&pdev->dev, "probed\n"); 1017 dev_info(&pdev->dev, "probed\n");
989 1018
990 return 0; 1019 return 0;
991 1020
992error4:
993 rspi_release_dma(rspi);
994 free_irq(irq, rspi);
995error3: 1021error3:
996 clk_put(rspi->clk); 1022 rspi_release_dma(rspi);
997error2: 1023error2:
998 iounmap(rspi->addr); 1024 clk_disable(rspi->clk);
999error1: 1025error1:
1000 spi_master_put(master); 1026 spi_master_put(master);
1001 1027
diff --git a/drivers/spi/spi-sc18is602.c b/drivers/spi/spi-sc18is602.c
index 9eda21d739c6..1edffed9e098 100644
--- a/drivers/spi/spi-sc18is602.c
+++ b/drivers/spi/spi-sc18is602.c
@@ -254,9 +254,6 @@ error:
254 254
255static int sc18is602_setup(struct spi_device *spi) 255static int sc18is602_setup(struct spi_device *spi)
256{ 256{
257 if (!spi->bits_per_word)
258 spi->bits_per_word = 8;
259
260 if (spi->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST)) 257 if (spi->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST))
261 return -EINVAL; 258 return -EINVAL;
262 259
@@ -319,7 +316,7 @@ static int sc18is602_probe(struct i2c_client *client,
319 master->transfer_one_message = sc18is602_transfer_one; 316 master->transfer_one_message = sc18is602_transfer_one;
320 master->dev.of_node = np; 317 master->dev.of_node = np;
321 318
322 error = spi_register_master(master); 319 error = devm_spi_register_master(dev, master);
323 if (error) 320 if (error)
324 goto error_reg; 321 goto error_reg;
325 322
@@ -330,16 +327,6 @@ error_reg:
330 return error; 327 return error;
331} 328}
332 329
333static int sc18is602_remove(struct i2c_client *client)
334{
335 struct sc18is602 *hw = i2c_get_clientdata(client);
336 struct spi_master *master = hw->master;
337
338 spi_unregister_master(master);
339
340 return 0;
341}
342
343static const struct i2c_device_id sc18is602_id[] = { 330static const struct i2c_device_id sc18is602_id[] = {
344 { "sc18is602", sc18is602 }, 331 { "sc18is602", sc18is602 },
345 { "sc18is602b", sc18is602b }, 332 { "sc18is602b", sc18is602b },
@@ -353,7 +340,6 @@ static struct i2c_driver sc18is602_driver = {
353 .name = "sc18is602", 340 .name = "sc18is602",
354 }, 341 },
355 .probe = sc18is602_probe, 342 .probe = sc18is602_probe,
356 .remove = sc18is602_remove,
357 .id_table = sc18is602_id, 343 .id_table = sc18is602_id,
358}; 344};
359 345
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c
index c120a70094f2..86a17d60a68c 100644
--- a/drivers/spi/spi-sh.c
+++ b/drivers/spi/spi-sh.c
@@ -358,9 +358,6 @@ static int spi_sh_setup(struct spi_device *spi)
358{ 358{
359 struct spi_sh_data *ss = spi_master_get_devdata(spi->master); 359 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
360 360
361 if (!spi->bits_per_word)
362 spi->bits_per_word = 8;
363
364 pr_debug("%s: enter\n", __func__); 361 pr_debug("%s: enter\n", __func__);
365 362
366 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */ 363 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index ed5e501c4652..e430689c3837 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -536,16 +536,9 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
536 536
537static int spi_sirfsoc_setup(struct spi_device *spi) 537static int spi_sirfsoc_setup(struct spi_device *spi)
538{ 538{
539 struct sirfsoc_spi *sspi;
540
541 if (!spi->max_speed_hz) 539 if (!spi->max_speed_hz)
542 return -EINVAL; 540 return -EINVAL;
543 541
544 sspi = spi_master_get_devdata(spi->master);
545
546 if (!spi->bits_per_word)
547 spi->bits_per_word = 8;
548
549 return spi_sirfsoc_setup_transfer(spi, NULL); 542 return spi_sirfsoc_setup_transfer(spi, NULL);
550} 543}
551 544
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 446131308acb..9322de9e13fb 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -466,12 +466,6 @@ static void pch_spi_reset(struct spi_master *master)
466 466
467static int pch_spi_setup(struct spi_device *pspi) 467static int pch_spi_setup(struct spi_device *pspi)
468{ 468{
469 /* check bits per word */
470 if (pspi->bits_per_word == 0) {
471 pspi->bits_per_word = 8;
472 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
473 }
474
475 /* Check baud rate setting */ 469 /* Check baud rate setting */
476 /* if baud rate of chip is greater than 470 /* if baud rate of chip is greater than
477 max we can support,return error */ 471 max we can support,return error */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 06:05:54 -0400