diff options
75 files changed, 18670 insertions, 0 deletions
diff --git a/drivers/staging/rtl8723au/include/Hal8723APhyCfg.h b/drivers/staging/rtl8723au/include/Hal8723APhyCfg.h new file mode 100644 index 000000000000..4aa8cdb5fb90 --- /dev/null +++ b/drivers/staging/rtl8723au/include/Hal8723APhyCfg.h | |||
| @@ -0,0 +1,234 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | #ifndef __INC_HAL8723PHYCFG_H__ | ||
| 17 | #define __INC_HAL8723PHYCFG_H__ | ||
| 18 | |||
| 19 | /*--------------------------Define Parameters-------------------------------*/ | ||
| 20 | #define LOOP_LIMIT 5 | ||
| 21 | #define MAX_STALL_TIME 50 /* us */ | ||
| 22 | #define AntennaDiversityValue 0x80 | ||
| 23 | #define MAX_TXPWR_IDX_NMODE_92S 63 | ||
| 24 | #define Reset_Cnt_Limit 3 | ||
| 25 | |||
| 26 | |||
| 27 | #define MAX_AGGR_NUM 0x0909 | ||
| 28 | |||
| 29 | /*--------------------------Define Parameters-------------------------------*/ | ||
| 30 | |||
| 31 | |||
| 32 | /*------------------------------Define structure----------------------------*/ | ||
| 33 | enum swchnlcmdid { | ||
| 34 | CmdID_End, | ||
| 35 | CmdID_SetTxPowerLevel, | ||
| 36 | CmdID_BBRegWrite10, | ||
| 37 | CmdID_WritePortUlong, | ||
| 38 | CmdID_WritePortUshort, | ||
| 39 | CmdID_WritePortUchar, | ||
| 40 | CmdID_RF_WriteReg, | ||
| 41 | }; | ||
| 42 | |||
| 43 | |||
| 44 | /* 1. Switch channel related */ | ||
| 45 | struct swchnlcmd { | ||
| 46 | enum swchnlcmdid CmdID; | ||
| 47 | u32 Para1; | ||
| 48 | u32 Para2; | ||
| 49 | u32 msDelay; | ||
| 50 | }; | ||
| 51 | |||
| 52 | enum HW90_BLOCK { | ||
| 53 | HW90_BLOCK_MAC = 0, | ||
| 54 | HW90_BLOCK_PHY0 = 1, | ||
| 55 | HW90_BLOCK_PHY1 = 2, | ||
| 56 | HW90_BLOCK_RF = 3, | ||
| 57 | HW90_BLOCK_MAXIMUM = 4, /* Never use this */ | ||
| 58 | }; | ||
| 59 | |||
| 60 | enum RF_RADIO_PATH { | ||
| 61 | RF_PATH_A = 0, /* Radio Path A */ | ||
| 62 | RF_PATH_B = 1, /* Radio Path B */ | ||
| 63 | RF_PATH_C = 2, /* Radio Path C */ | ||
| 64 | RF_PATH_D = 3, /* Radio Path D */ | ||
| 65 | RF_PATH_MAX /* Max RF number 90 support */ | ||
| 66 | }; | ||
| 67 | |||
| 68 | #define RF_PATH_MAX 3 | ||
| 69 | |||
| 70 | #define CHANNEL_MAX_NUMBER 14 /* 14 is the max channel number */ | ||
| 71 | #define CHANNEL_GROUP_MAX 3 /* ch1~3, ch4~9, ch10~14 total three groups */ | ||
| 72 | |||
| 73 | enum WIRELESS_MODE { | ||
| 74 | WIRELESS_MODE_UNKNOWN = 0x00, | ||
| 75 | WIRELESS_MODE_A = BIT2, | ||
| 76 | WIRELESS_MODE_B = BIT0, | ||
| 77 | WIRELESS_MODE_G = BIT1, | ||
| 78 | WIRELESS_MODE_AUTO = BIT5, | ||
| 79 | WIRELESS_MODE_N_24G = BIT3, | ||
| 80 | WIRELESS_MODE_N_5G = BIT4, | ||
| 81 | WIRELESS_MODE_AC = BIT6 | ||
| 82 | }; | ||
| 83 | |||
| 84 | enum baseband_config_type { | ||
| 85 | BaseBand_Config_PHY_REG = 0, /* Radio Path A */ | ||
| 86 | BaseBand_Config_AGC_TAB = 1, /* Radio Path B */ | ||
| 87 | }; | ||
| 88 | |||
| 89 | enum ra_offset_area { | ||
| 90 | RA_OFFSET_LEGACY_OFDM1, | ||
| 91 | RA_OFFSET_LEGACY_OFDM2, | ||
| 92 | RA_OFFSET_HT_OFDM1, | ||
| 93 | RA_OFFSET_HT_OFDM2, | ||
| 94 | RA_OFFSET_HT_OFDM3, | ||
| 95 | RA_OFFSET_HT_OFDM4, | ||
| 96 | RA_OFFSET_HT_CCK, | ||
| 97 | }; | ||
| 98 | |||
| 99 | |||
| 100 | /* BB/RF related */ | ||
| 101 | enum rf_type_8190p { | ||
| 102 | RF_TYPE_MIN, /* 0 */ | ||
| 103 | RF_8225 = 1, /* 1 11b/g RF for verification only */ | ||
| 104 | RF_8256 = 2, /* 2 11b/g/n */ | ||
| 105 | RF_8258 = 3, /* 3 11a/b/g/n RF */ | ||
| 106 | RF_6052 = 4, /* 4 11b/g/n RF */ | ||
| 107 | RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */ | ||
| 108 | }; | ||
| 109 | |||
| 110 | struct bb_reg_define { | ||
| 111 | u32 rfintfs; /* set software control: */ | ||
| 112 | /* 0x870~0x877[8 bytes] */ | ||
| 113 | u32 rfintfi; /* readback data: */ | ||
| 114 | /* 0x8e0~0x8e7[8 bytes] */ | ||
| 115 | u32 rfintfo; /* output data: */ | ||
| 116 | /* 0x860~0x86f [16 bytes] */ | ||
| 117 | u32 rfintfe; /* output enable: */ | ||
| 118 | /* 0x860~0x86f [16 bytes] */ | ||
| 119 | u32 rf3wireOffset; /* LSSI data: */ | ||
| 120 | /* 0x840~0x84f [16 bytes] */ | ||
| 121 | u32 rfLSSI_Select; /* BB Band Select: */ | ||
| 122 | /* 0x878~0x87f [8 bytes] */ | ||
| 123 | u32 rfTxGainStage; /* Tx gain stage: */ | ||
| 124 | /* 0x80c~0x80f [4 bytes] */ | ||
| 125 | u32 rfHSSIPara1; /* wire parameter control1 : */ | ||
| 126 | /* 0x820~0x823, 0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */ | ||
| 127 | u32 rfHSSIPara2; /* wire parameter control2 : */ | ||
| 128 | /* 0x824~0x827, 0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */ | ||
| 129 | u32 rfSwitchControl; /* Tx Rx antenna control : */ | ||
| 130 | /* 0x858~0x85f [16 bytes] */ | ||
| 131 | u32 rfAGCControl1; /* AGC parameter control1 : */ | ||
| 132 | /* 0xc50~0xc53, 0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */ | ||
| 133 | u32 rfAGCControl2; /* AGC parameter control2 : */ | ||
| 134 | /* 0xc54~0xc57, 0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */ | ||
| 135 | u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */ | ||
| 136 | /* 0xc14~0xc17, 0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */ | ||
| 137 | u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */ | ||
| 138 | /* 0xc10~0xc13, 0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */ | ||
| 139 | u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */ | ||
| 140 | /* 0xc80~0xc83, 0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */ | ||
| 141 | u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */ | ||
| 142 | /* 0xc84~0xc87, 0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */ | ||
| 143 | u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ | ||
| 144 | /* 0x8a0~0x8af [16 bytes] */ | ||
| 145 | u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */ | ||
| 146 | }; | ||
| 147 | |||
| 148 | struct r_antenna_sel_ofdm { | ||
| 149 | u32 r_tx_antenna:4; | ||
| 150 | u32 r_ant_l:4; | ||
| 151 | u32 r_ant_non_ht:4; | ||
| 152 | u32 r_ant_ht1:4; | ||
| 153 | u32 r_ant_ht2:4; | ||
| 154 | u32 r_ant_ht_s1:4; | ||
| 155 | u32 r_ant_non_ht_s1:4; | ||
| 156 | u32 OFDM_TXSC:2; | ||
| 157 | u32 Reserved:2; | ||
| 158 | }; | ||
| 159 | |||
| 160 | struct r_antenna_sel_cck { | ||
| 161 | u8 r_cckrx_enable_2:2; | ||
| 162 | u8 r_cckrx_enable:2; | ||
| 163 | u8 r_ccktx_enable:4; | ||
| 164 | }; | ||
| 165 | |||
| 166 | /*------------------------------Define structure----------------------------*/ | ||
| 167 | |||
| 168 | |||
| 169 | /*------------------------Export global variable----------------------------*/ | ||
| 170 | /*------------------------Export global variable----------------------------*/ | ||
| 171 | |||
| 172 | |||
| 173 | /*------------------------Export Macro Definition---------------------------*/ | ||
| 174 | /*------------------------Export Macro Definition---------------------------*/ | ||
| 175 | |||
| 176 | |||
| 177 | /*--------------------------Exported Function prototype---------------------*/ | ||
| 178 | /* */ | ||
| 179 | /* BB and RF register read/write */ | ||
| 180 | /* */ | ||
| 181 | u32 PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr, | ||
| 182 | u32 BitMask); | ||
| 183 | void PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr, | ||
| 184 | u32 BitMask, u32 Data); | ||
| 185 | u32 PHY_QueryRFReg(struct rtw_adapter *Adapter, | ||
| 186 | enum RF_RADIO_PATH eRFPath, u32 RegAddr, | ||
| 187 | u32 BitMask); | ||
| 188 | void PHY_SetRFReg(struct rtw_adapter *Adapter, | ||
| 189 | enum RF_RADIO_PATH eRFPath, u32 RegAddr, | ||
| 190 | u32 BitMask, u32 Data); | ||
| 191 | |||
| 192 | /* */ | ||
| 193 | /* BB TX Power R/W */ | ||
| 194 | /* */ | ||
| 195 | void PHY_SetTxPowerLevel8723A(struct rtw_adapter *Adapter, u8 channel); | ||
| 196 | |||
| 197 | /* */ | ||
| 198 | /* Switch bandwidth for 8723A */ | ||
| 199 | /* */ | ||
| 200 | void PHY_SetBWMode23a8723A(struct rtw_adapter *pAdapter, | ||
| 201 | enum ht_channel_width ChnlWidth, | ||
| 202 | unsigned char Offset); | ||
| 203 | |||
| 204 | /* */ | ||
| 205 | /* channel switch related funciton */ | ||
| 206 | /* */ | ||
| 207 | void PHY_SwChnl8723A(struct rtw_adapter *pAdapter, u8 channel); | ||
| 208 | /* Call after initialization */ | ||
| 209 | void ChkFwCmdIoDone(struct rtw_adapter *Adapter); | ||
| 210 | |||
| 211 | /* */ | ||
| 212 | /* Modify the value of the hw register when beacon interval be changed. */ | ||
| 213 | /* */ | ||
| 214 | void | ||
| 215 | rtl8192c_PHY_SetBeaconHwReg(struct rtw_adapter *Adapter, u16 BeaconInterval); | ||
| 216 | |||
| 217 | |||
| 218 | void PHY_SwitchEphyParameter(struct rtw_adapter *Adapter); | ||
| 219 | |||
| 220 | void PHY_EnableHostClkReq(struct rtw_adapter *Adapter); | ||
| 221 | |||
| 222 | bool | ||
| 223 | SetAntennaConfig92C(struct rtw_adapter *Adapter, u8 DefaultAnt); | ||
| 224 | |||
| 225 | /*--------------------------Exported Function prototype---------------------*/ | ||
| 226 | |||
| 227 | #define PHY_SetMacReg PHY_SetBBReg | ||
| 228 | |||
| 229 | /* MAC/BB/RF HAL config */ | ||
| 230 | int PHY_BBConfig8723A(struct rtw_adapter *Adapter); | ||
| 231 | int PHY_RFConfig8723A(struct rtw_adapter *Adapter); | ||
| 232 | s32 PHY_MACConfig8723A(struct rtw_adapter *padapter); | ||
| 233 | |||
| 234 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/Hal8723APhyReg.h b/drivers/staging/rtl8723au/include/Hal8723APhyReg.h new file mode 100644 index 000000000000..759928f78d6d --- /dev/null +++ b/drivers/staging/rtl8723au/include/Hal8723APhyReg.h | |||
| @@ -0,0 +1,1078 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | #ifndef __INC_HAL8723APHYREG_H__ | ||
| 17 | #define __INC_HAL8723APHYREG_H__ | ||
| 18 | |||
| 19 | /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ | ||
| 20 | /* 1. Page1(0x100) */ | ||
| 21 | #define rPMAC_Reset 0x100 | ||
| 22 | #define rPMAC_TxStart 0x104 | ||
| 23 | #define rPMAC_TxLegacySIG 0x108 | ||
| 24 | #define rPMAC_TxHTSIG1 0x10c | ||
| 25 | #define rPMAC_TxHTSIG2 0x110 | ||
| 26 | #define rPMAC_PHYDebug 0x114 | ||
| 27 | #define rPMAC_TxPacketNum 0x118 | ||
| 28 | #define rPMAC_TxIdle 0x11c | ||
| 29 | #define rPMAC_TxMACHeader0 0x120 | ||
| 30 | #define rPMAC_TxMACHeader1 0x124 | ||
| 31 | #define rPMAC_TxMACHeader2 0x128 | ||
| 32 | #define rPMAC_TxMACHeader3 0x12c | ||
| 33 | #define rPMAC_TxMACHeader4 0x130 | ||
| 34 | #define rPMAC_TxMACHeader5 0x134 | ||
| 35 | #define rPMAC_TxDataType 0x138 | ||
| 36 | #define rPMAC_TxRandomSeed 0x13c | ||
| 37 | #define rPMAC_CCKPLCPPreamble 0x140 | ||
| 38 | #define rPMAC_CCKPLCPHeader 0x144 | ||
| 39 | #define rPMAC_CCKCRC16 0x148 | ||
| 40 | #define rPMAC_OFDMRxCRC32OK 0x170 | ||
| 41 | #define rPMAC_OFDMRxCRC32Er 0x174 | ||
| 42 | #define rPMAC_OFDMRxParityEr 0x178 | ||
| 43 | #define rPMAC_OFDMRxCRC8Er 0x17c | ||
| 44 | #define rPMAC_CCKCRxRC16Er 0x180 | ||
| 45 | #define rPMAC_CCKCRxRC32Er 0x184 | ||
| 46 | #define rPMAC_CCKCRxRC32OK 0x188 | ||
| 47 | #define rPMAC_TxStatus 0x18c | ||
| 48 | |||
| 49 | /* 2. Page2(0x200) */ | ||
| 50 | /* The following two definition are only used for USB interface. */ | ||
| 51 | #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ | ||
| 52 | #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ | ||
| 53 | |||
| 54 | /* 3. Page8(0x800) */ | ||
| 55 | #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ | ||
| 56 | |||
| 57 | #define rFPGA0_TxInfo 0x804 /* Status report?? */ | ||
| 58 | #define rFPGA0_PSDFunction 0x808 | ||
| 59 | |||
| 60 | #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ | ||
| 61 | |||
| 62 | #define rFPGA0_RFTiming1 0x810 /* Useless now */ | ||
| 63 | #define rFPGA0_RFTiming2 0x814 | ||
| 64 | |||
| 65 | #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ | ||
| 66 | #define rFPGA0_XA_HSSIParameter2 0x824 | ||
| 67 | #define rFPGA0_XB_HSSIParameter1 0x828 | ||
| 68 | #define rFPGA0_XB_HSSIParameter2 0x82c | ||
| 69 | #define rTxAGC_B_Rate18_06 0x830 | ||
| 70 | #define rTxAGC_B_Rate54_24 0x834 | ||
| 71 | #define rTxAGC_B_CCK1_55_Mcs32 0x838 | ||
| 72 | #define rTxAGC_B_Mcs03_Mcs00 0x83c | ||
| 73 | |||
| 74 | #define rTxAGC_B_Mcs07_Mcs04 0x848 | ||
| 75 | #define rTxAGC_B_Mcs11_Mcs08 0x84c | ||
| 76 | |||
| 77 | #define rFPGA0_XA_LSSIParameter 0x840 | ||
| 78 | #define rFPGA0_XB_LSSIParameter 0x844 | ||
| 79 | |||
| 80 | #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ | ||
| 81 | #define rFPGA0_RFSleepUpParameter 0x854 | ||
| 82 | |||
| 83 | #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ | ||
| 84 | #define rFPGA0_XCD_SwitchControl 0x85c | ||
| 85 | |||
| 86 | #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ | ||
| 87 | #define rFPGA0_XB_RFInterfaceOE 0x864 | ||
| 88 | |||
| 89 | #define rTxAGC_B_Mcs15_Mcs12 0x868 | ||
| 90 | #define rTxAGC_B_CCK11_A_CCK2_11 0x86c | ||
| 91 | |||
| 92 | #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ | ||
| 93 | #define rFPGA0_XCD_RFInterfaceSW 0x874 | ||
| 94 | |||
| 95 | #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ | ||
| 96 | #define rFPGA0_XCD_RFParameter 0x87c | ||
| 97 | |||
| 98 | #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ | ||
| 99 | #define rFPGA0_AnalogParameter2 0x884 | ||
| 100 | #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ | ||
| 101 | #define rFPGA0_AnalogParameter4 0x88c | ||
| 102 | |||
| 103 | #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ | ||
| 104 | #define rFPGA0_XB_LSSIReadBack 0x8a4 | ||
| 105 | #define rFPGA0_XC_LSSIReadBack 0x8a8 | ||
| 106 | #define rFPGA0_XD_LSSIReadBack 0x8ac | ||
| 107 | |||
| 108 | #define rFPGA0_PSDReport 0x8b4 /* Useless now */ | ||
| 109 | #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ | ||
| 110 | #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ | ||
| 111 | #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */ | ||
| 112 | #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ | ||
| 113 | |||
| 114 | /* 4. Page9(0x900) */ | ||
| 115 | #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */ | ||
| 116 | |||
| 117 | #define rFPGA1_TxBlock 0x904 /* Useless now */ | ||
| 118 | #define rFPGA1_DebugSelect 0x908 /* Useless now */ | ||
| 119 | #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */ | ||
| 120 | |||
| 121 | /* 5. PageA(0xA00) */ | ||
| 122 | /* Set Control channel to upper or lower. These settings are required only for 40MHz */ | ||
| 123 | #define rCCK0_System 0xa00 | ||
| 124 | |||
| 125 | #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */ | ||
| 126 | #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */ | ||
| 127 | |||
| 128 | #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ | ||
| 129 | #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ | ||
| 130 | |||
| 131 | #define rCCK0_RxHP 0xa14 | ||
| 132 | |||
| 133 | #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ | ||
| 134 | #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ | ||
| 135 | |||
| 136 | #define rCCK0_TxFilter1 0xa20 | ||
| 137 | #define rCCK0_TxFilter2 0xa24 | ||
| 138 | #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ | ||
| 139 | #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ | ||
| 140 | #define rCCK0_TRSSIReport 0xa50 | ||
| 141 | #define rCCK0_RxReport 0xa54 /* 0xa57 */ | ||
| 142 | #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ | ||
| 143 | #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ | ||
| 144 | /* PageB(0xB00) */ | ||
| 145 | #define rPdp_AntA 0xb00 | ||
| 146 | #define rPdp_AntA_4 0xb04 | ||
| 147 | #define rConfig_Pmpd_AntA 0xb28 | ||
| 148 | #define rConfig_AntA 0xb68 | ||
| 149 | #define rConfig_AntB 0xb6c | ||
| 150 | #define rPdp_AntB 0xb70 | ||
| 151 | #define rPdp_AntB_4 0xb74 | ||
| 152 | #define rConfig_Pmpd_AntB 0xb98 | ||
| 153 | #define rAPK 0xbd8 | ||
| 154 | |||
| 155 | /* 6. PageC(0xC00) */ | ||
| 156 | #define rOFDM0_LSTF 0xc00 | ||
| 157 | |||
| 158 | #define rOFDM0_TRxPathEnable 0xc04 | ||
| 159 | #define rOFDM0_TRMuxPar 0xc08 | ||
| 160 | #define rOFDM0_TRSWIsolation 0xc0c | ||
| 161 | |||
| 162 | #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ | ||
| 163 | #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ | ||
| 164 | #define rOFDM0_XBRxAFE 0xc18 | ||
| 165 | #define rOFDM0_XBRxIQImbalance 0xc1c | ||
| 166 | #define rOFDM0_XCRxAFE 0xc20 | ||
| 167 | #define rOFDM0_XCRxIQImbalance 0xc24 | ||
| 168 | #define rOFDM0_XDRxAFE 0xc28 | ||
| 169 | #define rOFDM0_XDRxIQImbalance 0xc2c | ||
| 170 | |||
| 171 | #define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune init gain */ | ||
| 172 | #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ | ||
| 173 | #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ | ||
| 174 | #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ | ||
| 175 | |||
| 176 | #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ | ||
| 177 | #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ | ||
| 178 | #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ | ||
| 179 | #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ | ||
| 180 | |||
| 181 | #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ | ||
| 182 | #define rOFDM0_XAAGCCore2 0xc54 | ||
| 183 | #define rOFDM0_XBAGCCore1 0xc58 | ||
| 184 | #define rOFDM0_XBAGCCore2 0xc5c | ||
| 185 | #define rOFDM0_XCAGCCore1 0xc60 | ||
| 186 | #define rOFDM0_XCAGCCore2 0xc64 | ||
| 187 | #define rOFDM0_XDAGCCore1 0xc68 | ||
| 188 | #define rOFDM0_XDAGCCore2 0xc6c | ||
| 189 | |||
| 190 | #define rOFDM0_AGCParameter1 0xc70 | ||
| 191 | #define rOFDM0_AGCParameter2 0xc74 | ||
| 192 | #define rOFDM0_AGCRSSITable 0xc78 | ||
| 193 | #define rOFDM0_HTSTFAGC 0xc7c | ||
| 194 | |||
| 195 | #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ | ||
| 196 | #define rOFDM0_XATxAFE 0xc84 | ||
| 197 | #define rOFDM0_XBTxIQImbalance 0xc88 | ||
| 198 | #define rOFDM0_XBTxAFE 0xc8c | ||
| 199 | #define rOFDM0_XCTxIQImbalance 0xc90 | ||
| 200 | #define rOFDM0_XCTxAFE 0xc94 | ||
| 201 | #define rOFDM0_XDTxIQImbalance 0xc98 | ||
| 202 | #define rOFDM0_XDTxAFE 0xc9c | ||
| 203 | |||
| 204 | #define rOFDM0_RxIQExtAnta 0xca0 | ||
| 205 | #define rOFDM0_TxCoeff1 0xca4 | ||
| 206 | #define rOFDM0_TxCoeff2 0xca8 | ||
| 207 | #define rOFDM0_TxCoeff3 0xcac | ||
| 208 | #define rOFDM0_TxCoeff4 0xcb0 | ||
| 209 | #define rOFDM0_TxCoeff5 0xcb4 | ||
| 210 | #define rOFDM0_TxCoeff6 0xcb8 | ||
| 211 | #define rOFDM0_RxHPParameter 0xce0 | ||
| 212 | #define rOFDM0_TxPseudoNoiseWgt 0xce4 | ||
| 213 | #define rOFDM0_FrameSync 0xcf0 | ||
| 214 | #define rOFDM0_DFSReport 0xcf4 | ||
| 215 | |||
| 216 | /* 7. PageD(0xD00) */ | ||
| 217 | #define rOFDM1_LSTF 0xd00 | ||
| 218 | #define rOFDM1_TRxPathEnable 0xd04 | ||
| 219 | |||
| 220 | #define rOFDM1_CFO 0xd08 /* No setting now */ | ||
| 221 | #define rOFDM1_CSI1 0xd10 | ||
| 222 | #define rOFDM1_SBD 0xd14 | ||
| 223 | #define rOFDM1_CSI2 0xd18 | ||
| 224 | #define rOFDM1_CFOTracking 0xd2c | ||
| 225 | #define rOFDM1_TRxMesaure1 0xd34 | ||
| 226 | #define rOFDM1_IntfDet 0xd3c | ||
| 227 | #define rOFDM1_PseudoNoiseStateAB 0xd50 | ||
| 228 | #define rOFDM1_PseudoNoiseStateCD 0xd54 | ||
| 229 | #define rOFDM1_RxPseudoNoiseWgt 0xd58 | ||
| 230 | |||
| 231 | #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ | ||
| 232 | #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ | ||
| 233 | #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ | ||
| 234 | |||
| 235 | #define rOFDM_ShortCFOAB 0xdac /* No setting now */ | ||
| 236 | #define rOFDM_ShortCFOCD 0xdb0 | ||
| 237 | #define rOFDM_LongCFOAB 0xdb4 | ||
| 238 | #define rOFDM_LongCFOCD 0xdb8 | ||
| 239 | #define rOFDM_TailCFOAB 0xdbc | ||
| 240 | #define rOFDM_TailCFOCD 0xdc0 | ||
| 241 | #define rOFDM_PWMeasure1 0xdc4 | ||
| 242 | #define rOFDM_PWMeasure2 0xdc8 | ||
| 243 | #define rOFDM_BWReport 0xdcc | ||
| 244 | #define rOFDM_AGCReport 0xdd0 | ||
| 245 | #define rOFDM_RxSNR 0xdd4 | ||
| 246 | #define rOFDM_RxEVMCSI 0xdd8 | ||
| 247 | #define rOFDM_SIGReport 0xddc | ||
| 248 | |||
| 249 | |||
| 250 | /* 8. PageE(0xE00) */ | ||
| 251 | #define rTxAGC_A_Rate18_06 0xe00 | ||
| 252 | #define rTxAGC_A_Rate54_24 0xe04 | ||
| 253 | #define rTxAGC_A_CCK1_Mcs32 0xe08 | ||
| 254 | #define rTxAGC_A_Mcs03_Mcs00 0xe10 | ||
| 255 | #define rTxAGC_A_Mcs07_Mcs04 0xe14 | ||
| 256 | #define rTxAGC_A_Mcs11_Mcs08 0xe18 | ||
| 257 | #define rTxAGC_A_Mcs15_Mcs12 0xe1c | ||
| 258 | |||
| 259 | #define rFPGA0_IQK 0xe28 | ||
| 260 | #define rTx_IQK_Tone_A 0xe30 | ||
| 261 | #define rRx_IQK_Tone_A 0xe34 | ||
| 262 | #define rTx_IQK_PI_A 0xe38 | ||
| 263 | #define rRx_IQK_PI_A 0xe3c | ||
| 264 | |||
| 265 | #define rTx_IQK 0xe40 | ||
| 266 | #define rRx_IQK 0xe44 | ||
| 267 | #define rIQK_AGC_Pts 0xe48 | ||
| 268 | #define rIQK_AGC_Rsp 0xe4c | ||
| 269 | #define rTx_IQK_Tone_B 0xe50 | ||
| 270 | #define rRx_IQK_Tone_B 0xe54 | ||
| 271 | #define rTx_IQK_PI_B 0xe58 | ||
| 272 | #define rRx_IQK_PI_B 0xe5c | ||
| 273 | #define rIQK_AGC_Cont 0xe60 | ||
| 274 | |||
| 275 | #define rBlue_Tooth 0xe6c | ||
| 276 | #define rRx_Wait_CCA 0xe70 | ||
| 277 | #define rTx_CCK_RFON 0xe74 | ||
| 278 | #define rTx_CCK_BBON 0xe78 | ||
| 279 | #define rTx_OFDM_RFON 0xe7c | ||
| 280 | #define rTx_OFDM_BBON 0xe80 | ||
| 281 | #define rTx_To_Rx 0xe84 | ||
| 282 | #define rTx_To_Tx 0xe88 | ||
| 283 | #define rRx_CCK 0xe8c | ||
| 284 | |||
| 285 | #define rTx_Power_Before_IQK_A 0xe94 | ||
| 286 | #define rTx_Power_After_IQK_A 0xe9c | ||
| 287 | |||
| 288 | #define rRx_Power_Before_IQK_A 0xea0 | ||
| 289 | #define rRx_Power_Before_IQK_A_2 0xea4 | ||
| 290 | #define rRx_Power_After_IQK_A 0xea8 | ||
| 291 | #define rRx_Power_After_IQK_A_2 0xeac | ||
| 292 | |||
| 293 | #define rTx_Power_Before_IQK_B 0xeb4 | ||
| 294 | #define rTx_Power_After_IQK_B 0xebc | ||
| 295 | |||
| 296 | #define rRx_Power_Before_IQK_B 0xec0 | ||
| 297 | #define rRx_Power_Before_IQK_B_2 0xec4 | ||
| 298 | #define rRx_Power_After_IQK_B 0xec8 | ||
| 299 | #define rRx_Power_After_IQK_B_2 0xecc | ||
| 300 | |||
| 301 | #define rRx_OFDM 0xed0 | ||
| 302 | #define rRx_Wait_RIFS 0xed4 | ||
| 303 | #define rRx_TO_Rx 0xed8 | ||
| 304 | #define rStandby 0xedc | ||
| 305 | #define rSleep 0xee0 | ||
| 306 | #define rPMPD_ANAEN 0xeec | ||
| 307 | |||
| 308 | /* 7. RF Register 0x00-0x2E (RF 8256) */ | ||
| 309 | /* RF-0222D 0x00-3F */ | ||
| 310 | /* Zebra1 */ | ||
| 311 | #define rZebra1_HSSIEnable 0x0 /* Useless now */ | ||
| 312 | #define rZebra1_TRxEnable1 0x1 | ||
| 313 | #define rZebra1_TRxEnable2 0x2 | ||
| 314 | #define rZebra1_AGC 0x4 | ||
| 315 | #define rZebra1_ChargePump 0x5 | ||
| 316 | #define rZebra1_Channel 0x7 /* RF channel switch */ | ||
| 317 | |||
| 318 | #define rZebra1_TxGain 0x8 /* Useless now */ | ||
| 319 | #define rZebra1_TxLPF 0x9 | ||
| 320 | #define rZebra1_RxLPF 0xb | ||
| 321 | #define rZebra1_RxHPFCorner 0xc | ||
| 322 | |||
| 323 | /* Zebra4 */ | ||
| 324 | #define rGlobalCtrl 0 /* Useless now */ | ||
| 325 | #define rRTL8256_TxLPF 19 | ||
| 326 | #define rRTL8256_RxLPF 11 | ||
| 327 | |||
| 328 | /* RTL8258 */ | ||
| 329 | #define rRTL8258_TxLPF 0x11 /* Useless now */ | ||
| 330 | #define rRTL8258_RxLPF 0x13 | ||
| 331 | #define rRTL8258_RSSILPF 0xa | ||
| 332 | |||
| 333 | /* RL6052 Register definition */ | ||
| 334 | #define RF_AC 0x00 | ||
| 335 | #define RF_IQADJ_G1 0x01 | ||
| 336 | #define RF_IQADJ_G2 0x02 | ||
| 337 | #define RF_BS_PA_APSET_G1_G4 0x03 | ||
| 338 | #define RF_BS_PA_APSET_G5_G8 0x04 | ||
| 339 | #define RF_POW_TRSW 0x05 | ||
| 340 | #define RF_GAIN_RX 0x06 | ||
| 341 | #define RF_GAIN_TX 0x07 | ||
| 342 | #define RF_TXM_IDAC 0x08 | ||
| 343 | #define RF_IPA_G 0x09 | ||
| 344 | #define RF_TXBIAS_G 0x0A | ||
| 345 | #define RF_TXPA_AG 0x0B | ||
| 346 | #define RF_IPA_A 0x0C | ||
| 347 | #define RF_TXBIAS_A 0x0D | ||
| 348 | #define RF_BS_PA_APSET_G9_G11 0x0E | ||
| 349 | #define RF_BS_IQGEN 0x0F | ||
| 350 | #define RF_MODE1 0x10 | ||
| 351 | #define RF_MODE2 0x11 | ||
| 352 | #define RF_RX_AGC_HP 0x12 | ||
| 353 | #define RF_TX_AGC 0x13 | ||
| 354 | #define RF_BIAS 0x14 | ||
| 355 | #define RF_IPA 0x15 | ||
| 356 | #define RF_TXBIAS 0x16 | ||
| 357 | #define RF_POW_ABILITY 0x17 | ||
| 358 | #define RF_MODE_AG 0x18 | ||
| 359 | #define rRfChannel 0x18 /* RF channel and BW switch */ | ||
| 360 | #define RF_CHNLBW 0x18 /* RF channel and BW switch */ | ||
| 361 | #define RF_TOP 0x19 | ||
| 362 | #define RF_RX_G1 0x1A | ||
| 363 | #define RF_RX_G2 0x1B | ||
| 364 | #define RF_RX_BB2 0x1C | ||
| 365 | #define RF_RX_BB1 0x1D | ||
| 366 | #define RF_RCK1 0x1E | ||
| 367 | #define RF_RCK2 0x1F | ||
| 368 | #define RF_TX_G1 0x20 | ||
| 369 | #define RF_TX_G2 0x21 | ||
| 370 | #define RF_TX_G3 0x22 | ||
| 371 | #define RF_TX_BB1 0x23 | ||
| 372 | #define RF_T_METER 0x24 | ||
| 373 | #define RF_SYN_G1 0x25 /* RF TX Power control */ | ||
| 374 | #define RF_SYN_G2 0x26 /* RF TX Power control */ | ||
| 375 | #define RF_SYN_G3 0x27 /* RF TX Power control */ | ||
| 376 | #define RF_SYN_G4 0x28 /* RF TX Power control */ | ||
| 377 | #define RF_SYN_G5 0x29 /* RF TX Power control */ | ||
| 378 | #define RF_SYN_G6 0x2A /* RF TX Power control */ | ||
| 379 | #define RF_SYN_G7 0x2B /* RF TX Power control */ | ||
| 380 | #define RF_SYN_G8 0x2C /* RF TX Power control */ | ||
| 381 | |||
| 382 | #define RF_RCK_OS 0x30 /* RF TX PA control */ | ||
| 383 | |||
| 384 | #define RF_TXPA_G1 0x31 /* RF TX PA control */ | ||
| 385 | #define RF_TXPA_G2 0x32 /* RF TX PA control */ | ||
| 386 | #define RF_TXPA_G3 0x33 /* RF TX PA control */ | ||
| 387 | |||
| 388 | /* Bit Mask */ | ||
| 389 | /* 1. Page1(0x100) */ | ||
| 390 | #define bBBResetB 0x100 /* Useless now? */ | ||
| 391 | #define bGlobalResetB 0x200 | ||
| 392 | #define bOFDMTxStart 0x4 | ||
| 393 | #define bCCKTxStart 0x8 | ||
| 394 | #define bCRC32Debug 0x100 | ||
| 395 | #define bPMACLoopback 0x10 | ||
| 396 | #define bTxLSIG 0xffffff | ||
| 397 | #define bOFDMTxRate 0xf | ||
| 398 | #define bOFDMTxReserved 0x10 | ||
| 399 | #define bOFDMTxLength 0x1ffe0 | ||
| 400 | #define bOFDMTxParity 0x20000 | ||
| 401 | #define bTxHTSIG1 0xffffff | ||
| 402 | #define bTxHTMCSRate 0x7f | ||
| 403 | #define bTxHTBW 0x80 | ||
| 404 | #define bTxHTLength 0xffff00 | ||
| 405 | #define bTxHTSIG2 0xffffff | ||
| 406 | #define bTxHTSmoothing 0x1 | ||
| 407 | #define bTxHTSounding 0x2 | ||
| 408 | #define bTxHTReserved 0x4 | ||
| 409 | #define bTxHTAggreation 0x8 | ||
| 410 | #define bTxHTSTBC 0x30 | ||
| 411 | #define bTxHTAdvanceCoding 0x40 | ||
| 412 | #define bTxHTShortGI 0x80 | ||
| 413 | #define bTxHTNumberHT_LTF 0x300 | ||
| 414 | #define bTxHTCRC8 0x3fc00 | ||
| 415 | #define bCounterReset 0x10000 | ||
| 416 | #define bNumOfOFDMTx 0xffff | ||
| 417 | #define bNumOfCCKTx 0xffff0000 | ||
| 418 | #define bTxIdleInterval 0xffff | ||
| 419 | #define bOFDMService 0xffff0000 | ||
| 420 | #define bTxMACHeader 0xffffffff | ||
| 421 | #define bTxDataInit 0xff | ||
| 422 | #define bTxHTMode 0x100 | ||
| 423 | #define bTxDataType 0x30000 | ||
| 424 | #define bTxRandomSeed 0xffffffff | ||
| 425 | #define bCCKTxPreamble 0x1 | ||
| 426 | #define bCCKTxSFD 0xffff0000 | ||
| 427 | #define bCCKTxSIG 0xff | ||
| 428 | #define bCCKTxService 0xff00 | ||
| 429 | #define bCCKLengthExt 0x8000 | ||
| 430 | #define bCCKTxLength 0xffff0000 | ||
| 431 | #define bCCKTxCRC16 0xffff | ||
| 432 | #define bCCKTxStatus 0x1 | ||
| 433 | #define bOFDMTxStatus 0x2 | ||
| 434 | |||
| 435 | #define IS_BB_REG_OFFSET_92S(_Offset) \ | ||
| 436 | ((_Offset >= 0x800) && (_Offset <= 0xfff)) | ||
| 437 | |||
| 438 | /* 2. Page8(0x800) */ | ||
| 439 | #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ | ||
| 440 | #define bJapanMode 0x2 | ||
| 441 | #define bCCKTxSC 0x30 | ||
| 442 | #define bCCKEn 0x1000000 | ||
| 443 | #define bOFDMEn 0x2000000 | ||
| 444 | |||
| 445 | #define bOFDMRxADCPhase 0x10000 /* Useless now */ | ||
| 446 | #define bOFDMTxDACPhase 0x40000 | ||
| 447 | #define bXATxAGC 0x3f | ||
| 448 | |||
| 449 | #define bAntennaSelect 0x0300 | ||
| 450 | |||
| 451 | #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ | ||
| 452 | #define bXCTxAGC 0xf000 | ||
| 453 | #define bXDTxAGC 0xf0000 | ||
| 454 | |||
| 455 | #define bPAStart 0xf0000000 /* Useless now */ | ||
| 456 | #define bTRStart 0x00f00000 | ||
| 457 | #define bRFStart 0x0000f000 | ||
| 458 | #define bBBStart 0x000000f0 | ||
| 459 | #define bBBCCKStart 0x0000000f | ||
| 460 | #define bPAEnd 0xf /* Reg0x814 */ | ||
| 461 | #define bTREnd 0x0f000000 | ||
| 462 | #define bRFEnd 0x000f0000 | ||
| 463 | #define bCCAMask 0x000000f0 /* T2R */ | ||
| 464 | #define bR2RCCAMask 0x00000f00 | ||
| 465 | #define bHSSI_R2TDelay 0xf8000000 | ||
| 466 | #define bHSSI_T2RDelay 0xf80000 | ||
| 467 | #define bContTxHSSI 0x400 /* chane gain at continue Tx */ | ||
| 468 | #define bIGFromCCK 0x200 | ||
| 469 | #define bAGCAddress 0x3f | ||
| 470 | #define bRxHPTx 0x7000 | ||
| 471 | #define bRxHPT2R 0x38000 | ||
| 472 | #define bRxHPCCKIni 0xc0000 | ||
| 473 | #define bAGCTxCode 0xc00000 | ||
| 474 | #define bAGCRxCode 0x300000 | ||
| 475 | |||
| 476 | #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ | ||
| 477 | #define b3WireAddressLength 0x400 | ||
| 478 | |||
| 479 | #define b3WireRFPowerDown 0x1 /* Useless now */ | ||
| 480 | /* define bHWSISelect 0x8 */ | ||
| 481 | #define b5GPAPEPolarity 0x40000000 | ||
| 482 | #define b2GPAPEPolarity 0x80000000 | ||
| 483 | #define bRFSW_TxDefaultAnt 0x3 | ||
| 484 | #define bRFSW_TxOptionAnt 0x30 | ||
| 485 | #define bRFSW_RxDefaultAnt 0x300 | ||
| 486 | #define bRFSW_RxOptionAnt 0x3000 | ||
| 487 | #define bRFSI_3WireData 0x1 | ||
| 488 | #define bRFSI_3WireClock 0x2 | ||
| 489 | #define bRFSI_3WireLoad 0x4 | ||
| 490 | #define bRFSI_3WireRW 0x8 | ||
| 491 | #define bRFSI_3Wire 0xf | ||
| 492 | |||
| 493 | #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ | ||
| 494 | |||
| 495 | #define bRFSI_TRSW 0x20 /* Useless now */ | ||
| 496 | #define bRFSI_TRSWB 0x40 | ||
| 497 | #define bRFSI_ANTSW 0x100 | ||
| 498 | #define bRFSI_ANTSWB 0x200 | ||
| 499 | #define bRFSI_PAPE 0x400 | ||
| 500 | #define bRFSI_PAPE5G 0x800 | ||
| 501 | #define bBandSelect 0x1 | ||
| 502 | #define bHTSIG2_GI 0x80 | ||
| 503 | #define bHTSIG2_Smoothing 0x01 | ||
| 504 | #define bHTSIG2_Sounding 0x02 | ||
| 505 | #define bHTSIG2_Aggreaton 0x08 | ||
| 506 | #define bHTSIG2_STBC 0x30 | ||
| 507 | #define bHTSIG2_AdvCoding 0x40 | ||
| 508 | #define bHTSIG2_NumOfHTLTF 0x300 | ||
| 509 | #define bHTSIG2_CRC8 0x3fc | ||
| 510 | #define bHTSIG1_MCS 0x7f | ||
| 511 | #define bHTSIG1_BandWidth 0x80 | ||
| 512 | #define bHTSIG1_HTLength 0xffff | ||
| 513 | #define bLSIG_Rate 0xf | ||
| 514 | #define bLSIG_Reserved 0x10 | ||
| 515 | #define bLSIG_Length 0x1fffe | ||
| 516 | #define bLSIG_Parity 0x20 | ||
| 517 | #define bCCKRxPhase 0x4 | ||
| 518 | |||
| 519 | #define bLSSIReadAddress 0x7f800000 /* T65 RF */ | ||
| 520 | |||
| 521 | #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ | ||
| 522 | |||
| 523 | #define bLSSIReadBackData 0xfffff /* T65 RF */ | ||
| 524 | |||
| 525 | #define bLSSIReadOKFlag 0x1000 /* Useless now */ | ||
| 526 | #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ | ||
| 527 | #define bRegulator0Standby 0x1 | ||
| 528 | #define bRegulatorPLLStandby 0x2 | ||
| 529 | #define bRegulator1Standby 0x4 | ||
| 530 | #define bPLLPowerUp 0x8 | ||
| 531 | #define bDPLLPowerUp 0x10 | ||
| 532 | #define bDA10PowerUp 0x20 | ||
| 533 | #define bAD7PowerUp 0x200 | ||
| 534 | #define bDA6PowerUp 0x2000 | ||
| 535 | #define bXtalPowerUp 0x4000 | ||
| 536 | #define b40MDClkPowerUP 0x8000 | ||
| 537 | #define bDA6DebugMode 0x20000 | ||
| 538 | #define bDA6Swing 0x380000 | ||
| 539 | |||
| 540 | #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ | ||
| 541 | |||
| 542 | #define b80MClkDelay 0x18000000 /* Useless */ | ||
| 543 | #define bAFEWatchDogEnable 0x20000000 | ||
| 544 | |||
| 545 | #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ | ||
| 546 | #define bXtalCap23 0x3 | ||
| 547 | #define bXtalCap92x 0x0f000000 | ||
| 548 | #define bXtalCap 0x0f000000 | ||
| 549 | |||
| 550 | #define bIntDifClkEnable 0x400 /* Useless */ | ||
| 551 | #define bExtSigClkEnable 0x800 | ||
| 552 | #define bBandgapMbiasPowerUp 0x10000 | ||
| 553 | #define bAD11SHGain 0xc0000 | ||
| 554 | #define bAD11InputRange 0x700000 | ||
| 555 | #define bAD11OPCurrent 0x3800000 | ||
| 556 | #define bIPathLoopback 0x4000000 | ||
| 557 | #define bQPathLoopback 0x8000000 | ||
| 558 | #define bAFELoopback 0x10000000 | ||
| 559 | #define bDA10Swing 0x7e0 | ||
| 560 | #define bDA10Reverse 0x800 | ||
| 561 | #define bDAClkSource 0x1000 | ||
| 562 | #define bAD7InputRange 0x6000 | ||
| 563 | #define bAD7Gain 0x38000 | ||
| 564 | #define bAD7OutputCMMode 0x40000 | ||
| 565 | #define bAD7InputCMMode 0x380000 | ||
| 566 | #define bAD7Current 0xc00000 | ||
| 567 | #define bRegulatorAdjust 0x7000000 | ||
| 568 | #define bAD11PowerUpAtTx 0x1 | ||
| 569 | #define bDA10PSAtTx 0x10 | ||
| 570 | #define bAD11PowerUpAtRx 0x100 | ||
| 571 | #define bDA10PSAtRx 0x1000 | ||
| 572 | #define bCCKRxAGCFormat 0x200 | ||
| 573 | #define bPSDFFTSamplepPoint 0xc000 | ||
| 574 | #define bPSDAverageNum 0x3000 | ||
| 575 | #define bIQPathControl 0xc00 | ||
| 576 | #define bPSDFreq 0x3ff | ||
| 577 | #define bPSDAntennaPath 0x30 | ||
| 578 | #define bPSDIQSwitch 0x40 | ||
| 579 | #define bPSDRxTrigger 0x400000 | ||
| 580 | #define bPSDTxTrigger 0x80000000 | ||
| 581 | #define bPSDSineToneScale 0x7f000000 | ||
| 582 | #define bPSDReport 0xffff | ||
| 583 | |||
| 584 | /* 3. Page9(0x900) */ | ||
| 585 | #define bOFDMTxSC 0x30000000 /* Useless */ | ||
| 586 | #define bCCKTxOn 0x1 | ||
| 587 | #define bOFDMTxOn 0x2 | ||
| 588 | #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ | ||
| 589 | #define bDebugItem 0xff /* reset debug page and LWord */ | ||
| 590 | #define bAntL 0x10 | ||
| 591 | #define bAntNonHT 0x100 | ||
| 592 | #define bAntHT1 0x1000 | ||
| 593 | #define bAntHT2 0x10000 | ||
| 594 | #define bAntHT1S1 0x100000 | ||
| 595 | #define bAntNonHTS1 0x1000000 | ||
| 596 | |||
| 597 | /* 4. PageA(0xA00) */ | ||
| 598 | #define bCCKBBMode 0x3 /* Useless */ | ||
| 599 | #define bCCKTxPowerSaving 0x80 | ||
| 600 | #define bCCKRxPowerSaving 0x40 | ||
| 601 | |||
| 602 | #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ | ||
| 603 | |||
| 604 | #define bCCKScramble 0x8 /* Useless */ | ||
| 605 | #define bCCKAntDiversity 0x8000 | ||
| 606 | #define bCCKCarrierRecovery 0x4000 | ||
| 607 | #define bCCKTxRate 0x3000 | ||
| 608 | #define bCCKDCCancel 0x0800 | ||
| 609 | #define bCCKISICancel 0x0400 | ||
| 610 | #define bCCKMatchFilter 0x0200 | ||
| 611 | #define bCCKEqualizer 0x0100 | ||
| 612 | #define bCCKPreambleDetect 0x800000 | ||
| 613 | #define bCCKFastFalseCCA 0x400000 | ||
| 614 | #define bCCKChEstStart 0x300000 | ||
| 615 | #define bCCKCCACount 0x080000 | ||
| 616 | #define bCCKcs_lim 0x070000 | ||
| 617 | #define bCCKBistMode 0x80000000 | ||
| 618 | #define bCCKCCAMask 0x40000000 | ||
| 619 | #define bCCKTxDACPhase 0x4 | ||
| 620 | #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ | ||
| 621 | #define bCCKr_cp_mode0 0x0100 | ||
| 622 | #define bCCKTxDCOffset 0xf0 | ||
| 623 | #define bCCKRxDCOffset 0xf | ||
| 624 | #define bCCKCCAMode 0xc000 | ||
| 625 | #define bCCKFalseCS_lim 0x3f00 | ||
| 626 | #define bCCKCS_ratio 0xc00000 | ||
| 627 | #define bCCKCorgBit_sel 0x300000 | ||
| 628 | #define bCCKPD_lim 0x0f0000 | ||
| 629 | #define bCCKNewCCA 0x80000000 | ||
| 630 | #define bCCKRxHPofIG 0x8000 | ||
| 631 | #define bCCKRxIG 0x7f00 | ||
| 632 | #define bCCKLNAPolarity 0x800000 | ||
| 633 | #define bCCKRx1stGain 0x7f0000 | ||
| 634 | #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ | ||
| 635 | #define bCCKRxAGCSatLevel 0x1f000000 | ||
| 636 | #define bCCKRxAGCSatCount 0xe0 | ||
| 637 | #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ | ||
| 638 | #define bCCKFixedRxAGC 0x8000 | ||
| 639 | /* define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ | ||
| 640 | #define bCCKAntennaPolarity 0x2000 | ||
| 641 | #define bCCKTxFilterType 0x0c00 | ||
| 642 | #define bCCKRxAGCReportType 0x0300 | ||
| 643 | #define bCCKRxDAGCEn 0x80000000 | ||
| 644 | #define bCCKRxDAGCPeriod 0x20000000 | ||
| 645 | #define bCCKRxDAGCSatLevel 0x1f000000 | ||
| 646 | #define bCCKTimingRecovery 0x800000 | ||
| 647 | #define bCCKTxC0 0x3f0000 | ||
| 648 | #define bCCKTxC1 0x3f000000 | ||
| 649 | #define bCCKTxC2 0x3f | ||
| 650 | #define bCCKTxC3 0x3f00 | ||
| 651 | #define bCCKTxC4 0x3f0000 | ||
| 652 | #define bCCKTxC5 0x3f000000 | ||
| 653 | #define bCCKTxC6 0x3f | ||
| 654 | #define bCCKTxC7 0x3f00 | ||
| 655 | #define bCCKDebugPort 0xff0000 | ||
| 656 | #define bCCKDACDebug 0x0f000000 | ||
| 657 | #define bCCKFalseAlarmEnable 0x8000 | ||
| 658 | #define bCCKFalseAlarmRead 0x4000 | ||
| 659 | #define bCCKTRSSI 0x7f | ||
| 660 | #define bCCKRxAGCReport 0xfe | ||
| 661 | #define bCCKRxReport_AntSel 0x80000000 | ||
| 662 | #define bCCKRxReport_MFOff 0x40000000 | ||
| 663 | #define bCCKRxRxReport_SQLoss 0x20000000 | ||
| 664 | #define bCCKRxReport_Pktloss 0x10000000 | ||
| 665 | #define bCCKRxReport_Lockedbit 0x08000000 | ||
| 666 | #define bCCKRxReport_RateError 0x04000000 | ||
| 667 | #define bCCKRxReport_RxRate 0x03000000 | ||
| 668 | #define bCCKRxFACounterLower 0xff | ||
| 669 | #define bCCKRxFACounterUpper 0xff000000 | ||
| 670 | #define bCCKRxHPAGCStart 0xe000 | ||
| 671 | #define bCCKRxHPAGCFinal 0x1c00 | ||
| 672 | #define bCCKRxFalseAlarmEnable 0x8000 | ||
| 673 | #define bCCKFACounterFreeze 0x4000 | ||
| 674 | #define bCCKTxPathSel 0x10000000 | ||
| 675 | #define bCCKDefaultRxPath 0xc000000 | ||
| 676 | #define bCCKOptionRxPath 0x3000000 | ||
| 677 | |||
| 678 | /* 5. PageC(0xC00) */ | ||
| 679 | #define bNumOfSTF 0x3 /* Useless */ | ||
| 680 | #define bShift_L 0xc0 | ||
| 681 | #define bGI_TH 0xc | ||
| 682 | #define bRxPathA 0x1 | ||
| 683 | #define bRxPathB 0x2 | ||
| 684 | #define bRxPathC 0x4 | ||
| 685 | #define bRxPathD 0x8 | ||
| 686 | #define bTxPathA 0x1 | ||
| 687 | #define bTxPathB 0x2 | ||
| 688 | #define bTxPathC 0x4 | ||
| 689 | #define bTxPathD 0x8 | ||
| 690 | #define bTRSSIFreq 0x200 | ||
| 691 | #define bADCBackoff 0x3000 | ||
| 692 | #define bDFIRBackoff 0xc000 | ||
| 693 | #define bTRSSILatchPhase 0x10000 | ||
| 694 | #define bRxIDCOffset 0xff | ||
| 695 | #define bRxQDCOffset 0xff00 | ||
| 696 | #define bRxDFIRMode 0x1800000 | ||
| 697 | #define bRxDCNFType 0xe000000 | ||
| 698 | #define bRXIQImb_A 0x3ff | ||
| 699 | #define bRXIQImb_B 0xfc00 | ||
| 700 | #define bRXIQImb_C 0x3f0000 | ||
| 701 | #define bRXIQImb_D 0xffc00000 | ||
| 702 | #define bDC_dc_Notch 0x60000 | ||
| 703 | #define bRxNBINotch 0x1f000000 | ||
| 704 | #define bPD_TH 0xf | ||
| 705 | #define bPD_TH_Opt2 0xc000 | ||
| 706 | #define bPWED_TH 0x700 | ||
| 707 | #define bIfMF_Win_L 0x800 | ||
| 708 | #define bPD_Option 0x1000 | ||
| 709 | #define bMF_Win_L 0xe000 | ||
| 710 | #define bBW_Search_L 0x30000 | ||
| 711 | #define bwin_enh_L 0xc0000 | ||
| 712 | #define bBW_TH 0x700000 | ||
| 713 | #define bED_TH2 0x3800000 | ||
| 714 | #define bBW_option 0x4000000 | ||
| 715 | #define bRatio_TH 0x18000000 | ||
| 716 | #define bWindow_L 0xe0000000 | ||
| 717 | #define bSBD_Option 0x1 | ||
| 718 | #define bFrame_TH 0x1c | ||
| 719 | #define bFS_Option 0x60 | ||
| 720 | #define bDC_Slope_check 0x80 | ||
| 721 | #define bFGuard_Counter_DC_L 0xe00 | ||
| 722 | #define bFrame_Weight_Short 0x7000 | ||
| 723 | #define bSub_Tune 0xe00000 | ||
| 724 | #define bFrame_DC_Length 0xe000000 | ||
| 725 | #define bSBD_start_offset 0x30000000 | ||
| 726 | #define bFrame_TH_2 0x7 | ||
| 727 | #define bFrame_GI2_TH 0x38 | ||
| 728 | #define bGI2_Sync_en 0x40 | ||
| 729 | #define bSarch_Short_Early 0x300 | ||
| 730 | #define bSarch_Short_Late 0xc00 | ||
| 731 | #define bSarch_GI2_Late 0x70000 | ||
| 732 | #define bCFOAntSum 0x1 | ||
| 733 | #define bCFOAcc 0x2 | ||
| 734 | #define bCFOStartOffset 0xc | ||
| 735 | #define bCFOLookBack 0x70 | ||
| 736 | #define bCFOSumWeight 0x80 | ||
| 737 | #define bDAGCEnable 0x10000 | ||
| 738 | #define bTXIQImb_A 0x3ff | ||
| 739 | #define bTXIQImb_B 0xfc00 | ||
| 740 | #define bTXIQImb_C 0x3f0000 | ||
| 741 | #define bTXIQImb_D 0xffc00000 | ||
| 742 | #define bTxIDCOffset 0xff | ||
| 743 | #define bTxQDCOffset 0xff00 | ||
| 744 | #define bTxDFIRMode 0x10000 | ||
| 745 | #define bTxPesudoNoiseOn 0x4000000 | ||
| 746 | #define bTxPesudoNoise_A 0xff | ||
| 747 | #define bTxPesudoNoise_B 0xff00 | ||
| 748 | #define bTxPesudoNoise_C 0xff0000 | ||
| 749 | #define bTxPesudoNoise_D 0xff000000 | ||
| 750 | #define bCCADropOption 0x20000 | ||
| 751 | #define bCCADropThres 0xfff00000 | ||
| 752 | #define bEDCCA_H 0xf | ||
| 753 | #define bEDCCA_L 0xf0 | ||
| 754 | #define bLambda_ED 0x300 | ||
| 755 | #define bRxInitialGain 0x7f | ||
| 756 | #define bRxAntDivEn 0x80 | ||
| 757 | #define bRxAGCAddressForLNA 0x7f00 | ||
| 758 | #define bRxHighPowerFlow 0x8000 | ||
| 759 | #define bRxAGCFreezeThres 0xc0000 | ||
| 760 | #define bRxFreezeStep_AGC1 0x300000 | ||
| 761 | #define bRxFreezeStep_AGC2 0xc00000 | ||
| 762 | #define bRxFreezeStep_AGC3 0x3000000 | ||
| 763 | #define bRxFreezeStep_AGC0 0xc000000 | ||
| 764 | #define bRxRssi_Cmp_En 0x10000000 | ||
| 765 | #define bRxQuickAGCEn 0x20000000 | ||
| 766 | #define bRxAGCFreezeThresMode 0x40000000 | ||
| 767 | #define bRxOverFlowCheckType 0x80000000 | ||
| 768 | #define bRxAGCShift 0x7f | ||
| 769 | #define bTRSW_Tri_Only 0x80 | ||
| 770 | #define bPowerThres 0x300 | ||
| 771 | #define bRxAGCEn 0x1 | ||
| 772 | #define bRxAGCTogetherEn 0x2 | ||
| 773 | #define bRxAGCMin 0x4 | ||
| 774 | #define bRxHP_Ini 0x7 | ||
| 775 | #define bRxHP_TRLNA 0x70 | ||
| 776 | #define bRxHP_RSSI 0x700 | ||
| 777 | #define bRxHP_BBP1 0x7000 | ||
| 778 | #define bRxHP_BBP2 0x70000 | ||
| 779 | #define bRxHP_BBP3 0x700000 | ||
| 780 | #define bRSSI_H 0x7f0000 /* the threshold for high power */ | ||
| 781 | #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ | ||
| 782 | #define bRxSettle_TRSW 0x7 | ||
| 783 | #define bRxSettle_LNA 0x38 | ||
| 784 | #define bRxSettle_RSSI 0x1c0 | ||
| 785 | #define bRxSettle_BBP 0xe00 | ||
| 786 | #define bRxSettle_RxHP 0x7000 | ||
| 787 | #define bRxSettle_AntSW_RSSI 0x38000 | ||
| 788 | #define bRxSettle_AntSW 0xc0000 | ||
| 789 | #define bRxProcessTime_DAGC 0x300000 | ||
| 790 | #define bRxSettle_HSSI 0x400000 | ||
| 791 | #define bRxProcessTime_BBPPW 0x800000 | ||
| 792 | #define bRxAntennaPowerShift 0x3000000 | ||
| 793 | #define bRSSITableSelect 0xc000000 | ||
| 794 | #define bRxHP_Final 0x7000000 | ||
| 795 | #define bRxHTSettle_BBP 0x7 | ||
| 796 | #define bRxHTSettle_HSSI 0x8 | ||
| 797 | #define bRxHTSettle_RxHP 0x70 | ||
| 798 | #define bRxHTSettle_BBPPW 0x80 | ||
| 799 | #define bRxHTSettle_Idle 0x300 | ||
| 800 | #define bRxHTSettle_Reserved 0x1c00 | ||
| 801 | #define bRxHTRxHPEn 0x8000 | ||
| 802 | #define bRxHTAGCFreezeThres 0x30000 | ||
| 803 | #define bRxHTAGCTogetherEn 0x40000 | ||
| 804 | #define bRxHTAGCMin 0x80000 | ||
| 805 | #define bRxHTAGCEn 0x100000 | ||
| 806 | #define bRxHTDAGCEn 0x200000 | ||
| 807 | #define bRxHTRxHP_BBP 0x1c00000 | ||
| 808 | #define bRxHTRxHP_Final 0xe0000000 | ||
| 809 | #define bRxPWRatioTH 0x3 | ||
| 810 | #define bRxPWRatioEn 0x4 | ||
| 811 | #define bRxMFHold 0x3800 | ||
| 812 | #define bRxPD_Delay_TH1 0x38 | ||
| 813 | #define bRxPD_Delay_TH2 0x1c0 | ||
| 814 | #define bRxPD_DC_COUNT_MAX 0x600 | ||
| 815 | /* define bRxMF_Hold 0x3800 */ | ||
| 816 | #define bRxPD_Delay_TH 0x8000 | ||
| 817 | #define bRxProcess_Delay 0xf0000 | ||
| 818 | #define bRxSearchrange_GI2_Early 0x700000 | ||
| 819 | #define bRxFrame_Guard_Counter_L 0x3800000 | ||
| 820 | #define bRxSGI_Guard_L 0xc000000 | ||
| 821 | #define bRxSGI_Search_L 0x30000000 | ||
| 822 | #define bRxSGI_TH 0xc0000000 | ||
| 823 | #define bDFSCnt0 0xff | ||
| 824 | #define bDFSCnt1 0xff00 | ||
| 825 | #define bDFSFlag 0xf0000 | ||
| 826 | #define bMFWeightSum 0x300000 | ||
| 827 | #define bMinIdxTH 0x7f000000 | ||
| 828 | #define bDAFormat 0x40000 | ||
| 829 | #define bTxChEmuEnable 0x01000000 | ||
| 830 | #define bTRSWIsolation_A 0x7f | ||
| 831 | #define bTRSWIsolation_B 0x7f00 | ||
| 832 | #define bTRSWIsolation_C 0x7f0000 | ||
| 833 | #define bTRSWIsolation_D 0x7f000000 | ||
| 834 | #define bExtLNAGain 0x7c00 | ||
| 835 | |||
| 836 | /* 6. PageE(0xE00) */ | ||
| 837 | #define bSTBCEn 0x4 /* Useless */ | ||
| 838 | #define bAntennaMapping 0x10 | ||
| 839 | #define bNss 0x20 | ||
| 840 | #define bCFOAntSumD 0x200 | ||
| 841 | #define bPHYCounterReset 0x8000000 | ||
| 842 | #define bCFOReportGet 0x4000000 | ||
| 843 | #define bOFDMContinueTx 0x10000000 | ||
| 844 | #define bOFDMSingleCarrier 0x20000000 | ||
| 845 | #define bOFDMSingleTone 0x40000000 | ||
| 846 | /* define bRxPath1 0x01 */ | ||
| 847 | /* define bRxPath2 0x02 */ | ||
| 848 | /* define bRxPath3 0x04 */ | ||
| 849 | /* define bRxPath4 0x08 */ | ||
| 850 | /* define bTxPath1 0x10 */ | ||
| 851 | /* define bTxPath2 0x20 */ | ||
| 852 | #define bHTDetect 0x100 | ||
| 853 | #define bCFOEn 0x10000 | ||
| 854 | #define bCFOValue 0xfff00000 | ||
| 855 | #define bSigTone_Re 0x3f | ||
| 856 | #define bSigTone_Im 0x7f00 | ||
| 857 | #define bCounter_CCA 0xffff | ||
| 858 | #define bCounter_ParityFail 0xffff0000 | ||
| 859 | #define bCounter_RateIllegal 0xffff | ||
| 860 | #define bCounter_CRC8Fail 0xffff0000 | ||
| 861 | #define bCounter_MCSNoSupport 0xffff | ||
| 862 | #define bCounter_FastSync 0xffff | ||
| 863 | #define bShortCFO 0xfff | ||
| 864 | #define bShortCFOTLength 12 /* total */ | ||
| 865 | #define bShortCFOFLength 11 /* fraction */ | ||
| 866 | #define bLongCFO 0x7ff | ||
| 867 | #define bLongCFOTLength 11 | ||
| 868 | #define bLongCFOFLength 11 | ||
| 869 | #define bTailCFO 0x1fff | ||
| 870 | #define bTailCFOTLength 13 | ||
| 871 | #define bTailCFOFLength 12 | ||
| 872 | #define bmax_en_pwdB 0xffff | ||
| 873 | #define bCC_power_dB 0xffff0000 | ||
| 874 | #define bnoise_pwdB 0xffff | ||
| 875 | #define bPowerMeasTLength 10 | ||
| 876 | #define bPowerMeasFLength 3 | ||
| 877 | #define bRx_HT_BW 0x1 | ||
| 878 | #define bRxSC 0x6 | ||
| 879 | #define bRx_HT 0x8 | ||
| 880 | #define bNB_intf_det_on 0x1 | ||
| 881 | #define bIntf_win_len_cfg 0x30 | ||
| 882 | #define bNB_Intf_TH_cfg 0x1c0 | ||
| 883 | #define bRFGain 0x3f | ||
| 884 | #define bTableSel 0x40 | ||
| 885 | #define bTRSW 0x80 | ||
| 886 | #define bRxSNR_A 0xff | ||
| 887 | #define bRxSNR_B 0xff00 | ||
| 888 | #define bRxSNR_C 0xff0000 | ||
| 889 | #define bRxSNR_D 0xff000000 | ||
| 890 | #define bSNREVMTLength 8 | ||
| 891 | #define bSNREVMFLength 1 | ||
| 892 | #define bCSI1st 0xff | ||
| 893 | #define bCSI2nd 0xff00 | ||
| 894 | #define bRxEVM1st 0xff0000 | ||
| 895 | #define bRxEVM2nd 0xff000000 | ||
| 896 | #define bSIGEVM 0xff | ||
| 897 | #define bPWDB 0xff00 | ||
| 898 | #define bSGIEN 0x10000 | ||
| 899 | |||
| 900 | #define bSFactorQAM1 0xf /* Useless */ | ||
| 901 | #define bSFactorQAM2 0xf0 | ||
| 902 | #define bSFactorQAM3 0xf00 | ||
| 903 | #define bSFactorQAM4 0xf000 | ||
| 904 | #define bSFactorQAM5 0xf0000 | ||
| 905 | #define bSFactorQAM6 0xf0000 | ||
| 906 | #define bSFactorQAM7 0xf00000 | ||
| 907 | #define bSFactorQAM8 0xf000000 | ||
| 908 | #define bSFactorQAM9 0xf0000000 | ||
| 909 | #define bCSIScheme 0x100000 | ||
| 910 | |||
| 911 | #define bNoiseLvlTopSet 0x3 /* Useless */ | ||
| 912 | #define bChSmooth 0x4 | ||
| 913 | #define bChSmoothCfg1 0x38 | ||
| 914 | #define bChSmoothCfg2 0x1c0 | ||
| 915 | #define bChSmoothCfg3 0xe00 | ||
| 916 | #define bChSmoothCfg4 0x7000 | ||
| 917 | #define bMRCMode 0x800000 | ||
| 918 | #define bTHEVMCfg 0x7000000 | ||
| 919 | |||
| 920 | #define bLoopFitType 0x1 /* Useless */ | ||
| 921 | #define bUpdCFO 0x40 | ||
| 922 | #define bUpdCFOOffData 0x80 | ||
| 923 | #define bAdvUpdCFO 0x100 | ||
| 924 | #define bAdvTimeCtrl 0x800 | ||
| 925 | #define bUpdClko 0x1000 | ||
| 926 | #define bFC 0x6000 | ||
| 927 | #define bTrackingMode 0x8000 | ||
| 928 | #define bPhCmpEnable 0x10000 | ||
| 929 | #define bUpdClkoLTF 0x20000 | ||
| 930 | #define bComChCFO 0x40000 | ||
| 931 | #define bCSIEstiMode 0x80000 | ||
| 932 | #define bAdvUpdEqz 0x100000 | ||
| 933 | #define bUChCfg 0x7000000 | ||
| 934 | #define bUpdEqz 0x8000000 | ||
| 935 | |||
| 936 | /* Rx Pseduo noise */ | ||
| 937 | #define bRxPesudoNoiseOn 0x20000000 /* Useless */ | ||
| 938 | #define bRxPesudoNoise_A 0xff | ||
| 939 | #define bRxPesudoNoise_B 0xff00 | ||
| 940 | #define bRxPesudoNoise_C 0xff0000 | ||
| 941 | #define bRxPesudoNoise_D 0xff000000 | ||
| 942 | #define bPesudoNoiseState_A 0xffff | ||
| 943 | #define bPesudoNoiseState_B 0xffff0000 | ||
| 944 | #define bPesudoNoiseState_C 0xffff | ||
| 945 | #define bPesudoNoiseState_D 0xffff0000 | ||
| 946 | |||
| 947 | /* 7. RF Register */ | ||
| 948 | /* Zebra1 */ | ||
| 949 | #define bZebra1_HSSIEnable 0x8 /* Useless */ | ||
| 950 | #define bZebra1_TRxControl 0xc00 | ||
| 951 | #define bZebra1_TRxGainSetting 0x07f | ||
| 952 | #define bZebra1_RxCorner 0xc00 | ||
| 953 | #define bZebra1_TxChargePump 0x38 | ||
| 954 | #define bZebra1_RxChargePump 0x7 | ||
| 955 | #define bZebra1_ChannelNum 0xf80 | ||
| 956 | #define bZebra1_TxLPFBW 0x400 | ||
| 957 | #define bZebra1_RxLPFBW 0x600 | ||
| 958 | |||
| 959 | /* Zebra4 */ | ||
| 960 | #define bRTL8256RegModeCtrl1 0x100 /* Useless */ | ||
| 961 | #define bRTL8256RegModeCtrl0 0x40 | ||
| 962 | #define bRTL8256_TxLPFBW 0x18 | ||
| 963 | #define bRTL8256_RxLPFBW 0x600 | ||
| 964 | |||
| 965 | /* RTL8258 */ | ||
| 966 | #define bRTL8258_TxLPFBW 0xc /* Useless */ | ||
| 967 | #define bRTL8258_RxLPFBW 0xc00 | ||
| 968 | #define bRTL8258_RSSILPFBW 0xc0 | ||
| 969 | |||
| 970 | |||
| 971 | /* Other Definition */ | ||
| 972 | |||
| 973 | /* byte endable for sb_write */ | ||
| 974 | #define bByte0 0x1 /* Useless */ | ||
| 975 | #define bByte1 0x2 | ||
| 976 | #define bByte2 0x4 | ||
| 977 | #define bByte3 0x8 | ||
| 978 | #define bWord0 0x3 | ||
| 979 | #define bWord1 0xc | ||
| 980 | #define bDWord 0xf | ||
| 981 | |||
| 982 | /* for PutRegsetting & GetRegSetting BitMask */ | ||
| 983 | #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ | ||
| 984 | #define bMaskByte1 0xff00 | ||
| 985 | #define bMaskByte2 0xff0000 | ||
| 986 | #define bMaskByte3 0xff000000 | ||
| 987 | #define bMaskHWord 0xffff0000 | ||
| 988 | #define bMaskLWord 0x0000ffff | ||
| 989 | #define bMaskDWord 0xffffffff | ||
| 990 | #define bMask12Bits 0xfff | ||
| 991 | #define bMaskH4Bits 0xf0000000 | ||
| 992 | #define bMaskOFDM_D 0xffc00000 | ||
| 993 | #define bMaskCCK 0x3f3f3f3f | ||
| 994 | |||
| 995 | /* for PutRFRegsetting & GetRFRegSetting BitMask */ | ||
| 996 | #define bRFRegOffsetMask 0xfffff | ||
| 997 | |||
| 998 | #define bDisable 0x0 | ||
| 999 | |||
| 1000 | #define LeftAntenna 0x0 /* Useless */ | ||
| 1001 | #define RightAntenna 0x1 | ||
| 1002 | |||
| 1003 | #define tCheckTxStatus 500 /* 500ms Useless */ | ||
| 1004 | #define tUpdateRxCounter 100 /* 100ms */ | ||
| 1005 | |||
| 1006 | #define rateCCK 0 /* Useless */ | ||
| 1007 | #define rateOFDM 1 | ||
| 1008 | #define rateHT 2 | ||
| 1009 | |||
| 1010 | /* define Register-End */ | ||
| 1011 | #define bPMAC_End 0x1ff /* Useless */ | ||
| 1012 | #define bFPGAPHY0_End 0x8ff | ||
| 1013 | #define bFPGAPHY1_End 0x9ff | ||
| 1014 | #define bCCKPHY0_End 0xaff | ||
| 1015 | #define bOFDMPHY0_End 0xcff | ||
| 1016 | #define bOFDMPHY1_End 0xdff | ||
| 1017 | |||
| 1018 | /* define max debug item in each debug page */ | ||
| 1019 | /* define bMaxItem_FPGA_PHY0 0x9 */ | ||
| 1020 | /* define bMaxItem_FPGA_PHY1 0x3 */ | ||
| 1021 | /* define bMaxItem_PHY_11B 0x16 */ | ||
| 1022 | /* define bMaxItem_OFDM_PHY0 0x29 */ | ||
| 1023 | /* define bMaxItem_OFDM_PHY1 0x0 */ | ||
| 1024 | |||
| 1025 | #define bPMACControl 0x0 /* Useless */ | ||
| 1026 | #define bWMACControl 0x1 | ||
| 1027 | #define bWNICControl 0x2 | ||
| 1028 | |||
| 1029 | #define PathA 0x0 /* Useless */ | ||
| 1030 | #define PathB 0x1 | ||
| 1031 | #define PathC 0x2 | ||
| 1032 | #define PathD 0x3 | ||
| 1033 | |||
| 1034 | /* PageB(0xB00) */ | ||
| 1035 | #define rPdp_AntA 0xb00 | ||
| 1036 | #define rPdp_AntA_4 0xb04 | ||
| 1037 | #define rPdp_AntA_8 0xb08 | ||
| 1038 | #define rPdp_AntA_C 0xb0c | ||
| 1039 | #define rPdp_AntA_18 0xb18 | ||
| 1040 | #define rPdp_AntA_1C 0xb1c | ||
| 1041 | #define rPdp_AntA_20 0xb20 | ||
| 1042 | #define rPdp_AntA_24 0xb24 | ||
| 1043 | |||
| 1044 | #define rConfig_Pmpd_AntA 0xb28 | ||
| 1045 | #define rConfig_ram64x16 0xb2c | ||
| 1046 | |||
| 1047 | #define rBndA 0xb30 | ||
| 1048 | #define rHssiPar 0xb34 | ||
| 1049 | |||
| 1050 | #define rConfig_AntA 0xb68 | ||
| 1051 | #define rConfig_AntB 0xb6c | ||
| 1052 | |||
| 1053 | #define rPdp_AntB 0xb70 | ||
| 1054 | #define rPdp_AntB_4 0xb74 | ||
| 1055 | #define rPdp_AntB_8 0xb78 | ||
| 1056 | #define rPdp_AntB_C 0xb7c | ||
| 1057 | #define rPdp_AntB_10 0xb80 | ||
| 1058 | #define rPdp_AntB_14 0xb84 | ||
| 1059 | #define rPdp_AntB_18 0xb88 | ||
| 1060 | #define rPdp_AntB_1C 0xb8c | ||
| 1061 | #define rPdp_AntB_20 0xb90 | ||
| 1062 | #define rPdp_AntB_24 0xb94 | ||
| 1063 | |||
| 1064 | #define rConfig_Pmpd_AntB 0xb98 | ||
| 1065 | |||
| 1066 | #define rBndB 0xba0 | ||
| 1067 | |||
| 1068 | #define rAPK 0xbd8 | ||
| 1069 | #define rPm_Rx0_AntA 0xbdc | ||
| 1070 | #define rPm_Rx1_AntA 0xbe0 | ||
| 1071 | #define rPm_Rx2_AntA 0xbe4 | ||
| 1072 | #define rPm_Rx3_AntA 0xbe8 | ||
| 1073 | #define rPm_Rx0_AntB 0xbec | ||
| 1074 | #define rPm_Rx1_AntB 0xbf0 | ||
| 1075 | #define rPm_Rx2_AntB 0xbf4 | ||
| 1076 | #define rPm_Rx3_AntB 0xbf8 | ||
| 1077 | |||
| 1078 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/Hal8723PwrSeq.h b/drivers/staging/rtl8723au/include/Hal8723PwrSeq.h new file mode 100644 index 000000000000..7f3bdea6a55e --- /dev/null +++ b/drivers/staging/rtl8723au/include/Hal8723PwrSeq.h | |||
| @@ -0,0 +1,150 @@ | |||
| 1 | #ifndef __HAL8723PWRSEQ_H__ | ||
| 2 | #define __HAL8723PWRSEQ_H__ | ||
| 3 | /* | ||
| 4 | Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd | ||
| 5 | There are 6 HW Power States: | ||
| 6 | 0: POFF--Power Off | ||
| 7 | 1: PDN--Power Down | ||
| 8 | 2: CARDEMU--Card Emulation | ||
| 9 | 3: ACT--Active Mode | ||
| 10 | 4: LPS--Low Power State | ||
| 11 | 5: SUS--Suspend | ||
| 12 | |||
| 13 | The transision from different states are defined below | ||
| 14 | TRANS_CARDEMU_TO_ACT | ||
| 15 | TRANS_ACT_TO_CARDEMU | ||
| 16 | TRANS_CARDEMU_TO_SUS | ||
| 17 | TRANS_SUS_TO_CARDEMU | ||
| 18 | TRANS_CARDEMU_TO_PDN | ||
| 19 | TRANS_ACT_TO_LPS | ||
| 20 | TRANS_LPS_TO_ACT | ||
| 21 | |||
| 22 | TRANS_END | ||
| 23 | */ | ||
| 24 | #include "HalPwrSeqCmd.h" | ||
| 25 | #include "rtl8723a_spec.h" | ||
| 26 | |||
| 27 | #define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15 | ||
| 28 | #define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15 | ||
| 29 | #define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15 | ||
| 30 | #define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15 | ||
| 31 | #define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15 | ||
| 32 | #define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15 | ||
| 33 | #define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15 | ||
| 34 | #define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15 | ||
| 35 | #define RTL8723A_TRANS_END_STEPS 1 | ||
| 36 | |||
| 37 | |||
| 38 | /* format | ||
| 39 | * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here | ||
| 40 | */ | ||
| 41 | #define RTL8723A_TRANS_CARDEMU_TO_ACT \ | ||
| 42 | {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ | ||
| 43 | {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ | ||
| 44 | {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ | ||
| 45 | {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital , 1:isolation*/ \ | ||
| 46 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]= 0*/ \ | ||
| 47 | {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ | ||
| 48 | {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \ | ||
| 49 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]= 0*/ \ | ||
| 50 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ | ||
| 51 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ | ||
| 52 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \ | ||
| 53 | {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\ | ||
| 54 | |||
| 55 | #define RTL8723A_TRANS_ACT_TO_CARDEMU \ | ||
| 56 | {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ | ||
| 57 | {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ | ||
| 58 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ | ||
| 59 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ | ||
| 60 | {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital , 1:isolation*/ \ | ||
| 61 | {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \ | ||
| 62 | |||
| 63 | |||
| 64 | #define RTL8723A_TRANS_CARDEMU_TO_SUS \ | ||
| 65 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ | ||
| 66 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ | ||
| 67 | {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ | ||
| 68 | {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ | ||
| 69 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ | ||
| 70 | {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ | ||
| 71 | {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ | ||
| 72 | |||
| 73 | #define RTL8723A_TRANS_SUS_TO_CARDEMU \ | ||
| 74 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ | ||
| 75 | {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ | ||
| 76 | {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ | ||
| 77 | {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ | ||
| 78 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ | ||
| 79 | |||
| 80 | #define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \ | ||
| 81 | {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ | ||
| 82 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ | ||
| 83 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ | ||
| 84 | {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ | ||
| 85 | {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ | ||
| 86 | {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ | ||
| 87 | {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ | ||
| 88 | |||
| 89 | #define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \ | ||
| 90 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ | ||
| 91 | {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ | ||
| 92 | {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ | ||
| 93 | {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ | ||
| 94 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ | ||
| 95 | {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ | ||
| 96 | {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ | ||
| 97 | |||
| 98 | |||
| 99 | #define RTL8723A_TRANS_CARDEMU_TO_PDN \ | ||
| 100 | {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ | ||
| 101 | {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ | ||
| 102 | {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ | ||
| 103 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ | ||
| 104 | |||
| 105 | #define RTL8723A_TRANS_PDN_TO_CARDEMU \ | ||
| 106 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ | ||
| 107 | |||
| 108 | #define RTL8723A_TRANS_ACT_TO_LPS \ | ||
| 109 | {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ | ||
| 110 | {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ | ||
| 111 | {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ | ||
| 112 | {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ | ||
| 113 | {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ | ||
| 114 | {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ | ||
| 115 | {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ | ||
| 116 | {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ | ||
| 117 | {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ | ||
| 118 | {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ | ||
| 119 | {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ | ||
| 120 | {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ | ||
| 121 | {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ | ||
| 122 | |||
| 123 | #define RTL8723A_TRANS_LPS_TO_ACT \ | ||
| 124 | {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ | ||
| 125 | {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ | ||
| 126 | {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ | ||
| 127 | {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ | ||
| 128 | {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ | ||
| 129 | {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]= 0 TSF in 40M*/\ | ||
| 130 | {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ | ||
| 131 | {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ | ||
| 132 | {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ | ||
| 133 | {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ | ||
| 134 | {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ | ||
| 135 | |||
| 136 | #define RTL8723A_TRANS_END \ | ||
| 137 | {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, | ||
| 138 | |||
| 139 | |||
| 140 | extern struct wlan_pwr_cfg rtl8723AU_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 141 | extern struct wlan_pwr_cfg rtl8723AU_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 142 | extern struct wlan_pwr_cfg rtl8723AU_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 143 | extern struct wlan_pwr_cfg rtl8723AU_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 144 | extern struct wlan_pwr_cfg rtl8723AU_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 145 | extern struct wlan_pwr_cfg rtl8723AU_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 146 | extern struct wlan_pwr_cfg rtl8723AU_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 147 | extern struct wlan_pwr_cfg rtl8723AU_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 148 | extern struct wlan_pwr_cfg rtl8723AU_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]; | ||
| 149 | |||
| 150 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/Hal8723UHWImg_CE.h b/drivers/staging/rtl8723au/include/Hal8723UHWImg_CE.h new file mode 100644 index 000000000000..bbeaab48057a --- /dev/null +++ b/drivers/staging/rtl8723au/include/Hal8723UHWImg_CE.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | #ifndef __INC_HAL8723U_FW_IMG_H | ||
| 2 | #define __INC_HAL8723U_FW_IMG_H | ||
| 3 | |||
| 4 | /*Created on 2013/01/14, 15:51*/ | ||
| 5 | |||
| 6 | /* FW v16 enable usb interrupt */ | ||
| 7 | #define Rtl8723UImgArrayLength 22172 | ||
| 8 | extern u8 Rtl8723UFwImgArray[Rtl8723UImgArrayLength]; | ||
| 9 | #define Rtl8723UBTImgArrayLength 1 | ||
| 10 | extern u8 Rtl8723UFwBTImgArray[Rtl8723UBTImgArrayLength]; | ||
| 11 | |||
| 12 | #define Rtl8723UUMCBCutImgArrayWithBTLength 24118 | ||
| 13 | #define Rtl8723UUMCBCutImgArrayWithoutBTLength 19200 | ||
| 14 | |||
| 15 | extern u8 Rtl8723UFwUMCBCutImgArrayWithBT[Rtl8723UUMCBCutImgArrayWithBTLength]; | ||
| 16 | extern u8 Rtl8723UFwUMCBCutImgArrayWithoutBT[Rtl8723UUMCBCutImgArrayWithoutBTLength]; | ||
| 17 | |||
| 18 | #define Rtl8723SUMCBCutMPImgArrayLength 24174 | ||
| 19 | extern const u8 Rtl8723SFwUMCBCutMPImgArray[Rtl8723SUMCBCutMPImgArrayLength]; | ||
| 20 | |||
| 21 | #define Rtl8723EBTImgArrayLength 15276 | ||
| 22 | extern u8 Rtl8723EFwBTImgArray[Rtl8723EBTImgArrayLength] ; | ||
| 23 | |||
| 24 | #define Rtl8723UPHY_REG_Array_PGLength 336 | ||
| 25 | extern u32 Rtl8723UPHY_REG_Array_PG[Rtl8723UPHY_REG_Array_PGLength]; | ||
| 26 | #define Rtl8723UMACPHY_Array_PGLength 1 | ||
| 27 | extern u32 Rtl8723UMACPHY_Array_PG[Rtl8723UMACPHY_Array_PGLength]; | ||
| 28 | |||
| 29 | #endif /* ifndef __INC_HAL8723U_FW_IMG_H */ | ||
diff --git a/drivers/staging/rtl8723au/include/HalDMOutSrc8723A.h b/drivers/staging/rtl8723au/include/HalDMOutSrc8723A.h new file mode 100644 index 000000000000..d7651f7a665b --- /dev/null +++ b/drivers/staging/rtl8723au/include/HalDMOutSrc8723A.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | #ifndef __RTL8723A_ODM_H__ | ||
| 17 | #define __RTL8723A_ODM_H__ | ||
| 18 | /* */ | ||
| 19 | |||
| 20 | #define RSSI_CCK 0 | ||
| 21 | #define RSSI_OFDM 1 | ||
| 22 | #define RSSI_DEFAULT 2 | ||
| 23 | |||
| 24 | #define IQK_MAC_REG_NUM 4 | ||
| 25 | #define IQK_ADDA_REG_NUM 16 | ||
| 26 | #define IQK_BB_REG_NUM 9 | ||
| 27 | #define HP_THERMAL_NUM 8 | ||
| 28 | |||
| 29 | |||
| 30 | /* */ | ||
| 31 | /* structure and define */ | ||
| 32 | /* */ | ||
| 33 | |||
| 34 | |||
| 35 | |||
| 36 | |||
| 37 | /*------------------------Export global variable----------------------------*/ | ||
| 38 | /*------------------------Export global variable----------------------------*/ | ||
| 39 | /*------------------------Export Marco Definition---------------------------*/ | ||
| 40 | /* define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} */ | ||
| 41 | |||
| 42 | |||
| 43 | /* */ | ||
| 44 | /* function prototype */ | ||
| 45 | /* */ | ||
| 46 | |||
| 47 | /* */ | ||
| 48 | /* IQ calibrate */ | ||
| 49 | /* */ | ||
| 50 | void rtl8723a_phy_iq_calibrate(struct rtw_adapter *pAdapter, bool bReCovery); | ||
| 51 | |||
| 52 | /* */ | ||
| 53 | /* LC calibrate */ | ||
| 54 | /* */ | ||
| 55 | void rtl8723a_phy_lc_calibrate(struct rtw_adapter *pAdapter); | ||
| 56 | |||
| 57 | /* */ | ||
| 58 | /* AP calibrate */ | ||
| 59 | /* */ | ||
| 60 | void rtl8723a_phy_ap_calibrate(struct rtw_adapter *pAdapter, char delta); | ||
| 61 | |||
| 62 | void rtl8723a_odm_check_tx_power_tracking(struct rtw_adapter *Adapter); | ||
| 63 | |||
| 64 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/HalHWImg8723A_BB.h b/drivers/staging/rtl8723au/include/HalHWImg8723A_BB.h new file mode 100644 index 000000000000..e99833cc7929 --- /dev/null +++ b/drivers/staging/rtl8723au/include/HalHWImg8723A_BB.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | |||
| 17 | #ifndef __INC_BB_8723A_HW_IMG_H | ||
| 18 | #define __INC_BB_8723A_HW_IMG_H | ||
| 19 | |||
| 20 | /****************************************************************************** | ||
| 21 | * AGC_TAB_1T.TXT | ||
| 22 | ******************************************************************************/ | ||
| 23 | |||
| 24 | void ODM_ReadAndConfig_AGC_TAB_1T_8723A(struct dm_odm_t *pDM_Odm); | ||
| 25 | |||
| 26 | /****************************************************************************** | ||
| 27 | * PHY_REG_1T.TXT | ||
| 28 | ******************************************************************************/ | ||
| 29 | |||
| 30 | void ODM_ReadAndConfig_PHY_REG_1T_8723A(struct dm_odm_t *pDM_Odm); | ||
| 31 | |||
| 32 | /****************************************************************************** | ||
| 33 | * PHY_REG_MP.TXT | ||
| 34 | ******************************************************************************/ | ||
| 35 | |||
| 36 | void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm); | ||
| 37 | |||
| 38 | /****************************************************************************** | ||
| 39 | * PHY_REG_PG.TXT | ||
| 40 | ******************************************************************************/ | ||
| 41 | |||
| 42 | void ODM_ReadAndConfig_PHY_REG_PG_8723A(struct dm_odm_t *pDM_Odm); | ||
| 43 | |||
| 44 | #endif /* end of HWIMG_SUPPORT */ | ||
diff --git a/drivers/staging/rtl8723au/include/HalHWImg8723A_FW.h b/drivers/staging/rtl8723au/include/HalHWImg8723A_FW.h new file mode 100644 index 000000000000..7ee363b99b49 --- /dev/null +++ b/drivers/staging/rtl8723au/include/HalHWImg8723A_FW.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | |||
| 17 | #ifndef __INC_FW_8723A_HW_IMG_H | ||
| 18 | #define __INC_FW_8723A_HW_IMG_H | ||
| 19 | |||
| 20 | |||
| 21 | /****************************************************************************** | ||
| 22 | * rtl8723fw_B.TXT | ||
| 23 | ******************************************************************************/ | ||
| 24 | |||
| 25 | void ODM_ReadFirmware_8723A_rtl8723fw_B(struct dm_odm_t *pDM_Odm, | ||
| 26 | u8 *pFirmware, u32 *pFirmwareSize); | ||
| 27 | |||
| 28 | #endif /* end of HWIMG_SUPPORT */ | ||
diff --git a/drivers/staging/rtl8723au/include/HalHWImg8723A_MAC.h b/drivers/staging/rtl8723au/include/HalHWImg8723A_MAC.h new file mode 100644 index 000000000000..201be1f87292 --- /dev/null +++ b/drivers/staging/rtl8723au/include/HalHWImg8723A_MAC.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | |||
| 17 | #ifndef __INC_MAC_8723A_HW_IMG_H | ||
| 18 | #define __INC_MAC_8723A_HW_IMG_H | ||
| 19 | |||
| 20 | /****************************************************************************** | ||
| 21 | * MAC_REG.TXT | ||
| 22 | ******************************************************************************/ | ||
| 23 | |||
| 24 | void ODM_ReadAndConfig_MAC_REG_8723A(struct dm_odm_t *pDM_Odm); | ||
| 25 | |||
| 26 | #endif /* end of HWIMG_SUPPORT */ | ||
diff --git a/drivers/staging/rtl8723au/include/HalHWImg8723A_RF.h b/drivers/staging/rtl8723au/include/HalHWImg8723A_RF.h new file mode 100644 index 000000000000..c9af1c375339 --- /dev/null +++ b/drivers/staging/rtl8723au/include/HalHWImg8723A_RF.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef __INC_RF_8723A_HW_IMG_H | ||
| 17 | #define __INC_RF_8723A_HW_IMG_H | ||
| 18 | |||
| 19 | /****************************************************************************** | ||
| 20 | * RadioA_1T.TXT | ||
| 21 | ******************************************************************************/ | ||
| 22 | |||
| 23 | void ODM_ReadAndConfig_RadioA_1T_8723A(struct dm_odm_t *pDM_Odm); | ||
| 24 | |||
| 25 | #endif /* end of HWIMG_SUPPORT */ | ||
diff --git a/drivers/staging/rtl8723au/include/HalPwrSeqCmd.h b/drivers/staging/rtl8723au/include/HalPwrSeqCmd.h new file mode 100644 index 000000000000..12e03a36f2d3 --- /dev/null +++ b/drivers/staging/rtl8723au/include/HalPwrSeqCmd.h | |||
| @@ -0,0 +1,130 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | #ifndef __HALPWRSEQCMD_H__ | ||
| 17 | #define __HALPWRSEQCMD_H__ | ||
| 18 | |||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | /*---------------------------------------------*/ | ||
| 22 | /*---------------------------------------------*/ | ||
| 23 | #define PWR_CMD_READ 0x00 | ||
| 24 | /* offset: the read register offset */ | ||
| 25 | /* msk: the mask of the read value */ | ||
| 26 | /* value: N/A, left by 0 */ | ||
| 27 | /* note: dirver shall implement this function by read & msk */ | ||
| 28 | |||
| 29 | #define PWR_CMD_WRITE 0x01 | ||
| 30 | /* offset: the read register offset */ | ||
| 31 | /* msk: the mask of the write bits */ | ||
| 32 | /* value: write value */ | ||
| 33 | /* note: driver shall implement this cmd by read & msk after write */ | ||
| 34 | |||
| 35 | #define PWR_CMD_POLLING 0x02 | ||
| 36 | /* offset: the read register offset */ | ||
| 37 | /* msk: the mask of the polled value */ | ||
| 38 | /* value: the value to be polled, masked by the msd field. */ | ||
| 39 | /* note: driver shall implement this cmd by */ | ||
| 40 | /* do{ */ | ||
| 41 | /* if( (Read(offset) & msk) == (value & msk) ) */ | ||
| 42 | /* break; */ | ||
| 43 | /* } while(not timeout); */ | ||
| 44 | |||
| 45 | #define PWR_CMD_DELAY 0x03 | ||
| 46 | /* offset: the value to delay */ | ||
| 47 | /* msk: N/A */ | ||
| 48 | /* value: the unit of delay, 0: us, 1: ms */ | ||
| 49 | |||
| 50 | #define PWR_CMD_END 0x04 | ||
| 51 | /* offset: N/A */ | ||
| 52 | /* msk: N/A */ | ||
| 53 | /* value: N/A */ | ||
| 54 | |||
| 55 | /*---------------------------------------------*/ | ||
| 56 | /* 3 The value of base: 4 bits */ | ||
| 57 | /*---------------------------------------------*/ | ||
| 58 | /* define the base address of each block */ | ||
| 59 | #define PWR_BASEADDR_MAC 0x00 | ||
| 60 | #define PWR_BASEADDR_USB 0x01 | ||
| 61 | #define PWR_BASEADDR_PCIE 0x02 | ||
| 62 | #define PWR_BASEADDR_SDIO 0x03 | ||
| 63 | |||
| 64 | /*---------------------------------------------*/ | ||
| 65 | /* 3 The value of interface_msk: 4 bits */ | ||
| 66 | /*---------------------------------------------*/ | ||
| 67 | #define PWR_INTF_SDIO_MSK BIT(0) | ||
| 68 | #define PWR_INTF_USB_MSK BIT(1) | ||
| 69 | #define PWR_INTF_PCI_MSK BIT(2) | ||
| 70 | #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) | ||
| 71 | |||
| 72 | /*---------------------------------------------*/ | ||
| 73 | /* 3 The value of fab_msk: 4 bits */ | ||
| 74 | /*---------------------------------------------*/ | ||
| 75 | #define PWR_FAB_TSMC_MSK BIT(0) | ||
| 76 | #define PWR_FAB_UMC_MSK BIT(1) | ||
| 77 | #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) | ||
| 78 | |||
| 79 | /*---------------------------------------------*/ | ||
| 80 | /* 3 The value of cut_msk: 8 bits */ | ||
| 81 | /*---------------------------------------------*/ | ||
| 82 | #define PWR_CUT_TESTCHIP_MSK BIT(0) | ||
| 83 | #define PWR_CUT_A_MSK BIT(1) | ||
| 84 | #define PWR_CUT_B_MSK BIT(2) | ||
| 85 | #define PWR_CUT_C_MSK BIT(3) | ||
| 86 | #define PWR_CUT_D_MSK BIT(4) | ||
| 87 | #define PWR_CUT_E_MSK BIT(5) | ||
| 88 | #define PWR_CUT_F_MSK BIT(6) | ||
| 89 | #define PWR_CUT_G_MSK BIT(7) | ||
| 90 | #define PWR_CUT_ALL_MSK 0xFF | ||
| 91 | |||
| 92 | |||
| 93 | enum pwrseq_delay_unit { | ||
| 94 | PWRSEQ_DELAY_US, | ||
| 95 | PWRSEQ_DELAY_MS, | ||
| 96 | }; | ||
| 97 | |||
| 98 | struct wlan_pwr_cfg { | ||
| 99 | u16 offset; | ||
| 100 | u8 cut_msk; | ||
| 101 | u8 fab_msk:4; | ||
| 102 | u8 interface_msk:4; | ||
| 103 | u8 base:4; | ||
| 104 | u8 cmd:4; | ||
| 105 | u8 msk; | ||
| 106 | u8 value; | ||
| 107 | }; | ||
| 108 | |||
| 109 | |||
| 110 | #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset | ||
| 111 | #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk | ||
| 112 | #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk | ||
| 113 | #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk | ||
| 114 | #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base | ||
| 115 | #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd | ||
| 116 | #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk | ||
| 117 | #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value | ||
| 118 | |||
| 119 | |||
| 120 | /* */ | ||
| 121 | /* Prototype of protected function. */ | ||
| 122 | /* */ | ||
| 123 | u8 HalPwrSeqCmdParsing23a( | ||
| 124 | struct rtw_adapter *padapter, | ||
| 125 | u8 CutVersion, | ||
| 126 | u8 FabVersion, | ||
| 127 | u8 InterfaceType, | ||
| 128 | struct wlan_pwr_cfg PwrCfgCmd[]); | ||
| 129 | |||
| 130 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/HalVerDef.h b/drivers/staging/rtl8723au/include/HalVerDef.h new file mode 100644 index 000000000000..607b71f6e1e4 --- /dev/null +++ b/drivers/staging/rtl8723au/include/HalVerDef.h | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __HAL_VERSION_DEF_H__ | ||
| 16 | #define __HAL_VERSION_DEF_H__ | ||
| 17 | |||
| 18 | enum hal_ic_type { | ||
| 19 | CHIP_8192S = 0, | ||
| 20 | CHIP_8188C = 1, | ||
| 21 | CHIP_8192C = 2, | ||
| 22 | CHIP_8192D = 3, | ||
| 23 | CHIP_8723A = 4, | ||
| 24 | CHIP_8188E = 5, | ||
| 25 | CHIP_8881A = 6, | ||
| 26 | CHIP_8812A = 7, | ||
| 27 | CHIP_8821A = 8, | ||
| 28 | CHIP_8723B = 9, | ||
| 29 | CHIP_8192E = 10, | ||
| 30 | }; | ||
| 31 | |||
| 32 | enum hal_chip_type { | ||
| 33 | TEST_CHIP = 0, | ||
| 34 | NORMAL_CHIP = 1, | ||
| 35 | FPGA = 2, | ||
| 36 | }; | ||
| 37 | |||
| 38 | enum hal_cut_version { | ||
| 39 | A_CUT_VERSION = 0, | ||
| 40 | B_CUT_VERSION = 1, | ||
| 41 | C_CUT_VERSION = 2, | ||
| 42 | D_CUT_VERSION = 3, | ||
| 43 | E_CUT_VERSION = 4, | ||
| 44 | F_CUT_VERSION = 5, | ||
| 45 | G_CUT_VERSION = 6, | ||
| 46 | }; | ||
| 47 | |||
| 48 | /* HAL_Manufacturer */ | ||
| 49 | enum hal_vendor { | ||
| 50 | CHIP_VENDOR_TSMC = 0, | ||
| 51 | CHIP_VENDOR_UMC = 1, | ||
| 52 | }; | ||
| 53 | |||
| 54 | enum hal_rf_type { | ||
| 55 | RF_TYPE_1T1R = 0, | ||
| 56 | RF_TYPE_1T2R = 1, | ||
| 57 | RF_TYPE_2T2R = 2, | ||
| 58 | RF_TYPE_2T3R = 3, | ||
| 59 | RF_TYPE_2T4R = 4, | ||
| 60 | RF_TYPE_3T3R = 5, | ||
| 61 | RF_TYPE_3T4R = 6, | ||
| 62 | RF_TYPE_4T4R = 7, | ||
| 63 | }; | ||
| 64 | |||
| 65 | struct hal_version { | ||
| 66 | enum hal_ic_type ICType; | ||
| 67 | enum hal_chip_type ChipType; | ||
| 68 | enum hal_cut_version CUTVersion; | ||
| 69 | enum hal_vendor VendorType; | ||
| 70 | enum hal_rf_type RFType; | ||
| 71 | u8 ROMVer; | ||
| 72 | }; | ||
| 73 | |||
| 74 | /* Get element */ | ||
| 75 | #define GET_CVID_IC_TYPE(version) ((version).ICType) | ||
| 76 | #define GET_CVID_CHIP_TYPE(version) ((version).ChipType) | ||
| 77 | #define GET_CVID_RF_TYPE(version) ((version).RFType) | ||
| 78 | #define GET_CVID_MANUFACTUER(version) ((version).VendorType) | ||
| 79 | #define GET_CVID_CUT_VERSION(version) ((version).CUTVersion) | ||
| 80 | #define GET_CVID_ROM_VERSION(version) (((version).ROMVer) & ROM_VERSION_MASK) | ||
| 81 | |||
| 82 | /* Common Macro. -- */ | ||
| 83 | |||
| 84 | #define IS_81XXC(version) \ | ||
| 85 | (((GET_CVID_IC_TYPE(version) == CHIP_8192C) || \ | ||
| 86 | (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? true : false) | ||
| 87 | #define IS_8723_SERIES(version) \ | ||
| 88 | ((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? true : false) | ||
| 89 | |||
| 90 | #define IS_TEST_CHIP(version) \ | ||
| 91 | ((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? true : false) | ||
| 92 | #define IS_NORMAL_CHIP(version) \ | ||
| 93 | ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? true : false) | ||
| 94 | |||
| 95 | #define IS_A_CUT(version) \ | ||
| 96 | ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? true : false) | ||
| 97 | #define IS_B_CUT(version) \ | ||
| 98 | ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true : false) | ||
| 99 | #define IS_C_CUT(version) \ | ||
| 100 | ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? true : false) | ||
| 101 | #define IS_D_CUT(version) \ | ||
| 102 | ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? true : false) | ||
| 103 | #define IS_E_CUT(version) \ | ||
| 104 | ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? true : false) | ||
| 105 | |||
| 106 | #define IS_CHIP_VENDOR_TSMC(version) \ | ||
| 107 | ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? true : false) | ||
| 108 | #define IS_CHIP_VENDOR_UMC(version) \ | ||
| 109 | ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? true : false) | ||
| 110 | |||
| 111 | #define IS_1T1R(version) \ | ||
| 112 | ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? true : false) | ||
| 113 | #define IS_1T2R(version) \ | ||
| 114 | ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? true : false) | ||
| 115 | #define IS_2T2R(version) \ | ||
| 116 | ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? true : false) | ||
| 117 | |||
| 118 | /* Chip version Macro. -- */ | ||
| 119 | |||
| 120 | #define IS_92C_SERIAL(version) \ | ||
| 121 | ((IS_81XXC(version) && IS_2T2R(version)) ? true : false) | ||
| 122 | #define IS_81xxC_VENDOR_UMC_A_CUT(version) \ | ||
| 123 | (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? \ | ||
| 124 | (IS_A_CUT(version) ? true : false) : false) : false) | ||
| 125 | #define IS_81xxC_VENDOR_UMC_B_CUT(version) \ | ||
| 126 | (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \ | ||
| 127 | (IS_B_CUT(version) ? true : false) : false): false) | ||
| 128 | #define IS_81xxC_VENDOR_UMC_C_CUT(version) \ | ||
| 129 | (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? \ | ||
| 130 | (IS_C_CUT(version) ? true : false) : false) : false) | ||
| 131 | #define IS_8723A_A_CUT(version) \ | ||
| 132 | ((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? true : false) : false) | ||
| 133 | #define IS_8723A_B_CUT(version) \ | ||
| 134 | ((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? true : false) : false) | ||
| 135 | |||
| 136 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/cmd_osdep.h b/drivers/staging/rtl8723au/include/cmd_osdep.h new file mode 100644 index 000000000000..4866bee04054 --- /dev/null +++ b/drivers/staging/rtl8723au/include/cmd_osdep.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __CMD_OSDEP_H_ | ||
| 16 | #define __CMD_OSDEP_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | int _rtw_init_evt_priv23a(struct evt_priv *pevtpriv); | ||
| 22 | void _rtw_free_evt_priv23a(struct evt_priv *pevtpriv); | ||
| 23 | void _rtw_free_cmd_priv23a(struct cmd_priv *pcmdpriv); | ||
| 24 | int _rtw_enqueue_cmd23a(struct rtw_queue *queue, struct cmd_obj *obj); | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/drv_types.h b/drivers/staging/rtl8723au/include/drv_types.h new file mode 100644 index 000000000000..58479884254a --- /dev/null +++ b/drivers/staging/rtl8723au/include/drv_types.h | |||
| @@ -0,0 +1,364 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | /*----------------------------------------------------------------------------- | ||
| 16 | |||
| 17 | For type defines and data structure defines | ||
| 18 | |||
| 19 | ------------------------------------------------------------------------------*/ | ||
| 20 | |||
| 21 | |||
| 22 | #ifndef __DRV_TYPES_H__ | ||
| 23 | #define __DRV_TYPES_H__ | ||
| 24 | |||
| 25 | #include <osdep_service.h> | ||
| 26 | #include <wlan_bssdef.h> | ||
| 27 | |||
| 28 | |||
| 29 | enum _NIC_VERSION { | ||
| 30 | RTL8711_NIC, | ||
| 31 | RTL8712_NIC, | ||
| 32 | RTL8713_NIC, | ||
| 33 | RTL8716_NIC | ||
| 34 | |||
| 35 | }; | ||
| 36 | |||
| 37 | |||
| 38 | #include <rtw_ht.h> | ||
| 39 | |||
| 40 | #include <rtw_cmd.h> | ||
| 41 | #include <wlan_bssdef.h> | ||
| 42 | #include <rtw_xmit.h> | ||
| 43 | #include <rtw_recv.h> | ||
| 44 | #include <hal_intf.h> | ||
| 45 | #include <hal_com.h> | ||
| 46 | #include <rtw_qos.h> | ||
| 47 | #include <rtw_security.h> | ||
| 48 | #include <rtw_pwrctrl.h> | ||
| 49 | #include <rtw_io.h> | ||
| 50 | #include <rtw_eeprom.h> | ||
| 51 | #include <sta_info.h> | ||
| 52 | #include <rtw_mlme.h> | ||
| 53 | #include <rtw_debug.h> | ||
| 54 | #include <rtw_rf.h> | ||
| 55 | #include <rtw_event.h> | ||
| 56 | #include <rtw_led.h> | ||
| 57 | #include <rtw_mlme_ext.h> | ||
| 58 | #include <rtw_p2p.h> | ||
| 59 | #include <rtw_ap.h> | ||
| 60 | |||
| 61 | #include "ioctl_cfg80211.h" | ||
| 62 | |||
| 63 | #define SPEC_DEV_ID_NONE BIT(0) | ||
| 64 | #define SPEC_DEV_ID_DISABLE_HT BIT(1) | ||
| 65 | #define SPEC_DEV_ID_ENABLE_PS BIT(2) | ||
| 66 | #define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) | ||
| 67 | #define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) | ||
| 68 | #define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) | ||
| 69 | |||
| 70 | struct specific_device_id { | ||
| 71 | u32 flags; | ||
| 72 | |||
| 73 | u16 idVendor; | ||
| 74 | u16 idProduct; | ||
| 75 | |||
| 76 | }; | ||
| 77 | |||
| 78 | struct registry_priv { | ||
| 79 | u8 chip_version; | ||
| 80 | u8 rfintfs; | ||
| 81 | struct cfg80211_ssid ssid; | ||
| 82 | u8 channel;/* ad-hoc support requirement */ | ||
| 83 | u8 wireless_mode;/* A, B, G, auto */ | ||
| 84 | u8 scan_mode;/* active, passive */ | ||
| 85 | u8 preamble;/* long, short, auto */ | ||
| 86 | u8 vrtl_carrier_sense;/* Enable, Disable, Auto */ | ||
| 87 | u8 vcs_type;/* RTS/CTS, CTS-to-self */ | ||
| 88 | u16 rts_thresh; | ||
| 89 | u16 frag_thresh; | ||
| 90 | u8 adhoc_tx_pwr; | ||
| 91 | u8 soft_ap; | ||
| 92 | u8 power_mgnt; | ||
| 93 | u8 ips_mode; | ||
| 94 | u8 smart_ps; | ||
| 95 | u8 long_retry_lmt; | ||
| 96 | u8 short_retry_lmt; | ||
| 97 | u16 busy_thresh; | ||
| 98 | u8 ack_policy; | ||
| 99 | u8 software_encrypt; | ||
| 100 | u8 software_decrypt; | ||
| 101 | u8 acm_method; | ||
| 102 | /* UAPSD */ | ||
| 103 | u8 wmm_enable; | ||
| 104 | u8 uapsd_enable; | ||
| 105 | |||
| 106 | struct wlan_bssid_ex dev_network; | ||
| 107 | |||
| 108 | u8 ht_enable; | ||
| 109 | u8 cbw40_enable; | ||
| 110 | u8 ampdu_enable;/* for tx */ | ||
| 111 | u8 rx_stbc; | ||
| 112 | u8 ampdu_amsdu;/* A-MPDU Supports A-MSDU is permitted */ | ||
| 113 | u8 lowrate_two_xmit; | ||
| 114 | |||
| 115 | u8 rf_config; | ||
| 116 | u8 low_power; | ||
| 117 | |||
| 118 | u8 wifi_spec;/* !turbo_mode */ | ||
| 119 | |||
| 120 | u8 channel_plan; | ||
| 121 | #ifdef CONFIG_8723AU_BT_COEXIST | ||
| 122 | u8 btcoex; | ||
| 123 | u8 bt_iso; | ||
| 124 | u8 bt_sco; | ||
| 125 | u8 bt_ampdu; | ||
| 126 | #endif | ||
| 127 | bool bAcceptAddbaReq; | ||
| 128 | |||
| 129 | u8 antdiv_cfg; | ||
| 130 | u8 antdiv_type; | ||
| 131 | |||
| 132 | u8 usbss_enable;/* 0:disable,1:enable */ | ||
| 133 | u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */ | ||
| 134 | u8 hwpwrp_detect;/* 0:disable,1:enable */ | ||
| 135 | |||
| 136 | u8 hw_wps_pbc;/* 0:disable,1:enable */ | ||
| 137 | |||
| 138 | u8 max_roaming_times; /* max number driver will try to roaming */ | ||
| 139 | |||
| 140 | u8 enable80211d; | ||
| 141 | |||
| 142 | u8 ifname[16]; | ||
| 143 | u8 if2name[16]; | ||
| 144 | |||
| 145 | u8 notch_filter; | ||
| 146 | |||
| 147 | u8 regulatory_tid; | ||
| 148 | }; | ||
| 149 | |||
| 150 | |||
| 151 | #define MAX_CONTINUAL_URB_ERR 4 | ||
| 152 | |||
| 153 | #define GET_PRIMARY_ADAPTER(padapter) \ | ||
| 154 | (((struct rtw_adapter *)padapter)->dvobj->if1) | ||
| 155 | |||
| 156 | enum _IFACE_ID { | ||
| 157 | IFACE_ID0, /* maping to PRIMARY_ADAPTER */ | ||
| 158 | IFACE_ID1, /* maping to SECONDARY_ADAPTER */ | ||
| 159 | IFACE_ID2, | ||
| 160 | IFACE_ID3, | ||
| 161 | IFACE_ID_MAX, | ||
| 162 | }; | ||
| 163 | |||
| 164 | struct dvobj_priv { | ||
| 165 | struct rtw_adapter *if1; /* PRIMARY_ADAPTER */ | ||
| 166 | struct rtw_adapter *if2; /* SECONDARY_ADAPTER */ | ||
| 167 | |||
| 168 | /* for local/global synchronization */ | ||
| 169 | struct mutex hw_init_mutex; | ||
| 170 | struct mutex h2c_fwcmd_mutex; | ||
| 171 | struct mutex setch_mutex; | ||
| 172 | struct mutex setbw_mutex; | ||
| 173 | |||
| 174 | unsigned char oper_channel; /* saved chan info when set chan bw */ | ||
| 175 | unsigned char oper_bwmode; | ||
| 176 | unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */ | ||
| 177 | |||
| 178 | struct rtw_adapter *padapters[IFACE_ID_MAX]; | ||
| 179 | u8 iface_nums; /* total number of ifaces used runtime */ | ||
| 180 | |||
| 181 | /* For 92D, DMDP have 2 interface. */ | ||
| 182 | u8 InterfaceNumber; | ||
| 183 | u8 NumInterfaces; | ||
| 184 | |||
| 185 | /* In /Out Pipe information */ | ||
| 186 | int RtInPipe[2]; | ||
| 187 | int RtOutPipe[3]; | ||
| 188 | u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */ | ||
| 189 | |||
| 190 | u8 irq_alloc; | ||
| 191 | |||
| 192 | /*-------- below is for USB INTERFACE --------*/ | ||
| 193 | |||
| 194 | u8 nr_endpoint; | ||
| 195 | u8 ishighspeed; | ||
| 196 | u8 RtNumInPipes; | ||
| 197 | u8 RtNumOutPipes; | ||
| 198 | int ep_num[5]; /* endpoint number */ | ||
| 199 | |||
| 200 | int RegUsbSS; | ||
| 201 | |||
| 202 | struct semaphore usb_suspend_sema; | ||
| 203 | |||
| 204 | struct mutex usb_vendor_req_mutex; | ||
| 205 | |||
| 206 | u8 *usb_alloc_vendor_req_buf; | ||
| 207 | u8 *usb_vendor_req_buf; | ||
| 208 | |||
| 209 | struct usb_interface *pusbintf; | ||
| 210 | struct usb_device *pusbdev; | ||
| 211 | atomic_t continual_urb_error; | ||
| 212 | |||
| 213 | /*-------- below is for PCIE INTERFACE --------*/ | ||
| 214 | |||
| 215 | }; | ||
| 216 | |||
| 217 | static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj) | ||
| 218 | { | ||
| 219 | /* todo: get interface type from dvobj and the return the dev accordingly */ | ||
| 220 | return &dvobj->pusbintf->dev; | ||
| 221 | } | ||
| 222 | |||
| 223 | enum _IFACE_TYPE { | ||
| 224 | IFACE_PORT0, /* mapping to port0 for C/D series chips */ | ||
| 225 | IFACE_PORT1, /* mapping to port1 for C/D series chip */ | ||
| 226 | MAX_IFACE_PORT, | ||
| 227 | }; | ||
| 228 | |||
| 229 | enum _ADAPTER_TYPE { | ||
| 230 | PRIMARY_ADAPTER, | ||
| 231 | SECONDARY_ADAPTER, | ||
| 232 | MAX_ADAPTER, | ||
| 233 | }; | ||
| 234 | |||
| 235 | struct rtw_adapter { | ||
| 236 | int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */ | ||
| 237 | int bDongle;/* build-in module or external dongle */ | ||
| 238 | u16 chip_type; | ||
| 239 | u16 HardwareType; | ||
| 240 | |||
| 241 | struct dvobj_priv *dvobj; | ||
| 242 | struct mlme_priv mlmepriv; | ||
| 243 | struct mlme_ext_priv mlmeextpriv; | ||
| 244 | struct cmd_priv cmdpriv; | ||
| 245 | struct evt_priv evtpriv; | ||
| 246 | /* struct io_queue *pio_queue; */ | ||
| 247 | struct io_priv iopriv; | ||
| 248 | struct xmit_priv xmitpriv; | ||
| 249 | struct recv_priv recvpriv; | ||
| 250 | struct sta_priv stapriv; | ||
| 251 | struct security_priv securitypriv; | ||
| 252 | struct registry_priv registrypriv; | ||
| 253 | struct pwrctrl_priv pwrctrlpriv; | ||
| 254 | struct eeprom_priv eeprompriv; | ||
| 255 | struct led_priv ledpriv; | ||
| 256 | |||
| 257 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 258 | struct hostapd_priv *phostapdpriv; | ||
| 259 | #endif | ||
| 260 | |||
| 261 | #ifdef CONFIG_8723AU_P2P | ||
| 262 | struct cfg80211_wifidirect_info cfg80211_wdinfo; | ||
| 263 | #endif /* CONFIG_8723AU_P2P */ | ||
| 264 | u32 setband; | ||
| 265 | #ifdef CONFIG_8723AU_P2P | ||
| 266 | struct wifidirect_info wdinfo; | ||
| 267 | #endif /* CONFIG_8723AU_P2P */ | ||
| 268 | |||
| 269 | #ifdef CONFIG_8723AU_P2P | ||
| 270 | struct wifi_display_info wfd_info; | ||
| 271 | #endif /* CONFIG_8723AU_P2P */ | ||
| 272 | |||
| 273 | void *HalData; | ||
| 274 | u32 hal_data_sz; | ||
| 275 | struct hal_ops HalFunc; | ||
| 276 | |||
| 277 | s32 bDriverStopped; | ||
| 278 | s32 bSurpriseRemoved; | ||
| 279 | s32 bCardDisableWOHSM; | ||
| 280 | |||
| 281 | u32 IsrContent; | ||
| 282 | u32 ImrContent; | ||
| 283 | |||
| 284 | u8 EepromAddressSize; | ||
| 285 | u8 hw_init_completed; | ||
| 286 | u8 bDriverIsGoingToUnload; | ||
| 287 | u8 init_adpt_in_progress; | ||
| 288 | u8 bHaltInProgress; | ||
| 289 | |||
| 290 | void *cmdThread; | ||
| 291 | void *evtThread; | ||
| 292 | void *xmitThread; | ||
| 293 | void *recvThread; | ||
| 294 | |||
| 295 | void (*intf_start)(struct rtw_adapter *adapter); | ||
| 296 | void (*intf_stop)(struct rtw_adapter *adapter); | ||
| 297 | |||
| 298 | struct net_device *pnetdev; | ||
| 299 | |||
| 300 | /* used by rtw_rereg_nd_name related function */ | ||
| 301 | struct rereg_nd_name_data { | ||
| 302 | struct net_device *old_pnetdev; | ||
| 303 | char old_ifname[IFNAMSIZ]; | ||
| 304 | u8 old_ips_mode; | ||
| 305 | u8 old_bRegUseLed; | ||
| 306 | } rereg_nd_name_priv; | ||
| 307 | |||
| 308 | int bup; | ||
| 309 | struct net_device_stats stats; | ||
| 310 | struct iw_statistics iwstats; | ||
| 311 | struct proc_dir_entry *dir_dev;/* for proc directory */ | ||
| 312 | |||
| 313 | struct wireless_dev *rtw_wdev; | ||
| 314 | int net_closed; | ||
| 315 | |||
| 316 | u8 bFWReady; | ||
| 317 | u8 bBTFWReady; | ||
| 318 | u8 bReadPortCancel; | ||
| 319 | u8 bWritePortCancel; | ||
| 320 | u8 bRxRSSIDisplay; | ||
| 321 | /* The driver will show the desired chan nor when this flag is 1. */ | ||
| 322 | u8 bNotifyChannelChange; | ||
| 323 | #ifdef CONFIG_8723AU_P2P | ||
| 324 | /* driver will show current P2P status when the application reads it*/ | ||
| 325 | u8 bShowGetP2PState; | ||
| 326 | #endif | ||
| 327 | struct rtw_adapter *pbuddy_adapter; | ||
| 328 | |||
| 329 | /* extend to support multi interface */ | ||
| 330 | /* IFACE_ID0 is equals to PRIMARY_ADAPTER */ | ||
| 331 | /* IFACE_ID1 is equals to SECONDARY_ADAPTER */ | ||
| 332 | u8 iface_id; | ||
| 333 | |||
| 334 | #ifdef CONFIG_BR_EXT | ||
| 335 | _lock br_ext_lock; | ||
| 336 | /* unsigned int macclone_completed; */ | ||
| 337 | struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE]; | ||
| 338 | int pppoe_connection_in_progress; | ||
| 339 | unsigned char pppoe_addr[MACADDRLEN]; | ||
| 340 | unsigned char scdb_mac[MACADDRLEN]; | ||
| 341 | unsigned char scdb_ip[4]; | ||
| 342 | struct nat25_network_db_entry *scdb_entry; | ||
| 343 | unsigned char br_mac[MACADDRLEN]; | ||
| 344 | unsigned char br_ip[4]; | ||
| 345 | |||
| 346 | struct br_ext_info ethBrExtInfo; | ||
| 347 | #endif /* CONFIG_BR_EXT */ | ||
| 348 | |||
| 349 | u8 fix_rate; | ||
| 350 | |||
| 351 | unsigned char in_cta_test; | ||
| 352 | |||
| 353 | }; | ||
| 354 | |||
| 355 | #define adapter_to_dvobj(adapter) (adapter->dvobj) | ||
| 356 | |||
| 357 | int rtw_handle_dualmac23a(struct rtw_adapter *adapter, bool init); | ||
| 358 | |||
| 359 | static inline u8 *myid(struct eeprom_priv *peepriv) | ||
| 360 | { | ||
| 361 | return peepriv->mac_addr; | ||
| 362 | } | ||
| 363 | |||
| 364 | #endif /* __DRV_TYPES_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/ethernet.h b/drivers/staging/rtl8723au/include/ethernet.h new file mode 100644 index 000000000000..39fc6df88188 --- /dev/null +++ b/drivers/staging/rtl8723au/include/ethernet.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | /*! \file */ | ||
| 17 | #ifndef __INC_ETHERNET_H | ||
| 18 | #define __INC_ETHERNET_H | ||
| 19 | |||
| 20 | #define LLC_HEADER_SIZE 6 /* LLC Header Length */ | ||
| 21 | |||
| 22 | #endif /* #ifndef __INC_ETHERNET_H */ | ||
diff --git a/drivers/staging/rtl8723au/include/hal_com.h b/drivers/staging/rtl8723au/include/hal_com.h new file mode 100644 index 000000000000..20f983cfc2b7 --- /dev/null +++ b/drivers/staging/rtl8723au/include/hal_com.h | |||
| @@ -0,0 +1,211 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __HAL_COMMON_H__ | ||
| 16 | #define __HAL_COMMON_H__ | ||
| 17 | |||
| 18 | /* */ | ||
| 19 | /* Rate Definition */ | ||
| 20 | /* */ | ||
| 21 | /* CCK */ | ||
| 22 | #define RATR_1M 0x00000001 | ||
| 23 | #define RATR_2M 0x00000002 | ||
| 24 | #define RATR_55M 0x00000004 | ||
| 25 | #define RATR_11M 0x00000008 | ||
| 26 | /* OFDM */ | ||
| 27 | #define RATR_6M 0x00000010 | ||
| 28 | #define RATR_9M 0x00000020 | ||
| 29 | #define RATR_12M 0x00000040 | ||
| 30 | #define RATR_18M 0x00000080 | ||
| 31 | #define RATR_24M 0x00000100 | ||
| 32 | #define RATR_36M 0x00000200 | ||
| 33 | #define RATR_48M 0x00000400 | ||
| 34 | #define RATR_54M 0x00000800 | ||
| 35 | /* MCS 1 Spatial Stream */ | ||
| 36 | #define RATR_MCS0 0x00001000 | ||
| 37 | #define RATR_MCS1 0x00002000 | ||
| 38 | #define RATR_MCS2 0x00004000 | ||
| 39 | #define RATR_MCS3 0x00008000 | ||
| 40 | #define RATR_MCS4 0x00010000 | ||
| 41 | #define RATR_MCS5 0x00020000 | ||
| 42 | #define RATR_MCS6 0x00040000 | ||
| 43 | #define RATR_MCS7 0x00080000 | ||
| 44 | /* MCS 2 Spatial Stream */ | ||
| 45 | #define RATR_MCS8 0x00100000 | ||
| 46 | #define RATR_MCS9 0x00200000 | ||
| 47 | #define RATR_MCS10 0x00400000 | ||
| 48 | #define RATR_MCS11 0x00800000 | ||
| 49 | #define RATR_MCS12 0x01000000 | ||
| 50 | #define RATR_MCS13 0x02000000 | ||
| 51 | #define RATR_MCS14 0x04000000 | ||
| 52 | #define RATR_MCS15 0x08000000 | ||
| 53 | |||
| 54 | /* CCK */ | ||
| 55 | #define RATE_1M BIT(0) | ||
| 56 | #define RATE_2M BIT(1) | ||
| 57 | #define RATE_5_5M BIT(2) | ||
| 58 | #define RATE_11M BIT(3) | ||
| 59 | /* OFDM */ | ||
| 60 | #define RATE_6M BIT(4) | ||
| 61 | #define RATE_9M BIT(5) | ||
| 62 | #define RATE_12M BIT(6) | ||
| 63 | #define RATE_18M BIT(7) | ||
| 64 | #define RATE_24M BIT(8) | ||
| 65 | #define RATE_36M BIT(9) | ||
| 66 | #define RATE_48M BIT(10) | ||
| 67 | #define RATE_54M BIT(11) | ||
| 68 | /* MCS 1 Spatial Stream */ | ||
| 69 | #define RATE_MCS0 BIT(12) | ||
| 70 | #define RATE_MCS1 BIT(13) | ||
| 71 | #define RATE_MCS2 BIT(14) | ||
| 72 | #define RATE_MCS3 BIT(15) | ||
| 73 | #define RATE_MCS4 BIT(16) | ||
| 74 | #define RATE_MCS5 BIT(17) | ||
| 75 | #define RATE_MCS6 BIT(18) | ||
| 76 | #define RATE_MCS7 BIT(19) | ||
| 77 | /* MCS 2 Spatial Stream */ | ||
| 78 | #define RATE_MCS8 BIT(20) | ||
| 79 | #define RATE_MCS9 BIT(21) | ||
| 80 | #define RATE_MCS10 BIT(22) | ||
| 81 | #define RATE_MCS11 BIT(23) | ||
| 82 | #define RATE_MCS12 BIT(24) | ||
| 83 | #define RATE_MCS13 BIT(25) | ||
| 84 | #define RATE_MCS14 BIT(26) | ||
| 85 | #define RATE_MCS15 BIT(27) | ||
| 86 | |||
| 87 | /* ALL CCK Rate */ | ||
| 88 | #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) | ||
| 89 | #define RATE_ALL_OFDM_AG \ | ||
| 90 | (RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M| \ | ||
| 91 | RATR_36M|RATR_48M|RATR_54M) | ||
| 92 | #define RATE_ALL_OFDM_1SS \ | ||
| 93 | (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 | \ | ||
| 94 | RATR_MCS4 | RATR_MCS5 | RATR_MCS6 | RATR_MCS7) | ||
| 95 | #define RATE_ALL_OFDM_2SS \ | ||
| 96 | (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11| \ | ||
| 97 | RATR_MCS12 | RATR_MCS13 | RATR_MCS14 | RATR_MCS15) | ||
| 98 | |||
| 99 | /*------------------------------ Tx Desc definition Macro ------------------------*/ | ||
| 100 | /* pragma mark -- Tx Desc related definition. -- */ | ||
| 101 | /* */ | ||
| 102 | /* */ | ||
| 103 | /* Rate */ | ||
| 104 | /* */ | ||
| 105 | /* CCK Rates, TxHT = 0 */ | ||
| 106 | #define DESC_RATE1M 0x00 | ||
| 107 | #define DESC_RATE2M 0x01 | ||
| 108 | #define DESC_RATE5_5M 0x02 | ||
| 109 | #define DESC_RATE11M 0x03 | ||
| 110 | |||
| 111 | /* OFDM Rates, TxHT = 0 */ | ||
| 112 | #define DESC_RATE6M 0x04 | ||
| 113 | #define DESC_RATE9M 0x05 | ||
| 114 | #define DESC_RATE12M 0x06 | ||
| 115 | #define DESC_RATE18M 0x07 | ||
| 116 | #define DESC_RATE24M 0x08 | ||
| 117 | #define DESC_RATE36M 0x09 | ||
| 118 | #define DESC_RATE48M 0x0a | ||
| 119 | #define DESC_RATE54M 0x0b | ||
| 120 | |||
| 121 | /* MCS Rates, TxHT = 1 */ | ||
| 122 | #define DESC_RATEMCS0 0x0c | ||
| 123 | #define DESC_RATEMCS1 0x0d | ||
| 124 | #define DESC_RATEMCS2 0x0e | ||
| 125 | #define DESC_RATEMCS3 0x0f | ||
| 126 | #define DESC_RATEMCS4 0x10 | ||
| 127 | #define DESC_RATEMCS5 0x11 | ||
| 128 | #define DESC_RATEMCS6 0x12 | ||
| 129 | #define DESC_RATEMCS7 0x13 | ||
| 130 | #define DESC_RATEMCS8 0x14 | ||
| 131 | #define DESC_RATEMCS9 0x15 | ||
| 132 | #define DESC_RATEMCS10 0x16 | ||
| 133 | #define DESC_RATEMCS11 0x17 | ||
| 134 | #define DESC_RATEMCS12 0x18 | ||
| 135 | #define DESC_RATEMCS13 0x19 | ||
| 136 | #define DESC_RATEMCS14 0x1a | ||
| 137 | #define DESC_RATEMCS15 0x1b | ||
| 138 | #define DESC_RATEMCS15_SG 0x1c | ||
| 139 | #define DESC_RATEMCS32 0x20 | ||
| 140 | |||
| 141 | #define REG_P2P_CTWIN 0x0572 /* 1 Byte long (in unit of TU) */ | ||
| 142 | #define REG_NOA_DESC_SEL 0x05CF | ||
| 143 | #define REG_NOA_DESC_DURATION 0x05E0 | ||
| 144 | #define REG_NOA_DESC_INTERVAL 0x05E4 | ||
| 145 | #define REG_NOA_DESC_START 0x05E8 | ||
| 146 | #define REG_NOA_DESC_COUNT 0x05EC | ||
| 147 | |||
| 148 | #include "HalVerDef.h" | ||
| 149 | void dump_chip_info23a(struct hal_version ChipVersion); | ||
| 150 | |||
| 151 | |||
| 152 | u8 /* return the final channel plan decision */ | ||
| 153 | hal_com_get_channel_plan23a( | ||
| 154 | struct rtw_adapter *padapter, | ||
| 155 | u8 hw_channel_plan, /* channel plan from HW (efuse/eeprom) */ | ||
| 156 | u8 sw_channel_plan, /* channel plan from SW (registry/module param) */ | ||
| 157 | u8 def_channel_plan, /* channel plan used when the former two is invalid */ | ||
| 158 | bool AutoLoadFail | ||
| 159 | ); | ||
| 160 | |||
| 161 | u8 MRateToHwRate23a(u8 rate); | ||
| 162 | |||
| 163 | void HalSetBrateCfg23a(struct rtw_adapter *padapter, u8 *mBratesOS); | ||
| 164 | |||
| 165 | bool | ||
| 166 | Hal_MappingOutPipe23a(struct rtw_adapter *pAdapter, u8 NumOutPipe); | ||
| 167 | |||
| 168 | void hal_init_macaddr23a(struct rtw_adapter *adapter); | ||
| 169 | |||
| 170 | void c2h_evt_clear23a(struct rtw_adapter *adapter); | ||
| 171 | s32 c2h_evt_read23a(struct rtw_adapter *adapter, u8 *buf); | ||
| 172 | |||
| 173 | void rtl8723a_set_ampdu_min_space(struct rtw_adapter *padapter, u8 MinSpacingToSet); | ||
| 174 | void rtl8723a_set_ampdu_factor(struct rtw_adapter *padapter, u8 FactorToSet); | ||
| 175 | void rtl8723a_set_acm_ctrl(struct rtw_adapter *padapter, u8 ctrl); | ||
| 176 | void rtl8723a_set_media_status(struct rtw_adapter *padapter, u8 status); | ||
| 177 | void rtl8723a_set_media_status1(struct rtw_adapter *padapter, u8 status); | ||
| 178 | void rtl8723a_set_bcn_func(struct rtw_adapter *padapter, u8 val); | ||
| 179 | void rtl8723a_check_bssid(struct rtw_adapter *padapter, u8 val); | ||
| 180 | void rtl8723a_mlme_sitesurvey(struct rtw_adapter *padapter, u8 flag); | ||
| 181 | void rtl8723a_on_rcr_am(struct rtw_adapter *padapter); | ||
| 182 | void rtl8723a_off_rcr_am(struct rtw_adapter *padapter); | ||
| 183 | void rtl8723a_set_slot_time(struct rtw_adapter *padapter, u8 slottime); | ||
| 184 | void rtl8723a_ack_preamble(struct rtw_adapter *padapter, u8 bShortPreamble); | ||
| 185 | void rtl8723a_set_sec_cfg(struct rtw_adapter *padapter, u8 sec); | ||
| 186 | void rtl8723a_cam_empty_entry(struct rtw_adapter *padapter, u8 ucIndex); | ||
| 187 | void rtl8723a_cam_invalid_all(struct rtw_adapter *padapter); | ||
| 188 | void rtl8723a_cam_write(struct rtw_adapter *padapter, u32 val1, u32 val2); | ||
| 189 | void rtl8723a_fifo_cleanup(struct rtw_adapter *padapter); | ||
| 190 | void rtl8723a_set_apfm_on_mac(struct rtw_adapter *padapter, u8 val); | ||
| 191 | void rtl8723a_bcn_valid(struct rtw_adapter *padapter); | ||
| 192 | void rtl8723a_set_tx_pause(struct rtw_adapter *padapter, u8 pause); | ||
| 193 | void rtl8723a_set_beacon_interval(struct rtw_adapter *padapter, u16 interval); | ||
| 194 | void rtl8723a_set_resp_sifs(struct rtw_adapter *padapter, | ||
| 195 | u8 r2t1, u8 r2t2, u8 t2t1, u8 t2t2); | ||
| 196 | void rtl8723a_set_ac_param_vo(struct rtw_adapter *padapter, u32 vo); | ||
| 197 | void rtl8723a_set_ac_param_vi(struct rtw_adapter *padapter, u32 vi); | ||
| 198 | void rtl8723a_set_ac_param_be(struct rtw_adapter *padapter, u32 be); | ||
| 199 | void rtl8723a_set_ac_param_bk(struct rtw_adapter *padapter, u32 bk); | ||
| 200 | void rtl8723a_set_rxdma_agg_pg_th(struct rtw_adapter *padapter, u8 val); | ||
| 201 | void rtl8723a_set_nav_upper(struct rtw_adapter *padapter, u32 usNavUpper); | ||
| 202 | void rtl8723a_set_initial_gain(struct rtw_adapter *padapter, u32 rx_gain); | ||
| 203 | |||
| 204 | void rtl8723a_odm_support_ability_write(struct rtw_adapter *padapter, u32 val); | ||
| 205 | void rtl8723a_odm_support_ability_backup(struct rtw_adapter *padapter, u8 val); | ||
| 206 | void rtl8723a_odm_support_ability_set(struct rtw_adapter *padapter, u32 val); | ||
| 207 | void rtl8723a_odm_support_ability_clr(struct rtw_adapter *padapter, u32 val); | ||
| 208 | |||
| 209 | void rtl8723a_set_rpwm(struct rtw_adapter *padapter, u8 val); | ||
| 210 | |||
| 211 | #endif /* __HAL_COMMON_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/hal_intf.h b/drivers/staging/rtl8723au/include/hal_intf.h new file mode 100644 index 000000000000..d183f4ba1ecb --- /dev/null +++ b/drivers/staging/rtl8723au/include/hal_intf.h | |||
| @@ -0,0 +1,392 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __HAL_INTF_H__ | ||
| 16 | #define __HAL_INTF_H__ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | enum RTL871X_HCI_TYPE { | ||
| 22 | RTW_PCIE = BIT0, | ||
| 23 | RTW_USB = BIT1, | ||
| 24 | RTW_SDIO = BIT2, | ||
| 25 | RTW_GSPI = BIT3, | ||
| 26 | }; | ||
| 27 | |||
| 28 | enum _CHIP_TYPE { | ||
| 29 | NULL_CHIP_TYPE, | ||
| 30 | RTL8712_8188S_8191S_8192S, | ||
| 31 | RTL8188C_8192C, | ||
| 32 | RTL8192D, | ||
| 33 | RTL8723A, | ||
| 34 | RTL8188E, | ||
| 35 | MAX_CHIP_TYPE | ||
| 36 | }; | ||
| 37 | |||
| 38 | enum HW_VARIABLES { | ||
| 39 | HW_VAR_MEDIA_STATUS, | ||
| 40 | HW_VAR_MEDIA_STATUS1, | ||
| 41 | HW_VAR_SET_OPMODE, | ||
| 42 | HW_VAR_MAC_ADDR, | ||
| 43 | HW_VAR_BSSID, | ||
| 44 | HW_VAR_INIT_RTS_RATE, | ||
| 45 | HW_VAR_BASIC_RATE, | ||
| 46 | HW_VAR_TXPAUSE, | ||
| 47 | HW_VAR_BCN_FUNC, | ||
| 48 | HW_VAR_CORRECT_TSF, | ||
| 49 | HW_VAR_CHECK_BSSID, | ||
| 50 | HW_VAR_MLME_DISCONNECT, | ||
| 51 | HW_VAR_MLME_SITESURVEY, | ||
| 52 | HW_VAR_MLME_JOIN, | ||
| 53 | HW_VAR_ON_RCR_AM, | ||
| 54 | HW_VAR_OFF_RCR_AM, | ||
| 55 | HW_VAR_BEACON_INTERVAL, | ||
| 56 | HW_VAR_SLOT_TIME, | ||
| 57 | HW_VAR_RESP_SIFS, | ||
| 58 | HW_VAR_ACK_PREAMBLE, | ||
| 59 | HW_VAR_SEC_CFG, | ||
| 60 | HW_VAR_BCN_VALID, | ||
| 61 | HW_VAR_RF_TYPE, | ||
| 62 | HW_VAR_DM_FLAG, | ||
| 63 | HW_VAR_DM_FUNC_OP, | ||
| 64 | HW_VAR_DM_FUNC_SET, | ||
| 65 | HW_VAR_DM_FUNC_CLR, | ||
| 66 | HW_VAR_CAM_EMPTY_ENTRY, | ||
| 67 | HW_VAR_CAM_INVALID_ALL, | ||
| 68 | HW_VAR_CAM_WRITE, | ||
| 69 | HW_VAR_CAM_READ, | ||
| 70 | HW_VAR_AC_PARAM_VO, | ||
| 71 | HW_VAR_AC_PARAM_VI, | ||
| 72 | HW_VAR_AC_PARAM_BE, | ||
| 73 | HW_VAR_AC_PARAM_BK, | ||
| 74 | HW_VAR_ACM_CTRL, | ||
| 75 | HW_VAR_AMPDU_MIN_SPACE, | ||
| 76 | HW_VAR_AMPDU_FACTOR, | ||
| 77 | HW_VAR_RXDMA_AGG_PG_TH, | ||
| 78 | HW_VAR_SET_RPWM, | ||
| 79 | HW_VAR_H2C_FW_PWRMODE, | ||
| 80 | HW_VAR_H2C_FW_JOINBSSRPT, | ||
| 81 | HW_VAR_FWLPS_RF_ON, | ||
| 82 | HW_VAR_H2C_FW_P2P_PS_OFFLOAD, | ||
| 83 | HW_VAR_TDLS_WRCR, | ||
| 84 | HW_VAR_TDLS_INIT_CH_SEN, | ||
| 85 | HW_VAR_TDLS_RS_RCR, | ||
| 86 | HW_VAR_TDLS_DONE_CH_SEN, | ||
| 87 | HW_VAR_INITIAL_GAIN, | ||
| 88 | HW_VAR_TRIGGER_GPIO_0, | ||
| 89 | HW_VAR_BT_SET_COEXIST, | ||
| 90 | HW_VAR_BT_ISSUE_DELBA, | ||
| 91 | HW_VAR_CURRENT_ANTENNA, | ||
| 92 | HW_VAR_ANTENNA_DIVERSITY_LINK, | ||
| 93 | HW_VAR_ANTENNA_DIVERSITY_SELECT, | ||
| 94 | HW_VAR_SWITCH_EPHY_WoWLAN, | ||
| 95 | HW_VAR_EFUSE_BYTES, | ||
| 96 | HW_VAR_EFUSE_BT_BYTES, | ||
| 97 | HW_VAR_FIFO_CLEARN_UP, | ||
| 98 | HW_VAR_CHECK_TXBUF, | ||
| 99 | HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ | ||
| 100 | /* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */ | ||
| 101 | /* Unit in microsecond. 0 means disable this function. */ | ||
| 102 | HW_VAR_NAV_UPPER, | ||
| 103 | HW_VAR_RPT_TIMER_SETTING, | ||
| 104 | HW_VAR_TX_RPT_MAX_MACID, | ||
| 105 | HW_VAR_H2C_MEDIA_STATUS_RPT, | ||
| 106 | HW_VAR_CHK_HI_QUEUE_EMPTY, | ||
| 107 | HW_VAR_READ_LLT_TAB, | ||
| 108 | }; | ||
| 109 | |||
| 110 | enum hal_def_variable { | ||
| 111 | HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, | ||
| 112 | HAL_DEF_IS_SUPPORT_ANT_DIV, | ||
| 113 | HAL_DEF_CURRENT_ANTENNA, | ||
| 114 | HAL_DEF_DRVINFO_SZ, | ||
| 115 | HAL_DEF_MAX_RECVBUF_SZ, | ||
| 116 | HAL_DEF_RX_PACKET_OFFSET, | ||
| 117 | HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */ | ||
| 118 | HAL_DEF_DBG_DM_FUNC,/* for dbg */ | ||
| 119 | HAL_DEF_RA_DECISION_RATE, | ||
| 120 | HAL_DEF_RA_SGI, | ||
| 121 | HAL_DEF_PT_PWR_STATUS, | ||
| 122 | HW_VAR_MAX_RX_AMPDU_FACTOR, | ||
| 123 | HW_DEF_RA_INFO_DUMP, | ||
| 124 | HAL_DEF_DBG_DUMP_TXPKT, | ||
| 125 | HW_DEF_FA_CNT_DUMP, | ||
| 126 | HW_DEF_ODM_DBG_FLAG, | ||
| 127 | }; | ||
| 128 | |||
| 129 | enum hal_odm_variable { | ||
| 130 | HAL_ODM_STA_INFO, | ||
| 131 | HAL_ODM_P2P_STATE, | ||
| 132 | HAL_ODM_WIFI_DISPLAY_STATE, | ||
| 133 | }; | ||
| 134 | |||
| 135 | enum hal_intf_ps_func { | ||
| 136 | HAL_USB_SELECT_SUSPEND, | ||
| 137 | HAL_MAX_ID, | ||
| 138 | }; | ||
| 139 | |||
| 140 | struct hal_ops { | ||
| 141 | u32 (*hal_power_on)(struct rtw_adapter *padapter); | ||
| 142 | u32 (*hal_init)(struct rtw_adapter *padapter); | ||
| 143 | u32 (*hal_deinit)(struct rtw_adapter *padapter); | ||
| 144 | |||
| 145 | void (*free_hal_data)(struct rtw_adapter *padapter); | ||
| 146 | |||
| 147 | u32 (*inirp_init)(struct rtw_adapter *padapter); | ||
| 148 | u32 (*inirp_deinit)(struct rtw_adapter *padapter); | ||
| 149 | |||
| 150 | s32 (*init_xmit_priv)(struct rtw_adapter *padapter); | ||
| 151 | void (*free_xmit_priv)(struct rtw_adapter *padapter); | ||
| 152 | |||
| 153 | s32 (*init_recv_priv)(struct rtw_adapter *padapter); | ||
| 154 | void (*free_recv_priv)(struct rtw_adapter *padapter); | ||
| 155 | |||
| 156 | void (*InitSwLeds)(struct rtw_adapter *padapter); | ||
| 157 | void (*DeInitSwLeds)(struct rtw_adapter *padapter); | ||
| 158 | |||
| 159 | void (*dm_init)(struct rtw_adapter *padapter); | ||
| 160 | void (*dm_deinit)(struct rtw_adapter *padapter); | ||
| 161 | void (*read_chip_version)(struct rtw_adapter *padapter); | ||
| 162 | |||
| 163 | void (*init_default_value)(struct rtw_adapter *padapter); | ||
| 164 | |||
| 165 | void (*intf_chip_configure)(struct rtw_adapter *padapter); | ||
| 166 | |||
| 167 | void (*read_adapter_info)(struct rtw_adapter *padapter); | ||
| 168 | |||
| 169 | void (*enable_interrupt)(struct rtw_adapter *padapter); | ||
| 170 | void (*disable_interrupt)(struct rtw_adapter *padapter); | ||
| 171 | s32 (*interrupt_handler)(struct rtw_adapter *padapter); | ||
| 172 | void (*set_bwmode_handler)(struct rtw_adapter *padapter, | ||
| 173 | enum ht_channel_width Bandwidth, u8 Offset); | ||
| 174 | void (*set_channel_handler)(struct rtw_adapter *padapter, u8 channel); | ||
| 175 | |||
| 176 | void (*hal_dm_watchdog)(struct rtw_adapter *padapter); | ||
| 177 | |||
| 178 | void (*SetHwRegHandler)(struct rtw_adapter *padapter, | ||
| 179 | u8 variable, u8 *val); | ||
| 180 | void (*GetHwRegHandler)(struct rtw_adapter *padapter, | ||
| 181 | u8 variable, u8 *val); | ||
| 182 | |||
| 183 | u8 (*GetHalDefVarHandler)(struct rtw_adapter *padapter, | ||
| 184 | enum hal_def_variable eVariable, | ||
| 185 | void *pValue); | ||
| 186 | u8 (*SetHalDefVarHandler)(struct rtw_adapter *padapter, | ||
| 187 | enum hal_def_variable eVariable, | ||
| 188 | void *pValue); | ||
| 189 | |||
| 190 | void (*GetHalODMVarHandler)(struct rtw_adapter *padapter, | ||
| 191 | enum hal_odm_variable eVariable, | ||
| 192 | void *pValue1, bool bSet); | ||
| 193 | void (*SetHalODMVarHandler)(struct rtw_adapter *padapter, | ||
| 194 | enum hal_odm_variable eVariable, | ||
| 195 | void *pValue1, bool bSet); | ||
| 196 | |||
| 197 | void (*UpdateRAMaskHandler)(struct rtw_adapter *padapter, | ||
| 198 | u32 mac_id, u8 rssi_level); | ||
| 199 | void (*SetBeaconRelatedRegistersHandler)(struct rtw_adapter *padapter); | ||
| 200 | |||
| 201 | void (*Add_RateATid)(struct rtw_adapter *padapter, u32 bitmap, | ||
| 202 | u8 arg, u8 rssi_level); | ||
| 203 | void (*run_thread)(struct rtw_adapter *padapter); | ||
| 204 | void (*cancel_thread)(struct rtw_adapter *padapter); | ||
| 205 | |||
| 206 | u8 (*interface_ps_func)(struct rtw_adapter *padapter, | ||
| 207 | enum hal_intf_ps_func efunc_id, u8 *val); | ||
| 208 | |||
| 209 | s32 (*hal_xmit)(struct rtw_adapter *padapter, | ||
| 210 | struct xmit_frame *pxmitframe); | ||
| 211 | s32 (*mgnt_xmit)(struct rtw_adapter *padapter, | ||
| 212 | struct xmit_frame *pmgntframe); | ||
| 213 | s32 (*hal_xmitframe_enqueue)(struct rtw_adapter *padapter, | ||
| 214 | struct xmit_frame *pxmitframe); | ||
| 215 | |||
| 216 | u32 (*read_bbreg)(struct rtw_adapter *padapter, u32 RegAddr, | ||
| 217 | u32 BitMask); | ||
| 218 | void (*write_bbreg)(struct rtw_adapter *padapter, u32 RegAddr, | ||
| 219 | u32 BitMask, u32 Data); | ||
| 220 | u32 (*read_rfreg)(struct rtw_adapter *padapter, u32 eRFPath, | ||
| 221 | u32 RegAddr, u32 BitMask); | ||
| 222 | void (*write_rfreg)(struct rtw_adapter *padapter, u32 eRFPath, | ||
| 223 | u32 RegAddr, u32 BitMask, u32 Data); | ||
| 224 | |||
| 225 | void (*EfusePowerSwitch)(struct rtw_adapter *padapter, u8 bWrite, | ||
| 226 | u8 PwrState); | ||
| 227 | void (*ReadEFuse)(struct rtw_adapter *padapter, u8 efuseType, | ||
| 228 | u16 _offset, u16 _size_byte, u8 *pbuf); | ||
| 229 | void (*EFUSEGetEfuseDefinition)(struct rtw_adapter *padapter, | ||
| 230 | u8 efuseType, u8 type, void *pOut); | ||
| 231 | u16 (*EfuseGetCurrentSize)(struct rtw_adapter *padapter, u8 efuseType); | ||
| 232 | int (*Efuse_PgPacketRead23a)(struct rtw_adapter *padapter, | ||
| 233 | u8 offset, u8 *data); | ||
| 234 | int (*Efuse_PgPacketWrite23a)(struct rtw_adapter *padapter, | ||
| 235 | u8 offset, u8 word_en, u8 *data); | ||
| 236 | u8 (*Efuse_WordEnableDataWrite23a)(struct rtw_adapter *padapter, | ||
| 237 | u16 efuse_addr, u8 word_en, | ||
| 238 | u8 *data); | ||
| 239 | bool (*Efuse_PgPacketWrite23a_BT)(struct rtw_adapter *padapter, | ||
| 240 | u8 offset, u8 word_en, u8 *data); | ||
| 241 | |||
| 242 | void (*sreset_init_value23a)(struct rtw_adapter *padapter); | ||
| 243 | void (*sreset_reset_value23a)(struct rtw_adapter *padapter); | ||
| 244 | void (*silentreset)(struct rtw_adapter *padapter); | ||
| 245 | void (*sreset_xmit_status_check)(struct rtw_adapter *padapter); | ||
| 246 | void (*sreset_linked_status_check) (struct rtw_adapter *padapter); | ||
| 247 | u8 (*sreset_get_wifi_status23a)(struct rtw_adapter *padapter); | ||
| 248 | bool (*sreset_inprogress)(struct rtw_adapter *padapter); | ||
| 249 | |||
| 250 | void (*hal_notch_filter)(struct rtw_adapter *adapter, bool enable); | ||
| 251 | void (*hal_reset_security_engine)(struct rtw_adapter *adapter); | ||
| 252 | s32 (*c2h_handler)(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt); | ||
| 253 | c2h_id_filter c2h_id_filter_ccx; | ||
| 254 | }; | ||
| 255 | |||
| 256 | enum rt_eeprom_type { | ||
| 257 | EEPROM_93C46, | ||
| 258 | EEPROM_93C56, | ||
| 259 | EEPROM_BOOT_EFUSE, | ||
| 260 | }; | ||
| 261 | |||
| 262 | |||
| 263 | |||
| 264 | #define RF_CHANGE_BY_INIT 0 | ||
| 265 | #define RF_CHANGE_BY_IPS BIT28 | ||
| 266 | #define RF_CHANGE_BY_PS BIT29 | ||
| 267 | #define RF_CHANGE_BY_HW BIT30 | ||
| 268 | #define RF_CHANGE_BY_SW BIT31 | ||
| 269 | |||
| 270 | enum hardware_type { | ||
| 271 | HARDWARE_TYPE_RTL8180, | ||
| 272 | HARDWARE_TYPE_RTL8185, | ||
| 273 | HARDWARE_TYPE_RTL8187, | ||
| 274 | HARDWARE_TYPE_RTL8188, | ||
| 275 | HARDWARE_TYPE_RTL8190P, | ||
| 276 | HARDWARE_TYPE_RTL8192E, | ||
| 277 | HARDWARE_TYPE_RTL819xU, | ||
| 278 | HARDWARE_TYPE_RTL8192SE, | ||
| 279 | HARDWARE_TYPE_RTL8192SU, | ||
| 280 | HARDWARE_TYPE_RTL8192CE, | ||
| 281 | HARDWARE_TYPE_RTL8192CU, | ||
| 282 | HARDWARE_TYPE_RTL8192DE, | ||
| 283 | HARDWARE_TYPE_RTL8192DU, | ||
| 284 | HARDWARE_TYPE_RTL8723AE, | ||
| 285 | HARDWARE_TYPE_RTL8723AU, | ||
| 286 | HARDWARE_TYPE_RTL8723AS, | ||
| 287 | HARDWARE_TYPE_RTL8188EE, | ||
| 288 | HARDWARE_TYPE_RTL8188EU, | ||
| 289 | HARDWARE_TYPE_RTL8188ES, | ||
| 290 | HARDWARE_TYPE_MAX, | ||
| 291 | }; | ||
| 292 | |||
| 293 | #define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv) | ||
| 294 | #define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse) | ||
| 295 | |||
| 296 | extern int rtw_ht_enable23A; | ||
| 297 | extern int rtw_cbw40_enable23A; | ||
| 298 | extern int rtw_ampdu_enable23A;/* for enable tx_ampdu */ | ||
| 299 | |||
| 300 | void rtw_hal_def_value_init23a(struct rtw_adapter *padapter); | ||
| 301 | int pm_netdev_open23a(struct net_device *pnetdev, u8 bnormal); | ||
| 302 | int rtw_resume_process23a(struct rtw_adapter *padapter); | ||
| 303 | |||
| 304 | void rtw_hal_free_data23a(struct rtw_adapter *padapter); | ||
| 305 | |||
| 306 | void rtw_hal_dm_init23a(struct rtw_adapter *padapter); | ||
| 307 | void rtw_hal_dm_deinit23a(struct rtw_adapter *padapter); | ||
| 308 | void rtw_hal_sw_led_init23a(struct rtw_adapter *padapter); | ||
| 309 | void rtw_hal_sw_led_deinit23a(struct rtw_adapter *padapter); | ||
| 310 | |||
| 311 | u32 rtw_hal_power_on23a(struct rtw_adapter *padapter); | ||
| 312 | uint rtw_hal_init23a(struct rtw_adapter *padapter); | ||
| 313 | uint rtw_hal_deinit23a(struct rtw_adapter *padapter); | ||
| 314 | void rtw_hal_stop(struct rtw_adapter *padapter); | ||
| 315 | void rtw_hal_set_hwreg23a(struct rtw_adapter *padapter, u8 variable, u8 *val); | ||
| 316 | void rtw23a_hal_get_hwreg(struct rtw_adapter *padapter, u8 variable, u8 *val); | ||
| 317 | |||
| 318 | void rtw_hal_chip_configure23a(struct rtw_adapter *padapter); | ||
| 319 | void rtw_hal_read_chip_info23a(struct rtw_adapter *padapter); | ||
| 320 | void rtw_hal_read_chip_version23a(struct rtw_adapter *padapter); | ||
| 321 | |||
| 322 | u8 rtw_hal_set_def_var23a(struct rtw_adapter *padapter, | ||
| 323 | enum hal_def_variable eVariable, | ||
| 324 | void *pValue); | ||
| 325 | u8 rtw_hal_get_def_var23a(struct rtw_adapter *padapter, | ||
| 326 | enum hal_def_variable eVariable, | ||
| 327 | void *pValue); | ||
| 328 | |||
| 329 | void rtw_hal_set_odm_var23a(struct rtw_adapter *padapter, | ||
| 330 | enum hal_odm_variable eVariable, | ||
| 331 | void *pValue1, bool bSet); | ||
| 332 | void rtw_hal_get_odm_var23a(struct rtw_adapter *padapter, | ||
| 333 | enum hal_odm_variable eVariable, | ||
| 334 | void *pValue1, bool bSet); | ||
| 335 | |||
| 336 | void rtw_hal_enable_interrupt23a(struct rtw_adapter *padapter); | ||
| 337 | void rtw_hal_disable_interrupt23a(struct rtw_adapter *padapter); | ||
| 338 | |||
| 339 | u32 rtw_hal_inirp_init23a(struct rtw_adapter *padapter); | ||
| 340 | u32 rtw_hal_inirp_deinit23a(struct rtw_adapter *padapter); | ||
| 341 | |||
| 342 | u8 rtw_hal_intf_ps_func23a(struct rtw_adapter *padapter, | ||
| 343 | enum hal_intf_ps_func efunc_id, u8 *val); | ||
| 344 | |||
| 345 | s32 rtw_hal_xmit23aframe_enqueue(struct rtw_adapter *padapter, | ||
| 346 | struct xmit_frame *pxmitframe); | ||
| 347 | s32 rtw_hal_xmit23a(struct rtw_adapter *padapter, | ||
| 348 | struct xmit_frame *pxmitframe); | ||
| 349 | s32 rtw_hal_mgnt_xmit23a(struct rtw_adapter *padapter, | ||
| 350 | struct xmit_frame *pmgntframe); | ||
| 351 | |||
| 352 | s32 rtw_hal_init23a_xmit_priv(struct rtw_adapter *padapter); | ||
| 353 | void rtw_hal_free_xmit_priv23a(struct rtw_adapter *padapter); | ||
| 354 | |||
| 355 | s32 rtw_hal_init23a_recv_priv(struct rtw_adapter *padapter); | ||
| 356 | void rtw_hal_free_recv_priv23a(struct rtw_adapter *padapter); | ||
| 357 | |||
| 358 | void rtw_hal_update_ra_mask23a(struct sta_info *psta, u8 rssi_level); | ||
| 359 | void rtw_hal_add_ra_tid23a(struct rtw_adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level); | ||
| 360 | void rtw_hal_clone_data(struct rtw_adapter *dst_padapter, struct rtw_adapter *src_padapter); | ||
| 361 | void rtw_hal_start_thread23a(struct rtw_adapter *padapter); | ||
| 362 | void rtw_hal_stop_thread23a(struct rtw_adapter *padapter); | ||
| 363 | |||
| 364 | void rtw_hal_bcn_related_reg_setting23a(struct rtw_adapter *padapter); | ||
| 365 | |||
| 366 | u32 rtw_hal_read_bbreg23a(struct rtw_adapter *padapter, u32 RegAddr, u32 BitMask); | ||
| 367 | void rtw_hal_write_bbreg23a(struct rtw_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); | ||
| 368 | u32 rtw_hal_read_rfreg23a(struct rtw_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); | ||
| 369 | void rtw_hal_write_rfreg23a(struct rtw_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); | ||
| 370 | |||
| 371 | s32 rtw_hal_interrupt_handler23a(struct rtw_adapter *padapter); | ||
| 372 | |||
| 373 | void rtw_hal_set_bwmode23a(struct rtw_adapter *padapter, | ||
| 374 | enum ht_channel_width Bandwidth, u8 Offset); | ||
| 375 | void rtw_hal_set_chan23a(struct rtw_adapter *padapter, u8 channel); | ||
| 376 | void rtw_hal_dm_watchdog23a(struct rtw_adapter *padapter); | ||
| 377 | |||
| 378 | void rtw_hal_sreset_init23a(struct rtw_adapter *padapter); | ||
| 379 | void rtw_hal_sreset_reset23a(struct rtw_adapter *padapter); | ||
| 380 | void rtw_hal_sreset_reset23a_value23a(struct rtw_adapter *padapter); | ||
| 381 | void rtw_hal_sreset_xmit_status_check23a(struct rtw_adapter *padapter); | ||
| 382 | void rtw_hal_sreset_linked_status_check23a (struct rtw_adapter *padapter); | ||
| 383 | u8 rtw_hal_sreset_get_wifi_status23a(struct rtw_adapter *padapter); | ||
| 384 | bool rtw_hal_sreset_inprogress(struct rtw_adapter *padapter); | ||
| 385 | |||
| 386 | void rtw_hal_notch_filter23a(struct rtw_adapter *adapter, bool enable); | ||
| 387 | void rtw_hal_reset_security_engine23a(struct rtw_adapter *adapter); | ||
| 388 | |||
| 389 | s32 rtw_hal_c2h_handler23a(struct rtw_adapter *adapter, struct c2h_evt_hdr *c2h_evt); | ||
| 390 | c2h_id_filter rtw_hal_c2h_id_filter_ccx23a(struct rtw_adapter *adapter); | ||
| 391 | |||
| 392 | #endif /* __HAL_INTF_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/ieee80211.h b/drivers/staging/rtl8723au/include/ieee80211.h new file mode 100644 index 000000000000..28e4ab239fb9 --- /dev/null +++ b/drivers/staging/rtl8723au/include/ieee80211.h | |||
| @@ -0,0 +1,603 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __IEEE80211_H | ||
| 16 | #define __IEEE80211_H | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | #include "linux/ieee80211.h" | ||
| 21 | #include "wifi.h" | ||
| 22 | |||
| 23 | #include <linux/wireless.h> | ||
| 24 | |||
| 25 | #if (WIRELESS_EXT < 22) | ||
| 26 | #error "Obsolete pre 2007 wireless extensions are not supported" | ||
| 27 | #endif | ||
| 28 | |||
| 29 | |||
| 30 | #define MGMT_QUEUE_NUM 5 | ||
| 31 | |||
| 32 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 33 | |||
| 34 | /* STA flags */ | ||
| 35 | #define WLAN_STA_AUTH BIT(0) | ||
| 36 | #define WLAN_STA_ASSOC BIT(1) | ||
| 37 | #define WLAN_STA_PS BIT(2) | ||
| 38 | #define WLAN_STA_TIM BIT(3) | ||
| 39 | #define WLAN_STA_PERM BIT(4) | ||
| 40 | #define WLAN_STA_AUTHORIZED BIT(5) | ||
| 41 | #define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ | ||
| 42 | #define WLAN_STA_SHORT_PREAMBLE BIT(7) | ||
| 43 | #define WLAN_STA_PREAUTH BIT(8) | ||
| 44 | #define WLAN_STA_WME BIT(9) | ||
| 45 | #define WLAN_STA_MFP BIT(10) | ||
| 46 | #define WLAN_STA_HT BIT(11) | ||
| 47 | #define WLAN_STA_WPS BIT(12) | ||
| 48 | #define WLAN_STA_MAYBE_WPS BIT(13) | ||
| 49 | #define WLAN_STA_NONERP BIT(31) | ||
| 50 | |||
| 51 | #endif | ||
| 52 | |||
| 53 | #define IEEE_CMD_SET_WPA_PARAM 1 | ||
| 54 | #define IEEE_CMD_SET_WPA_IE 2 | ||
| 55 | #define IEEE_CMD_SET_ENCRYPTION 3 | ||
| 56 | |||
| 57 | #define IEEE_CRYPT_ALG_NAME_LEN 16 | ||
| 58 | |||
| 59 | #define WPA_CIPHER_NONE BIT(0) | ||
| 60 | #define WPA_CIPHER_WEP40 BIT(1) | ||
| 61 | #define WPA_CIPHER_WEP104 BIT(2) | ||
| 62 | #define WPA_CIPHER_TKIP BIT(3) | ||
| 63 | #define WPA_CIPHER_CCMP BIT(4) | ||
| 64 | |||
| 65 | |||
| 66 | |||
| 67 | #define WPA_SELECTOR_LEN 4 | ||
| 68 | extern u8 RTW_WPA_OUI23A_TYPE[] ; | ||
| 69 | extern u16 RTW_WPA_VERSION23A ; | ||
| 70 | extern u8 WPA_AUTH_KEY_MGMT_NONE23A[]; | ||
| 71 | extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X23A[]; | ||
| 72 | extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X23A[]; | ||
| 73 | extern u8 WPA_CIPHER_SUITE_NONE23A[]; | ||
| 74 | extern u8 WPA_CIPHER_SUITE_WEP4023A[]; | ||
| 75 | extern u8 WPA_CIPHER_SUITE_TKIP23A[]; | ||
| 76 | extern u8 WPA_CIPHER_SUITE_WRAP23A[]; | ||
| 77 | extern u8 WPA_CIPHER_SUITE_CCMP23A[]; | ||
| 78 | extern u8 WPA_CIPHER_SUITE_WEP10423A[]; | ||
| 79 | |||
| 80 | |||
| 81 | #define RSN_HEADER_LEN 4 | ||
| 82 | #define RSN_SELECTOR_LEN 4 | ||
| 83 | |||
| 84 | extern u16 RSN_VERSION_BSD23A; | ||
| 85 | extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X23A[]; | ||
| 86 | extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X23A[]; | ||
| 87 | extern u8 RSN_CIPHER_SUITE_NONE23A[]; | ||
| 88 | extern u8 RSN_CIPHER_SUITE_WEP4023A[]; | ||
| 89 | extern u8 RSN_CIPHER_SUITE_TKIP23A[]; | ||
| 90 | extern u8 RSN_CIPHER_SUITE_WRAP23A[]; | ||
| 91 | extern u8 RSN_CIPHER_SUITE_CCMP23A[]; | ||
| 92 | extern u8 RSN_CIPHER_SUITE_WEP10423A[]; | ||
| 93 | |||
| 94 | enum ratr_table_mode { | ||
| 95 | RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */ | ||
| 96 | RATR_INX_WIRELESS_NG = 1, /* GN or N */ | ||
| 97 | RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */ | ||
| 98 | RATR_INX_WIRELESS_N = 3, | ||
| 99 | RATR_INX_WIRELESS_GB = 4, | ||
| 100 | RATR_INX_WIRELESS_G = 5, | ||
| 101 | RATR_INX_WIRELESS_B = 6, | ||
| 102 | RATR_INX_WIRELESS_MC = 7, | ||
| 103 | RATR_INX_WIRELESS_AC_N = 8, | ||
| 104 | }; | ||
| 105 | |||
| 106 | enum NETWORK_TYPE | ||
| 107 | { | ||
| 108 | WIRELESS_INVALID = 0, | ||
| 109 | /* Sub-Element */ | ||
| 110 | WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */ | ||
| 111 | WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */ | ||
| 112 | WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */ | ||
| 113 | WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */ | ||
| 114 | WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */ | ||
| 115 | /* WIRELESS_AUTO = BIT(5), */ | ||
| 116 | WIRELESS_AC = BIT(6), | ||
| 117 | |||
| 118 | /* Combination */ | ||
| 119 | WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */ | ||
| 120 | WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */ | ||
| 121 | WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ | ||
| 122 | WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ | ||
| 123 | WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ | ||
| 124 | WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), | ||
| 125 | }; | ||
| 126 | |||
| 127 | #define SUPPORTED_24G_NETTYPE_MSK (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N) | ||
| 128 | #define SUPPORTED_5G_NETTYPE_MSK (WIRELESS_11A | WIRELESS_11_5N) | ||
| 129 | |||
| 130 | #define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? true : false) | ||
| 131 | #define IsSupported5G(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? true : false) | ||
| 132 | |||
| 133 | #define IsEnableHWCCK(NetType) IsSupported24G(NetType) | ||
| 134 | #define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11_24N|SUPPORTED_5G_NETTYPE_MSK) ? true : false) | ||
| 135 | |||
| 136 | #define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) | ||
| 137 | #define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) | ||
| 138 | #define IsSupportedRxMCS(NetType) IsEnableHWOFDM(NetType) | ||
| 139 | |||
| 140 | #define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? true : false) | ||
| 141 | #define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? true : false) | ||
| 142 | #define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? true : false) | ||
| 143 | |||
| 144 | |||
| 145 | struct ieee_param { | ||
| 146 | u32 cmd; | ||
| 147 | u8 sta_addr[ETH_ALEN]; | ||
| 148 | union { | ||
| 149 | struct { | ||
| 150 | u8 name; | ||
| 151 | u32 value; | ||
| 152 | } wpa_param; | ||
| 153 | struct { | ||
| 154 | u32 len; | ||
| 155 | u8 reserved[32]; | ||
| 156 | u8 data[0]; | ||
| 157 | } wpa_ie; | ||
| 158 | struct{ | ||
| 159 | int command; | ||
| 160 | int reason_code; | ||
| 161 | } mlme; | ||
| 162 | struct { | ||
| 163 | u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; | ||
| 164 | u8 set_tx; | ||
| 165 | u32 err; | ||
| 166 | u8 idx; | ||
| 167 | u8 seq[8]; /* sequence counter (set: RX, get: TX) */ | ||
| 168 | u16 key_len; | ||
| 169 | u8 key[0]; | ||
| 170 | } crypt; | ||
| 171 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 172 | struct { | ||
| 173 | u16 aid; | ||
| 174 | u16 capability; | ||
| 175 | int flags; | ||
| 176 | u8 tx_supp_rates[16]; | ||
| 177 | struct ieee80211_ht_cap ht_cap; | ||
| 178 | } add_sta; | ||
| 179 | struct { | ||
| 180 | u8 reserved[2];/* for set max_num_sta */ | ||
| 181 | u8 buf[0]; | ||
| 182 | } bcn_ie; | ||
| 183 | #endif | ||
| 184 | |||
| 185 | } u; | ||
| 186 | }; | ||
| 187 | |||
| 188 | |||
| 189 | #define MIN_FRAG_THRESHOLD 256U | ||
| 190 | #define MAX_FRAG_THRESHOLD 2346U | ||
| 191 | |||
| 192 | /* QoS,QOS */ | ||
| 193 | #define NORMAL_ACK 0 | ||
| 194 | #define NO_ACK 1 | ||
| 195 | #define NON_EXPLICIT_ACK 2 | ||
| 196 | #define BLOCK_ACK 3 | ||
| 197 | |||
| 198 | /* IEEE 802.11 defines */ | ||
| 199 | |||
| 200 | #define P80211_OUI_LEN 3 | ||
| 201 | |||
| 202 | struct ieee80211_snap_hdr { | ||
| 203 | |||
| 204 | u8 dsap; /* always 0xAA */ | ||
| 205 | u8 ssap; /* always 0xAA */ | ||
| 206 | u8 ctrl; /* always 0x03 */ | ||
| 207 | u8 oui[P80211_OUI_LEN]; /* organizational universal id */ | ||
| 208 | |||
| 209 | } __attribute__ ((packed)); | ||
| 210 | |||
| 211 | |||
| 212 | #define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) | ||
| 213 | |||
| 214 | #define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE) | ||
| 215 | #define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE) | ||
| 216 | |||
| 217 | #define WLAN_QC_GET_TID(qc) ((qc) & 0x0f) | ||
| 218 | |||
| 219 | #define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG) | ||
| 220 | #define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ) | ||
| 221 | |||
| 222 | |||
| 223 | #define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 | ||
| 224 | #define WLAN_REASON_EXPIRATION_CHK 65535 | ||
| 225 | |||
| 226 | |||
| 227 | |||
| 228 | #define IEEE80211_STATMASK_SIGNAL (1<<0) | ||
| 229 | #define IEEE80211_STATMASK_RSSI (1<<1) | ||
| 230 | #define IEEE80211_STATMASK_NOISE (1<<2) | ||
| 231 | #define IEEE80211_STATMASK_RATE (1<<3) | ||
| 232 | #define IEEE80211_STATMASK_WEMASK 0x7 | ||
| 233 | |||
| 234 | |||
| 235 | #define IEEE80211_CCK_MODULATION (1<<0) | ||
| 236 | #define IEEE80211_OFDM_MODULATION (1<<1) | ||
| 237 | |||
| 238 | #define IEEE80211_24GHZ_BAND (1<<0) | ||
| 239 | #define IEEE80211_52GHZ_BAND (1<<1) | ||
| 240 | |||
| 241 | #define IEEE80211_CCK_RATE_LEN 4 | ||
| 242 | #define IEEE80211_NUM_OFDM_RATESLEN 8 | ||
| 243 | |||
| 244 | |||
| 245 | #define IEEE80211_CCK_RATE_1MB 0x02 | ||
| 246 | #define IEEE80211_CCK_RATE_2MB 0x04 | ||
| 247 | #define IEEE80211_CCK_RATE_5MB 0x0B | ||
| 248 | #define IEEE80211_CCK_RATE_11MB 0x16 | ||
| 249 | #define IEEE80211_OFDM_RATE_LEN 8 | ||
| 250 | #define IEEE80211_OFDM_RATE_6MB 0x0C | ||
| 251 | #define IEEE80211_OFDM_RATE_9MB 0x12 | ||
| 252 | #define IEEE80211_OFDM_RATE_12MB 0x18 | ||
| 253 | #define IEEE80211_OFDM_RATE_18MB 0x24 | ||
| 254 | #define IEEE80211_OFDM_RATE_24MB 0x30 | ||
| 255 | #define IEEE80211_OFDM_RATE_36MB 0x48 | ||
| 256 | #define IEEE80211_OFDM_RATE_48MB 0x60 | ||
| 257 | #define IEEE80211_OFDM_RATE_54MB 0x6C | ||
| 258 | #define IEEE80211_BASIC_RATE_MASK 0x80 | ||
| 259 | |||
| 260 | #define IEEE80211_CCK_RATE_1MB_MASK (1<<0) | ||
| 261 | #define IEEE80211_CCK_RATE_2MB_MASK (1<<1) | ||
| 262 | #define IEEE80211_CCK_RATE_5MB_MASK (1<<2) | ||
| 263 | #define IEEE80211_CCK_RATE_11MB_MASK (1<<3) | ||
| 264 | #define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) | ||
| 265 | #define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) | ||
| 266 | #define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) | ||
| 267 | #define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) | ||
| 268 | #define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) | ||
| 269 | #define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) | ||
| 270 | #define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) | ||
| 271 | #define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) | ||
| 272 | |||
| 273 | #define IEEE80211_CCK_RATES_MASK 0x0000000F | ||
| 274 | #define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ | ||
| 275 | IEEE80211_CCK_RATE_2MB_MASK) | ||
| 276 | #define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ | ||
| 277 | IEEE80211_CCK_RATE_5MB_MASK | \ | ||
| 278 | IEEE80211_CCK_RATE_11MB_MASK) | ||
| 279 | |||
| 280 | #define IEEE80211_OFDM_RATES_MASK 0x00000FF0 | ||
| 281 | #define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ | ||
| 282 | IEEE80211_OFDM_RATE_12MB_MASK | \ | ||
| 283 | IEEE80211_OFDM_RATE_24MB_MASK) | ||
| 284 | #define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ | ||
| 285 | IEEE80211_OFDM_RATE_9MB_MASK | \ | ||
| 286 | IEEE80211_OFDM_RATE_18MB_MASK | \ | ||
| 287 | IEEE80211_OFDM_RATE_36MB_MASK | \ | ||
| 288 | IEEE80211_OFDM_RATE_48MB_MASK | \ | ||
| 289 | IEEE80211_OFDM_RATE_54MB_MASK) | ||
| 290 | #define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ | ||
| 291 | IEEE80211_CCK_DEFAULT_RATES_MASK) | ||
| 292 | |||
| 293 | #define IEEE80211_NUM_OFDM_RATES 8 | ||
| 294 | #define IEEE80211_NUM_CCK_RATES 4 | ||
| 295 | #define IEEE80211_OFDM_SHIFT_MASK_A 4 | ||
| 296 | |||
| 297 | #define WEP_KEYS 4 | ||
| 298 | #define WEP_KEY_LEN 13 | ||
| 299 | |||
| 300 | |||
| 301 | |||
| 302 | /* | ||
| 303 | |||
| 304 | 802.11 data frame from AP | ||
| 305 | |||
| 306 | ,-------------------------------------------------------------------. | ||
| 307 | Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | | ||
| 308 | |------|------|---------|---------|---------|------|---------|------| | ||
| 309 | Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | | ||
| 310 | | | tion | (BSSID) | | | ence | data | | | ||
| 311 | `-------------------------------------------------------------------' | ||
| 312 | |||
| 313 | Total: 28-2340 bytes | ||
| 314 | |||
| 315 | */ | ||
| 316 | |||
| 317 | struct ieee80211_header_data { | ||
| 318 | u16 frame_ctl; | ||
| 319 | u16 duration_id; | ||
| 320 | u8 addr1[6]; | ||
| 321 | u8 addr2[6]; | ||
| 322 | u8 addr3[6]; | ||
| 323 | u16 seq_ctrl; | ||
| 324 | }; | ||
| 325 | |||
| 326 | struct ieee80211_info_element_hdr { | ||
| 327 | u8 id; | ||
| 328 | u8 len; | ||
| 329 | } __attribute__ ((packed)); | ||
| 330 | |||
| 331 | struct ieee80211_info_element { | ||
| 332 | u8 id; | ||
| 333 | u8 len; | ||
| 334 | u8 data[0]; | ||
| 335 | } __attribute__ ((packed)); | ||
| 336 | |||
| 337 | |||
| 338 | struct ieee80211_txb { | ||
| 339 | u8 nr_frags; | ||
| 340 | u8 encrypted; | ||
| 341 | u16 reserved; | ||
| 342 | u16 frag_size; | ||
| 343 | u16 payload_size; | ||
| 344 | struct sk_buff *fragments[0]; | ||
| 345 | }; | ||
| 346 | |||
| 347 | |||
| 348 | /* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs | ||
| 349 | * only use 8, and then use extended rates for the remaining supported | ||
| 350 | * rates. Other APs, however, stick all of their supported rates on the | ||
| 351 | * main rates information element... */ | ||
| 352 | #define MAX_RATES_LENGTH ((u8)12) | ||
| 353 | #define MAX_RATES_EX_LENGTH ((u8)16) | ||
| 354 | #define MAX_CHANNEL_NUMBER 161 | ||
| 355 | |||
| 356 | #define MAX_WPA_IE_LEN (256) | ||
| 357 | #define MAX_WPS_IE_LEN (512) | ||
| 358 | #define MAX_P2P_IE_LEN (256) | ||
| 359 | #define MAX_WFD_IE_LEN (128) | ||
| 360 | |||
| 361 | #define IW_ESSID_MAX_SIZE 32 | ||
| 362 | |||
| 363 | /* | ||
| 364 | join_res: | ||
| 365 | -1: authentication fail | ||
| 366 | -2: association fail | ||
| 367 | > 0: TID | ||
| 368 | */ | ||
| 369 | |||
| 370 | #define DEFAULT_MAX_SCAN_AGE (15 * HZ) | ||
| 371 | #define DEFAULT_FTS 2346 | ||
| 372 | #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" | ||
| 373 | #define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] | ||
| 374 | |||
| 375 | #define CFG_IEEE80211_RESERVE_FCS (1<<0) | ||
| 376 | #define CFG_IEEE80211_COMPUTE_FCS (1<<1) | ||
| 377 | |||
| 378 | #define MAXTID 16 | ||
| 379 | |||
| 380 | #define IEEE_A (1<<0) | ||
| 381 | #define IEEE_B (1<<1) | ||
| 382 | #define IEEE_G (1<<2) | ||
| 383 | #define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) | ||
| 384 | |||
| 385 | /* Baron move to ieee80211.c */ | ||
| 386 | int ieee80211_is_empty_essid23a(const char *essid, int essid_len); | ||
| 387 | |||
| 388 | enum _PUBLIC_ACTION{ | ||
| 389 | ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */ | ||
| 390 | ACT_PUBLIC_DSE_ENABLE = 1, | ||
| 391 | ACT_PUBLIC_DSE_DEENABLE = 2, | ||
| 392 | ACT_PUBLIC_DSE_REG_LOCATION = 3, | ||
| 393 | ACT_PUBLIC_EXT_CHL_SWITCH = 4, | ||
| 394 | ACT_PUBLIC_DSE_MSR_REQ = 5, | ||
| 395 | ACT_PUBLIC_DSE_MSR_RPRT = 6, | ||
| 396 | ACT_PUBLIC_MP = 7, /* Measurement Pilot */ | ||
| 397 | ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8, | ||
| 398 | ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */ | ||
| 399 | ACT_PUBLIC_GAS_INITIAL_REQ = 10, | ||
| 400 | ACT_PUBLIC_GAS_INITIAL_RSP = 11, | ||
| 401 | ACT_PUBLIC_GAS_COMEBACK_REQ = 12, | ||
| 402 | ACT_PUBLIC_GAS_COMEBACK_RSP = 13, | ||
| 403 | ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14, | ||
| 404 | ACT_PUBLIC_LOCATION_TRACK = 15, | ||
| 405 | ACT_PUBLIC_MAX | ||
| 406 | }; | ||
| 407 | |||
| 408 | #define WME_OUI_TYPE 2 | ||
| 409 | #define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 | ||
| 410 | #define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 | ||
| 411 | #define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 | ||
| 412 | #define WME_VERSION 1 | ||
| 413 | |||
| 414 | |||
| 415 | #define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */ | ||
| 416 | |||
| 417 | #define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ | ||
| 418 | |||
| 419 | /* Represent channel details, subset of ieee80211_channel */ | ||
| 420 | struct rtw_ieee80211_channel { | ||
| 421 | /* enum ieee80211_band band; */ | ||
| 422 | /* u16 center_freq; */ | ||
| 423 | u16 hw_value; | ||
| 424 | u32 flags; | ||
| 425 | /* int max_antenna_gain; */ | ||
| 426 | /* int max_power; */ | ||
| 427 | /* int max_reg_power; */ | ||
| 428 | /* bool beacon_found; */ | ||
| 429 | /* u32 orig_flags; */ | ||
| 430 | /* int orig_mag; */ | ||
| 431 | /* int orig_mpwr; */ | ||
| 432 | }; | ||
| 433 | |||
| 434 | #define CHAN_FMT \ | ||
| 435 | /*"band:%d, "*/ \ | ||
| 436 | /*"center_freq:%u, "*/ \ | ||
| 437 | "hw_value:%u, " \ | ||
| 438 | "flags:0x%08x" \ | ||
| 439 | /*"max_antenna_gain:%d\n"*/ \ | ||
| 440 | /*"max_power:%d\n"*/ \ | ||
| 441 | /*"max_reg_power:%d\n"*/ \ | ||
| 442 | /*"beacon_found:%u\n"*/ \ | ||
| 443 | /*"orig_flags:0x%08x\n"*/ \ | ||
| 444 | /*"orig_mag:%d\n"*/ \ | ||
| 445 | /*"orig_mpwr:%d\n"*/ | ||
| 446 | |||
| 447 | #define CHAN_ARG(channel) \ | ||
| 448 | /*(channel)->band*/ \ | ||
| 449 | /*, (channel)->center_freq*/ \ | ||
| 450 | (channel)->hw_value \ | ||
| 451 | , (channel)->flags \ | ||
| 452 | /*, (channel)->max_antenna_gain*/ \ | ||
| 453 | /*, (channel)->max_power*/ \ | ||
| 454 | /*, (channel)->max_reg_power*/ \ | ||
| 455 | /*, (channel)->beacon_found*/ \ | ||
| 456 | /*, (channel)->orig_flags*/ \ | ||
| 457 | /*, (channel)->orig_mag*/ \ | ||
| 458 | /*, (channel)->orig_mpwr*/ \ | ||
| 459 | |||
| 460 | /* Parsed Information Elements */ | ||
| 461 | struct rtw_ieee802_11_elems { | ||
| 462 | u8 *ssid; | ||
| 463 | u8 ssid_len; | ||
| 464 | u8 *supp_rates; | ||
| 465 | u8 supp_rates_len; | ||
| 466 | u8 *fh_params; | ||
| 467 | u8 fh_params_len; | ||
| 468 | u8 *ds_params; | ||
| 469 | u8 ds_params_len; | ||
| 470 | u8 *cf_params; | ||
| 471 | u8 cf_params_len; | ||
| 472 | u8 *tim; | ||
| 473 | u8 tim_len; | ||
| 474 | u8 *ibss_params; | ||
| 475 | u8 ibss_params_len; | ||
| 476 | u8 *challenge; | ||
| 477 | u8 challenge_len; | ||
| 478 | u8 *erp_info; | ||
| 479 | u8 erp_info_len; | ||
| 480 | u8 *ext_supp_rates; | ||
| 481 | u8 ext_supp_rates_len; | ||
| 482 | u8 *wpa_ie; | ||
| 483 | u8 wpa_ie_len; | ||
| 484 | u8 *rsn_ie; | ||
| 485 | u8 rsn_ie_len; | ||
| 486 | u8 *wme; | ||
| 487 | u8 wme_len; | ||
| 488 | u8 *wme_tspec; | ||
| 489 | u8 wme_tspec_len; | ||
| 490 | u8 *wps_ie; | ||
| 491 | u8 wps_ie_len; | ||
| 492 | u8 *power_cap; | ||
| 493 | u8 power_cap_len; | ||
| 494 | u8 *supp_channels; | ||
| 495 | u8 supp_channels_len; | ||
| 496 | u8 *mdie; | ||
| 497 | u8 mdie_len; | ||
| 498 | u8 *ftie; | ||
| 499 | u8 ftie_len; | ||
| 500 | u8 *timeout_int; | ||
| 501 | u8 timeout_int_len; | ||
| 502 | u8 *ht_capabilities; | ||
| 503 | u8 ht_capabilities_len; | ||
| 504 | u8 *ht_operation; | ||
| 505 | u8 ht_operation_len; | ||
| 506 | u8 *vendor_ht_cap; | ||
| 507 | u8 vendor_ht_cap_len; | ||
| 508 | }; | ||
| 509 | |||
| 510 | enum parse_res { | ||
| 511 | ParseOK = 0, | ||
| 512 | ParseUnknown = 1, | ||
| 513 | ParseFailed = -1 | ||
| 514 | }; | ||
| 515 | |||
| 516 | enum parse_res rtw_ieee802_11_parse_elems23a(u8 *start, uint len, | ||
| 517 | struct rtw_ieee802_11_elems *elems, | ||
| 518 | int show_errors); | ||
| 519 | |||
| 520 | u8 *rtw_set_fixed_ie23a(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); | ||
| 521 | u8 *rtw_set_ie23a(u8 *pbuf, int index, uint len, u8 *source, uint *frlen); | ||
| 522 | |||
| 523 | enum secondary_ch_offset { | ||
| 524 | SCN = 0, /* no secondary channel */ | ||
| 525 | SCA = 1, /* secondary channel above */ | ||
| 526 | SCB = 3, /* secondary channel below */ | ||
| 527 | }; | ||
| 528 | u8 secondary_ch_offset_to_hal_ch_offset23a(u8 ch_offset); | ||
| 529 | u8 hal_ch_offset_to_secondary_ch_offset23a(u8 ch_offset); | ||
| 530 | u8 *rtw_set_ie23a_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt); | ||
| 531 | u8 *rtw_set_ie23a_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset); | ||
| 532 | u8 *rtw_set_ie23a_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence); | ||
| 533 | |||
| 534 | u8 *rtw_get_ie23a(u8*pbuf, int index, int *len, int limit); | ||
| 535 | u8 *rtw_get_ie23a_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); | ||
| 536 | int rtw_ies_remove_ie23a(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); | ||
| 537 | |||
| 538 | void rtw_set_supported_rate23a(u8* SupportedRates, uint mode) ; | ||
| 539 | |||
| 540 | unsigned char *rtw_get_wpa_ie23a(unsigned char *pie, int *wpa_ie_len, int limit); | ||
| 541 | unsigned char *rtw_get_wpa2_ie23a(unsigned char *pie, int *rsn_ie_len, int limit); | ||
| 542 | int rtw_get_wpa_cipher_suite23a(u8 *s); | ||
| 543 | int rtw_get_wpa2_cipher_suite23a(u8 *s); | ||
| 544 | int rtw_parse_wpa_ie23a(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); | ||
| 545 | int rtw_parse_wpa2_ie23a(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); | ||
| 546 | |||
| 547 | int rtw_get_sec_ie23a(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len); | ||
| 548 | |||
| 549 | u8 rtw_is_wps_ie23a(u8 *ie_ptr, uint *wps_ielen); | ||
| 550 | u8 *rtw_get_wps_ie23a(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); | ||
| 551 | u8 *rtw_get_wps_attr23a(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr); | ||
| 552 | u8 *rtw_get_wps_attr_content23a(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content); | ||
| 553 | |||
| 554 | /** | ||
| 555 | * for_each_ie - iterate over continuous IEs | ||
| 556 | * @ie: | ||
| 557 | * @buf: | ||
| 558 | * @buf_len: | ||
| 559 | */ | ||
| 560 | #define for_each_ie(ie, buf, buf_len) \ | ||
| 561 | for (ie = (void*)buf; (((u8*)ie) - ((u8*)buf) + 1) < buf_len; ie = (void*)(((u8*)ie) + *(((u8*)ie)+1) + 2)) | ||
| 562 | |||
| 563 | void dump_ies23a(u8 *buf, u32 buf_len); | ||
| 564 | void dump_wps_ie23a(u8 *ie, u32 ie_len); | ||
| 565 | |||
| 566 | #ifdef CONFIG_8723AU_P2P | ||
| 567 | void dump_p2p_ie23a(u8 *ie, u32 ie_len); | ||
| 568 | u8 *rtw_get_p2p_ie23a(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); | ||
| 569 | u8 *rtw_get_p2p_attr23a(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr); | ||
| 570 | u8 *rtw_get_p2p_attr23a_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content); | ||
| 571 | u32 rtw_set_p2p_attr_content23a(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); | ||
| 572 | void rtw_wlan_bssid_ex_remove_p2p_attr23a(struct wlan_bssid_ex *bss_ex, u8 attr_id); | ||
| 573 | #endif | ||
| 574 | |||
| 575 | #ifdef CONFIG_8723AU_P2P | ||
| 576 | int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); | ||
| 577 | int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen); | ||
| 578 | #endif /* CONFIG_8723AU_P2P */ | ||
| 579 | |||
| 580 | uint rtw_get_rateset_len23a(u8 *rateset); | ||
| 581 | |||
| 582 | struct registry_priv; | ||
| 583 | int rtw_generate_ie23a(struct registry_priv *pregistrypriv); | ||
| 584 | |||
| 585 | |||
| 586 | int rtw_get_bit_value_from_ieee_value23a(u8 val); | ||
| 587 | |||
| 588 | uint rtw_is_cckrates_included23a(u8 *rate); | ||
| 589 | |||
| 590 | uint rtw_is_cckratesonly_included23a(u8 *rate); | ||
| 591 | |||
| 592 | int rtw_check_network_type23a(unsigned char *rate, int ratelen, int channel); | ||
| 593 | |||
| 594 | void rtw_get_bcn_info23a(struct wlan_network *pnetwork); | ||
| 595 | |||
| 596 | void rtw_macaddr_cfg23a(u8 *mac_addr); | ||
| 597 | |||
| 598 | u16 rtw_mcs_rate23a(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char * MCS_rate); | ||
| 599 | |||
| 600 | int rtw_action_frame_parse23a(const u8 *frame, u32 frame_len, u8* category, u8 *action); | ||
| 601 | const char *action_public_str23a(u8 action); | ||
| 602 | |||
| 603 | #endif /* IEEE80211_H */ | ||
diff --git a/drivers/staging/rtl8723au/include/ioctl_cfg80211.h b/drivers/staging/rtl8723au/include/ioctl_cfg80211.h new file mode 100644 index 000000000000..0eb9036d7250 --- /dev/null +++ b/drivers/staging/rtl8723au/include/ioctl_cfg80211.h | |||
| @@ -0,0 +1,119 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __IOCTL_CFG80211_H__ | ||
| 16 | #define __IOCTL_CFG80211_H__ | ||
| 17 | |||
| 18 | struct rtw_wdev_invit_info { | ||
| 19 | u8 token; | ||
| 20 | u8 flags; | ||
| 21 | u8 status; | ||
| 22 | u8 req_op_ch; | ||
| 23 | u8 rsp_op_ch; | ||
| 24 | }; | ||
| 25 | |||
| 26 | #define rtw_wdev_invit_info_init(invit_info) \ | ||
| 27 | do { \ | ||
| 28 | (invit_info)->token = 0; \ | ||
| 29 | (invit_info)->flags = 0x00; \ | ||
| 30 | (invit_info)->status = 0xff; \ | ||
| 31 | (invit_info)->req_op_ch = 0; \ | ||
| 32 | (invit_info)->rsp_op_ch = 0; \ | ||
| 33 | } while (0) | ||
| 34 | |||
| 35 | struct rtw_wdev_priv { | ||
| 36 | struct wireless_dev *rtw_wdev; | ||
| 37 | |||
| 38 | struct rtw_adapter *padapter; | ||
| 39 | |||
| 40 | struct cfg80211_scan_request *scan_request; | ||
| 41 | spinlock_t scan_req_lock; | ||
| 42 | |||
| 43 | struct net_device *pmon_ndev;/* for monitor interface */ | ||
| 44 | char ifname_mon[IFNAMSIZ + 1]; /* name for monitor interface */ | ||
| 45 | |||
| 46 | u8 p2p_enabled; | ||
| 47 | |||
| 48 | u8 provdisc_req_issued; | ||
| 49 | |||
| 50 | struct rtw_wdev_invit_info invit_info; | ||
| 51 | |||
| 52 | bool block; | ||
| 53 | bool power_mgmt; | ||
| 54 | }; | ||
| 55 | |||
| 56 | #define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w))) | ||
| 57 | |||
| 58 | #define wiphy_to_adapter(x) \ | ||
| 59 | (struct rtw_adapter *)(((struct rtw_wdev_priv *) \ | ||
| 60 | wiphy_priv(x))->padapter) | ||
| 61 | |||
| 62 | #define wiphy_to_wdev(x) \ | ||
| 63 | (struct wireless_dev *)(((struct rtw_wdev_priv *) \ | ||
| 64 | wiphy_priv(x))->rtw_wdev) | ||
| 65 | |||
| 66 | int rtw_wdev_alloc(struct rtw_adapter *padapter, struct device *dev); | ||
| 67 | void rtw_wdev_free(struct wireless_dev *wdev); | ||
| 68 | void rtw_wdev_unregister(struct wireless_dev *wdev); | ||
| 69 | |||
| 70 | void rtw_cfg80211_init_wiphy(struct rtw_adapter *padapter); | ||
| 71 | |||
| 72 | void rtw_cfg80211_surveydone_event_callback(struct rtw_adapter *padapter); | ||
| 73 | |||
| 74 | void rtw_cfg80211_indicate_connect(struct rtw_adapter *padapter); | ||
| 75 | void rtw_cfg80211_indicate_disconnect(struct rtw_adapter *padapter); | ||
| 76 | void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, | ||
| 77 | bool aborted); | ||
| 78 | |||
| 79 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 80 | void rtw_cfg80211_indicate_sta_assoc(struct rtw_adapter *padapter, | ||
| 81 | u8 *pmgmt_frame, uint frame_len); | ||
| 82 | void rtw_cfg80211_indicate_sta_disassoc(struct rtw_adapter *padapter, | ||
| 83 | unsigned char *da, unsigned short reason); | ||
| 84 | #endif /* CONFIG_8723AU_AP_MODE */ | ||
| 85 | |||
| 86 | void rtw_cfg80211_issue_p2p_provision_request23a(struct rtw_adapter *padapter, | ||
| 87 | const u8 *buf, size_t len); | ||
| 88 | void rtw_cfg80211_rx_p2p_action_public(struct rtw_adapter *padapter, | ||
| 89 | u8 *pmgmt_frame, uint frame_len); | ||
| 90 | void rtw_cfg80211_rx_action_p2p(struct rtw_adapter *padapter, | ||
| 91 | u8 *pmgmt_frame, uint frame_len); | ||
| 92 | void rtw_cfg80211_rx_action(struct rtw_adapter *adapter, u8 *frame, | ||
| 93 | uint frame_len, const char*msg); | ||
| 94 | |||
| 95 | int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, | ||
| 96 | int type); | ||
| 97 | |||
| 98 | bool rtw_cfg80211_pwr_mgmt(struct rtw_adapter *adapter); | ||
| 99 | |||
| 100 | #define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) \ | ||
| 101 | cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, 0, gfp) | ||
| 102 | |||
| 103 | #define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) \ | ||
| 104 | cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len) | ||
| 105 | |||
| 106 | #define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) \ | ||
| 107 | cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, \ | ||
| 108 | len, ack, gfp) | ||
| 109 | |||
| 110 | #define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, \ | ||
| 111 | channel_type, duration, gfp) \ | ||
| 112 | cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, \ | ||
| 113 | duration, gfp) | ||
| 114 | #define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, \ | ||
| 115 | chan_type, gfp) \ | ||
| 116 | cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, \ | ||
| 117 | cookie, chan, gfp) | ||
| 118 | |||
| 119 | #endif /* __IOCTL_CFG80211_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/mlme_osdep.h b/drivers/staging/rtl8723au/include/mlme_osdep.h new file mode 100644 index 000000000000..b7132a9a1378 --- /dev/null +++ b/drivers/staging/rtl8723au/include/mlme_osdep.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __MLME_OSDEP_H_ | ||
| 16 | #define __MLME_OSDEP_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | void rtw_os_indicate_disconnect23a(struct rtw_adapter *adapter); | ||
| 22 | void rtw_os_indicate_connect23a(struct rtw_adapter *adapter); | ||
| 23 | void rtw_os_indicate_scan_done23a(struct rtw_adapter *padapter, bool aborted); | ||
| 24 | void rtw_report_sec_ie23a(struct rtw_adapter *adapter, u8 authmode, u8 *sec_ie); | ||
| 25 | |||
| 26 | void rtw_reset_securitypriv23a(struct rtw_adapter *adapter); | ||
| 27 | |||
| 28 | #endif /* _MLME_OSDEP_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/mp_custom_oid.h b/drivers/staging/rtl8723au/include/mp_custom_oid.h new file mode 100644 index 000000000000..da197cf678a1 --- /dev/null +++ b/drivers/staging/rtl8723au/include/mp_custom_oid.h | |||
| @@ -0,0 +1,342 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __CUSTOM_OID_H | ||
| 16 | #define __CUSTOM_OID_H | ||
| 17 | |||
| 18 | /* 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit */ | ||
| 19 | /* 0xFF818500 - 0xFF81850F RTL8185 Setup Utility */ | ||
| 20 | /* 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility */ | ||
| 21 | |||
| 22 | /* For Production Kit with Agilent Equipments */ | ||
| 23 | /* in order to make our custom oids hopefully somewhat unique */ | ||
| 24 | /* we will use 0xFF (indicating implementation specific OID) */ | ||
| 25 | /* 81(first byte of non zero Realtek unique identifier) */ | ||
| 26 | /* 80 (second byte of non zero Realtek unique identifier) */ | ||
| 27 | /* XX (the custom OID number - providing 255 possible custom oids) */ | ||
| 28 | |||
| 29 | #define OID_RT_PRO_RESET_DUT 0xFF818000 | ||
| 30 | #define OID_RT_PRO_SET_DATA_RATE 0xFF818001 | ||
| 31 | #define OID_RT_PRO_START_TEST 0xFF818002 | ||
| 32 | #define OID_RT_PRO_STOP_TEST 0xFF818003 | ||
| 33 | #define OID_RT_PRO_SET_PREAMBLE 0xFF818004 | ||
| 34 | #define OID_RT_PRO_SET_SCRAMBLER 0xFF818005 | ||
| 35 | #define OID_RT_PRO_SET_FILTER_BB 0xFF818006 | ||
| 36 | #define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007 | ||
| 37 | #define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008 | ||
| 38 | #define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009 | ||
| 39 | #define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A | ||
| 40 | |||
| 41 | #define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D | ||
| 42 | #define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E | ||
| 43 | #define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F | ||
| 44 | #define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010 | ||
| 45 | #define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011 | ||
| 46 | #define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012 | ||
| 47 | #define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013 | ||
| 48 | #define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014 | ||
| 49 | #define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015 | ||
| 50 | #define OID_RT_PRO_SET_INTEGRATOR 0xFF818016 | ||
| 51 | #define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017 | ||
| 52 | #define OID_RT_PRO_GET_INTEGRATOR 0xFF818018 | ||
| 53 | #define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019 | ||
| 54 | #define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A | ||
| 55 | #define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B | ||
| 56 | #define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C | ||
| 57 | #define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D | ||
| 58 | #define OID_RT_PRO_READ_CIS_DATA 0xFF81801E | ||
| 59 | #define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F | ||
| 60 | #define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020 | ||
| 61 | #define OID_RT_PRO_WRITE_EEPROM 0xFF818021 | ||
| 62 | #define OID_RT_PRO_READ_EEPROM 0xFF818022 | ||
| 63 | #define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023 | ||
| 64 | #define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024 | ||
| 65 | #define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025 | ||
| 66 | #define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026 | ||
| 67 | #define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027 | ||
| 68 | #define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028 | ||
| 69 | #define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029 | ||
| 70 | #define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A | ||
| 71 | #define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C | ||
| 72 | /* added by Owen on 04/08/03 for Cameo's request */ | ||
| 73 | #define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D | ||
| 74 | #define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E | ||
| 75 | #define OID_RT_PRO_SET_MODULATION 0xFF81802F | ||
| 76 | /* */ | ||
| 77 | |||
| 78 | #define OID_RT_DRIVER_OPTION 0xFF818080 | ||
| 79 | #define OID_RT_RF_OFF 0xFF818081 | ||
| 80 | #define OID_RT_AUTH_STATUS 0xFF818082 | ||
| 81 | |||
| 82 | /* */ | ||
| 83 | #define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B | ||
| 84 | #define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C | ||
| 85 | #define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B | ||
| 86 | #define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043 | ||
| 87 | /* */ | ||
| 88 | |||
| 89 | |||
| 90 | /* by Owen for RTL8185 Phy Status Report Utility */ | ||
| 91 | #define OID_RT_UTILITYfalse_ALARM_COUNTERS 0xFF818580 | ||
| 92 | #define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581 | ||
| 93 | #define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582 | ||
| 94 | #define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583 | ||
| 95 | #define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584 | ||
| 96 | #define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585 | ||
| 97 | #define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586 | ||
| 98 | |||
| 99 | /* by Owen on 03/09/19-03/09/22 for RTL8185 */ | ||
| 100 | #define OID_RT_WIRELESS_MODE 0xFF818500 | ||
| 101 | #define OID_RT_SUPPORTED_RATES 0xFF818501 | ||
| 102 | #define OID_RT_DESIRED_RATES 0xFF818502 | ||
| 103 | #define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503 | ||
| 104 | /* */ | ||
| 105 | |||
| 106 | #define OID_RT_GET_CONNECT_STATE 0xFF030001 | ||
| 107 | #define OID_RT_RESCAN 0xFF030002 | ||
| 108 | #define OID_RT_SET_KEY_LENGTH 0xFF030003 | ||
| 109 | #define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004 | ||
| 110 | |||
| 111 | #define OID_RT_SET_CHANNEL 0xFF010182 | ||
| 112 | #define OID_RT_SET_SNIFFER_MODE 0xFF010183 | ||
| 113 | #define OID_RT_GET_SIGNAL_QUALITY 0xFF010184 | ||
| 114 | #define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185 | ||
| 115 | #define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186 | ||
| 116 | #define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187 | ||
| 117 | #define OID_RT_GET_TX_RETRY 0xFF010188 | ||
| 118 | #define OID_RT_GET_RX_RETRY 0xFF010189 | ||
| 119 | #define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A/* S */ | ||
| 120 | #define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B/* S */ | ||
| 121 | |||
| 122 | #define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190 | ||
| 123 | #define OID_RT_GET_TX_BEACON_OK 0xFF010191 | ||
| 124 | #define OID_RT_GET_TX_BEACON_ERR 0xFF010192 | ||
| 125 | #define OID_RT_GET_RX_ICV_ERR 0xFF010193 | ||
| 126 | #define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194 | ||
| 127 | #define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195 | ||
| 128 | #define OID_RT_GET_PREAMBLE_MODE 0xFF010196 | ||
| 129 | #define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197 | ||
| 130 | #define OID_RT_GET_AP_IP 0xFF010198 | ||
| 131 | #define OID_RT_GET_CHANNELPLAN 0xFF010199 | ||
| 132 | #define OID_RT_SET_PREAMBLE_MODE 0xFF01019A | ||
| 133 | #define OID_RT_SET_BCN_INTVL 0xFF01019B | ||
| 134 | #define OID_RT_GET_RF_VENDER 0xFF01019C | ||
| 135 | #define OID_RT_DEDICATE_PROBE 0xFF01019D | ||
| 136 | #define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E | ||
| 137 | |||
| 138 | #define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F | ||
| 139 | |||
| 140 | #define OID_RT_GET_CCA_ERR 0xFF0101A0 | ||
| 141 | #define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1 | ||
| 142 | #define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2 | ||
| 143 | |||
| 144 | #define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3 | ||
| 145 | #define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4 | ||
| 146 | |||
| 147 | /* by Owen on 03/31/03 for Cameo's request */ | ||
| 148 | #define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5 | ||
| 149 | /* */ | ||
| 150 | #define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5 | ||
| 151 | #define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6 | ||
| 152 | #define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7 | ||
| 153 | #define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8 | ||
| 154 | #define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9 | ||
| 155 | #define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA | ||
| 156 | #define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB | ||
| 157 | #define OID_RT_GET_CHANNEL 0xFF0101AC | ||
| 158 | |||
| 159 | #define OID_RT_SET_CHANNELPLAN 0xFF0101AD | ||
| 160 | #define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE | ||
| 161 | #define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF | ||
| 162 | #define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0 | ||
| 163 | #define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1 | ||
| 164 | #define OID_RT_GET_IS_ROAMING 0xFF0101B2 | ||
| 165 | #define OID_RT_GET_IS_PRIVACY 0xFF0101B3 | ||
| 166 | #define OID_RT_GET_KEY_MISMATCH 0xFF0101B4 | ||
| 167 | #define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5 | ||
| 168 | #define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6 | ||
| 169 | #define OID_RT_RESET_LOG 0xFF0101B7 | ||
| 170 | #define OID_RT_GET_LOG 0xFF0101B8 | ||
| 171 | #define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9 | ||
| 172 | #define OID_RT_GET_HEADER_FAIL 0xFF0101BA | ||
| 173 | #define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB | ||
| 174 | #define OID_RT_GET_CHANNEL_LIST 0xFF0101BC | ||
| 175 | #define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD | ||
| 176 | #define OID_RT_GET_TX_INFO 0xFF0101BE | ||
| 177 | #define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF | ||
| 178 | #define OID_RT_RF_READ_WRITE 0xFF0101C0 | ||
| 179 | |||
| 180 | /* For Netgear request. 2005.01.13, by rcnjko. */ | ||
| 181 | #define OID_RT_FORCED_DATA_RATE 0xFF0101C1 | ||
| 182 | #define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2 | ||
| 183 | /* For Netgear request. 2005.02.17, by rcnjko. */ | ||
| 184 | #define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3 | ||
| 185 | /* For AZ project. 2005.06.27, by rcnjko. */ | ||
| 186 | #define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4 | ||
| 187 | |||
| 188 | /* Vincent 8185MP */ | ||
| 189 | #define OID_RT_PRO_RX_FILTER 0xFF0111C0 | ||
| 190 | |||
| 191 | /* Andy TEST */ | ||
| 192 | /* define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 */ | ||
| 193 | /* define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 */ | ||
| 194 | #define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1 | ||
| 195 | #define OID_CE_USB_READ_REGISTRY 0xFF0111C2 | ||
| 196 | |||
| 197 | |||
| 198 | #define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3 | ||
| 199 | #define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4 | ||
| 200 | #define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5 | ||
| 201 | #define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6 | ||
| 202 | #define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7 | ||
| 203 | #define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8 | ||
| 204 | #define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9 | ||
| 205 | #define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA | ||
| 206 | |||
| 207 | /* AP OID */ | ||
| 208 | #define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300 | ||
| 209 | #define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301 | ||
| 210 | #define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302 | ||
| 211 | #define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303 | ||
| 212 | #define OID_RT_AP_SUPPORTED 0xFF010304 /* Determine if driver supports AP mode. 2004.08.27, by rcnjko. */ | ||
| 213 | #define OID_RT_AP_SET_PASSPHRASE 0xFF010305 /* Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. */ | ||
| 214 | |||
| 215 | /* 8187MP. 2004.09.06, by rcnjko. */ | ||
| 216 | #define OID_RT_PRO8187_WI_POLL 0xFF818780 | ||
| 217 | #define OID_RT_PRO_WRITE_BB_REG 0xFF818781 | ||
| 218 | #define OID_RT_PRO_READ_BB_REG 0xFF818782 | ||
| 219 | #define OID_RT_PRO_WRITE_RF_REG 0xFF818783 | ||
| 220 | #define OID_RT_PRO_READ_RF_REG 0xFF818784 | ||
| 221 | |||
| 222 | /* Meeting House. added by Annie, 2005-07-20. */ | ||
| 223 | #define OID_RT_MH_VENDER_ID 0xFFEDC100 | ||
| 224 | |||
| 225 | /* 8711 MP OID added 20051230. */ | ||
| 226 | #define OID_RT_PRO8711_JOIN_BSS 0xFF871100/* S */ | ||
| 227 | |||
| 228 | #define OID_RT_PRO_READ_REGISTER 0xFF871101 /* Q */ | ||
| 229 | #define OID_RT_PRO_WRITE_REGISTER 0xFF871102 /* S */ | ||
| 230 | |||
| 231 | #define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 /* Q */ | ||
| 232 | #define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 /* S */ | ||
| 233 | |||
| 234 | #define OID_RT_PRO_WRITE_TXCMD 0xFF871105 /* S */ | ||
| 235 | |||
| 236 | #define OID_RT_PRO_READ16_EEPROM 0xFF871106 /* Q */ | ||
| 237 | #define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 /* S */ | ||
| 238 | |||
| 239 | #define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 /* S */ | ||
| 240 | #define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 /* Q */ | ||
| 241 | |||
| 242 | #define OID_RT_PRO8711_WI_POLL 0xFF87110A /* Q */ | ||
| 243 | #define OID_RT_PRO8711_PKT_LOSS 0xFF87110B /* Q */ | ||
| 244 | #define OID_RT_RD_ATTRIB_MEM 0xFF87110C/* Q */ | ||
| 245 | #define OID_RT_WR_ATTRIB_MEM 0xFF87110D/* S */ | ||
| 246 | |||
| 247 | |||
| 248 | /* Method 2 for H2C/C2H */ | ||
| 249 | #define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 /* S */ | ||
| 250 | #define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 /* Q */ | ||
| 251 | #define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 /* S */ | ||
| 252 | #define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 /* Q */ | ||
| 253 | #define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114/* Q */ | ||
| 254 | |||
| 255 | #define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 /* Q, S */ | ||
| 256 | |||
| 257 | #define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 /* S */ | ||
| 258 | #define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 /* Q,S */ | ||
| 259 | #define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 /* Q */ | ||
| 260 | #define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 /* Q */ | ||
| 261 | |||
| 262 | #define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A /* S */ | ||
| 263 | #define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B /* Q */ | ||
| 264 | #define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C /* S */ | ||
| 265 | #define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D /* Q */ | ||
| 266 | #define OID_RT_PRO_SET_RF_INTFS 0xFF87111E /* S */ | ||
| 267 | #define OID_RT_POLL_RX_STATUS 0xFF87111F /* Q */ | ||
| 268 | |||
| 269 | #define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 /* Q,S */ | ||
| 270 | #define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121/* S */ | ||
| 271 | #define OID_RT_PRO_SET_BASIC_RATE 0xFF871122/* S */ | ||
| 272 | #define OID_RT_PRO_READ_TSSI 0xFF871123/* S */ | ||
| 273 | #define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124/* S */ | ||
| 274 | |||
| 275 | |||
| 276 | #define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 /* Q */ | ||
| 277 | #define OID_RT_PRO_SET_PWRSTATE 0xFF871151 /* S */ | ||
| 278 | |||
| 279 | /* Method 2 , using workitem */ | ||
| 280 | #define OID_RT_SET_READ_REG 0xFF871181 /* S */ | ||
| 281 | #define OID_RT_SET_WRITE_REG 0xFF871182 /* S */ | ||
| 282 | #define OID_RT_SET_BURST_READ_REG 0xFF871183 /* S */ | ||
| 283 | #define OID_RT_SET_BURST_WRITE_REG 0xFF871184 /* S */ | ||
| 284 | #define OID_RT_SET_WRITE_TXCMD 0xFF871185 /* S */ | ||
| 285 | #define OID_RT_SET_READ16_EEPROM 0xFF871186 /* S */ | ||
| 286 | #define OID_RT_SET_WRITE16_EEPROM 0xFF871187 /* S */ | ||
| 287 | #define OID_RT_QRY_POLL_WKITEM 0xFF871188 /* Q */ | ||
| 288 | |||
| 289 | /* For SDIO INTERFACE only */ | ||
| 290 | #define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 /* Q, S */ | ||
| 291 | #define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1 | ||
| 292 | |||
| 293 | /* For USB INTERFACE only */ | ||
| 294 | #define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 /* Q, S */ | ||
| 295 | #define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 /* S */ | ||
| 296 | #define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 /* S */ | ||
| 297 | #define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 /* Q */ | ||
| 298 | #define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 /* Q */ | ||
| 299 | |||
| 300 | #define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB /* S */ | ||
| 301 | #define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC /* S */ | ||
| 302 | #define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE | ||
| 303 | |||
| 304 | #define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 /* Q, S */ | ||
| 305 | #define OID_RT_PRO_ADD_STA_INFO 0xFF871201 /* S */ | ||
| 306 | #define OID_RT_PRO_DELE_STA_INFO 0xFF871202 /* S */ | ||
| 307 | #define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 /* Q */ | ||
| 308 | |||
| 309 | #define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 /* Q, S */ | ||
| 310 | |||
| 311 | #define OID_RT_PRO_READ_EFUSE 0xFF871205 /* Q */ | ||
| 312 | #define OID_RT_PRO_WRITE_EFUSE 0xFF871206 /* S */ | ||
| 313 | #define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 /* Q, S */ | ||
| 314 | #define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 /* Q */ | ||
| 315 | |||
| 316 | #define OID_RT_SET_BANDWIDTH 0xFF871209 /* S */ | ||
| 317 | #define OID_RT_SET_CRYSTAL_CAP 0xFF87120A /* S */ | ||
| 318 | |||
| 319 | #define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B /* S */ | ||
| 320 | |||
| 321 | #define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C /* Q */ | ||
| 322 | |||
| 323 | #define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D /* S */ | ||
| 324 | |||
| 325 | #define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E /* S */ | ||
| 326 | |||
| 327 | #define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F /* S */ | ||
| 328 | |||
| 329 | #define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 /* Q */ | ||
| 330 | |||
| 331 | #define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 /* S */ | ||
| 332 | #define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 /* Q */ | ||
| 333 | #define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 /* Q */ | ||
| 334 | |||
| 335 | #define OID_RT_SET_POWER_DOWN 0xFF871214 /* S */ | ||
| 336 | |||
| 337 | #define OID_RT_GET_POWER_MODE 0xFF871215 /* Q */ | ||
| 338 | |||
| 339 | #define OID_RT_PRO_EFUSE 0xFF871216 /* Q, S */ | ||
| 340 | #define OID_RT_PRO_EFUSE_MAP 0xFF871217 /* Q, S */ | ||
| 341 | |||
| 342 | #endif /* ifndef __CUSTOM_OID_H */ | ||
diff --git a/drivers/staging/rtl8723au/include/odm.h b/drivers/staging/rtl8723au/include/odm.h new file mode 100644 index 000000000000..ac4273288cca --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm.h | |||
| @@ -0,0 +1,1210 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | |||
| 17 | #ifndef __HALDMOUTSRC_H__ | ||
| 18 | #define __HALDMOUTSRC_H__ | ||
| 19 | |||
| 20 | /* */ | ||
| 21 | /* Definition */ | ||
| 22 | /* */ | ||
| 23 | /* */ | ||
| 24 | /* 2011/09/22 MH Define all team supprt ability. */ | ||
| 25 | /* */ | ||
| 26 | |||
| 27 | /* */ | ||
| 28 | /* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */ | ||
| 29 | /* */ | ||
| 30 | /* define DM_ODM_SUPPORT_AP 0 */ | ||
| 31 | /* define DM_ODM_SUPPORT_ADSL 0 */ | ||
| 32 | /* define DM_ODM_SUPPORT_CE 0 */ | ||
| 33 | /* define DM_ODM_SUPPORT_MP 1 */ | ||
| 34 | |||
| 35 | #define TP_MODE 0 | ||
| 36 | #define RSSI_MODE 1 | ||
| 37 | #define TRAFFIC_LOW 0 | ||
| 38 | #define TRAFFIC_HIGH 1 | ||
| 39 | |||
| 40 | |||
| 41 | /* */ | ||
| 42 | /* 3 Tx Power Tracking */ | ||
| 43 | /* 3============================================================ */ | ||
| 44 | #define DPK_DELTA_MAPPING_NUM 13 | ||
| 45 | #define index_mapping_HP_NUM 15 | ||
| 46 | |||
| 47 | |||
| 48 | /* */ | ||
| 49 | /* 3 PSD Handler */ | ||
| 50 | /* 3============================================================ */ | ||
| 51 | |||
| 52 | #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ | ||
| 53 | #define MODE_40M 0 /* 0:20M, 1:40M */ | ||
| 54 | #define PSD_TH2 3 | ||
| 55 | #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ | ||
| 56 | #define SIR_STEP_SIZE 3 | ||
| 57 | #define Smooth_Size_1 5 | ||
| 58 | #define Smooth_TH_1 3 | ||
| 59 | #define Smooth_Size_2 10 | ||
| 60 | #define Smooth_TH_2 4 | ||
| 61 | #define Smooth_Size_3 20 | ||
| 62 | #define Smooth_TH_3 4 | ||
| 63 | #define Smooth_Step_Size 5 | ||
| 64 | #define Adaptive_SIR 1 | ||
| 65 | #define PSD_RESCAN 4 | ||
| 66 | #define PSD_SCAN_INTERVAL 700 /* ms */ | ||
| 67 | |||
| 68 | /* 8723A High Power IGI Setting */ | ||
| 69 | #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 | ||
| 70 | #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 | ||
| 71 | #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a | ||
| 72 | |||
| 73 | /* LPS define */ | ||
| 74 | #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ | ||
| 75 | #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ | ||
| 76 | #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ | ||
| 77 | #define RSSI_OFFSET_DIG 0x05; | ||
| 78 | |||
| 79 | /* ANT Test */ | ||
| 80 | #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ | ||
| 81 | #define ANTTESTA 0x01 /* Ant A will be Testing */ | ||
| 82 | #define ANTTESTB 0x02 /* Ant B will be testing */ | ||
| 83 | |||
| 84 | |||
| 85 | /* */ | ||
| 86 | /* structure and define */ | ||
| 87 | /* */ | ||
| 88 | |||
| 89 | /* */ | ||
| 90 | /* 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. */ | ||
| 91 | /* We need to remove to other position??? */ | ||
| 92 | /* */ | ||
| 93 | struct rtl8723a_priv { | ||
| 94 | u8 temp; | ||
| 95 | }; | ||
| 96 | |||
| 97 | |||
| 98 | struct dig_t { | ||
| 99 | u8 Dig_Enable_Flag; | ||
| 100 | u8 Dig_Ext_Port_Stage; | ||
| 101 | |||
| 102 | int RssiLowThresh; | ||
| 103 | int RssiHighThresh; | ||
| 104 | |||
| 105 | u32 FALowThresh; | ||
| 106 | u32 FAHighThresh; | ||
| 107 | |||
| 108 | u8 CurSTAConnectState; | ||
| 109 | u8 PreSTAConnectState; | ||
| 110 | u8 CurMultiSTAConnectState; | ||
| 111 | |||
| 112 | u8 PreIGValue; | ||
| 113 | u8 CurIGValue; | ||
| 114 | u8 BackupIGValue; | ||
| 115 | |||
| 116 | s8 BackoffVal; | ||
| 117 | s8 BackoffVal_range_max; | ||
| 118 | s8 BackoffVal_range_min; | ||
| 119 | u8 rx_gain_range_max; | ||
| 120 | u8 rx_gain_range_min; | ||
| 121 | u8 Rssi_val_min; | ||
| 122 | |||
| 123 | u8 PreCCK_CCAThres; | ||
| 124 | u8 CurCCK_CCAThres; | ||
| 125 | u8 PreCCKPDState; | ||
| 126 | u8 CurCCKPDState; | ||
| 127 | |||
| 128 | u8 LargeFAHit; | ||
| 129 | u8 ForbiddenIGI; | ||
| 130 | u32 Recover_cnt; | ||
| 131 | |||
| 132 | u8 DIG_Dynamic_MIN_0; | ||
| 133 | u8 DIG_Dynamic_MIN_1; | ||
| 134 | bool bMediaConnect_0; | ||
| 135 | bool bMediaConnect_1; | ||
| 136 | |||
| 137 | u32 AntDiv_RSSI_max; | ||
| 138 | u32 RSSI_max; | ||
| 139 | }; | ||
| 140 | |||
| 141 | struct dynamic_pwr_sav { | ||
| 142 | u8 PreCCAState; | ||
| 143 | u8 CurCCAState; | ||
| 144 | |||
| 145 | u8 PreRFState; | ||
| 146 | u8 CurRFState; | ||
| 147 | |||
| 148 | int Rssi_val_min; | ||
| 149 | |||
| 150 | u8 initialize; | ||
| 151 | u32 Reg874,RegC70,Reg85C,RegA74; | ||
| 152 | }; | ||
| 153 | |||
| 154 | struct false_alarm_stats { | ||
| 155 | u32 Cnt_Parity_Fail; | ||
| 156 | u32 Cnt_Rate_Illegal; | ||
| 157 | u32 Cnt_Crc8_fail; | ||
| 158 | u32 Cnt_Mcs_fail; | ||
| 159 | u32 Cnt_Ofdm_fail; | ||
| 160 | u32 Cnt_Cck_fail; | ||
| 161 | u32 Cnt_all; | ||
| 162 | u32 Cnt_Fast_Fsync; | ||
| 163 | u32 Cnt_SB_Search_fail; | ||
| 164 | u32 Cnt_OFDM_CCA; | ||
| 165 | u32 Cnt_CCK_CCA; | ||
| 166 | u32 Cnt_CCA_all; | ||
| 167 | u32 Cnt_BW_USC; /* Gary */ | ||
| 168 | u32 Cnt_BW_LSC; /* Gary */ | ||
| 169 | }; | ||
| 170 | |||
| 171 | struct pri_cca { | ||
| 172 | u8 PriCCA_flag; | ||
| 173 | u8 intf_flag; | ||
| 174 | u8 intf_type; | ||
| 175 | u8 DupRTS_flag; | ||
| 176 | u8 Monitor_flag; | ||
| 177 | }; | ||
| 178 | |||
| 179 | struct rx_hp { | ||
| 180 | u8 RXHP_flag; | ||
| 181 | u8 PSD_func_trigger; | ||
| 182 | u8 PSD_bitmap_RXHP[80]; | ||
| 183 | u8 Pre_IGI; | ||
| 184 | u8 Cur_IGI; | ||
| 185 | u8 Pre_pw_th; | ||
| 186 | u8 Cur_pw_th; | ||
| 187 | bool First_time_enter; | ||
| 188 | bool RXHP_enable; | ||
| 189 | u8 TP_Mode; | ||
| 190 | struct timer_list PSDTimer; | ||
| 191 | }; | ||
| 192 | |||
| 193 | #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ | ||
| 194 | #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM | ||
| 195 | |||
| 196 | /* This indicates two different the steps. */ | ||
| 197 | /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ | ||
| 198 | /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ | ||
| 199 | /* with original RSSI to determine if it is necessary to switch antenna. */ | ||
| 200 | #define SWAW_STEP_PEAK 0 | ||
| 201 | #define SWAW_STEP_DETERMINE 1 | ||
| 202 | |||
| 203 | #define TP_MODE 0 | ||
| 204 | #define RSSI_MODE 1 | ||
| 205 | #define TRAFFIC_LOW 0 | ||
| 206 | #define TRAFFIC_HIGH 1 | ||
| 207 | |||
| 208 | struct sw_ant_sw { | ||
| 209 | u8 try_flag; | ||
| 210 | s32 PreRSSI; | ||
| 211 | u8 CurAntenna; | ||
| 212 | u8 PreAntenna; | ||
| 213 | u8 RSSI_Trying; | ||
| 214 | u8 TestMode; | ||
| 215 | u8 bTriggerAntennaSwitch; | ||
| 216 | u8 SelectAntennaMap; | ||
| 217 | u8 RSSI_target; | ||
| 218 | |||
| 219 | /* Before link Antenna Switch check */ | ||
| 220 | u8 SWAS_NoLink_State; | ||
| 221 | u32 SWAS_NoLink_BK_Reg860; | ||
| 222 | bool ANTA_ON; /* To indicate Ant A is or not */ | ||
| 223 | bool ANTB_ON; /* To indicate Ant B is on or not */ | ||
| 224 | |||
| 225 | s32 RSSI_sum_A; | ||
| 226 | s32 RSSI_sum_B; | ||
| 227 | s32 RSSI_cnt_A; | ||
| 228 | s32 RSSI_cnt_B; | ||
| 229 | |||
| 230 | u64 lastTxOkCnt; | ||
| 231 | u64 lastRxOkCnt; | ||
| 232 | u64 TXByteCnt_A; | ||
| 233 | u64 TXByteCnt_B; | ||
| 234 | u64 RXByteCnt_A; | ||
| 235 | u64 RXByteCnt_B; | ||
| 236 | u8 TrafficLoad; | ||
| 237 | struct timer_list SwAntennaSwitchTimer; | ||
| 238 | }; | ||
| 239 | |||
| 240 | struct edca_turbo { | ||
| 241 | bool bCurrentTurboEDCA; | ||
| 242 | bool bIsCurRDLState; | ||
| 243 | u32 prv_traffic_idx; /* edca turbo */ | ||
| 244 | |||
| 245 | }; | ||
| 246 | |||
| 247 | struct odm_rate_adapt { | ||
| 248 | u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ | ||
| 249 | u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ | ||
| 250 | u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ | ||
| 251 | u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ | ||
| 252 | u32 LastRATR; /* RATR Register Content */ | ||
| 253 | }; | ||
| 254 | |||
| 255 | #define IQK_MAC_REG_NUM 4 | ||
| 256 | #define IQK_ADDA_REG_NUM 16 | ||
| 257 | #define IQK_BB_REG_NUM_MAX 10 | ||
| 258 | #define IQK_BB_REG_NUM 9 | ||
| 259 | #define HP_THERMAL_NUM 8 | ||
| 260 | |||
| 261 | #define AVG_THERMAL_NUM 8 | ||
| 262 | #define IQK_Matrix_REG_NUM 8 | ||
| 263 | #define IQK_Matrix_Settings_NUM 1+24+21 | ||
| 264 | |||
| 265 | #define DM_Type_ByFW 0 | ||
| 266 | #define DM_Type_ByDriver 1 | ||
| 267 | |||
| 268 | /* */ | ||
| 269 | /* Declare for common info */ | ||
| 270 | /* */ | ||
| 271 | /* Declare for common info */ | ||
| 272 | /* */ | ||
| 273 | #define MAX_PATH_NUM_92CS 2 | ||
| 274 | |||
| 275 | struct odm_phy_info { | ||
| 276 | u8 RxPWDBAll; | ||
| 277 | u8 SignalQuality; /* in 0-100 index. */ | ||
| 278 | u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ | ||
| 279 | u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */ | ||
| 280 | s8 RxPower; /* in dBm Translate from PWdB */ | ||
| 281 | s8 RecvSignalPower;/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ | ||
| 282 | u8 BTRxRSSIPercentage; | ||
| 283 | u8 SignalStrength; /* in 0-100 index. */ | ||
| 284 | u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ | ||
| 285 | u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ | ||
| 286 | }; | ||
| 287 | |||
| 288 | |||
| 289 | struct odm_phy_dbg_info { | ||
| 290 | /* ODM Write,debug info */ | ||
| 291 | s8 RxSNRdB[MAX_PATH_NUM_92CS]; | ||
| 292 | u64 NumQryPhyStatus; | ||
| 293 | u64 NumQryPhyStatusCCK; | ||
| 294 | u64 NumQryPhyStatusOFDM; | ||
| 295 | /* Others */ | ||
| 296 | s32 RxEVM[MAX_PATH_NUM_92CS]; | ||
| 297 | |||
| 298 | }; | ||
| 299 | |||
| 300 | struct odm_packet_info { | ||
| 301 | u8 Rate; | ||
| 302 | u8 StationID; | ||
| 303 | bool bPacketMatchBSSID; | ||
| 304 | bool bPacketToSelf; | ||
| 305 | bool bPacketBeacon; | ||
| 306 | }; | ||
| 307 | |||
| 308 | struct odm_mac_info { | ||
| 309 | u8 test; | ||
| 310 | |||
| 311 | }; | ||
| 312 | |||
| 313 | |||
| 314 | enum { | ||
| 315 | /* BB Team */ | ||
| 316 | ODM_DIG = 0x00000001, | ||
| 317 | ODM_HIGH_POWER = 0x00000002, | ||
| 318 | ODM_CCK_CCA_TH = 0x00000004, | ||
| 319 | ODM_FA_STATISTICS = 0x00000008, | ||
| 320 | ODM_RAMASK = 0x00000010, | ||
| 321 | ODM_RSSI_MONITOR = 0x00000020, | ||
| 322 | ODM_SW_ANTDIV = 0x00000040, | ||
| 323 | ODM_HW_ANTDIV = 0x00000080, | ||
| 324 | ODM_BB_PWRSV = 0x00000100, | ||
| 325 | ODM_2TPATHDIV = 0x00000200, | ||
| 326 | ODM_1TPATHDIV = 0x00000400, | ||
| 327 | ODM_PSD2AFH = 0x00000800 | ||
| 328 | }; | ||
| 329 | |||
| 330 | /* */ | ||
| 331 | /* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */ | ||
| 332 | /* Please declare below ODM relative info in your STA info structure. */ | ||
| 333 | /* */ | ||
| 334 | struct odm_sta_info { | ||
| 335 | /* Driver Write */ | ||
| 336 | bool bUsed; /* record the sta status link or not? */ | ||
| 337 | u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ | ||
| 338 | |||
| 339 | /* ODM Write */ | ||
| 340 | /* 1 PHY_STATUS_INFO */ | ||
| 341 | u8 RSSI_Path[4]; /* */ | ||
| 342 | u8 RSSI_Ave; | ||
| 343 | u8 RXEVM[4]; | ||
| 344 | u8 RXSNR[4]; | ||
| 345 | |||
| 346 | /* ODM Write */ | ||
| 347 | /* 1 TX_INFO (may changed by IC) */ | ||
| 348 | |||
| 349 | /* */ | ||
| 350 | /* Please use compile flag to disable the structure for other IC except 88E. */ | ||
| 351 | /* Move To lower layer. */ | ||
| 352 | /* */ | ||
| 353 | /* ODM Write Wilson will handle this part(said by Luke.Lee) */ | ||
| 354 | }; | ||
| 355 | |||
| 356 | /* */ | ||
| 357 | /* 2011/10/20 MH Define Common info enum for all team. */ | ||
| 358 | /* */ | ||
| 359 | |||
| 360 | enum odm_cmninfo { | ||
| 361 | /* Fixed value: */ | ||
| 362 | /* */ | ||
| 363 | |||
| 364 | ODM_CMNINFO_PLATFORM = 0, | ||
| 365 | ODM_CMNINFO_ABILITY, /* enum odm_ability */ | ||
| 366 | ODM_CMNINFO_INTERFACE, /* enum odm_interface_def */ | ||
| 367 | ODM_CMNINFO_MP_TEST_CHIP, | ||
| 368 | ODM_CMNINFO_IC_TYPE, /* enum odm_ic_type_def */ | ||
| 369 | ODM_CMNINFO_CUT_VER, /* enum odm_cut_version */ | ||
| 370 | ODM_CMNINFO_FAB_VER, /* enum odm_fab_version */ | ||
| 371 | ODM_CMNINFO_RF_TYPE, /* enum rf_path_def or enum odm_rf_type? */ | ||
| 372 | ODM_CMNINFO_BOARD_TYPE, /* enum odm_board_type */ | ||
| 373 | ODM_CMNINFO_EXT_LNA, /* true */ | ||
| 374 | ODM_CMNINFO_EXT_PA, | ||
| 375 | ODM_CMNINFO_EXT_TRSW, | ||
| 376 | ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ | ||
| 377 | ODM_CMNINFO_BINHCT_TEST, | ||
| 378 | ODM_CMNINFO_BWIFI_TEST, | ||
| 379 | ODM_CMNINFO_SMART_CONCURRENT, | ||
| 380 | |||
| 381 | |||
| 382 | /* */ | ||
| 383 | /* Dynamic value: */ | ||
| 384 | /* */ | ||
| 385 | ODM_CMNINFO_MAC_PHY_MODE, /* enum odm_mac_phy_mode */ | ||
| 386 | ODM_CMNINFO_TX_UNI, | ||
| 387 | ODM_CMNINFO_RX_UNI, | ||
| 388 | ODM_CMNINFO_WM_MODE, /* enum odm_wireless_mode */ | ||
| 389 | ODM_CMNINFO_BAND, /* enum odm_band_type */ | ||
| 390 | ODM_CMNINFO_SEC_CHNL_OFFSET, /* enum odm_sec_chnl_offset */ | ||
| 391 | ODM_CMNINFO_SEC_MODE, /* enum odm_security */ | ||
| 392 | ODM_CMNINFO_BW, /* enum odm_band_width */ | ||
| 393 | ODM_CMNINFO_CHNL, | ||
| 394 | |||
| 395 | ODM_CMNINFO_DMSP_GET_VALUE, | ||
| 396 | ODM_CMNINFO_BUDDY_ADAPTOR, | ||
| 397 | ODM_CMNINFO_DMSP_IS_MASTER, | ||
| 398 | ODM_CMNINFO_SCAN, | ||
| 399 | ODM_CMNINFO_POWER_SAVING, | ||
| 400 | ODM_CMNINFO_ONE_PATH_CCA, /* enum odm_cca_path */ | ||
| 401 | ODM_CMNINFO_DRV_STOP, | ||
| 402 | ODM_CMNINFO_PNP_IN, | ||
| 403 | ODM_CMNINFO_INIT_ON, | ||
| 404 | ODM_CMNINFO_ANT_TEST, | ||
| 405 | ODM_CMNINFO_NET_CLOSED, | ||
| 406 | ODM_CMNINFO_MP_MODE, | ||
| 407 | |||
| 408 | ODM_CMNINFO_WIFI_DIRECT, | ||
| 409 | ODM_CMNINFO_WIFI_DISPLAY, | ||
| 410 | ODM_CMNINFO_LINK, | ||
| 411 | ODM_CMNINFO_RSSI_MIN, | ||
| 412 | ODM_CMNINFO_DBG_COMP, /* u64 */ | ||
| 413 | ODM_CMNINFO_DBG_LEVEL, /* u32 */ | ||
| 414 | ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ | ||
| 415 | ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ | ||
| 416 | ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ | ||
| 417 | ODM_CMNINFO_BT_DISABLED, | ||
| 418 | ODM_CMNINFO_BT_OPERATION, | ||
| 419 | ODM_CMNINFO_BT_DIG, | ||
| 420 | ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ | ||
| 421 | ODM_CMNINFO_BT_DISABLE_EDCA, | ||
| 422 | |||
| 423 | /* */ | ||
| 424 | /* Dynamic ptr array hook itms. */ | ||
| 425 | /* */ | ||
| 426 | ODM_CMNINFO_STA_STATUS, | ||
| 427 | ODM_CMNINFO_PHY_STATUS, | ||
| 428 | ODM_CMNINFO_MAC_STATUS, | ||
| 429 | |||
| 430 | ODM_CMNINFO_MAX, | ||
| 431 | }; | ||
| 432 | |||
| 433 | /* Define ODM support ability. ODM_CMNINFO_ABILITY */ | ||
| 434 | enum { | ||
| 435 | /* BB ODM section BIT 0-15 */ | ||
| 436 | ODM_BB_DIG = BIT0, | ||
| 437 | ODM_BB_RA_MASK = BIT1, | ||
| 438 | ODM_BB_DYNAMIC_TXPWR = BIT2, | ||
| 439 | ODM_BB_FA_CNT = BIT3, | ||
| 440 | ODM_BB_RSSI_MONITOR = BIT4, | ||
| 441 | ODM_BB_CCK_PD = BIT5, | ||
| 442 | ODM_BB_ANT_DIV = BIT6, | ||
| 443 | ODM_BB_PWR_SAVE = BIT7, | ||
| 444 | ODM_BB_PWR_TRAIN = BIT8, | ||
| 445 | ODM_BB_RATE_ADAPTIVE = BIT9, | ||
| 446 | ODM_BB_PATH_DIV = BIT10, | ||
| 447 | ODM_BB_PSD = BIT11, | ||
| 448 | ODM_BB_RXHP = BIT12, | ||
| 449 | |||
| 450 | /* MAC DM section BIT 16-23 */ | ||
| 451 | ODM_MAC_EDCA_TURBO = BIT16, | ||
| 452 | ODM_MAC_EARLY_MODE = BIT17, | ||
| 453 | |||
| 454 | /* RF ODM section BIT 24-31 */ | ||
| 455 | ODM_RF_TX_PWR_TRACK = BIT24, | ||
| 456 | ODM_RF_RX_GAIN_TRACK = BIT25, | ||
| 457 | ODM_RF_CALIBRATION = BIT26, | ||
| 458 | |||
| 459 | }; | ||
| 460 | |||
| 461 | /* ODM_CMNINFO_INTERFACE */ | ||
| 462 | enum odm_interface_def { | ||
| 463 | ODM_ITRF_PCIE = 0x1, | ||
| 464 | ODM_ITRF_USB = 0x2, | ||
| 465 | ODM_ITRF_SDIO = 0x4, | ||
| 466 | ODM_ITRF_ALL = 0x7, | ||
| 467 | }; | ||
| 468 | |||
| 469 | /* ODM_CMNINFO_IC_TYPE */ | ||
| 470 | enum odm_ic_type_def { | ||
| 471 | ODM_RTL8192S = BIT0, | ||
| 472 | ODM_RTL8192C = BIT1, | ||
| 473 | ODM_RTL8192D = BIT2, | ||
| 474 | ODM_RTL8723A = BIT3, | ||
| 475 | ODM_RTL8188E = BIT4, | ||
| 476 | ODM_RTL8812 = BIT5, | ||
| 477 | ODM_RTL8821 = BIT6, | ||
| 478 | }; | ||
| 479 | |||
| 480 | #define ODM_IC_11N_SERIES \ | ||
| 481 | (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E) | ||
| 482 | #define ODM_IC_11AC_SERIES (ODM_RTL8812) | ||
| 483 | |||
| 484 | /* ODM_CMNINFO_CUT_VER */ | ||
| 485 | enum odm_cut_version { | ||
| 486 | ODM_CUT_A = 1, | ||
| 487 | ODM_CUT_B = 2, | ||
| 488 | ODM_CUT_C = 3, | ||
| 489 | ODM_CUT_D = 4, | ||
| 490 | ODM_CUT_E = 5, | ||
| 491 | ODM_CUT_F = 6, | ||
| 492 | ODM_CUT_TEST = 7, | ||
| 493 | }; | ||
| 494 | |||
| 495 | /* ODM_CMNINFO_FAB_VER */ | ||
| 496 | enum odm_fab_version { | ||
| 497 | ODM_TSMC = 0, | ||
| 498 | ODM_UMC = 1, | ||
| 499 | }; | ||
| 500 | |||
| 501 | /* ODM_CMNINFO_RF_TYPE */ | ||
| 502 | /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ | ||
| 503 | enum rf_path_def { | ||
| 504 | ODM_RF_TX_A = BIT0, | ||
| 505 | ODM_RF_TX_B = BIT1, | ||
| 506 | ODM_RF_TX_C = BIT2, | ||
| 507 | ODM_RF_TX_D = BIT3, | ||
| 508 | ODM_RF_RX_A = BIT4, | ||
| 509 | ODM_RF_RX_B = BIT5, | ||
| 510 | ODM_RF_RX_C = BIT6, | ||
| 511 | ODM_RF_RX_D = BIT7, | ||
| 512 | }; | ||
| 513 | |||
| 514 | |||
| 515 | enum odm_rf_type { | ||
| 516 | ODM_1T1R = 0, | ||
| 517 | ODM_1T2R = 1, | ||
| 518 | ODM_2T2R = 2, | ||
| 519 | ODM_2T3R = 3, | ||
| 520 | ODM_2T4R = 4, | ||
| 521 | ODM_3T3R = 5, | ||
| 522 | ODM_3T4R = 6, | ||
| 523 | ODM_4T4R = 7, | ||
| 524 | }; | ||
| 525 | |||
| 526 | /* ODM Dynamic common info value definition */ | ||
| 527 | |||
| 528 | enum odm_mac_phy_mode { | ||
| 529 | ODM_SMSP = 0, | ||
| 530 | ODM_DMSP = 1, | ||
| 531 | ODM_DMDP = 2, | ||
| 532 | }; | ||
| 533 | |||
| 534 | |||
| 535 | enum odm_bt_coexist { | ||
| 536 | ODM_BT_BUSY = 1, | ||
| 537 | ODM_BT_ON = 2, | ||
| 538 | ODM_BT_OFF = 3, | ||
| 539 | ODM_BT_NONE = 4, | ||
| 540 | }; | ||
| 541 | |||
| 542 | /* ODM_CMNINFO_OP_MODE */ | ||
| 543 | enum odm_operation_mode { | ||
| 544 | ODM_NO_LINK = BIT0, | ||
| 545 | ODM_LINK = BIT1, | ||
| 546 | ODM_SCAN = BIT2, | ||
| 547 | ODM_POWERSAVE = BIT3, | ||
| 548 | ODM_AP_MODE = BIT4, | ||
| 549 | ODM_CLIENT_MODE = BIT5, | ||
| 550 | ODM_AD_HOC = BIT6, | ||
| 551 | ODM_WIFI_DIRECT = BIT7, | ||
| 552 | ODM_WIFI_DISPLAY = BIT8, | ||
| 553 | }; | ||
| 554 | |||
| 555 | /* ODM_CMNINFO_WM_MODE */ | ||
| 556 | enum odm_wireless_mode { | ||
| 557 | ODM_WM_UNKNOW = 0x0, | ||
| 558 | ODM_WM_B = BIT0, | ||
| 559 | ODM_WM_G = BIT1, | ||
| 560 | ODM_WM_A = BIT2, | ||
| 561 | ODM_WM_N24G = BIT3, | ||
| 562 | ODM_WM_N5G = BIT4, | ||
| 563 | ODM_WM_AUTO = BIT5, | ||
| 564 | ODM_WM_AC = BIT6, | ||
| 565 | }; | ||
| 566 | |||
| 567 | /* ODM_CMNINFO_BAND */ | ||
| 568 | enum odm_band_type { | ||
| 569 | ODM_BAND_2_4G = BIT0, | ||
| 570 | ODM_BAND_5G = BIT1, | ||
| 571 | |||
| 572 | }; | ||
| 573 | |||
| 574 | /* ODM_CMNINFO_SEC_CHNL_OFFSET */ | ||
| 575 | enum odm_sec_chnl_offset { | ||
| 576 | ODM_DONT_CARE = 0, | ||
| 577 | ODM_BELOW = 1, | ||
| 578 | ODM_ABOVE = 2 | ||
| 579 | }; | ||
| 580 | |||
| 581 | /* ODM_CMNINFO_SEC_MODE */ | ||
| 582 | enum odm_security { | ||
| 583 | ODM_SEC_OPEN = 0, | ||
| 584 | ODM_SEC_WEP40 = 1, | ||
| 585 | ODM_SEC_TKIP = 2, | ||
| 586 | ODM_SEC_RESERVE = 3, | ||
| 587 | ODM_SEC_AESCCMP = 4, | ||
| 588 | ODM_SEC_WEP104 = 5, | ||
| 589 | ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ | ||
| 590 | ODM_SEC_SMS4 = 7, | ||
| 591 | }; | ||
| 592 | |||
| 593 | /* ODM_CMNINFO_BW */ | ||
| 594 | enum odm_band_width { | ||
| 595 | ODM_BW20M = 0, | ||
| 596 | ODM_BW40M = 1, | ||
| 597 | ODM_BW80M = 2, | ||
| 598 | ODM_BW160M = 3, | ||
| 599 | ODM_BW10M = 4, | ||
| 600 | }; | ||
| 601 | |||
| 602 | /* ODM_CMNINFO_CHNL */ | ||
| 603 | |||
| 604 | /* ODM_CMNINFO_BOARD_TYPE */ | ||
| 605 | enum odm_board_type { | ||
| 606 | ODM_BOARD_NORMAL = 0, | ||
| 607 | ODM_BOARD_HIGHPWR = 1, | ||
| 608 | ODM_BOARD_MINICARD = 2, | ||
| 609 | ODM_BOARD_SLIM = 3, | ||
| 610 | ODM_BOARD_COMBO = 4, | ||
| 611 | |||
| 612 | }; | ||
| 613 | |||
| 614 | /* ODM_CMNINFO_ONE_PATH_CCA */ | ||
| 615 | enum odm_cca_path { | ||
| 616 | ODM_CCA_2R = 0, | ||
| 617 | ODM_CCA_1R_A = 1, | ||
| 618 | ODM_CCA_1R_B = 2, | ||
| 619 | }; | ||
| 620 | |||
| 621 | struct odm_ra_info { | ||
| 622 | u8 RateID; | ||
| 623 | u32 RateMask; | ||
| 624 | u32 RAUseRate; | ||
| 625 | u8 RateSGI; | ||
| 626 | u8 RssiStaRA; | ||
| 627 | u8 PreRssiStaRA; | ||
| 628 | u8 SGIEnable; | ||
| 629 | u8 DecisionRate; | ||
| 630 | u8 PreRate; | ||
| 631 | u8 HighestRate; | ||
| 632 | u8 LowestRate; | ||
| 633 | u32 NscUp; | ||
| 634 | u32 NscDown; | ||
| 635 | u16 RTY[5]; | ||
| 636 | u32 TOTAL; | ||
| 637 | u16 DROP; | ||
| 638 | u8 Active; | ||
| 639 | u16 RptTime; | ||
| 640 | u8 RAWaitingCounter; | ||
| 641 | u8 RAPendingCounter; | ||
| 642 | u8 PTActive; /* on or off */ | ||
| 643 | u8 PTTryState; /* 0 trying state, 1 for decision state */ | ||
| 644 | u8 PTStage; /* 0~6 */ | ||
| 645 | u8 PTStopCount; /* Stop PT counter */ | ||
| 646 | u8 PTPreRate; /* if rate change do PT */ | ||
| 647 | u8 PTPreRssi; /* if RSSI change 5% do PT */ | ||
| 648 | u8 PTModeSS; /* decide whitch rate should do PT */ | ||
| 649 | u8 RAstage; /* StageRA, decide how many times RA will be done between PT */ | ||
| 650 | u8 PTSmoothFactor; | ||
| 651 | }; | ||
| 652 | |||
| 653 | struct iqk_matrix_regs_set { | ||
| 654 | bool bIQKDone; | ||
| 655 | s32 Value[1][IQK_Matrix_REG_NUM]; | ||
| 656 | }; | ||
| 657 | |||
| 658 | struct odm_rf_cal_t { | ||
| 659 | /* for tx power tracking */ | ||
| 660 | |||
| 661 | u32 RegA24; /* for TempCCK */ | ||
| 662 | s32 RegE94; | ||
| 663 | s32 RegE9C; | ||
| 664 | s32 RegEB4; | ||
| 665 | s32 RegEBC; | ||
| 666 | |||
| 667 | /* u8 bTXPowerTracking; */ | ||
| 668 | u8 TXPowercount; | ||
| 669 | bool bTXPowerTrackingInit; | ||
| 670 | bool bTXPowerTracking; | ||
| 671 | u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ | ||
| 672 | u8 TM_Trigger; | ||
| 673 | u8 InternalPA5G[2]; /* pathA / pathB */ | ||
| 674 | |||
| 675 | u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ | ||
| 676 | u8 ThermalValue; | ||
| 677 | u8 ThermalValue_LCK; | ||
| 678 | u8 ThermalValue_IQK; | ||
| 679 | u8 ThermalValue_DPK; | ||
| 680 | u8 ThermalValue_AVG[AVG_THERMAL_NUM]; | ||
| 681 | u8 ThermalValue_AVG_index; | ||
| 682 | u8 ThermalValue_RxGain; | ||
| 683 | u8 ThermalValue_Crystal; | ||
| 684 | u8 ThermalValue_DPKstore; | ||
| 685 | u8 ThermalValue_DPKtrack; | ||
| 686 | bool TxPowerTrackingInProgress; | ||
| 687 | bool bDPKenable; | ||
| 688 | |||
| 689 | bool bReloadtxpowerindex; | ||
| 690 | u8 bRfPiEnable; | ||
| 691 | u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ | ||
| 692 | |||
| 693 | u8 bCCKinCH14; | ||
| 694 | u8 CCK_index; | ||
| 695 | u8 OFDM_index[2]; | ||
| 696 | bool bDoneTxpower; | ||
| 697 | |||
| 698 | u8 ThermalValue_HP[HP_THERMAL_NUM]; | ||
| 699 | u8 ThermalValue_HP_index; | ||
| 700 | struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; | ||
| 701 | |||
| 702 | u8 Delta_IQK; | ||
| 703 | u8 Delta_LCK; | ||
| 704 | |||
| 705 | /* for IQK */ | ||
| 706 | u32 RegC04; | ||
| 707 | u32 Reg874; | ||
| 708 | u32 RegC08; | ||
| 709 | u32 RegB68; | ||
| 710 | u32 RegB6C; | ||
| 711 | u32 Reg870; | ||
| 712 | u32 Reg860; | ||
| 713 | u32 Reg864; | ||
| 714 | |||
| 715 | bool bIQKInitialized; | ||
| 716 | bool bLCKInProgress; | ||
| 717 | bool bAntennaDetected; | ||
| 718 | u32 ADDA_backup[IQK_ADDA_REG_NUM]; | ||
| 719 | u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; | ||
| 720 | u32 IQK_BB_backup_recover[9]; | ||
| 721 | u32 IQK_BB_backup[IQK_BB_REG_NUM]; | ||
| 722 | |||
| 723 | /* for APK */ | ||
| 724 | u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ | ||
| 725 | u8 bAPKdone; | ||
| 726 | u8 bAPKThermalMeterIgnore; | ||
| 727 | u8 bDPdone; | ||
| 728 | u8 bDPPathAOK; | ||
| 729 | u8 bDPPathBOK; | ||
| 730 | }; | ||
| 731 | |||
| 732 | /* ODM Dynamic common info value definition */ | ||
| 733 | struct odm_fat_t { | ||
| 734 | u8 Bssid[6]; | ||
| 735 | u8 antsel_rx_keep_0; | ||
| 736 | u8 antsel_rx_keep_1; | ||
| 737 | u8 antsel_rx_keep_2; | ||
| 738 | u32 antSumRSSI[7]; | ||
| 739 | u32 antRSSIcnt[7]; | ||
| 740 | u32 antAveRSSI[7]; | ||
| 741 | u8 FAT_State; | ||
| 742 | u32 TrainIdx; | ||
| 743 | u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; | ||
| 744 | u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; | ||
| 745 | u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; | ||
| 746 | u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; | ||
| 747 | u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; | ||
| 748 | u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; | ||
| 749 | u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; | ||
| 750 | u8 RxIdleAnt; | ||
| 751 | bool bBecomeLinked; | ||
| 752 | }; | ||
| 753 | |||
| 754 | enum fat_state { | ||
| 755 | FAT_NORMAL_STATE = 0, | ||
| 756 | FAT_TRAINING_STATE = 1, | ||
| 757 | }; | ||
| 758 | |||
| 759 | enum ant_dif_type { | ||
| 760 | NO_ANTDIV = 0xFF, | ||
| 761 | CG_TRX_HW_ANTDIV = 0x01, | ||
| 762 | CGCS_RX_HW_ANTDIV = 0x02, | ||
| 763 | FIXED_HW_ANTDIV = 0x03, | ||
| 764 | CG_TRX_SMART_ANTDIV = 0x04, | ||
| 765 | CGCS_RX_SW_ANTDIV = 0x05, | ||
| 766 | }; | ||
| 767 | |||
| 768 | /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ | ||
| 769 | struct dm_odm_t { | ||
| 770 | /* struct timer_list FastAntTrainingTimer; */ | ||
| 771 | /* */ | ||
| 772 | /* Add for different team use temporarily */ | ||
| 773 | /* */ | ||
| 774 | struct rtw_adapter *Adapter; /* For CE/NIC team */ | ||
| 775 | struct rtl8723a_priv *priv; /* For AP/ADSL team */ | ||
| 776 | /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ | ||
| 777 | bool odm_ready; | ||
| 778 | |||
| 779 | struct rtl8723a_priv fake_priv; | ||
| 780 | |||
| 781 | u64 DebugComponents; | ||
| 782 | u32 DebugLevel; | ||
| 783 | |||
| 784 | /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ | ||
| 785 | bool bCckHighPower; | ||
| 786 | u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ | ||
| 787 | u8 ControlChannel; | ||
| 788 | /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ | ||
| 789 | |||
| 790 | /* 1 COMMON INFORMATION */ | ||
| 791 | |||
| 792 | /* Init Value */ | ||
| 793 | /* HOOK BEFORE REG INIT----------- */ | ||
| 794 | /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */ | ||
| 795 | u32 SupportAbility; | ||
| 796 | /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ | ||
| 797 | u8 SupportInterface; | ||
| 798 | /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ | ||
| 799 | u32 SupportICType; | ||
| 800 | /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ | ||
| 801 | u8 CutVersion; | ||
| 802 | /* Fab Version TSMC/UMC = 0/1 */ | ||
| 803 | u8 FabVersion; | ||
| 804 | /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ | ||
| 805 | u8 RFType; | ||
| 806 | /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ | ||
| 807 | u8 BoardType; | ||
| 808 | /* with external LNA NO/Yes = 0/1 */ | ||
| 809 | u8 ExtLNA; | ||
| 810 | /* with external PA NO/Yes = 0/1 */ | ||
| 811 | u8 ExtPA; | ||
| 812 | /* with external TRSW NO/Yes = 0/1 */ | ||
| 813 | u8 ExtTRSW; | ||
| 814 | u8 PatchID; /* Customer ID */ | ||
| 815 | bool bInHctTest; | ||
| 816 | bool bWIFITest; | ||
| 817 | |||
| 818 | bool bDualMacSmartConcurrent; | ||
| 819 | u32 BK_SupportAbility; | ||
| 820 | u8 AntDivType; | ||
| 821 | /* HOOK BEFORE REG INIT----------- */ | ||
| 822 | |||
| 823 | /* */ | ||
| 824 | /* Dynamic Value */ | ||
| 825 | /* */ | ||
| 826 | /* POINTER REFERENCE----------- */ | ||
| 827 | |||
| 828 | u8 u8_temp; | ||
| 829 | bool bool_temp; | ||
| 830 | struct rtw_adapter *PADAPTER_temp; | ||
| 831 | |||
| 832 | /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ | ||
| 833 | u8 *pMacPhyMode; | ||
| 834 | /* TX Unicast byte count */ | ||
| 835 | u64 *pNumTxBytesUnicast; | ||
| 836 | /* RX Unicast byte count */ | ||
| 837 | u64 *pNumRxBytesUnicast; | ||
| 838 | /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ | ||
| 839 | u8 *pWirelessMode; /* enum odm_wireless_mode */ | ||
| 840 | /* Frequence band 2.4G/5G = 0/1 */ | ||
| 841 | u8 *pBandType; | ||
| 842 | /* Secondary channel offset don't_care/below/above = 0/1/2 */ | ||
| 843 | u8 *pSecChOffset; | ||
| 844 | /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ | ||
| 845 | u8 *pSecurity; | ||
| 846 | /* BW info 20M/40M/80M = 0/1/2 */ | ||
| 847 | u8 *pBandWidth; | ||
| 848 | /* Central channel location Ch1/Ch2/.... */ | ||
| 849 | u8 *pChannel; /* central channel number */ | ||
| 850 | /* Common info for 92D DMSP */ | ||
| 851 | |||
| 852 | bool *pbGetValueFromOtherMac; | ||
| 853 | struct rtw_adapter **pBuddyAdapter; | ||
| 854 | bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ | ||
| 855 | /* Common info for Status */ | ||
| 856 | bool *pbScanInProcess; | ||
| 857 | bool *pbPowerSaving; | ||
| 858 | /* CCA Path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path. */ | ||
| 859 | u8 *pOnePathCCA; | ||
| 860 | /* pMgntInfo->AntennaTest */ | ||
| 861 | u8 *pAntennaTest; | ||
| 862 | bool *pbNet_closed; | ||
| 863 | /* POINTER REFERENCE----------- */ | ||
| 864 | /* */ | ||
| 865 | /* CALL BY VALUE------------- */ | ||
| 866 | bool bWIFI_Direct; | ||
| 867 | bool bWIFI_Display; | ||
| 868 | bool bLinked; | ||
| 869 | u8 RSSI_Min; | ||
| 870 | u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ | ||
| 871 | bool bIsMPChip; | ||
| 872 | bool bOneEntryOnly; | ||
| 873 | /* Common info for BTDM */ | ||
| 874 | bool bBtDisabled; /* BT is disabled */ | ||
| 875 | bool bBtHsOperation; /* BT HS mode is under progress */ | ||
| 876 | u8 btHsDigVal; /* use BT rssi to decide the DIG value */ | ||
| 877 | bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ | ||
| 878 | bool bBtBusy; /* BT is busy. */ | ||
| 879 | /* CALL BY VALUE------------- */ | ||
| 880 | |||
| 881 | /* 2 Define STA info. */ | ||
| 882 | /* _ODM_STA_INFO */ | ||
| 883 | /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ | ||
| 884 | struct sta_info * pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; | ||
| 885 | |||
| 886 | /* */ | ||
| 887 | /* 2012/02/14 MH Add to share 88E ra with other SW team. */ | ||
| 888 | /* We need to colelct all support abilit to a proper area. */ | ||
| 889 | /* */ | ||
| 890 | bool RaSupport88E; | ||
| 891 | |||
| 892 | /* Define ........... */ | ||
| 893 | |||
| 894 | /* Latest packet phy info (ODM write) */ | ||
| 895 | struct odm_phy_dbg_info PhyDbgInfo; | ||
| 896 | /* PHY_INFO_88E PhyInfo; */ | ||
| 897 | |||
| 898 | /* Latest packet phy info (ODM write) */ | ||
| 899 | struct odm_mac_info *pMacInfo; | ||
| 900 | /* MAC_INFO_88E MacInfo; */ | ||
| 901 | |||
| 902 | /* Different Team independt structure?? */ | ||
| 903 | |||
| 904 | /* */ | ||
| 905 | /* TX_RTP_CMN TX_retrpo; */ | ||
| 906 | /* TX_RTP_88E TX_retrpo; */ | ||
| 907 | /* TX_RTP_8195 TX_retrpo; */ | ||
| 908 | |||
| 909 | /* */ | ||
| 910 | /* ODM Structure */ | ||
| 911 | /* */ | ||
| 912 | struct odm_fat_t DM_FatTable; | ||
| 913 | struct dig_t DM_DigTable; | ||
| 914 | struct dynamic_pwr_sav DM_PSTable; | ||
| 915 | struct pri_cca DM_PriCCA; | ||
| 916 | struct rx_hp DM_RXHP_Table; | ||
| 917 | struct false_alarm_stats FalseAlmCnt; | ||
| 918 | struct false_alarm_stats FlaseAlmCntBuddyAdapter; | ||
| 919 | struct sw_ant_sw DM_SWAT_Table; | ||
| 920 | bool RSSI_test; | ||
| 921 | |||
| 922 | struct edca_turbo DM_EDCA_Table; | ||
| 923 | u32 WMMEDCA_BE; | ||
| 924 | /* Copy from SD4 structure */ | ||
| 925 | /* */ | ||
| 926 | /* ================================================== */ | ||
| 927 | /* */ | ||
| 928 | |||
| 929 | /* common */ | ||
| 930 | bool *pbDriverStopped; | ||
| 931 | bool *pbDriverIsGoingToPnpSetPowerSleep; | ||
| 932 | bool *pinit_adpt_in_progress; | ||
| 933 | |||
| 934 | /* PSD */ | ||
| 935 | bool bUserAssignLevel; | ||
| 936 | struct timer_list PSDTimer; | ||
| 937 | u8 RSSI_BT; /* come from BT */ | ||
| 938 | bool bPSDinProcess; | ||
| 939 | bool bDMInitialGainEnable; | ||
| 940 | |||
| 941 | /* for rate adaptive, in fact, 88c/92c fw will handle this */ | ||
| 942 | u8 bUseRAMask; | ||
| 943 | |||
| 944 | struct odm_rate_adapt RateAdaptive; | ||
| 945 | |||
| 946 | |||
| 947 | struct odm_rf_cal_t RFCalibrateInfo; | ||
| 948 | |||
| 949 | /* */ | ||
| 950 | /* TX power tracking */ | ||
| 951 | /* */ | ||
| 952 | u8 BbSwingIdxOfdm; | ||
| 953 | u8 BbSwingIdxOfdmCurrent; | ||
| 954 | u8 BbSwingIdxOfdmBase; | ||
| 955 | bool BbSwingFlagOfdm; | ||
| 956 | u8 BbSwingIdxCck; | ||
| 957 | u8 BbSwingIdxCckCurrent; | ||
| 958 | u8 BbSwingIdxCckBase; | ||
| 959 | bool BbSwingFlagCck; | ||
| 960 | /* */ | ||
| 961 | /* ODM system resource. */ | ||
| 962 | /* */ | ||
| 963 | |||
| 964 | /* ODM relative time. */ | ||
| 965 | struct timer_list PathDivSwitchTimer; | ||
| 966 | /* 2011.09.27 add for Path Diversity */ | ||
| 967 | struct timer_list CCKPathDiversityTimer; | ||
| 968 | struct timer_list FastAntTrainingTimer; | ||
| 969 | |||
| 970 | /* ODM relative workitem. */ | ||
| 971 | }; /* DM_Dynamic_Mechanism_Structure */ | ||
| 972 | |||
| 973 | enum odm_rf_content { | ||
| 974 | odm_radioa_txt = 0x1000, | ||
| 975 | odm_radiob_txt = 0x1001, | ||
| 976 | odm_radioc_txt = 0x1002, | ||
| 977 | odm_radiod_txt = 0x1003 | ||
| 978 | }; | ||
| 979 | |||
| 980 | enum odm_bb_config_type { | ||
| 981 | CONFIG_BB_PHY_REG, | ||
| 982 | CONFIG_BB_AGC_TAB, | ||
| 983 | CONFIG_BB_AGC_TAB_2G, | ||
| 984 | CONFIG_BB_AGC_TAB_5G, | ||
| 985 | CONFIG_BB_PHY_REG_PG, | ||
| 986 | }; | ||
| 987 | |||
| 988 | /* Status code */ | ||
| 989 | enum rt_status { | ||
| 990 | RT_STATUS_SUCCESS, | ||
| 991 | RT_STATUS_FAILURE, | ||
| 992 | RT_STATUS_PENDING, | ||
| 993 | RT_STATUS_RESOURCE, | ||
| 994 | RT_STATUS_INVALID_CONTEXT, | ||
| 995 | RT_STATUS_INVALID_PARAMETER, | ||
| 996 | RT_STATUS_NOT_SUPPORT, | ||
| 997 | RT_STATUS_OS_API_FAILED, | ||
| 998 | }; | ||
| 999 | |||
| 1000 | /* include "odm_function.h" */ | ||
| 1001 | |||
| 1002 | /* 3=========================================================== */ | ||
| 1003 | /* 3 DIG */ | ||
| 1004 | /* 3=========================================================== */ | ||
| 1005 | |||
| 1006 | enum dm_dig_op { | ||
| 1007 | DIG_TYPE_THRESH_HIGH = 0, | ||
| 1008 | DIG_TYPE_THRESH_LOW = 1, | ||
| 1009 | DIG_TYPE_BACKOFF = 2, | ||
| 1010 | DIG_TYPE_RX_GAIN_MIN = 3, | ||
| 1011 | DIG_TYPE_RX_GAIN_MAX = 4, | ||
| 1012 | DIG_TYPE_ENABLE = 5, | ||
| 1013 | DIG_TYPE_DISABLE = 6, | ||
| 1014 | DIG_OP_TYPE_MAX | ||
| 1015 | }; | ||
| 1016 | |||
| 1017 | #define DM_DIG_THRESH_HIGH 40 | ||
| 1018 | #define DM_DIG_THRESH_LOW 35 | ||
| 1019 | |||
| 1020 | #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ | ||
| 1021 | |||
| 1022 | |||
| 1023 | #define DM_FALSEALARM_THRESH_LOW 400 | ||
| 1024 | #define DM_FALSEALARM_THRESH_HIGH 1000 | ||
| 1025 | |||
| 1026 | #define DM_DIG_MAX_NIC 0x4e | ||
| 1027 | #define DM_DIG_MIN_NIC 0x1e | ||
| 1028 | |||
| 1029 | #define DM_DIG_MAX_AP 0x32 | ||
| 1030 | #define DM_DIG_MIN_AP 0x20 | ||
| 1031 | |||
| 1032 | #define DM_DIG_MAX_NIC_HP 0x46 | ||
| 1033 | #define DM_DIG_MIN_NIC_HP 0x2e | ||
| 1034 | |||
| 1035 | #define DM_DIG_MAX_AP_HP 0x42 | ||
| 1036 | #define DM_DIG_MIN_AP_HP 0x30 | ||
| 1037 | |||
| 1038 | /* vivi 92c&92d has different definition, 20110504 */ | ||
| 1039 | /* this is for 92c */ | ||
| 1040 | #define DM_DIG_FA_TH0 0x200 | ||
| 1041 | #define DM_DIG_FA_TH1 0x300 | ||
| 1042 | #define DM_DIG_FA_TH2 0x400 | ||
| 1043 | /* this is for 92d */ | ||
| 1044 | #define DM_DIG_FA_TH0_92D 0x100 | ||
| 1045 | #define DM_DIG_FA_TH1_92D 0x400 | ||
| 1046 | #define DM_DIG_FA_TH2_92D 0x600 | ||
| 1047 | |||
| 1048 | #define DM_DIG_BACKOFF_MAX 12 | ||
| 1049 | #define DM_DIG_BACKOFF_MIN -4 | ||
| 1050 | #define DM_DIG_BACKOFF_DEFAULT 10 | ||
| 1051 | |||
| 1052 | /* 3=========================================================== */ | ||
| 1053 | /* 3 AGC RX High Power Mode */ | ||
| 1054 | /* 3=========================================================== */ | ||
| 1055 | #define LNA_Low_Gain_1 0x64 | ||
| 1056 | #define LNA_Low_Gain_2 0x5A | ||
| 1057 | #define LNA_Low_Gain_3 0x58 | ||
| 1058 | |||
| 1059 | #define FA_RXHP_TH1 5000 | ||
| 1060 | #define FA_RXHP_TH2 1500 | ||
| 1061 | #define FA_RXHP_TH3 800 | ||
| 1062 | #define FA_RXHP_TH4 600 | ||
| 1063 | #define FA_RXHP_TH5 500 | ||
| 1064 | |||
| 1065 | /* 3=========================================================== */ | ||
| 1066 | /* 3 EDCA */ | ||
| 1067 | /* 3=========================================================== */ | ||
| 1068 | |||
| 1069 | /* 3=========================================================== */ | ||
| 1070 | /* 3 Dynamic Tx Power */ | ||
| 1071 | /* 3=========================================================== */ | ||
| 1072 | /* Dynamic Tx Power Control Threshold */ | ||
| 1073 | #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 | ||
| 1074 | #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 | ||
| 1075 | #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F | ||
| 1076 | |||
| 1077 | #define TxHighPwrLevel_Normal 0 | ||
| 1078 | #define TxHighPwrLevel_Level1 1 | ||
| 1079 | #define TxHighPwrLevel_Level2 2 | ||
| 1080 | #define TxHighPwrLevel_BT1 3 | ||
| 1081 | #define TxHighPwrLevel_BT2 4 | ||
| 1082 | #define TxHighPwrLevel_15 5 | ||
| 1083 | #define TxHighPwrLevel_35 6 | ||
| 1084 | #define TxHighPwrLevel_50 7 | ||
| 1085 | #define TxHighPwrLevel_70 8 | ||
| 1086 | #define TxHighPwrLevel_100 9 | ||
| 1087 | |||
| 1088 | /* 3=========================================================== */ | ||
| 1089 | /* 3 Rate Adaptive */ | ||
| 1090 | /* 3=========================================================== */ | ||
| 1091 | #define DM_RATR_STA_INIT 0 | ||
| 1092 | #define DM_RATR_STA_HIGH 1 | ||
| 1093 | #define DM_RATR_STA_MIDDLE 2 | ||
| 1094 | #define DM_RATR_STA_LOW 3 | ||
| 1095 | |||
| 1096 | /* 3=========================================================== */ | ||
| 1097 | /* 3 BB Power Save */ | ||
| 1098 | /* 3=========================================================== */ | ||
| 1099 | |||
| 1100 | |||
| 1101 | enum dm_1r_cca { | ||
| 1102 | CCA_1R =0, | ||
| 1103 | CCA_2R = 1, | ||
| 1104 | CCA_MAX = 2, | ||
| 1105 | }; | ||
| 1106 | |||
| 1107 | enum dm_rf_def { | ||
| 1108 | RF_Save =0, | ||
| 1109 | RF_Normal = 1, | ||
| 1110 | RF_MAX = 2, | ||
| 1111 | }; | ||
| 1112 | |||
| 1113 | /* 3=========================================================== */ | ||
| 1114 | /* 3 Antenna Diversity */ | ||
| 1115 | /* 3=========================================================== */ | ||
| 1116 | enum dm_swas { | ||
| 1117 | Antenna_A = 1, | ||
| 1118 | Antenna_B = 2, | ||
| 1119 | Antenna_MAX = 3, | ||
| 1120 | }; | ||
| 1121 | |||
| 1122 | /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ | ||
| 1123 | #define MAX_ANTENNA_DETECTION_CNT 10 | ||
| 1124 | |||
| 1125 | /* */ | ||
| 1126 | /* Extern Global Variables. */ | ||
| 1127 | /* */ | ||
| 1128 | #define OFDM_TABLE_SIZE_92C 37 | ||
| 1129 | #define OFDM_TABLE_SIZE_92D 43 | ||
| 1130 | #define CCK_TABLE_SIZE 33 | ||
| 1131 | |||
| 1132 | extern u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D]; | ||
| 1133 | extern u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8]; | ||
| 1134 | extern u8 CCKSwingTable_Ch1423A [CCK_TABLE_SIZE][8]; | ||
| 1135 | |||
| 1136 | |||
| 1137 | |||
| 1138 | /* */ | ||
| 1139 | /* check Sta pointer valid or not */ | ||
| 1140 | /* */ | ||
| 1141 | #define IS_STA_VALID(pSta) (pSta) | ||
| 1142 | /* 20100514 Joseph: Add definition for antenna switching test after link. */ | ||
| 1143 | /* This indicates two different the steps. */ | ||
| 1144 | /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ | ||
| 1145 | /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ | ||
| 1146 | /* with original RSSI to determine if it is necessary to switch antenna. */ | ||
| 1147 | #define SWAW_STEP_PEAK 0 | ||
| 1148 | #define SWAW_STEP_DETERMINE 1 | ||
| 1149 | |||
| 1150 | void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8 CurrentIGI); | ||
| 1151 | void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres); | ||
| 1152 | |||
| 1153 | void ODM_SetAntenna(struct dm_odm_t *pDM_Odm, u8 Antenna); | ||
| 1154 | |||
| 1155 | |||
| 1156 | #define dm_RF_Saving ODM_RF_Saving23a | ||
| 1157 | void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal); | ||
| 1158 | |||
| 1159 | #define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink | ||
| 1160 | void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm); | ||
| 1161 | |||
| 1162 | #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck23a | ||
| 1163 | void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm); | ||
| 1164 | |||
| 1165 | bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate, | ||
| 1166 | u8 *pRATRState); | ||
| 1167 | |||
| 1168 | |||
| 1169 | #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi | ||
| 1170 | void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID, | ||
| 1171 | struct odm_phy_info *pPhyInfo); | ||
| 1172 | |||
| 1173 | u32 ConvertTo_dB23a(u32 Value); | ||
| 1174 | |||
| 1175 | u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd); | ||
| 1176 | |||
| 1177 | void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm); | ||
| 1178 | |||
| 1179 | u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level); | ||
| 1180 | |||
| 1181 | |||
| 1182 | void ODM23a_DMInit(struct dm_odm_t *pDM_Odm); | ||
| 1183 | |||
| 1184 | void ODM_DMWatchdog23a(struct dm_odm_t *pDM_Odm); /* For common use in the future */ | ||
| 1185 | |||
| 1186 | void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u32 Value); | ||
| 1187 | |||
| 1188 | void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, void *pValue); | ||
| 1189 | |||
| 1190 | void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u16 Index, void *pValue); | ||
| 1191 | |||
| 1192 | void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); | ||
| 1193 | |||
| 1194 | void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm); | ||
| 1195 | |||
| 1196 | void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm); | ||
| 1197 | |||
| 1198 | void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm); | ||
| 1199 | |||
| 1200 | void ODM_ResetIQKResult(struct dm_odm_t *pDM_Odm); | ||
| 1201 | |||
| 1202 | void ODM_AntselStatistics_88C(struct dm_odm_t *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate); | ||
| 1203 | |||
| 1204 | void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm); | ||
| 1205 | |||
| 1206 | bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode); | ||
| 1207 | |||
| 1208 | void odm_dtc(struct dm_odm_t *pDM_Odm); | ||
| 1209 | |||
| 1210 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/odm_HWConfig.h b/drivers/staging/rtl8723au/include/odm_HWConfig.h new file mode 100644 index 000000000000..057fdb012a47 --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_HWConfig.h | |||
| @@ -0,0 +1,174 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | |||
| 17 | #ifndef __HALHWOUTSRC_H__ | ||
| 18 | #define __HALHWOUTSRC_H__ | ||
| 19 | |||
| 20 | #include <Hal8723APhyCfg.h> | ||
| 21 | |||
| 22 | /* */ | ||
| 23 | /* Definition */ | ||
| 24 | /* */ | ||
| 25 | /* */ | ||
| 26 | /* */ | ||
| 27 | /* CCK Rates, TxHT = 0 */ | ||
| 28 | #define DESC92C_RATE1M 0x00 | ||
| 29 | #define DESC92C_RATE2M 0x01 | ||
| 30 | #define DESC92C_RATE5_5M 0x02 | ||
| 31 | #define DESC92C_RATE11M 0x03 | ||
| 32 | |||
| 33 | /* OFDM Rates, TxHT = 0 */ | ||
| 34 | #define DESC92C_RATE6M 0x04 | ||
| 35 | #define DESC92C_RATE9M 0x05 | ||
| 36 | #define DESC92C_RATE12M 0x06 | ||
| 37 | #define DESC92C_RATE18M 0x07 | ||
| 38 | #define DESC92C_RATE24M 0x08 | ||
| 39 | #define DESC92C_RATE36M 0x09 | ||
| 40 | #define DESC92C_RATE48M 0x0a | ||
| 41 | #define DESC92C_RATE54M 0x0b | ||
| 42 | |||
| 43 | /* MCS Rates, TxHT = 1 */ | ||
| 44 | #define DESC92C_RATEMCS0 0x0c | ||
| 45 | #define DESC92C_RATEMCS1 0x0d | ||
| 46 | #define DESC92C_RATEMCS2 0x0e | ||
| 47 | #define DESC92C_RATEMCS3 0x0f | ||
| 48 | #define DESC92C_RATEMCS4 0x10 | ||
| 49 | #define DESC92C_RATEMCS5 0x11 | ||
| 50 | #define DESC92C_RATEMCS6 0x12 | ||
| 51 | #define DESC92C_RATEMCS7 0x13 | ||
| 52 | #define DESC92C_RATEMCS8 0x14 | ||
| 53 | #define DESC92C_RATEMCS9 0x15 | ||
| 54 | #define DESC92C_RATEMCS10 0x16 | ||
| 55 | #define DESC92C_RATEMCS11 0x17 | ||
| 56 | #define DESC92C_RATEMCS12 0x18 | ||
| 57 | #define DESC92C_RATEMCS13 0x19 | ||
| 58 | #define DESC92C_RATEMCS14 0x1a | ||
| 59 | #define DESC92C_RATEMCS15 0x1b | ||
| 60 | #define DESC92C_RATEMCS15_SG 0x1c | ||
| 61 | #define DESC92C_RATEMCS32 0x20 | ||
| 62 | |||
| 63 | |||
| 64 | /* */ | ||
| 65 | /* structure and define */ | ||
| 66 | /* */ | ||
| 67 | |||
| 68 | struct phy_rx_agc_info { | ||
| 69 | #ifdef __LITTLE_ENDIAN | ||
| 70 | u8 gain:7,trsw:1; | ||
| 71 | #else | ||
| 72 | u8 trsw:1,gain:7; | ||
| 73 | #endif | ||
| 74 | }; | ||
| 75 | |||
| 76 | struct phy_status_rpt { | ||
| 77 | struct phy_rx_agc_info path_agc[2]; | ||
| 78 | u8 ch_corr[2]; | ||
| 79 | u8 cck_sig_qual_ofdm_pwdb_all; | ||
| 80 | u8 cck_agc_rpt_ofdm_cfosho_a; | ||
| 81 | u8 cck_rpt_b_ofdm_cfosho_b; | ||
| 82 | u8 rsvd_1;/* ch_corr_msb; */ | ||
| 83 | u8 noise_power_db_msb; | ||
| 84 | u8 path_cfotail[2]; | ||
| 85 | u8 pcts_mask[2]; | ||
| 86 | s8 stream_rxevm[2]; | ||
| 87 | u8 path_rxsnr[2]; | ||
| 88 | u8 noise_power_db_lsb; | ||
| 89 | u8 rsvd_2[3]; | ||
| 90 | u8 stream_csi[2]; | ||
| 91 | u8 stream_target_csi[2]; | ||
| 92 | s8 sig_evm; | ||
| 93 | u8 rsvd_3; | ||
| 94 | |||
| 95 | #ifdef __LITTLE_ENDIAN | ||
| 96 | u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ | ||
| 97 | u8 sgi_en:1; | ||
| 98 | u8 rxsc:2; | ||
| 99 | u8 idle_long:1; | ||
| 100 | u8 r_ant_train_en:1; | ||
| 101 | u8 ant_sel_b:1; | ||
| 102 | u8 ant_sel:1; | ||
| 103 | #else /* _BIG_ENDIAN_ */ | ||
| 104 | u8 ant_sel:1; | ||
| 105 | u8 ant_sel_b:1; | ||
| 106 | u8 r_ant_train_en:1; | ||
| 107 | u8 idle_long:1; | ||
| 108 | u8 rxsc:2; | ||
| 109 | u8 sgi_en:1; | ||
| 110 | u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ | ||
| 111 | #endif | ||
| 112 | }; | ||
| 113 | |||
| 114 | |||
| 115 | struct phy_status_rpt_8195 { | ||
| 116 | struct phy_rx_agc_info path_agc[2]; | ||
| 117 | u8 ch_num[2]; | ||
| 118 | u8 cck_sig_qual_ofdm_pwdb_all; | ||
| 119 | u8 cck_agc_rpt_ofdm_cfosho_a; | ||
| 120 | u8 cck_bb_pwr_ofdm_cfosho_b; | ||
| 121 | u8 cck_rx_path; /* CCK_RX_PATH [3:0] (with regA07[3:0] definition) */ | ||
| 122 | u8 rsvd_1; | ||
| 123 | u8 path_cfotail[2]; | ||
| 124 | u8 pcts_mask[2]; | ||
| 125 | s8 stream_rxevm[2]; | ||
| 126 | u8 path_rxsnr[2]; | ||
| 127 | u8 rsvd_2[2]; | ||
| 128 | u8 stream_snr[2]; | ||
| 129 | u8 stream_csi[2]; | ||
| 130 | u8 rsvd_3[2]; | ||
| 131 | s8 sig_evm; | ||
| 132 | u8 rsvd_4; | ||
| 133 | #ifdef __LITTLE_ENDIAN | ||
| 134 | u8 antidx_anta:3; | ||
| 135 | u8 antidx_antb:3; | ||
| 136 | u8 rsvd_5:2; | ||
| 137 | #else /* _BIG_ENDIAN_ */ | ||
| 138 | u8 rsvd_5:2; | ||
| 139 | u8 antidx_antb:3; | ||
| 140 | u8 antidx_anta:3; | ||
| 141 | #endif | ||
| 142 | }; | ||
| 143 | |||
| 144 | |||
| 145 | void odm_Init_RSSIForDM23a(struct dm_odm_t *pDM_Odm); | ||
| 146 | |||
| 147 | void | ||
| 148 | ODM_PhyStatusQuery23a( | ||
| 149 | struct dm_odm_t *pDM_Odm, | ||
| 150 | struct odm_phy_info *pPhyInfo, | ||
| 151 | u8 * pPhyStatus, | ||
| 152 | struct odm_packet_info *pPktinfo | ||
| 153 | ); | ||
| 154 | |||
| 155 | void ODM_MacStatusQuery23a(struct dm_odm_t *pDM_Odm, | ||
| 156 | u8 *pMacStatus, | ||
| 157 | u8 MacID, | ||
| 158 | bool bPacketMatchBSSID, | ||
| 159 | bool bPacketToSelf, | ||
| 160 | bool bPacketBeacon | ||
| 161 | ); | ||
| 162 | |||
| 163 | enum hal_status ODM_ConfigRFWithHeaderFile23a(struct dm_odm_t *pDM_Odm, | ||
| 164 | enum RF_RADIO_PATH Content, | ||
| 165 | enum RF_RADIO_PATH eRFPath | ||
| 166 | ); | ||
| 167 | |||
| 168 | enum hal_status ODM_ConfigBBWithHeaderFile23a(struct dm_odm_t *pDM_Odm, | ||
| 169 | enum odm_bb_config_type ConfigType | ||
| 170 | ); | ||
| 171 | |||
| 172 | enum hal_status ODM_ConfigMACWithHeaderFile23a(struct dm_odm_t *pDM_Odm); | ||
| 173 | |||
| 174 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/odm_RegConfig8723A.h b/drivers/staging/rtl8723au/include/odm_RegConfig8723A.h new file mode 100644 index 000000000000..4ea579b2e8bd --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_RegConfig8723A.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __INC_ODM_REGCONFIG_H_8723A | ||
| 16 | #define __INC_ODM_REGCONFIG_H_8723A | ||
| 17 | |||
| 18 | void odm_ConfigRFReg_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Data, | ||
| 19 | enum RF_RADIO_PATH RF_PATH, u32 RegAddr); | ||
| 20 | |||
| 21 | void odm_ConfigRF_RadioA_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Data); | ||
| 22 | |||
| 23 | void odm_ConfigRF_RadioB_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Data); | ||
| 24 | |||
| 25 | void odm_ConfigMAC_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u8 Data); | ||
| 26 | |||
| 27 | void odm_ConfigBB_AGC_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, | ||
| 28 | u32 Bitmask, u32 Data); | ||
| 29 | |||
| 30 | void odm_ConfigBB_PHY_REG_PG_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data); | ||
| 31 | |||
| 32 | void odm_ConfigBB_PHY_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data); | ||
| 33 | |||
| 34 | #endif /* end of SUPPORT */ | ||
diff --git a/drivers/staging/rtl8723au/include/odm_RegDefine11AC.h b/drivers/staging/rtl8723au/include/odm_RegDefine11AC.h new file mode 100644 index 000000000000..77b7acec5ea8 --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_RegDefine11AC.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef __ODM_REGDEFINE11AC_H__ | ||
| 17 | #define __ODM_REGDEFINE11AC_H__ | ||
| 18 | |||
| 19 | /* 2 RF REG LIST */ | ||
| 20 | |||
| 21 | |||
| 22 | |||
| 23 | /* 2 BB REG LIST */ | ||
| 24 | /* PAGE 8 */ | ||
| 25 | /* PAGE 9 */ | ||
| 26 | #define ODM_REG_OFDM_FA_RST_11AC 0x9A4 | ||
| 27 | /* PAGE A */ | ||
| 28 | #define ODM_REG_CCK_CCA_11AC 0xA0A | ||
| 29 | #define ODM_REG_CCK_FA_RST_11AC 0xA2C | ||
| 30 | #define ODM_REG_CCK_FA_11AC 0xA5C | ||
| 31 | /* PAGE C */ | ||
| 32 | #define ODM_REG_IGI_A_11AC 0xC50 | ||
| 33 | /* PAGE E */ | ||
| 34 | #define ODM_REG_IGI_B_11AC 0xE50 | ||
| 35 | /* PAGE F */ | ||
| 36 | #define ODM_REG_OFDM_FA_11AC 0xF48 | ||
| 37 | |||
| 38 | |||
| 39 | /* 2 MAC REG LIST */ | ||
| 40 | |||
| 41 | |||
| 42 | |||
| 43 | |||
| 44 | /* DIG Related */ | ||
| 45 | #define ODM_BIT_IGI_11AC 0xFFFFFFFF | ||
| 46 | |||
| 47 | |||
| 48 | |||
| 49 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/odm_RegDefine11N.h b/drivers/staging/rtl8723au/include/odm_RegDefine11N.h new file mode 100644 index 000000000000..27782154f502 --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_RegDefine11N.h | |||
| @@ -0,0 +1,165 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef __ODM_REGDEFINE11N_H__ | ||
| 17 | #define __ODM_REGDEFINE11N_H__ | ||
| 18 | |||
| 19 | |||
| 20 | /* 2 RF REG LIST */ | ||
| 21 | #define ODM_REG_RF_MODE_11N 0x00 | ||
| 22 | #define ODM_REG_RF_0B_11N 0x0B | ||
| 23 | #define ODM_REG_CHNBW_11N 0x18 | ||
| 24 | #define ODM_REG_T_METER_11N 0x24 | ||
| 25 | #define ODM_REG_RF_25_11N 0x25 | ||
| 26 | #define ODM_REG_RF_26_11N 0x26 | ||
| 27 | #define ODM_REG_RF_27_11N 0x27 | ||
| 28 | #define ODM_REG_RF_2B_11N 0x2B | ||
| 29 | #define ODM_REG_RF_2C_11N 0x2C | ||
| 30 | #define ODM_REG_RXRF_A3_11N 0x3C | ||
| 31 | #define ODM_REG_T_METER_92D_11N 0x42 | ||
| 32 | #define ODM_REG_T_METER_88E_11N 0x42 | ||
| 33 | |||
| 34 | |||
| 35 | |||
| 36 | /* 2 BB REG LIST */ | ||
| 37 | /* PAGE 8 */ | ||
| 38 | #define ODM_REG_BB_CTRL_11N 0x800 | ||
| 39 | #define ODM_REG_RF_PIN_11N 0x804 | ||
| 40 | #define ODM_REG_PSD_CTRL_11N 0x808 | ||
| 41 | #define ODM_REG_TX_ANT_CTRL_11N 0x80C | ||
| 42 | #define ODM_REG_BB_PWR_SAV5_11N 0x818 | ||
| 43 | #define ODM_REG_CCK_RPT_FORMAT_11N 0x824 | ||
| 44 | #define ODM_REG_RX_DEFUALT_A_11N 0x858 | ||
| 45 | #define ODM_REG_RX_DEFUALT_B_11N 0x85A | ||
| 46 | #define ODM_REG_BB_PWR_SAV3_11N 0x85C | ||
| 47 | #define ODM_REG_ANTSEL_CTRL_11N 0x860 | ||
| 48 | #define ODM_REG_RX_ANT_CTRL_11N 0x864 | ||
| 49 | #define ODM_REG_PIN_CTRL_11N 0x870 | ||
| 50 | #define ODM_REG_BB_PWR_SAV1_11N 0x874 | ||
| 51 | #define ODM_REG_ANTSEL_PATH_11N 0x878 | ||
| 52 | #define ODM_REG_BB_3WIRE_11N 0x88C | ||
| 53 | #define ODM_REG_SC_CNT_11N 0x8C4 | ||
| 54 | #define ODM_REG_PSD_DATA_11N 0x8B4 | ||
| 55 | /* PAGE 9 */ | ||
| 56 | #define ODM_REG_ANT_MAPPING1_11N 0x914 | ||
| 57 | #define ODM_REG_ANT_MAPPING2_11N 0x918 | ||
| 58 | /* PAGE A */ | ||
| 59 | #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 | ||
| 60 | #define ODM_REG_CCK_CCA_11N 0xA0A | ||
| 61 | #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C | ||
| 62 | #define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 | ||
| 63 | #define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 | ||
| 64 | #define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 | ||
| 65 | #define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 | ||
| 66 | #define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 | ||
| 67 | #define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 | ||
| 68 | #define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 | ||
| 69 | #define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 | ||
| 70 | #define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 | ||
| 71 | #define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 | ||
| 72 | #define ODM_REG_CCK_FA_RST_11N 0xA2C | ||
| 73 | #define ODM_REG_CCK_FA_MSB_11N 0xA58 | ||
| 74 | #define ODM_REG_CCK_FA_LSB_11N 0xA5C | ||
| 75 | #define ODM_REG_CCK_CCA_CNT_11N 0xA60 | ||
| 76 | #define ODM_REG_BB_PWR_SAV4_11N 0xA74 | ||
| 77 | /* PAGE B */ | ||
| 78 | #define ODM_REG_LNA_SWITCH_11N 0xB2C | ||
| 79 | #define ODM_REG_PATH_SWITCH_11N 0xB30 | ||
| 80 | #define ODM_REG_RSSI_CTRL_11N 0xB38 | ||
| 81 | #define ODM_REG_CONFIG_ANTA_11N 0xB68 | ||
| 82 | #define ODM_REG_RSSI_BT_11N 0xB9C | ||
| 83 | /* PAGE C */ | ||
| 84 | #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 | ||
| 85 | #define ODM_REG_RX_PATH_11N 0xC04 | ||
| 86 | #define ODM_REG_TRMUX_11N 0xC08 | ||
| 87 | #define ODM_REG_OFDM_FA_RSTC_11N 0xC0C | ||
| 88 | #define ODM_REG_RXIQI_MATRIX_11N 0xC14 | ||
| 89 | #define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C | ||
| 90 | #define ODM_REG_IGI_A_11N 0xC50 | ||
| 91 | #define ODM_REG_ANTDIV_PARA2_11N 0xC54 | ||
| 92 | #define ODM_REG_IGI_B_11N 0xC58 | ||
| 93 | #define ODM_REG_ANTDIV_PARA3_11N 0xC5C | ||
| 94 | #define ODM_REG_BB_PWR_SAV2_11N 0xC70 | ||
| 95 | #define ODM_REG_RX_OFF_11N 0xC7C | ||
| 96 | #define ODM_REG_TXIQK_MATRIXA_11N 0xC80 | ||
| 97 | #define ODM_REG_TXIQK_MATRIXB_11N 0xC88 | ||
| 98 | #define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 | ||
| 99 | #define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C | ||
| 100 | #define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 | ||
| 101 | #define ODM_REG_ANTDIV_PARA1_11N 0xCA4 | ||
| 102 | #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 | ||
| 103 | /* PAGE D */ | ||
| 104 | #define ODM_REG_OFDM_FA_RSTD_11N 0xD00 | ||
| 105 | #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 | ||
| 106 | #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 | ||
| 107 | #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 | ||
| 108 | /* PAGE E */ | ||
| 109 | #define ODM_REG_TXAGC_A_6_18_11N 0xE00 | ||
| 110 | #define ODM_REG_TXAGC_A_24_54_11N 0xE04 | ||
| 111 | #define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 | ||
| 112 | #define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 | ||
| 113 | #define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 | ||
| 114 | #define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 | ||
| 115 | #define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C | ||
| 116 | #define ODM_REG_FPGA0_IQK_11N 0xE28 | ||
| 117 | #define ODM_REG_TXIQK_TONE_A_11N 0xE30 | ||
| 118 | #define ODM_REG_RXIQK_TONE_A_11N 0xE34 | ||
| 119 | #define ODM_REG_TXIQK_PI_A_11N 0xE38 | ||
| 120 | #define ODM_REG_RXIQK_PI_A_11N 0xE3C | ||
| 121 | #define ODM_REG_TXIQK_11N 0xE40 | ||
| 122 | #define ODM_REG_RXIQK_11N 0xE44 | ||
| 123 | #define ODM_REG_IQK_AGC_PTS_11N 0xE48 | ||
| 124 | #define ODM_REG_IQK_AGC_RSP_11N 0xE4C | ||
| 125 | #define ODM_REG_BLUETOOTH_11N 0xE6C | ||
| 126 | #define ODM_REG_RX_WAIT_CCA_11N 0xE70 | ||
| 127 | #define ODM_REG_TX_CCK_RFON_11N 0xE74 | ||
| 128 | #define ODM_REG_TX_CCK_BBON_11N 0xE78 | ||
| 129 | #define ODM_REG_OFDM_RFON_11N 0xE7C | ||
| 130 | #define ODM_REG_OFDM_BBON_11N 0xE80 | ||
| 131 | #define ODM_REG_TX2RX_11N 0xE84 | ||
| 132 | #define ODM_REG_TX2TX_11N 0xE88 | ||
| 133 | #define ODM_REG_RX_CCK_11N 0xE8C | ||
| 134 | #define ODM_REG_RX_OFDM_11N 0xED0 | ||
| 135 | #define ODM_REG_RX_WAIT_RIFS_11N 0xED4 | ||
| 136 | #define ODM_REG_RX2RX_11N 0xED8 | ||
| 137 | #define ODM_REG_STANDBY_11N 0xEDC | ||
| 138 | #define ODM_REG_SLEEP_11N 0xEE0 | ||
| 139 | #define ODM_REG_PMPD_ANAEN_11N 0xEEC | ||
| 140 | |||
| 141 | |||
| 142 | |||
| 143 | |||
| 144 | |||
| 145 | |||
| 146 | |||
| 147 | /* 2 MAC REG LIST */ | ||
| 148 | #define ODM_REG_BB_RST_11N 0x02 | ||
| 149 | #define ODM_REG_ANTSEL_PIN_11N 0x4C | ||
| 150 | #define ODM_REG_EARLY_MODE_11N 0x4D0 | ||
| 151 | #define ODM_REG_RSSI_MONITOR_11N 0x4FE | ||
| 152 | #define ODM_REG_EDCA_VO_11N 0x500 | ||
| 153 | #define ODM_REG_EDCA_VI_11N 0x504 | ||
| 154 | #define ODM_REG_EDCA_BE_11N 0x508 | ||
| 155 | #define ODM_REG_EDCA_BK_11N 0x50C | ||
| 156 | #define ODM_REG_TXPAUSE_11N 0x522 | ||
| 157 | #define ODM_REG_RESP_TX_11N 0x6D8 | ||
| 158 | #define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 | ||
| 159 | #define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 | ||
| 160 | |||
| 161 | |||
| 162 | /* DIG Related */ | ||
| 163 | #define ODM_BIT_IGI_11N 0x0000007F | ||
| 164 | |||
| 165 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/odm_debug.h b/drivers/staging/rtl8723au/include/odm_debug.h new file mode 100644 index 000000000000..5bc51d09e52f --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_debug.h | |||
| @@ -0,0 +1,139 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | |||
| 17 | #ifndef __ODM_DBG_H__ | ||
| 18 | #define __ODM_DBG_H__ | ||
| 19 | |||
| 20 | |||
| 21 | /* */ | ||
| 22 | /* Define the debug levels */ | ||
| 23 | /* */ | ||
| 24 | /* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */ | ||
| 25 | /* So that, they can help SW engineer to develope or trace states changed */ | ||
| 26 | /* and also help HW enginner to trace every operation to and from HW, */ | ||
| 27 | /* e.g IO, Tx, Rx. */ | ||
| 28 | /* */ | ||
| 29 | /* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */ | ||
| 30 | /* which help us to debug SW or HW. */ | ||
| 31 | /* */ | ||
| 32 | /* */ | ||
| 33 | /* */ | ||
| 34 | /* Never used in a call to ODM_RT_TRACE()! */ | ||
| 35 | /* */ | ||
| 36 | #define ODM_DBG_OFF 1 | ||
| 37 | |||
| 38 | /* */ | ||
| 39 | /* Fatal bug. */ | ||
| 40 | /* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */ | ||
| 41 | /* resource allocation failed, unexpected HW behavior, HW BUG and so on. */ | ||
| 42 | /* */ | ||
| 43 | #define ODM_DBG_SERIOUS 2 | ||
| 44 | |||
| 45 | /* */ | ||
| 46 | /* Abnormal, rare, or unexpeted cases. */ | ||
| 47 | /* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. */ | ||
| 48 | /* */ | ||
| 49 | #define ODM_DBG_WARNING 3 | ||
| 50 | |||
| 51 | /* */ | ||
| 52 | /* Normal case with useful information about current SW or HW state. */ | ||
| 53 | /* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, */ | ||
| 54 | /* SW protocol state change, dynamic mechanism state change and so on. */ | ||
| 55 | /* */ | ||
| 56 | #define ODM_DBG_LOUD 4 | ||
| 57 | |||
| 58 | /* */ | ||
| 59 | /* Normal case with detail execution flow or information. */ | ||
| 60 | /* */ | ||
| 61 | #define ODM_DBG_TRACE 5 | ||
| 62 | |||
| 63 | /* */ | ||
| 64 | /* Define the tracing components */ | ||
| 65 | /* */ | ||
| 66 | /* */ | ||
| 67 | /* BB Functions */ | ||
| 68 | #define ODM_COMP_DIG BIT0 | ||
| 69 | #define ODM_COMP_RA_MASK BIT1 | ||
| 70 | #define ODM_COMP_DYNAMIC_TXPWR BIT2 | ||
| 71 | #define ODM_COMP_FA_CNT BIT3 | ||
| 72 | #define ODM_COMP_RSSI_MONITOR BIT4 | ||
| 73 | #define ODM_COMP_CCK_PD BIT5 | ||
| 74 | #define ODM_COMP_ANT_DIV BIT6 | ||
| 75 | #define ODM_COMP_PWR_SAVE BIT7 | ||
| 76 | #define ODM_COMP_PWR_TRAIN BIT8 | ||
| 77 | #define ODM_COMP_RATE_ADAPTIVE BIT9 | ||
| 78 | #define ODM_COMP_PATH_DIV BIT10 | ||
| 79 | #define ODM_COMP_PSD BIT11 | ||
| 80 | #define ODM_COMP_DYNAMIC_PRICCA BIT12 | ||
| 81 | #define ODM_COMP_RXHP BIT13 | ||
| 82 | /* MAC Functions */ | ||
| 83 | #define ODM_COMP_EDCA_TURBO BIT16 | ||
| 84 | #define ODM_COMP_EARLY_MODE BIT17 | ||
| 85 | /* RF Functions */ | ||
| 86 | #define ODM_COMP_TX_PWR_TRACK BIT24 | ||
| 87 | #define ODM_COMP_RX_GAIN_TRACK BIT25 | ||
| 88 | #define ODM_COMP_CALIBRATION BIT26 | ||
| 89 | /* Common Functions */ | ||
| 90 | #define ODM_COMP_COMMON BIT30 | ||
| 91 | #define ODM_COMP_INIT BIT31 | ||
| 92 | |||
| 93 | /*------------------------Export Macro Definition---------------------------*/ | ||
| 94 | #define DbgPrint printk | ||
| 95 | #define RT_PRINTK(fmt, args...) DbgPrint("%s(): " fmt, __func__, ## args); | ||
| 96 | |||
| 97 | #ifndef ASSERT | ||
| 98 | #define ASSERT(expr) | ||
| 99 | #endif | ||
| 100 | |||
| 101 | #define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ | ||
| 102 | if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ | ||
| 103 | { \ | ||
| 104 | DbgPrint("[ODM-8723A] "); \ | ||
| 105 | RT_PRINTK fmt; \ | ||
| 106 | } | ||
| 107 | |||
| 108 | #define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ | ||
| 109 | if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ | ||
| 110 | { \ | ||
| 111 | RT_PRINTK fmt; \ | ||
| 112 | } | ||
| 113 | |||
| 114 | #define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ | ||
| 115 | if(!(expr)) { \ | ||
| 116 | DbgPrint("Assertion failed! %s at ......\n", #expr); \ | ||
| 117 | DbgPrint(" ......%s,%s,line=%d\n", __FILE__, __func__, __LINE__);\ | ||
| 118 | RT_PRINTK fmt; \ | ||
| 119 | ASSERT(false); \ | ||
| 120 | } | ||
| 121 | #define ODM_dbg_enter() { DbgPrint("==> %s\n", __func__); } | ||
| 122 | #define ODM_dbg_exit() { DbgPrint("<== %s\n", __func__); } | ||
| 123 | #define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __func__, str); } | ||
| 124 | |||
| 125 | #define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ | ||
| 126 | if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel){ \ | ||
| 127 | int __i; \ | ||
| 128 | u8 * __ptr = (u8 *)ptr; \ | ||
| 129 | DbgPrint("[ODM] "); \ | ||
| 130 | DbgPrint(title_str); \ | ||
| 131 | DbgPrint(" "); \ | ||
| 132 | for (__i=0; __i < 6; __i++) \ | ||
| 133 | DbgPrint("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \ | ||
| 134 | DbgPrint("\n"); \ | ||
| 135 | } | ||
| 136 | |||
| 137 | void ODM_InitDebugSetting23a(struct dm_odm_t *pDM_Odm); | ||
| 138 | |||
| 139 | #endif /* __ODM_DBG_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/odm_interface.h b/drivers/staging/rtl8723au/include/odm_interface.h new file mode 100644 index 000000000000..f216b5846f92 --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_interface.h | |||
| @@ -0,0 +1,131 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | |||
| 17 | #ifndef __ODM_INTERFACE_H__ | ||
| 18 | #define __ODM_INTERFACE_H__ | ||
| 19 | |||
| 20 | |||
| 21 | |||
| 22 | /* */ | ||
| 23 | /* =========== Constant/Structure/Enum/... Define */ | ||
| 24 | /* */ | ||
| 25 | |||
| 26 | |||
| 27 | |||
| 28 | /* */ | ||
| 29 | /* =========== Macro Define */ | ||
| 30 | /* */ | ||
| 31 | |||
| 32 | #define _reg_all(_name) ODM_##_name | ||
| 33 | #define _reg_ic(_name, _ic) ODM_##_name##_ic | ||
| 34 | #define _bit_all(_name) BIT_##_name | ||
| 35 | #define _bit_ic(_name, _ic) BIT_##_name##_ic | ||
| 36 | |||
| 37 | /* _cat: implemented by Token-Pasting Operator. */ | ||
| 38 | |||
| 39 | /*=================================== | ||
| 40 | |||
| 41 | #define ODM_REG_DIG_11N 0xC50 | ||
| 42 | #define ODM_REG_DIG_11AC 0xDDD | ||
| 43 | |||
| 44 | ODM_REG(DIG,_pDM_Odm) | ||
| 45 | =====================================*/ | ||
| 46 | |||
| 47 | #define _reg_11N(_name) ODM_REG_##_name##_11N | ||
| 48 | #define _reg_11AC(_name) ODM_REG_##_name##_11AC | ||
| 49 | #define _bit_11N(_name) ODM_BIT_##_name##_11N | ||
| 50 | #define _bit_11AC(_name) ODM_BIT_##_name##_11AC | ||
| 51 | |||
| 52 | #define _cat(_name, _ic_type, _func) \ | ||
| 53 | ( \ | ||
| 54 | ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ | ||
| 55 | _func##_11AC(_name) \ | ||
| 56 | ) | ||
| 57 | |||
| 58 | /* _name: name of register or bit. */ | ||
| 59 | /* Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" */ | ||
| 60 | /* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. */ | ||
| 61 | #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) | ||
| 62 | #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) | ||
| 63 | |||
| 64 | /* */ | ||
| 65 | /* 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. */ | ||
| 66 | /* Suggest HW team to use thread instead of workitem. Windows also support the feature. */ | ||
| 67 | /* */ | ||
| 68 | typedef void (*RT_WORKITEM_CALL_BACK)(struct work_struct *pContext); | ||
| 69 | |||
| 70 | /* */ | ||
| 71 | /* =========== Extern Variable ??? It should be forbidden. */ | ||
| 72 | /* */ | ||
| 73 | |||
| 74 | |||
| 75 | /* */ | ||
| 76 | /* =========== EXtern Function Prototype */ | ||
| 77 | /* */ | ||
| 78 | |||
| 79 | |||
| 80 | u8 ODM_Read1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr); | ||
| 81 | |||
| 82 | u16 ODM_Read2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr); | ||
| 83 | |||
| 84 | u32 ODM_Read4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr); | ||
| 85 | |||
| 86 | void ODM_Write1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u8 Data); | ||
| 87 | |||
| 88 | void ODM_Write2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u16 Data); | ||
| 89 | |||
| 90 | void ODM_Write4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 Data); | ||
| 91 | |||
| 92 | void ODM_SetMACReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data); | ||
| 93 | |||
| 94 | u32 ODM_GetMACReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask); | ||
| 95 | |||
| 96 | void ODM_SetBBReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data); | ||
| 97 | |||
| 98 | u32 ODM_GetBBReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask); | ||
| 99 | |||
| 100 | void ODM_SetRFReg(struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath, | ||
| 101 | u32 RegAddr, u32 BitMask, u32 Data); | ||
| 102 | |||
| 103 | u32 ODM_GetRFReg(struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath, | ||
| 104 | u32 RegAddr, u32 BitMask); | ||
| 105 | |||
| 106 | /* Memory Relative Function. */ | ||
| 107 | void ODM_AllocateMemory(struct dm_odm_t *pDM_Odm, void **pPtr, u32 length); | ||
| 108 | void ODM_FreeMemory(struct dm_odm_t *pDM_Odm, void *pPtr, u32 length); | ||
| 109 | |||
| 110 | s32 ODM_CompareMemory(struct dm_odm_t *pDM_Odm, void *pBuf1, void *pBuf2, u32 length); | ||
| 111 | |||
| 112 | /* ODM MISC-spin lock relative API. */ | ||
| 113 | void ODM_AcquireSpinLock(struct dm_odm_t *pDM_Odm, enum rt_spinlock_type type); | ||
| 114 | |||
| 115 | void ODM_ReleaseSpinLock(struct dm_odm_t *pDM_Odm, enum rt_spinlock_type type); | ||
| 116 | |||
| 117 | /* ODM MISC-workitem relative API. */ | ||
| 118 | void ODM_InitializeWorkItem(struct dm_odm_t *pDM_Odm, void *pRtWorkItem, | ||
| 119 | RT_WORKITEM_CALL_BACK RtWorkItemCallback, void *pContext, const char *szID); | ||
| 120 | |||
| 121 | /* ODM Timer relative API. */ | ||
| 122 | void ODM_SetTimer(struct dm_odm_t *pDM_Odm, struct timer_list *pTimer, u32 msDelay); | ||
| 123 | |||
| 124 | void ODM_ReleaseTimer(struct dm_odm_t *pDM_Odm, struct timer_list *pTimer); | ||
| 125 | |||
| 126 | /* ODM FW relative API. */ | ||
| 127 | u32 ODM_FillH2CCmd(u8 *pH2CBuffer, u32 H2CBufferLen, u32 CmdNum, | ||
| 128 | u32 *pElementID, u32 *pCmdLen, u8 **pCmbBuffer, | ||
| 129 | u8 *CmdStartSeq); | ||
| 130 | |||
| 131 | #endif /* __ODM_INTERFACE_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/odm_precomp.h b/drivers/staging/rtl8723au/include/odm_precomp.h new file mode 100644 index 000000000000..f3fc2fad9884 --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_precomp.h | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef __ODM_PRECOMP_H__ | ||
| 17 | #define __ODM_PRECOMP_H__ | ||
| 18 | |||
| 19 | #include "odm_types.h" | ||
| 20 | |||
| 21 | #define TEST_FALG___ 1 | ||
| 22 | |||
| 23 | /* 2 Config Flags and Structs - defined by each ODM Type */ | ||
| 24 | |||
| 25 | #include <osdep_service.h> | ||
| 26 | #include <drv_types.h> | ||
| 27 | #include <hal_intf.h> | ||
| 28 | |||
| 29 | |||
| 30 | /* 2 Hardware Parameter Files */ | ||
| 31 | #include "Hal8723UHWImg_CE.h" | ||
| 32 | |||
| 33 | |||
| 34 | /* 2 OutSrc Header Files */ | ||
| 35 | |||
| 36 | #include "odm.h" | ||
| 37 | #include "odm_HWConfig.h" | ||
| 38 | #include "odm_debug.h" | ||
| 39 | #include "odm_RegDefine11AC.h" | ||
| 40 | #include "odm_RegDefine11N.h" | ||
| 41 | |||
| 42 | #include "HalDMOutSrc8723A.h" /* for IQK,LCK,Power-tracking */ | ||
| 43 | #include "rtl8723a_hal.h" | ||
| 44 | |||
| 45 | #include "odm_interface.h" | ||
| 46 | #include "odm_reg.h" | ||
| 47 | |||
| 48 | #include "HalHWImg8723A_MAC.h" | ||
| 49 | #include "HalHWImg8723A_RF.h" | ||
| 50 | #include "HalHWImg8723A_BB.h" | ||
| 51 | #include "HalHWImg8723A_FW.h" | ||
| 52 | #include "odm_RegConfig8723A.h" | ||
| 53 | |||
| 54 | #endif /* __ODM_PRECOMP_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/odm_reg.h b/drivers/staging/rtl8723au/include/odm_reg.h new file mode 100644 index 000000000000..56191e9fdcdb --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_reg.h | |||
| @@ -0,0 +1,114 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | /* */ | ||
| 16 | /* File Name: odm_reg.h */ | ||
| 17 | /* */ | ||
| 18 | /* Description: */ | ||
| 19 | /* */ | ||
| 20 | /* This file is for general register definition. */ | ||
| 21 | /* */ | ||
| 22 | /* */ | ||
| 23 | /* */ | ||
| 24 | #ifndef __HAL_ODM_REG_H__ | ||
| 25 | #define __HAL_ODM_REG_H__ | ||
| 26 | |||
| 27 | /* */ | ||
| 28 | /* Register Definition */ | ||
| 29 | /* */ | ||
| 30 | |||
| 31 | /* MAC REG */ | ||
| 32 | #define ODM_BB_RESET 0x002 | ||
| 33 | #define ODM_DUMMY 0x4fe | ||
| 34 | #define ODM_EDCA_VO_PARAM 0x500 | ||
| 35 | #define ODM_EDCA_VI_PARAM 0x504 | ||
| 36 | #define ODM_EDCA_BE_PARAM 0x508 | ||
| 37 | #define ODM_EDCA_BK_PARAM 0x50C | ||
| 38 | #define ODM_TXPAUSE 0x522 | ||
| 39 | |||
| 40 | /* BB REG */ | ||
| 41 | #define ODM_FPGA_PHY0_PAGE8 0x800 | ||
| 42 | #define ODM_PSD_SETTING 0x808 | ||
| 43 | #define ODM_AFE_SETTING 0x818 | ||
| 44 | #define ODM_TXAGC_B_6_18 0x830 | ||
| 45 | #define ODM_TXAGC_B_24_54 0x834 | ||
| 46 | #define ODM_TXAGC_B_MCS32_5 0x838 | ||
| 47 | #define ODM_TXAGC_B_MCS0_MCS3 0x83c | ||
| 48 | #define ODM_TXAGC_B_MCS4_MCS7 0x848 | ||
| 49 | #define ODM_TXAGC_B_MCS8_MCS11 0x84c | ||
| 50 | #define ODM_ANALOG_REGISTER 0x85c | ||
| 51 | #define ODM_RF_INTERFACE_OUTPUT 0x860 | ||
| 52 | #define ODM_TXAGC_B_MCS12_MCS15 0x868 | ||
| 53 | #define ODM_TXAGC_B_11_A_2_11 0x86c | ||
| 54 | #define ODM_AD_DA_LSB_MASK 0x874 | ||
| 55 | #define ODM_ENABLE_3_WIRE 0x88c | ||
| 56 | #define ODM_PSD_REPORT 0x8b4 | ||
| 57 | #define ODM_R_ANT_SELECT 0x90c | ||
| 58 | #define ODM_CCK_ANT_SELECT 0xa07 | ||
| 59 | #define ODM_CCK_PD_THRESH 0xa0a | ||
| 60 | #define ODM_CCK_RF_REG1 0xa11 | ||
| 61 | #define ODM_CCK_MATCH_FILTER 0xa20 | ||
| 62 | #define ODM_CCK_RAKE_MAC 0xa2e | ||
| 63 | #define ODM_CCK_CNT_RESET 0xa2d | ||
| 64 | #define ODM_CCK_TX_DIVERSITY 0xa2f | ||
| 65 | #define ODM_CCK_FA_CNT_MSB 0xa5b | ||
| 66 | #define ODM_CCK_FA_CNT_LSB 0xa5c | ||
| 67 | #define ODM_CCK_NEW_FUNCTION 0xa75 | ||
| 68 | #define ODM_OFDM_PHY0_PAGE_C 0xc00 | ||
| 69 | #define ODM_OFDM_RX_ANT 0xc04 | ||
| 70 | #define ODM_R_A_RXIQI 0xc14 | ||
| 71 | #define ODM_R_A_AGC_CORE1 0xc50 | ||
| 72 | #define ODM_R_A_AGC_CORE2 0xc54 | ||
| 73 | #define ODM_R_B_AGC_CORE1 0xc58 | ||
| 74 | #define ODM_R_AGC_PAR 0xc70 | ||
| 75 | #define ODM_R_HTSTF_AGC_PAR 0xc7c | ||
| 76 | #define ODM_TX_PWR_TRAINING_A 0xc90 | ||
| 77 | #define ODM_TX_PWR_TRAINING_B 0xc98 | ||
| 78 | #define ODM_OFDM_FA_CNT1 0xcf0 | ||
| 79 | #define ODM_OFDM_PHY0_PAGE_D 0xd00 | ||
| 80 | #define ODM_OFDM_FA_CNT2 0xda0 | ||
| 81 | #define ODM_OFDM_FA_CNT3 0xda4 | ||
| 82 | #define ODM_OFDM_FA_CNT4 0xda8 | ||
| 83 | #define ODM_TXAGC_A_6_18 0xe00 | ||
| 84 | #define ODM_TXAGC_A_24_54 0xe04 | ||
| 85 | #define ODM_TXAGC_A_1_MCS32 0xe08 | ||
| 86 | #define ODM_TXAGC_A_MCS0_MCS3 0xe10 | ||
| 87 | #define ODM_TXAGC_A_MCS4_MCS7 0xe14 | ||
| 88 | #define ODM_TXAGC_A_MCS8_MCS11 0xe18 | ||
| 89 | #define ODM_TXAGC_A_MCS12_MCS15 0xe1c | ||
| 90 | |||
| 91 | /* RF REG */ | ||
| 92 | #define ODM_GAIN_SETTING 0x00 | ||
| 93 | #define ODM_CHANNEL 0x18 | ||
| 94 | |||
| 95 | /* Ant Detect Reg */ | ||
| 96 | #define ODM_DPDT 0x300 | ||
| 97 | |||
| 98 | /* PSD Init */ | ||
| 99 | #define ODM_PSDREG 0x808 | ||
| 100 | |||
| 101 | /* 92D Path Div */ | ||
| 102 | #define PATHDIV_REG 0xB30 | ||
| 103 | #define PATHDIV_TRI 0xBA0 | ||
| 104 | |||
| 105 | |||
| 106 | /* */ | ||
| 107 | /* Bitmap Definition */ | ||
| 108 | /* */ | ||
| 109 | |||
| 110 | #define BIT_FA_RESET BIT0 | ||
| 111 | |||
| 112 | |||
| 113 | |||
| 114 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/odm_types.h b/drivers/staging/rtl8723au/include/odm_types.h new file mode 100644 index 000000000000..a866769ea178 --- /dev/null +++ b/drivers/staging/rtl8723au/include/odm_types.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __ODM_TYPES_H__ | ||
| 16 | #define __ODM_TYPES_H__ | ||
| 17 | |||
| 18 | /* Define Different SW team support */ | ||
| 19 | |||
| 20 | enum hal_status { | ||
| 21 | HAL_STATUS_SUCCESS, | ||
| 22 | HAL_STATUS_FAILURE, | ||
| 23 | }; | ||
| 24 | |||
| 25 | enum rt_spinlock_type { | ||
| 26 | RT_TEMP =1, | ||
| 27 | }; | ||
| 28 | |||
| 29 | #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) \ | ||
| 30 | SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) | ||
| 31 | #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) \ | ||
| 32 | SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) | ||
| 33 | #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) \ | ||
| 34 | SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) | ||
| 35 | |||
| 36 | #endif /* __ODM_TYPES_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/osdep_intf.h b/drivers/staging/rtl8723au/include/osdep_intf.h new file mode 100644 index 000000000000..b603cf532900 --- /dev/null +++ b/drivers/staging/rtl8723au/include/osdep_intf.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef __OSDEP_INTF_H_ | ||
| 17 | #define __OSDEP_INTF_H_ | ||
| 18 | |||
| 19 | #include <osdep_service.h> | ||
| 20 | #include <drv_types.h> | ||
| 21 | |||
| 22 | int rtw_hw_suspend23a(struct rtw_adapter *padapter); | ||
| 23 | int rtw_hw_resume23a(struct rtw_adapter *padapter); | ||
| 24 | |||
| 25 | u8 rtw_init_drv_sw23a(struct rtw_adapter *padapter); | ||
| 26 | u8 rtw_free_drv_sw23a(struct rtw_adapter *padapter); | ||
| 27 | u8 rtw_reset_drv_sw23a(struct rtw_adapter *padapter); | ||
| 28 | |||
| 29 | u32 rtw_start_drv_threads23a(struct rtw_adapter *padapter); | ||
| 30 | void rtw_stop_drv_threads23a (struct rtw_adapter *padapter); | ||
| 31 | void rtw_cancel_all_timer23a(struct rtw_adapter *padapter); | ||
| 32 | |||
| 33 | int rtw_init_netdev23a_name23a(struct net_device *pnetdev, const char *ifname); | ||
| 34 | struct net_device *rtw_init_netdev23a(struct rtw_adapter *padapter); | ||
| 35 | |||
| 36 | u16 rtw_recv_select_queue23a(struct sk_buff *skb); | ||
| 37 | |||
| 38 | void rtw_ips_dev_unload23a(struct rtw_adapter *padapter); | ||
| 39 | |||
| 40 | int rtw_ips_pwr_up23a(struct rtw_adapter *padapter); | ||
| 41 | void rtw_ips_pwr_down23a(struct rtw_adapter *padapter); | ||
| 42 | |||
| 43 | int rtw_drv_register_netdev(struct rtw_adapter *padapter); | ||
| 44 | void rtw_ndev_destructor(struct net_device *ndev); | ||
| 45 | |||
| 46 | #endif /* _OSDEP_INTF_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/osdep_service.h b/drivers/staging/rtl8723au/include/osdep_service.h new file mode 100644 index 000000000000..cb7b5cdcbe55 --- /dev/null +++ b/drivers/staging/rtl8723au/include/osdep_service.h | |||
| @@ -0,0 +1,340 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __OSDEP_SERVICE_H_ | ||
| 16 | #define __OSDEP_SERVICE_H_ | ||
| 17 | |||
| 18 | #define _FAIL 0 | ||
| 19 | #define _SUCCESS 1 | ||
| 20 | #define RTW_RX_HANDLED 2 | ||
| 21 | |||
| 22 | #include <linux/version.h> | ||
| 23 | #include <linux/spinlock.h> | ||
| 24 | #include <linux/compiler.h> | ||
| 25 | #include <linux/kernel.h> | ||
| 26 | #include <linux/errno.h> | ||
| 27 | #include <linux/init.h> | ||
| 28 | #include <linux/slab.h> | ||
| 29 | #include <linux/module.h> | ||
| 30 | #include <linux/kref.h> | ||
| 31 | #include <linux/netdevice.h> | ||
| 32 | #include <linux/skbuff.h> | ||
| 33 | #include <linux/circ_buf.h> | ||
| 34 | #include <asm/uaccess.h> | ||
| 35 | #include <asm/byteorder.h> | ||
| 36 | #include <asm/atomic.h> | ||
| 37 | #include <asm/io.h> | ||
| 38 | #include <linux/semaphore.h> | ||
| 39 | #include <linux/sem.h> | ||
| 40 | #include <linux/sched.h> | ||
| 41 | #include <linux/etherdevice.h> | ||
| 42 | #include <linux/wireless.h> | ||
| 43 | #include <net/iw_handler.h> | ||
| 44 | #include <linux/if_arp.h> | ||
| 45 | #include <linux/rtnetlink.h> | ||
| 46 | #include <linux/delay.h> | ||
| 47 | #include <linux/proc_fs.h> /* Necessary because we use the proc fs */ | ||
| 48 | #include <linux/interrupt.h> /* for struct tasklet_struct */ | ||
| 49 | #include <linux/ip.h> | ||
| 50 | #include <linux/kthread.h> | ||
| 51 | |||
| 52 | |||
| 53 | /* #include <linux/ieee80211.h> */ | ||
| 54 | #include <net/ieee80211_radiotap.h> | ||
| 55 | #include <net/cfg80211.h> | ||
| 56 | #include <linux/usb.h> | ||
| 57 | #include <linux/usb/ch9.h> | ||
| 58 | |||
| 59 | struct rtw_adapter; | ||
| 60 | struct c2h_evt_hdr; | ||
| 61 | |||
| 62 | typedef s32 (*c2h_id_filter)(u8 id); | ||
| 63 | |||
| 64 | struct rtw_queue { | ||
| 65 | struct list_head queue; | ||
| 66 | spinlock_t lock; | ||
| 67 | }; | ||
| 68 | |||
| 69 | static inline struct list_head *get_list_head(struct rtw_queue *queue) | ||
| 70 | { | ||
| 71 | return (&queue->queue); | ||
| 72 | } | ||
| 73 | |||
| 74 | static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) | ||
| 75 | { | ||
| 76 | return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && | ||
| 77 | netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) && | ||
| 78 | netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) && | ||
| 79 | netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)) ); | ||
| 80 | } | ||
| 81 | |||
| 82 | #ifndef BIT | ||
| 83 | #define BIT(x) ( 1 << (x)) | ||
| 84 | #endif | ||
| 85 | static inline u32 CHKBIT(u32 x) | ||
| 86 | { | ||
| 87 | WARN_ON(x >= 32); | ||
| 88 | if (x >= 32) | ||
| 89 | return 0; | ||
| 90 | return BIT(x); | ||
| 91 | } | ||
| 92 | |||
| 93 | #define BIT0 0x00000001 | ||
| 94 | #define BIT1 0x00000002 | ||
| 95 | #define BIT2 0x00000004 | ||
| 96 | #define BIT3 0x00000008 | ||
| 97 | #define BIT4 0x00000010 | ||
| 98 | #define BIT5 0x00000020 | ||
| 99 | #define BIT6 0x00000040 | ||
| 100 | #define BIT7 0x00000080 | ||
| 101 | #define BIT8 0x00000100 | ||
| 102 | #define BIT9 0x00000200 | ||
| 103 | #define BIT10 0x00000400 | ||
| 104 | #define BIT11 0x00000800 | ||
| 105 | #define BIT12 0x00001000 | ||
| 106 | #define BIT13 0x00002000 | ||
| 107 | #define BIT14 0x00004000 | ||
| 108 | #define BIT15 0x00008000 | ||
| 109 | #define BIT16 0x00010000 | ||
| 110 | #define BIT17 0x00020000 | ||
| 111 | #define BIT18 0x00040000 | ||
| 112 | #define BIT19 0x00080000 | ||
| 113 | #define BIT20 0x00100000 | ||
| 114 | #define BIT21 0x00200000 | ||
| 115 | #define BIT22 0x00400000 | ||
| 116 | #define BIT23 0x00800000 | ||
| 117 | #define BIT24 0x01000000 | ||
| 118 | #define BIT25 0x02000000 | ||
| 119 | #define BIT26 0x04000000 | ||
| 120 | #define BIT27 0x08000000 | ||
| 121 | #define BIT28 0x10000000 | ||
| 122 | #define BIT29 0x20000000 | ||
| 123 | #define BIT30 0x40000000 | ||
| 124 | #define BIT31 0x80000000 | ||
| 125 | #define BIT32 0x0100000000 | ||
| 126 | #define BIT33 0x0200000000 | ||
| 127 | #define BIT34 0x0400000000 | ||
| 128 | #define BIT35 0x0800000000 | ||
| 129 | #define BIT36 0x1000000000 | ||
| 130 | |||
| 131 | int RTW_STATUS_CODE23a(int error_code); | ||
| 132 | |||
| 133 | u8* _rtw_vmalloc(u32 sz); | ||
| 134 | u8* _rtw_zvmalloc(u32 sz); | ||
| 135 | void _rtw_vmfree(u8 *pbuf, u32 sz); | ||
| 136 | #define rtw_vmalloc(sz) _rtw_vmalloc((sz)) | ||
| 137 | #define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) | ||
| 138 | #define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) | ||
| 139 | |||
| 140 | extern unsigned char REALTEK_96B_IE23A[]; | ||
| 141 | extern unsigned char MCS_rate_2R23A[16]; | ||
| 142 | extern unsigned char RTW_WPA_OUI23A[]; | ||
| 143 | extern unsigned char WPA_TKIP_CIPHER23A[4]; | ||
| 144 | extern unsigned char RSN_TKIP_CIPHER23A[4]; | ||
| 145 | |||
| 146 | extern unsigned char MCS_rate_2R23A[16]; | ||
| 147 | extern unsigned char MCS_rate_1R23A[16]; | ||
| 148 | |||
| 149 | void _rtw_init_queue23a(struct rtw_queue *pqueue); | ||
| 150 | u32 _rtw_queue_empty23a(struct rtw_queue *pqueue); | ||
| 151 | |||
| 152 | u32 rtw_get_current_time(void); | ||
| 153 | u32 rtw_systime_to_ms23a(u32 systime); | ||
| 154 | u32 rtw_ms_to_systime23a(u32 ms); | ||
| 155 | s32 rtw_get_passing_time_ms23a(u32 start); | ||
| 156 | s32 rtw_get_time_interval_ms23a(u32 start, u32 end); | ||
| 157 | |||
| 158 | #define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) | ||
| 159 | #define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2) | ||
| 160 | |||
| 161 | static inline u32 _RND4(u32 sz) | ||
| 162 | { | ||
| 163 | |||
| 164 | u32 val; | ||
| 165 | |||
| 166 | val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2; | ||
| 167 | |||
| 168 | return val; | ||
| 169 | |||
| 170 | } | ||
| 171 | |||
| 172 | static inline u32 _RND8(u32 sz) | ||
| 173 | { | ||
| 174 | |||
| 175 | u32 val; | ||
| 176 | |||
| 177 | val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3; | ||
| 178 | |||
| 179 | return val; | ||
| 180 | |||
| 181 | } | ||
| 182 | |||
| 183 | static inline u32 _RND128(u32 sz) | ||
| 184 | { | ||
| 185 | |||
| 186 | u32 val; | ||
| 187 | |||
| 188 | val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7; | ||
| 189 | |||
| 190 | return val; | ||
| 191 | |||
| 192 | } | ||
| 193 | |||
| 194 | static inline u32 _RND256(u32 sz) | ||
| 195 | { | ||
| 196 | |||
| 197 | u32 val; | ||
| 198 | |||
| 199 | val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8; | ||
| 200 | |||
| 201 | return val; | ||
| 202 | |||
| 203 | } | ||
| 204 | |||
| 205 | static inline u32 _RND512(u32 sz) | ||
| 206 | { | ||
| 207 | |||
| 208 | u32 val; | ||
| 209 | |||
| 210 | val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9; | ||
| 211 | |||
| 212 | return val; | ||
| 213 | |||
| 214 | } | ||
| 215 | |||
| 216 | static inline u32 bitshift(u32 bitmask) | ||
| 217 | { | ||
| 218 | u32 i; | ||
| 219 | |||
| 220 | for (i = 0; i <= 31; i++) | ||
| 221 | if (((bitmask>>i) & 0x1) == 1) break; | ||
| 222 | |||
| 223 | return i; | ||
| 224 | } | ||
| 225 | |||
| 226 | #define STRUCT_PACKED __attribute__ ((packed)) | ||
| 227 | |||
| 228 | /* limitation of path length */ | ||
| 229 | #define PATH_LENGTH_MAX PATH_MAX | ||
| 230 | |||
| 231 | void rtw_suspend_lock_init(void); | ||
| 232 | void rtw_suspend_lock_uninit(void); | ||
| 233 | void rtw_lock_suspend(void); | ||
| 234 | void rtw_unlock_suspend(void); | ||
| 235 | |||
| 236 | /* File operation APIs, just for linux now */ | ||
| 237 | int rtw_is_file_readable(char *path); | ||
| 238 | int rtw_retrive_from_file(char *path, u8* buf, u32 sz); | ||
| 239 | int rtw_store_to_file(char *path, u8* buf, u32 sz); | ||
| 240 | |||
| 241 | #define NDEV_FMT "%s" | ||
| 242 | #define NDEV_ARG(ndev) ndev->name | ||
| 243 | #define ADPT_FMT "%s" | ||
| 244 | #define ADPT_ARG(adapter) adapter->pnetdev->name | ||
| 245 | #define FUNC_NDEV_FMT "%s(%s)" | ||
| 246 | #define FUNC_NDEV_ARG(ndev) __func__, ndev->name | ||
| 247 | #define FUNC_ADPT_FMT "%s(%s)" | ||
| 248 | #define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name | ||
| 249 | |||
| 250 | #define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1) | ||
| 251 | |||
| 252 | u64 rtw_modular6423a(u64 x, u64 y); | ||
| 253 | u64 rtw_division6423a(u64 x, u64 y); | ||
| 254 | |||
| 255 | |||
| 256 | /* Macros for handling unaligned memory accesses */ | ||
| 257 | |||
| 258 | #define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1])) | ||
| 259 | #define RTW_PUT_BE16(a, val) \ | ||
| 260 | do { \ | ||
| 261 | (a)[0] = ((u16) (val)) >> 8; \ | ||
| 262 | (a)[1] = ((u16) (val)) & 0xff; \ | ||
| 263 | } while (0) | ||
| 264 | |||
| 265 | #define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0])) | ||
| 266 | #define RTW_PUT_LE16(a, val) \ | ||
| 267 | do { \ | ||
| 268 | (a)[1] = ((u16) (val)) >> 8; \ | ||
| 269 | (a)[0] = ((u16) (val)) & 0xff; \ | ||
| 270 | } while (0) | ||
| 271 | |||
| 272 | #define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \ | ||
| 273 | ((u32) (a)[2])) | ||
| 274 | #define RTW_PUT_BE24(a, val) \ | ||
| 275 | do { \ | ||
| 276 | (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \ | ||
| 277 | (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ | ||
| 278 | (a)[2] = (u8) (((u32) (val)) & 0xff); \ | ||
| 279 | } while (0) | ||
| 280 | |||
| 281 | #define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ | ||
| 282 | (((u32) (a)[2]) << 8) | ((u32) (a)[3])) | ||
| 283 | #define RTW_PUT_BE32(a, val) \ | ||
| 284 | do { \ | ||
| 285 | (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ | ||
| 286 | (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ | ||
| 287 | (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ | ||
| 288 | (a)[3] = (u8) (((u32) (val)) & 0xff); \ | ||
| 289 | } while (0) | ||
| 290 | |||
| 291 | #define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \ | ||
| 292 | (((u32) (a)[1]) << 8) | ((u32) (a)[0])) | ||
| 293 | #define RTW_PUT_LE32(a, val) \ | ||
| 294 | do { \ | ||
| 295 | (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ | ||
| 296 | (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ | ||
| 297 | (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ | ||
| 298 | (a)[0] = (u8) (((u32) (val)) & 0xff); \ | ||
| 299 | } while (0) | ||
| 300 | |||
| 301 | #define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \ | ||
| 302 | (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \ | ||
| 303 | (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \ | ||
| 304 | (((u64) (a)[6]) << 8) | ((u64) (a)[7])) | ||
| 305 | #define RTW_PUT_BE64(a, val) \ | ||
| 306 | do { \ | ||
| 307 | (a)[0] = (u8) (((u64) (val)) >> 56); \ | ||
| 308 | (a)[1] = (u8) (((u64) (val)) >> 48); \ | ||
| 309 | (a)[2] = (u8) (((u64) (val)) >> 40); \ | ||
| 310 | (a)[3] = (u8) (((u64) (val)) >> 32); \ | ||
| 311 | (a)[4] = (u8) (((u64) (val)) >> 24); \ | ||
| 312 | (a)[5] = (u8) (((u64) (val)) >> 16); \ | ||
| 313 | (a)[6] = (u8) (((u64) (val)) >> 8); \ | ||
| 314 | (a)[7] = (u8) (((u64) (val)) & 0xff); \ | ||
| 315 | } while (0) | ||
| 316 | |||
| 317 | #define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \ | ||
| 318 | (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ | ||
| 319 | (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ | ||
| 320 | (((u64) (a)[1]) << 8) | ((u64) (a)[0])) | ||
| 321 | |||
| 322 | struct rtw_cbuf { | ||
| 323 | u32 write; | ||
| 324 | u32 read; | ||
| 325 | u32 size; | ||
| 326 | void *bufs[0]; | ||
| 327 | }; | ||
| 328 | |||
| 329 | bool rtw_cbuf_full23a(struct rtw_cbuf *cbuf); | ||
| 330 | bool rtw_cbuf_empty23a(struct rtw_cbuf *cbuf); | ||
| 331 | bool rtw_cbuf_push23a(struct rtw_cbuf *cbuf, void *buf); | ||
| 332 | void *rtw_cbuf_pop23a(struct rtw_cbuf *cbuf); | ||
| 333 | struct rtw_cbuf *rtw_cbuf_alloc23a(u32 size); | ||
| 334 | void rtw_cbuf_free(struct rtw_cbuf *cbuf); | ||
| 335 | int rtw_change_ifname(struct rtw_adapter *padapter, const char *ifname); | ||
| 336 | s32 c2h_evt_hdl(struct rtw_adapter *adapter, struct c2h_evt_hdr *c2h_evt, c2h_id_filter filter); | ||
| 337 | void indicate_wx_scan_complete_event(struct rtw_adapter *padapter); | ||
| 338 | u8 rtw_do_join23a(struct rtw_adapter *padapter); | ||
| 339 | |||
| 340 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/recv_osdep.h b/drivers/staging/rtl8723au/include/recv_osdep.h new file mode 100644 index 000000000000..15c94b6168bf --- /dev/null +++ b/drivers/staging/rtl8723au/include/recv_osdep.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RECV_OSDEP_H_ | ||
| 16 | #define __RECV_OSDEP_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | int _rtw_init_recv_priv23a(struct recv_priv *precvpriv, struct rtw_adapter *padapter); | ||
| 22 | void _rtw_free_recv_priv23a (struct recv_priv *precvpriv); | ||
| 23 | |||
| 24 | int rtw_recv_entry23a(struct recv_frame *precv_frame); | ||
| 25 | int rtw_recv_indicatepkt23a(struct rtw_adapter *adapter, struct recv_frame *precv_frame); | ||
| 26 | void rtw_recv_returnpacket(struct net_device *cnxt, struct sk_buff *preturnedpkt); | ||
| 27 | |||
| 28 | void rtw_hostapd_mlme_rx23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 29 | void rtw_handle_tkip_mic_err23a(struct rtw_adapter *padapter, u8 bgroup); | ||
| 30 | |||
| 31 | int rtw_init_recv_priv(struct recv_priv *precvpriv, struct rtw_adapter *padapter); | ||
| 32 | void rtw_free_recv_priv (struct recv_priv *precvpriv); | ||
| 33 | |||
| 34 | int rtw_os_recv_resource_init(struct recv_priv *precvpriv, struct rtw_adapter *padapter); | ||
| 35 | int rtw_os_recv_resource_alloc23a(struct rtw_adapter *padapter, struct recv_frame *precvframe); | ||
| 36 | void rtw_os_recv_resource_free(struct recv_priv *precvpriv); | ||
| 37 | |||
| 38 | int rtw_os_recvbuf_resource_alloc23a(struct rtw_adapter *padapter, struct recv_buf *precvbuf); | ||
| 39 | int rtw_os_recvbuf_resource_free23a(struct rtw_adapter *padapter, struct recv_buf *precvbuf); | ||
| 40 | |||
| 41 | void rtw_os_read_port23a(struct rtw_adapter *padapter, struct recv_buf *precvbuf); | ||
| 42 | |||
| 43 | void rtw_init_recv_timer23a(struct recv_reorder_ctrl *preorder_ctrl); | ||
| 44 | |||
| 45 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_bt-coexist.h b/drivers/staging/rtl8723au/include/rtl8723a_bt-coexist.h new file mode 100644 index 000000000000..5777eda01403 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_bt-coexist.h | |||
| @@ -0,0 +1,1672 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_BT_COEXIST_H__ | ||
| 16 | #define __RTL8723A_BT_COEXIST_H__ | ||
| 17 | |||
| 18 | #include <drv_types.h> | ||
| 19 | #include "odm_precomp.h" | ||
| 20 | |||
| 21 | |||
| 22 | #define __BT_C__ 1 | ||
| 23 | #define __BT_HANDLEPACKET_C__ 1 | ||
| 24 | #define __BT_HCI_C__ 1 | ||
| 25 | #define __HALBTC87231ANT_C__ 1 | ||
| 26 | #define __HALBTC87232ANT_C__ 1 | ||
| 27 | #define __HALBTC8723_C__ 1 | ||
| 28 | #define __HALBTCCSR1ANT_C__ 1 | ||
| 29 | #define __HALBTCCSR2ANT_C__ 1 | ||
| 30 | #define __HALBTCOEXIST_C__ 1 | ||
| 31 | #define __HALBT_C__ 1 | ||
| 32 | |||
| 33 | #ifdef __BT_C__ /* COMMON/BT.h */ | ||
| 34 | |||
| 35 | /* HEADER/PlatformDef.h */ | ||
| 36 | enum rt_media_status { | ||
| 37 | RT_MEDIA_DISCONNECT = 0, | ||
| 38 | RT_MEDIA_CONNECT = 1 | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* ===== Below this line is sync from SD7 driver COMMON/BT.h ===== */ | ||
| 42 | |||
| 43 | #define BT_TMP_BUF_SIZE 100 | ||
| 44 | |||
| 45 | void BT_SignalCompensation(struct rtw_adapter *padapter, | ||
| 46 | u8 *rssi_wifi, u8 *rssi_bt); | ||
| 47 | void BT_WifiScanNotify(struct rtw_adapter *padapter, u8 scanType); | ||
| 48 | void BT_WifiAssociateNotify(struct rtw_adapter *padapter, u8 action); | ||
| 49 | void BT_WifiMediaStatusNotify(struct rtw_adapter *padapter, | ||
| 50 | enum rt_media_status mstatus); | ||
| 51 | void BT_SpecialPacketNotify(struct rtw_adapter * padapter); | ||
| 52 | void BT_HaltProcess(struct rtw_adapter * padapter); | ||
| 53 | void BT_LpsLeave(struct rtw_adapter * padapter); | ||
| 54 | |||
| 55 | |||
| 56 | #define BT_HsConnectionEstablished(Adapter) false | ||
| 57 | /* ===== End of sync from SD7 driver COMMON/BT.h ===== */ | ||
| 58 | #endif /* __BT_C__ */ | ||
| 59 | |||
| 60 | #ifdef __BT_HCI_C__ /* COMMON/bt_hci.h */ | ||
| 61 | |||
| 62 | /* HEADER/SecurityType.h */ | ||
| 63 | #define TKIP_ENC_KEY_POS 32 /* KEK_LEN+KEK_LEN) */ | ||
| 64 | #define MAXRSNIELEN 256 | ||
| 65 | |||
| 66 | /* COMMON/Protocol802_11.h */ | ||
| 67 | /* */ | ||
| 68 | /* 802.11 Management frame Status Code field */ | ||
| 69 | /* */ | ||
| 70 | struct octet_string { | ||
| 71 | u8 *Octet; | ||
| 72 | u16 Length; | ||
| 73 | }; | ||
| 74 | |||
| 75 | |||
| 76 | /* AES_CCMP specific */ | ||
| 77 | enum { | ||
| 78 | AESCCMP_BLK_SIZE = 16, /* # octets in an AES block */ | ||
| 79 | AESCCMP_MAX_PACKET = 4*512, /* largest packet size */ | ||
| 80 | AESCCMP_N_RESERVED = 0, /* reserved nonce octet value */ | ||
| 81 | AESCCMP_A_DATA = 0x40, /* the Adata bit in the flags */ | ||
| 82 | AESCCMP_M_SHIFT = 3, /* how much to shift the 3-bit M field */ | ||
| 83 | AESCCMP_L_SHIFT = 0, /* how much to shift the 3-bit L field */ | ||
| 84 | AESCCMP_L_SIZE = 2, /* size of the l(m) length field (in octets) */ | ||
| 85 | AESCCMP_OFFSET_SC = 22, | ||
| 86 | AESCCMP_OFFSET_DURATION = 4, | ||
| 87 | AESCCMP_OFFSET_A2 = 10, | ||
| 88 | AESCCMP_OFFSET_A4 = 24, | ||
| 89 | AESCCMP_QC_TID_MASK = 0x0f, | ||
| 90 | AESCCMP_BLK_SIZE_TOTAL = 16*16, /* Added by Annie for CKIP AES MIC BSOD, 2006-08-17. */ | ||
| 91 | /* 16*8 < 4*60 Resove to 16*16 */ | ||
| 92 | }; | ||
| 93 | |||
| 94 | /* Key Length */ | ||
| 95 | #define PMK_LEN 32 | ||
| 96 | #define PTK_LEN_TKIP 64 | ||
| 97 | #define GTK_LEN 32 | ||
| 98 | #define KEY_NONCE_LEN 32 | ||
| 99 | |||
| 100 | |||
| 101 | /* COMMON/Dot11d.h */ | ||
| 102 | struct chnl_txpower_triple { | ||
| 103 | u8 FirstChnl; | ||
| 104 | u8 NumChnls; | ||
| 105 | s8 MaxTxPowerInDbm; | ||
| 106 | }; | ||
| 107 | |||
| 108 | |||
| 109 | /* ===== Below this line is sync from SD7 driver COMMON/bt_hci.h ===== */ | ||
| 110 | /* The following is for BT 3.0 + HS HCI COMMAND ERRORS CODES */ | ||
| 111 | |||
| 112 | #define Max80211PALPDUSize 1492 | ||
| 113 | #define Max80211AMPASSOCLen 672 | ||
| 114 | #define MinGUserPrio 4 | ||
| 115 | #define MaxGUserPrio 7 | ||
| 116 | #define BEUserPrio0 0 | ||
| 117 | #define BEUserPrio1 3 | ||
| 118 | #define Max80211BeaconPeriod 2000 | ||
| 119 | #define ShortRangeModePowerMax 4 | ||
| 120 | |||
| 121 | #define BT_Default_Chnl 10 | ||
| 122 | #define ACLDataHeaderLen 4 | ||
| 123 | |||
| 124 | #define BTTotalDataBlockNum 0x100 | ||
| 125 | #define BTLocalBufNum 0x200 | ||
| 126 | #define BTMaxDataBlockLen 0x800 | ||
| 127 | #define BTTOTALBANDWIDTH 0x7530 | ||
| 128 | #define BTMAXBANDGUBANDWIDTH 0x4e20 | ||
| 129 | #define TmpLocalBufSize 0x100 | ||
| 130 | #define BTSynDataPacketLength 0xff | ||
| 131 | /* */ | ||
| 132 | |||
| 133 | #define BTMaxAuthCount 5 | ||
| 134 | #define BTMaxAsocCount 5 | ||
| 135 | |||
| 136 | #define MAX_LOGICAL_LINK_NUM 2 /* temporarily define */ | ||
| 137 | #define MAX_BT_ASOC_ENTRY_NUM 2 /* temporarily define */ | ||
| 138 | |||
| 139 | #define INVALID_PL_HANDLE 0xff | ||
| 140 | #define INVALID_ENTRY_NUM 0xff | ||
| 141 | /* */ | ||
| 142 | |||
| 143 | #define CAM_BT_START_INDEX (HALF_CAM_ENTRY - 4) /* MAX_BT_ASOC_ENTRY_NUM : 4 !!! */ | ||
| 144 | #define BT_HWCAM_STAR CAM_BT_START_INDEX /* We used HALF_CAM_ENTRY ~ HALF_CAM_ENTRY -MAX_BT_ASOC_ENTRY_NUM */ | ||
| 145 | |||
| 146 | enum hci_status { | ||
| 147 | HCI_STATUS_SUCCESS = 0x00, /* Success */ | ||
| 148 | HCI_STATUS_UNKNOW_HCI_CMD = 0x01, /* Unknown HCI Command */ | ||
| 149 | HCI_STATUS_UNKNOW_CONNECT_ID = 0X02, /* Unknown Connection Identifier */ | ||
| 150 | HCI_STATUS_HW_FAIL = 0X03, /* Hardware Failure */ | ||
| 151 | HCI_STATUS_PAGE_TIMEOUT = 0X04, /* Page Timeout */ | ||
| 152 | HCI_STATUS_AUTH_FAIL = 0X05, /* Authentication Failure */ | ||
| 153 | HCI_STATUS_PIN_OR_KEY_MISSING = 0X06, /* PIN or Key Missing */ | ||
| 154 | HCI_STATUS_MEM_CAP_EXCEED = 0X07, /* Memory Capacity Exceeded */ | ||
| 155 | HCI_STATUS_CONNECT_TIMEOUT = 0X08, /* Connection Timeout */ | ||
| 156 | HCI_STATUS_CONNECT_LIMIT = 0X09, /* Connection Limit Exceeded */ | ||
| 157 | HCI_STATUS_SYN_CONNECT_LIMIT = 0X0a, /* Synchronous Connection Limit To A Device Exceeded */ | ||
| 158 | HCI_STATUS_ACL_CONNECT_EXISTS = 0X0b, /* ACL Connection Already Exists */ | ||
| 159 | HCI_STATUS_CMD_DISALLOW = 0X0c, /* Command Disallowed */ | ||
| 160 | HCI_STATUS_CONNECT_RJT_LIMIT_RESOURCE = 0X0d, /* Connection Rejected due to Limited Resources */ | ||
| 161 | HCI_STATUS_CONNECT_RJT_SEC_REASON = 0X0e, /* Connection Rejected Due To Security Reasons */ | ||
| 162 | HCI_STATUS_CONNECT_RJT_UNACCEPT_BD_ADDR = 0X0f, /* Connection Rejected due to Unacceptable BD_ADDR */ | ||
| 163 | HCI_STATUS_CONNECT_ACCEPT_TIMEOUT = 0X10, /* Connection Accept Timeout Exceeded */ | ||
| 164 | HCI_STATUS_UNSUPPORT_FEATURE_PARA_VALUE = 0X11, /* Unsupported Feature or Parameter Value */ | ||
| 165 | HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE = 0X12, /* Invalid HCI Command Parameters */ | ||
| 166 | HCI_STATUS_REMOTE_USER_TERMINATE_CONNECT = 0X13, /* Remote User Terminated Connection */ | ||
| 167 | HCI_STATUS_REMOTE_DEV_TERMINATE_LOW_RESOURCE = 0X14, /* Remote Device Terminated Connection due to Low Resources */ | ||
| 168 | HCI_STATUS_REMOTE_DEV_TERMINATE_CONNECT_POWER_OFF = 0X15, /* Remote Device Terminated Connection due to Power Off */ | ||
| 169 | HCI_STATUS_CONNECT_TERMINATE_LOCAL_HOST = 0X16, /* Connection Terminated By Local Host */ | ||
| 170 | HCI_STATUS_REPEATE_ATTEMPT = 0X17, /* Repeated Attempts */ | ||
| 171 | HCI_STATUS_PAIR_NOT_ALLOW = 0X18, /* Pairing Not Allowed */ | ||
| 172 | HCI_STATUS_UNKNOW_LMP_PDU = 0X19, /* Unknown LMP PDU */ | ||
| 173 | HCI_STATUS_UNSUPPORT_REMOTE_LMP_FEATURE = 0X1a, /* Unsupported Remote Feature / Unsupported LMP Feature */ | ||
| 174 | HCI_STATUS_SOC_OFFSET_REJECT = 0X1b, /* SCO Offset Rejected */ | ||
| 175 | HCI_STATUS_SOC_INTERVAL_REJECT = 0X1c, /* SCO Interval Rejected */ | ||
| 176 | HCI_STATUS_SOC_AIR_MODE_REJECT = 0X1d,/* SCO Air Mode Rejected */ | ||
| 177 | HCI_STATUS_INVALID_LMP_PARA = 0X1e, /* Invalid LMP Parameters */ | ||
| 178 | HCI_STATUS_UNSPECIFIC_ERROR = 0X1f, /* Unspecified Error */ | ||
| 179 | HCI_STATUS_UNSUPPORT_LMP_PARA_VALUE = 0X20, /* Unsupported LMP Parameter Value */ | ||
| 180 | HCI_STATUS_ROLE_CHANGE_NOT_ALLOW = 0X21, /* Role Change Not Allowed */ | ||
| 181 | HCI_STATUS_LMP_RESPONSE_TIMEOUT = 0X22, /* LMP Response Timeout */ | ||
| 182 | HCI_STATUS_LMP_ERROR_TRANSACTION_COLLISION = 0X23, /* LMP Error Transaction Collision */ | ||
| 183 | HCI_STATUS_LMP_PDU_NOT_ALLOW = 0X24, /* LMP PDU Not Allowed */ | ||
| 184 | HCI_STATUS_ENCRYPTION_MODE_NOT_ALLOW = 0X25, /* Encryption Mode Not Acceptable */ | ||
| 185 | HCI_STATUS_LINK_KEY_CAN_NOT_CHANGE = 0X26, /* Link Key Can Not be Changed */ | ||
| 186 | HCI_STATUS_REQUEST_QOS_NOT_SUPPORT = 0X27, /* Requested QoS Not Supported */ | ||
| 187 | HCI_STATUS_INSTANT_PASSED = 0X28, /* Instant Passed */ | ||
| 188 | HCI_STATUS_PAIRING_UNIT_KEY_NOT_SUPPORT = 0X29, /* Pairing With Unit Key Not Supported */ | ||
| 189 | HCI_STATUS_DIFFERENT_TRANSACTION_COLLISION = 0X2a, /* Different Transaction Collision */ | ||
| 190 | HCI_STATUS_RESERVE_1 = 0X2b, /* Reserved */ | ||
| 191 | HCI_STATUS_QOS_UNACCEPT_PARA = 0X2c, /* QoS Unacceptable Parameter */ | ||
| 192 | HCI_STATUS_QOS_REJECT = 0X2d, /* QoS Rejected */ | ||
| 193 | HCI_STATUS_CHNL_CLASSIFICATION_NOT_SUPPORT = 0X2e, /* Channel Classification Not Supported */ | ||
| 194 | HCI_STATUS_INSUFFICIENT_SECURITY = 0X2f, /* Insufficient Security */ | ||
| 195 | HCI_STATUS_PARA_OUT_OF_RANGE = 0x30, /* Parameter Out Of Mandatory Range */ | ||
| 196 | HCI_STATUS_RESERVE_2 = 0X31, /* Reserved */ | ||
| 197 | HCI_STATUS_ROLE_SWITCH_PENDING = 0X32, /* Role Switch Pending */ | ||
| 198 | HCI_STATUS_RESERVE_3 = 0X33, /* Reserved */ | ||
| 199 | HCI_STATUS_RESERVE_SOLT_VIOLATION = 0X34, /* Reserved Slot Violation */ | ||
| 200 | HCI_STATUS_ROLE_SWITCH_FAIL = 0X35, /* Role Switch Failed */ | ||
| 201 | HCI_STATUS_EXTEND_INQUIRY_RSP_TOO_LARGE = 0X36, /* Extended Inquiry Response Too Large */ | ||
| 202 | HCI_STATUS_SEC_SIMPLE_PAIRING_NOT_SUPPORT = 0X37, /* Secure Simple Pairing Not Supported By Host. */ | ||
| 203 | HCI_STATUS_HOST_BUSY_PAIRING = 0X38, /* Host Busy - Pairing */ | ||
| 204 | HCI_STATUS_CONNECT_REJ_NOT_SUIT_CHNL_FOUND = 0X39, /* Connection Rejected due to No Suitable Channel Found */ | ||
| 205 | HCI_STATUS_CONTROLLER_BUSY = 0X3a /* CONTROLLER BUSY */ | ||
| 206 | }; | ||
| 207 | |||
| 208 | /* */ | ||
| 209 | /* The following is for BT 3.0 + HS HCI COMMAND */ | ||
| 210 | /* */ | ||
| 211 | |||
| 212 | /* bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ | ||
| 213 | /* | OCF | OGF | */ | ||
| 214 | /* */ | ||
| 215 | |||
| 216 | /* OGF 0x01 */ | ||
| 217 | #define LINK_CONTROL_COMMANDS 0x01 | ||
| 218 | enum link_control_commands { | ||
| 219 | HCI_INQUIRY = 0x0001, | ||
| 220 | HCI_INQUIRY_CANCEL = 0x0002, | ||
| 221 | HCI_PERIODIC_INQUIRY_MODE = 0x0003, | ||
| 222 | HCI_EXIT_PERIODIC_INQUIRY_MODE = 0x0004, | ||
| 223 | HCI_CREATE_CONNECTION = 0x0005, | ||
| 224 | HCI_DISCONNECT = 0x0006, | ||
| 225 | HCI_CREATE_CONNECTION_CANCEL = 0x0008, | ||
| 226 | HCI_ACCEPT_CONNECTIONREQUEST = 0x0009, | ||
| 227 | HCI_REJECT_CONNECTION_REQUEST = 0x000a, | ||
| 228 | HCI_LINK_KEY_REQUEST_REPLY = 0x000b, | ||
| 229 | HCI_LINK_KEY_REQUEST_NEGATIVE_REPLY = 0x000c, | ||
| 230 | HCI_PIN_CODE_REQUEST_REPLY = 0x000d, | ||
| 231 | HCI_PIN_CODE_REQUEST_NEGATIVE_REPLY = 0x000e, | ||
| 232 | HCI_CHANGE_CONNECTION_PACKET_TYPE = 0x000f, | ||
| 233 | HCI_AUTHENTICATION_REQUESTED = 0x0011, | ||
| 234 | HCI_SET_CONNECTION_ENCRYPTION = 0x0013, | ||
| 235 | HCI_CHANGE_CONNECTION_LINK_KEY = 0x0015, | ||
| 236 | HCI_MASTER_LINK_KEY = 0x0017, | ||
| 237 | HCI_REMOTE_NAME_REQUEST = 0x0019, | ||
| 238 | HCI_REMOTE_NAME_REQUEST_CANCEL = 0x001a, | ||
| 239 | HCI_READ_REMOTE_SUPPORTED_FEATURES = 0x001b, | ||
| 240 | HCI_READ_REMOTE_EXTENDED_FEATURES = 0x001c, | ||
| 241 | HCI_READ_REMOTE_VERSION_INFORMATION = 0x001d, | ||
| 242 | HCI_READ_CLOCK_OFFSET = 0x001f, | ||
| 243 | HCI_READ_LMP_HANDLE = 0x0020, | ||
| 244 | HCI_SETUP_SYNCHRONOUS_CONNECTION = 0x0028, | ||
| 245 | HCI_ACCEPT_SYNCHRONOUS_CONNECTION_REQUEST = 0x0029, | ||
| 246 | HCI_REJECT_SYNCHRONOUS_CONNECTION_REQUEST = 0x002a, | ||
| 247 | HCI_IO_CAPABILITY_REQUEST_REPLY = 0x002b, | ||
| 248 | HCI_USER_CONFIRMATION_REQUEST_REPLY = 0x002c, | ||
| 249 | HCI_USER_CONFIRMATION_REQUEST_NEGATIVE_REPLY = 0x002d, | ||
| 250 | HCI_USER_PASSKEY_REQUEST_REPLY = 0x002e, | ||
| 251 | HCI_USER_PASSKEY_REQUESTNEGATIVE_REPLY = 0x002f, | ||
| 252 | HCI_REMOTE_OOB_DATA_REQUEST_REPLY = 0x0030, | ||
| 253 | HCI_REMOTE_OOB_DATA_REQUEST_NEGATIVE_REPLY = 0x0033, | ||
| 254 | HCI_IO_CAPABILITY_REQUEST_NEGATIVE_REPLY = 0x0034, | ||
| 255 | HCI_CREATE_PHYSICAL_LINK = 0x0035, | ||
| 256 | HCI_ACCEPT_PHYSICAL_LINK = 0x0036, | ||
| 257 | HCI_DISCONNECT_PHYSICAL_LINK = 0x0037, | ||
| 258 | HCI_CREATE_LOGICAL_LINK = 0x0038, | ||
| 259 | HCI_ACCEPT_LOGICAL_LINK = 0x0039, | ||
| 260 | HCI_DISCONNECT_LOGICAL_LINK = 0x003a, | ||
| 261 | HCI_LOGICAL_LINK_CANCEL = 0x003b, | ||
| 262 | HCI_FLOW_SPEC_MODIFY = 0x003c | ||
| 263 | }; | ||
| 264 | |||
| 265 | /* OGF 0x02 */ | ||
| 266 | #define HOLD_MODE_COMMAND 0x02 | ||
| 267 | enum hold_mode_command { | ||
| 268 | HCI_HOLD_MODE = 0x0001, | ||
| 269 | HCI_SNIFF_MODE = 0x0002, | ||
| 270 | HCI_EXIT_SNIFF_MODE = 0x0003, | ||
| 271 | HCI_PARK_STATE = 0x0005, | ||
| 272 | HCI_EXIT_PARK_STATE = 0x0006, | ||
| 273 | HCI_QOS_SETUP = 0x0007, | ||
| 274 | HCI_ROLE_DISCOVERY = 0x0009, | ||
| 275 | HCI_SWITCH_ROLE = 0x000b, | ||
| 276 | HCI_READ_LINK_POLICY_SETTINGS = 0x000c, | ||
| 277 | HCI_WRITE_LINK_POLICY_SETTINGS = 0x000d, | ||
| 278 | HCI_READ_DEFAULT_LINK_POLICY_SETTINGS = 0x000e, | ||
| 279 | HCI_WRITE_DEFAULT_LINK_POLICY_SETTINGS = 0x000f, | ||
| 280 | HCI_FLOW_SPECIFICATION = 0x0010, | ||
| 281 | HCI_SNIFF_SUBRATING = 0x0011 | ||
| 282 | }; | ||
| 283 | |||
| 284 | /* OGF 0x03 */ | ||
| 285 | #define OGF_SET_EVENT_MASK_COMMAND 0x03 | ||
| 286 | enum set_event_mask_command { | ||
| 287 | HCI_SET_EVENT_MASK = 0x0001, | ||
| 288 | HCI_RESET = 0x0003, | ||
| 289 | HCI_SET_EVENT_FILTER = 0x0005, | ||
| 290 | HCI_FLUSH = 0x0008, | ||
| 291 | HCI_READ_PIN_TYPE = 0x0009, | ||
| 292 | HCI_WRITE_PIN_TYPE = 0x000a, | ||
| 293 | HCI_CREATE_NEW_UNIT_KEY = 0x000b, | ||
| 294 | HCI_READ_STORED_LINK_KEY = 0x000d, | ||
| 295 | HCI_WRITE_STORED_LINK_KEY = 0x0011, | ||
| 296 | HCI_DELETE_STORED_LINK_KEY = 0x0012, | ||
| 297 | HCI_WRITE_LOCAL_NAME = 0x0013, | ||
| 298 | HCI_READ_LOCAL_NAME = 0x0014, | ||
| 299 | HCI_READ_CONNECTION_ACCEPT_TIMEOUT = 0x0015, | ||
| 300 | HCI_WRITE_CONNECTION_ACCEPT_TIMEOUT = 0x0016, | ||
| 301 | HCI_READ_PAGE_TIMEOUT = 0x0017, | ||
| 302 | HCI_WRITE_PAGE_TIMEOUT = 0x0018, | ||
| 303 | HCI_READ_SCAN_ENABLE = 0x0019, | ||
| 304 | HCI_WRITE_SCAN_ENABLE = 0x001a, | ||
| 305 | HCI_READ_PAGE_SCAN_ACTIVITY = 0x001b, | ||
| 306 | HCI_WRITE_PAGE_SCAN_ACTIVITY = 0x001c, | ||
| 307 | HCI_READ_INQUIRY_SCAN_ACTIVITY = 0x001d, | ||
| 308 | HCI_WRITE_INQUIRY_SCAN_ACTIVITY = 0x001e, | ||
| 309 | HCI_READ_AUTHENTICATION_ENABLE = 0x001f, | ||
| 310 | HCI_WRITE_AUTHENTICATION_ENABLE = 0x0020, | ||
| 311 | HCI_READ_CLASS_OF_DEVICE = 0x0023, | ||
| 312 | HCI_WRITE_CLASS_OF_DEVICE = 0x0024, | ||
| 313 | HCI_READ_VOICE_SETTING = 0x0025, | ||
| 314 | HCI_WRITE_VOICE_SETTING = 0x0026, | ||
| 315 | HCI_READ_AUTOMATIC_FLUSH_TIMEOUT = 0x0027, | ||
| 316 | HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT = 0x0028, | ||
| 317 | HCI_READ_NUM_BROADCAST_RETRANSMISSIONS = 0x0029, | ||
| 318 | HCI_WRITE_NUM_BROADCAST_RETRANSMISSIONS = 0x002a, | ||
| 319 | HCI_READ_HOLD_MODE_ACTIVITY = 0x002b, | ||
| 320 | HCI_WRITE_HOLD_MODE_ACTIVITY = 0x002c, | ||
| 321 | HCI_READ_SYNCHRONOUS_FLOW_CONTROL_ENABLE = 0x002e, | ||
| 322 | HCI_WRITE_SYNCHRONOUS_FLOW_CONTROL_ENABLE = 0x002f, | ||
| 323 | HCI_SET_CONTROLLER_TO_HOST_FLOW_CONTROL = 0x0031, | ||
| 324 | HCI_HOST_BUFFER_SIZE = 0x0033, | ||
| 325 | HCI_HOST_NUMBER_OF_COMPLETED_PACKETS = 0x0035, | ||
| 326 | HCI_READ_LINK_SUPERVISION_TIMEOUT = 0x0036, | ||
| 327 | HCI_WRITE_LINK_SUPERVISION_TIMEOUT = 0x0037, | ||
| 328 | HCI_READ_NUMBER_OF_SUPPORTED_IAC = 0x0038, | ||
| 329 | HCI_READ_CURRENT_IAC_LAP = 0x0039, | ||
| 330 | HCI_WRITE_CURRENT_IAC_LAP = 0x003a, | ||
| 331 | HCI_READ_PAGE_SCAN_MODE = 0x003d, | ||
| 332 | HCI_WRITE_PAGE_SCAN_MODE = 0x003e, | ||
| 333 | HCI_SET_AFH_HOST_CHANNEL_CLASSIFICATION = 0x003f, | ||
| 334 | HCI_READ_INQUIRY_SCAN_TYPE = 0x0042, | ||
| 335 | HCI_WRITE_INQUIRY_SCAN_TYPE = 0x0043, | ||
| 336 | HCI_READ_INQUIRY_MODE = 0x0044, | ||
| 337 | HCI_WRITE_INQUIRY_MODE = 0x0045, | ||
| 338 | HCI_READ_PAGE_SCAN_TYPE = 0x0046, | ||
| 339 | HCI_WRITE_PAGE_SCAN_TYPE = 0x0047, | ||
| 340 | HCI_READ_AFH_CHANNEL_ASSESSMENT_MODE = 0x0048, | ||
| 341 | HCI_WRITE_AFH_CHANNEL_ASSESSMENT_MODE = 0x0049, | ||
| 342 | HCI_READ_EXTENDED_INQUIRY_RESPONSE = 0x0051, | ||
| 343 | HCI_WRITE_EXTENDED_INQUIRY_RESPONSE = 0x0052, | ||
| 344 | HCI_REFRESH_ENCRYPTION_KEY = 0x0053, | ||
| 345 | HCI_READ_SIMPLE_PAIRING_MODE = 0x0055, | ||
| 346 | HCI_WRITE_SIMPLE_PAIRING_MODE = 0x0056, | ||
| 347 | HCI_READ_LOCAL_OOB_DATA = 0x0057, | ||
| 348 | HCI_READ_INQUIRY_RESPONSE_TRANSMIT_POWER_LEVEL = 0x0058, | ||
| 349 | HCI_WRITE_INQUIRY_TRANSMIT_POWER_LEVEL = 0x0059, | ||
| 350 | HCI_READ_DEFAULT_ERRONEOUS_DATA_REPORTING = 0x005a, | ||
| 351 | HCI_WRITE_DEFAULT_ERRONEOUS_DATA_REPORTING = 0x005b, | ||
| 352 | HCI_ENHANCED_FLUSH = 0x005f, | ||
| 353 | HCI_SEND_KEYPRESS_NOTIFICATION = 0x0060, | ||
| 354 | HCI_READ_LOGICAL_LINK_ACCEPT_TIMEOUT = 0x0061, | ||
| 355 | HCI_WRITE_LOGICAL_LINK_ACCEPT_TIMEOUT = 0x0062, | ||
| 356 | HCI_SET_EVENT_MASK_PAGE_2 = 0x0063, | ||
| 357 | HCI_READ_LOCATION_DATA = 0x0064, | ||
| 358 | HCI_WRITE_LOCATION_DATA = 0x0065, | ||
| 359 | HCI_READ_FLOW_CONTROL_MODE = 0x0066, | ||
| 360 | HCI_WRITE_FLOW_CONTROL_MODE = 0x0067, | ||
| 361 | HCI_READ_ENHANCE_TRANSMIT_POWER_LEVEL = 0x0068, | ||
| 362 | HCI_READ_BEST_EFFORT_FLUSH_TIMEOUT = 0x0069, | ||
| 363 | HCI_WRITE_BEST_EFFORT_FLUSH_TIMEOUT = 0x006a, | ||
| 364 | HCI_SHORT_RANGE_MODE = 0x006b | ||
| 365 | }; | ||
| 366 | |||
| 367 | /* OGF 0x04 */ | ||
| 368 | #define OGF_INFORMATIONAL_PARAMETERS 0x04 | ||
| 369 | enum informational_params { | ||
| 370 | HCI_READ_LOCAL_VERSION_INFORMATION = 0x0001, | ||
| 371 | HCI_READ_LOCAL_SUPPORTED_COMMANDS = 0x0002, | ||
| 372 | HCI_READ_LOCAL_SUPPORTED_FEATURES = 0x0003, | ||
| 373 | HCI_READ_LOCAL_EXTENDED_FEATURES = 0x0004, | ||
| 374 | HCI_READ_BUFFER_SIZE = 0x0005, | ||
| 375 | HCI_READ_BD_ADDR = 0x0009, | ||
| 376 | HCI_READ_DATA_BLOCK_SIZE = 0x000a | ||
| 377 | }; | ||
| 378 | |||
| 379 | /* OGF 0x05 */ | ||
| 380 | #define OGF_STATUS_PARAMETERS 0x05 | ||
| 381 | enum status_params { | ||
| 382 | HCI_READ_FAILED_CONTACT_COUNTER = 0x0001, | ||
| 383 | HCI_RESET_FAILED_CONTACT_COUNTER = 0x0002, | ||
| 384 | HCI_READ_LINK_QUALITY = 0x0003, | ||
| 385 | HCI_READ_RSSI = 0x0005, | ||
| 386 | HCI_READ_AFH_CHANNEL_MAP = 0x0006, | ||
| 387 | HCI_READ_CLOCK = 0x0007, | ||
| 388 | HCI_READ_ENCRYPTION_KEY_SIZE = 0x0008, | ||
| 389 | HCI_READ_LOCAL_AMP_INFO = 0x0009, | ||
| 390 | HCI_READ_LOCAL_AMP_ASSOC = 0x000a, | ||
| 391 | HCI_WRITE_REMOTE_AMP_ASSOC = 0x000b | ||
| 392 | }; | ||
| 393 | |||
| 394 | /* OGF 0x06 */ | ||
| 395 | #define OGF_TESTING_COMMANDS 0x06 | ||
| 396 | enum testing_commands { | ||
| 397 | HCI_READ_LOOPBACK_MODE = 0x0001, | ||
| 398 | HCI_WRITE_LOOPBACK_MODE = 0x0002, | ||
| 399 | HCI_ENABLE_DEVICE_UNDER_TEST_MODE = 0x0003, | ||
| 400 | HCI_WRITE_SIMPLE_PAIRING_DEBUG_MODE = 0x0004, | ||
| 401 | HCI_ENABLE_AMP_RECEIVER_REPORTS = 0x0007, | ||
| 402 | HCI_AMP_TEST_END = 0x0008, | ||
| 403 | HCI_AMP_TEST_COMMAND = 0x0009 | ||
| 404 | }; | ||
| 405 | |||
| 406 | /* OGF 0x3f */ | ||
| 407 | #define OGF_EXTENSION 0X3f | ||
| 408 | enum hci_extension_commands { | ||
| 409 | HCI_SET_ACL_LINK_DATA_FLOW_MODE = 0x0010, | ||
| 410 | HCI_SET_ACL_LINK_STATUS = 0x0020, | ||
| 411 | HCI_SET_SCO_LINK_STATUS = 0x0030, | ||
| 412 | HCI_SET_RSSI_VALUE = 0x0040, | ||
| 413 | HCI_SET_CURRENT_BLUETOOTH_STATUS = 0x0041, | ||
| 414 | |||
| 415 | /* The following is for RTK8723 */ | ||
| 416 | HCI_EXTENSION_VERSION_NOTIFY = 0x0100, | ||
| 417 | HCI_LINK_STATUS_NOTIFY = 0x0101, | ||
| 418 | HCI_BT_OPERATION_NOTIFY = 0x0102, | ||
| 419 | HCI_ENABLE_WIFI_SCAN_NOTIFY = 0x0103, | ||
| 420 | |||
| 421 | |||
| 422 | /* The following is for IVT */ | ||
| 423 | HCI_WIFI_CURRENT_CHANNEL = 0x0300, | ||
| 424 | HCI_WIFI_CURRENT_BANDWIDTH = 0x0301, | ||
| 425 | HCI_WIFI_CONNECTION_STATUS = 0x0302, | ||
| 426 | }; | ||
| 427 | |||
| 428 | enum bt_spec { | ||
| 429 | BT_SPEC_1_0_b = 0x00, | ||
| 430 | BT_SPEC_1_1 = 0x01, | ||
| 431 | BT_SPEC_1_2 = 0x02, | ||
| 432 | BT_SPEC_2_0_EDR = 0x03, | ||
| 433 | BT_SPEC_2_1_EDR = 0x04, | ||
| 434 | BT_SPEC_3_0_HS = 0x05, | ||
| 435 | BT_SPEC_4_0 = 0x06 | ||
| 436 | }; | ||
| 437 | |||
| 438 | /* The following is for BT 3.0 + HS EVENTS */ | ||
| 439 | enum hci_event { | ||
| 440 | HCI_EVENT_INQUIRY_COMPLETE = 0x01, | ||
| 441 | HCI_EVENT_INQUIRY_RESULT = 0x02, | ||
| 442 | HCI_EVENT_CONNECTION_COMPLETE = 0x03, | ||
| 443 | HCI_EVENT_CONNECTION_REQUEST = 0x04, | ||
| 444 | HCI_EVENT_DISCONNECTION_COMPLETE = 0x05, | ||
| 445 | HCI_EVENT_AUTHENTICATION_COMPLETE = 0x06, | ||
| 446 | HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE = 0x07, | ||
| 447 | HCI_EVENT_ENCRYPTION_CHANGE = 0x08, | ||
| 448 | HCI_EVENT_CHANGE_LINK_KEY_COMPLETE = 0x09, | ||
| 449 | HCI_EVENT_MASTER_LINK_KEY_COMPLETE = 0x0a, | ||
| 450 | HCI_EVENT_READ_REMOTE_SUPPORT_FEATURES_COMPLETE = 0x0b, | ||
| 451 | HCI_EVENT_READ_REMOTE_VER_INFO_COMPLETE = 0x0c, | ||
| 452 | HCI_EVENT_QOS_SETUP_COMPLETE = 0x0d, | ||
| 453 | HCI_EVENT_COMMAND_COMPLETE = 0x0e, | ||
| 454 | HCI_EVENT_COMMAND_STATUS = 0x0f, | ||
| 455 | HCI_EVENT_HARDWARE_ERROR = 0x10, | ||
| 456 | HCI_EVENT_FLUSH_OCCRUED = 0x11, | ||
| 457 | HCI_EVENT_ROLE_CHANGE = 0x12, | ||
| 458 | HCI_EVENT_NUMBER_OF_COMPLETE_PACKETS = 0x13, | ||
| 459 | HCI_EVENT_MODE_CHANGE = 0x14, | ||
| 460 | HCI_EVENT_RETURN_LINK_KEYS = 0x15, | ||
| 461 | HCI_EVENT_PIN_CODE_REQUEST = 0x16, | ||
| 462 | HCI_EVENT_LINK_KEY_REQUEST = 0x17, | ||
| 463 | HCI_EVENT_LINK_KEY_NOTIFICATION = 0x18, | ||
| 464 | HCI_EVENT_LOOPBACK_COMMAND = 0x19, | ||
| 465 | HCI_EVENT_DATA_BUFFER_OVERFLOW = 0x1a, | ||
| 466 | HCI_EVENT_MAX_SLOTS_CHANGE = 0x1b, | ||
| 467 | HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE = 0x1c, | ||
| 468 | HCI_EVENT_CONNECT_PACKET_TYPE_CHANGE = 0x1d, | ||
| 469 | HCI_EVENT_QOS_VIOLATION = 0x1e, | ||
| 470 | HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE = 0x20, | ||
| 471 | HCI_EVENT_FLOW_SEPC_COMPLETE = 0x21, | ||
| 472 | HCI_EVENT_INQUIRY_RESULT_WITH_RSSI = 0x22, | ||
| 473 | HCI_EVENT_READ_REMOTE_EXT_FEATURES_COMPLETE = 0x23, | ||
| 474 | HCI_EVENT_SYNC_CONNECT_COMPLETE = 0x2c, | ||
| 475 | HCI_EVENT_SYNC_CONNECT_CHANGE = 0x2d, | ||
| 476 | HCI_EVENT_SNIFFER_SUBRATING = 0x2e, | ||
| 477 | HCI_EVENT_EXTENTED_INQUIRY_RESULT = 0x2f, | ||
| 478 | HCI_EVENT_ENCRYPTION_KEY_REFLASH_COMPLETE = 0x30, | ||
| 479 | HCI_EVENT_IO_CAPIBILITY_COMPLETE = 0x31, | ||
| 480 | HCI_EVENT_IO_CAPIBILITY_RESPONSE = 0x32, | ||
| 481 | HCI_EVENT_USER_CONFIRMTION_REQUEST = 0x33, | ||
| 482 | HCI_EVENT_USER_PASSKEY_REQUEST = 0x34, | ||
| 483 | HCI_EVENT_REMOTE_OOB_DATA_REQUEST = 0x35, | ||
| 484 | HCI_EVENT_SIMPLE_PAIRING_COMPLETE = 0x36, | ||
| 485 | HCI_EVENT_LINK_SUPERVISION_TIMEOUT_CHANGE = 0x38, | ||
| 486 | HCI_EVENT_ENHANCED_FLUSH_COMPLETE = 0x39, | ||
| 487 | HCI_EVENT_USER_PASSKEY_NOTIFICATION = 0x3b, | ||
| 488 | HCI_EVENT_KEYPRESS_NOTIFICATION = 0x3c, | ||
| 489 | HCI_EVENT_REMOTE_HOST_SUPPORT_FEATURES_NOTIFICATION = 0x3d, | ||
| 490 | HCI_EVENT_PHY_LINK_COMPLETE = 0x40, | ||
| 491 | HCI_EVENT_CHANNEL_SELECT = 0x41, | ||
| 492 | HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE = 0x42, | ||
| 493 | HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING = 0x43, | ||
| 494 | HCI_EVENT_PHY_LINK_RECOVER = 0x44, | ||
| 495 | HCI_EVENT_LOGICAL_LINK_COMPLETE = 0x45, | ||
| 496 | HCI_EVENT_DISCONNECT_LOGICAL_LINK_COMPLETE = 0x46, | ||
| 497 | HCI_EVENT_FLOW_SPEC_MODIFY_COMPLETE = 0x47, | ||
| 498 | HCI_EVENT_NUM_OF_COMPLETE_DATA_BLOCKS = 0x48, | ||
| 499 | HCI_EVENT_AMP_START_TEST = 0x49, | ||
| 500 | HCI_EVENT_AMP_TEST_END = 0x4a, | ||
| 501 | HCI_EVENT_AMP_RECEIVER_REPORT = 0x4b, | ||
| 502 | HCI_EVENT_SHORT_RANGE_MODE_CHANGE_COMPLETE = 0x4c, | ||
| 503 | HCI_EVENT_AMP_STATUS_CHANGE = 0x4d, | ||
| 504 | HCI_EVENT_EXTENSION_RTK = 0xfe, | ||
| 505 | HCI_EVENT_EXTENSION_MOTO = 0xff, | ||
| 506 | }; | ||
| 507 | |||
| 508 | enum hci_extension_event_moto { | ||
| 509 | HCI_EVENT_GET_BT_RSSI = 0x01, | ||
| 510 | }; | ||
| 511 | |||
| 512 | enum hci_extension_event { | ||
| 513 | HCI_EVENT_EXT_WIFI_SCAN_NOTIFY = 0x01, | ||
| 514 | }; | ||
| 515 | |||
| 516 | enum hci_event_mask_page_2 { | ||
| 517 | EMP2_HCI_EVENT_PHY_LINK_COMPLETE = 0x0000000000000001, | ||
| 518 | EMP2_HCI_EVENT_CHANNEL_SELECT = 0x0000000000000002, | ||
| 519 | EMP2_HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE = 0x0000000000000004, | ||
| 520 | EMP2_HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING = 0x0000000000000008, | ||
| 521 | EMP2_HCI_EVENT_PHY_LINK_RECOVER = 0x0000000000000010, | ||
| 522 | EMP2_HCI_EVENT_LOGICAL_LINK_COMPLETE = 0x0000000000000020, | ||
| 523 | EMP2_HCI_EVENT_DISCONNECT_LOGICAL_LINK_COMPLETE = 0x0000000000000040, | ||
| 524 | EMP2_HCI_EVENT_FLOW_SPEC_MODIFY_COMPLETE = 0x0000000000000080, | ||
| 525 | EMP2_HCI_EVENT_NUM_OF_COMPLETE_DATA_BLOCKS = 0x0000000000000100, | ||
| 526 | EMP2_HCI_EVENT_AMP_START_TEST = 0x0000000000000200, | ||
| 527 | EMP2_HCI_EVENT_AMP_TEST_END = 0x0000000000000400, | ||
| 528 | EMP2_HCI_EVENT_AMP_RECEIVER_REPORT = 0x0000000000000800, | ||
| 529 | EMP2_HCI_EVENT_SHORT_RANGE_MODE_CHANGE_COMPLETE = 0x0000000000001000, | ||
| 530 | EMP2_HCI_EVENT_AMP_STATUS_CHANGE = 0x0000000000002000, | ||
| 531 | }; | ||
| 532 | |||
| 533 | enum hci_state_machine { | ||
| 534 | HCI_STATE_STARTING = 0x01, | ||
| 535 | HCI_STATE_CONNECTING = 0x02, | ||
| 536 | HCI_STATE_AUTHENTICATING = 0x04, | ||
| 537 | HCI_STATE_CONNECTED = 0x08, | ||
| 538 | HCI_STATE_DISCONNECTING = 0x10, | ||
| 539 | HCI_STATE_DISCONNECTED = 0x20 | ||
| 540 | }; | ||
| 541 | |||
| 542 | enum amp_assoc_structure_type { | ||
| 543 | AMP_MAC_ADDR = 0x01, | ||
| 544 | AMP_PREFERRED_CHANNEL_LIST = 0x02, | ||
| 545 | AMP_CONNECTED_CHANNEL = 0x03, | ||
| 546 | AMP_80211_PAL_CAP_LIST = 0x04, | ||
| 547 | AMP_80211_PAL_VISION = 0x05, | ||
| 548 | AMP_RESERVED_FOR_TESTING = 0x33 | ||
| 549 | }; | ||
| 550 | |||
| 551 | enum amp_btap_type { | ||
| 552 | AMP_BTAP_NONE, | ||
| 553 | AMP_BTAP_CREATOR, | ||
| 554 | AMP_BTAP_JOINER | ||
| 555 | }; | ||
| 556 | |||
| 557 | enum hci_state_with_cmd { | ||
| 558 | STATE_CMD_CREATE_PHY_LINK, | ||
| 559 | STATE_CMD_ACCEPT_PHY_LINK, | ||
| 560 | STATE_CMD_DISCONNECT_PHY_LINK, | ||
| 561 | STATE_CMD_CONNECT_ACCEPT_TIMEOUT, | ||
| 562 | STATE_CMD_MAC_START_COMPLETE, | ||
| 563 | STATE_CMD_MAC_START_FAILED, | ||
| 564 | STATE_CMD_MAC_CONNECT_COMPLETE, | ||
| 565 | STATE_CMD_MAC_CONNECT_FAILED, | ||
| 566 | STATE_CMD_MAC_DISCONNECT_INDICATE, | ||
| 567 | STATE_CMD_MAC_CONNECT_CANCEL_INDICATE, | ||
| 568 | STATE_CMD_4WAY_FAILED, | ||
| 569 | STATE_CMD_4WAY_SUCCESSED, | ||
| 570 | STATE_CMD_ENTER_STATE, | ||
| 571 | STATE_CMD_NO_SUCH_CMD, | ||
| 572 | }; | ||
| 573 | |||
| 574 | enum hci_service_type { | ||
| 575 | SERVICE_NO_TRAFFIC, | ||
| 576 | SERVICE_BEST_EFFORT, | ||
| 577 | SERVICE_GUARANTEE | ||
| 578 | }; | ||
| 579 | |||
| 580 | enum hci_traffic_mode { | ||
| 581 | TRAFFIC_MODE_BEST_EFFORT = 0x00, | ||
| 582 | TRAFFIC_MODE_GUARANTEED_LATENCY = 0x01, | ||
| 583 | TRAFFIC_MODE_GUARANTEED_BANDWIDTH = 0x02, | ||
| 584 | TRAFFIC_MODE_GUARANTEED_LATENCY_AND_BANDWIDTH = 0x03 | ||
| 585 | }; | ||
| 586 | |||
| 587 | #define HCIOPCODE(_OCF, _OGF) (_OGF<<10|_OCF) | ||
| 588 | #define HCIOPCODELOW(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)&0x00ff) | ||
| 589 | #define HCIOPCODEHIGHT(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)>>8) | ||
| 590 | |||
| 591 | #define TWOBYTE_HIGHTBYTE(_DATA) (u8)(_DATA>>8) | ||
| 592 | #define TWOBYTE_LOWBYTE(_DATA) (u8)(_DATA) | ||
| 593 | |||
| 594 | enum amp_status { | ||
| 595 | AMP_STATUS_AVA_PHY_PWR_DWN = 0x0, | ||
| 596 | AMP_STATUS_BT_USE_ONLY = 0x1, | ||
| 597 | AMP_STATUS_NO_CAPACITY_FOR_BT = 0x2, | ||
| 598 | AMP_STATUS_LOW_CAPACITY_FOR_BT = 0x3, | ||
| 599 | AMP_STATUS_MEDIUM_CAPACITY_FOR_BT = 0x4, | ||
| 600 | AMP_STATUS_HIGH_CAPACITY_FOR_BT = 0x5, | ||
| 601 | AMP_STATUS_FULL_CAPACITY_FOR_BT = 0x6 | ||
| 602 | }; | ||
| 603 | |||
| 604 | enum bt_wpa_msg_type { | ||
| 605 | Type_BT_4way1st = 0, | ||
| 606 | Type_BT_4way2nd = 1, | ||
| 607 | Type_BT_4way3rd = 2, | ||
| 608 | Type_BT_4way4th = 3, | ||
| 609 | Type_BT_unknow = 4 | ||
| 610 | }; | ||
| 611 | |||
| 612 | enum bt_connect_type { | ||
| 613 | BT_CONNECT_AUTH_REQ = 0x00, | ||
| 614 | BT_CONNECT_AUTH_RSP = 0x01, | ||
| 615 | BT_CONNECT_ASOC_REQ = 0x02, | ||
| 616 | BT_CONNECT_ASOC_RSP = 0x03, | ||
| 617 | BT_DISCONNECT = 0x04 | ||
| 618 | }; | ||
| 619 | |||
| 620 | enum bt_ll_service_type { | ||
| 621 | BT_LL_BE = 0x01, | ||
| 622 | BT_LL_GU = 0x02 | ||
| 623 | }; | ||
| 624 | |||
| 625 | enum bt_ll_flowspec { | ||
| 626 | BT_TX_BE_FS, /* TX best effort flowspec */ | ||
| 627 | BT_RX_BE_FS, /* RX best effort flowspec */ | ||
| 628 | BT_TX_GU_FS, /* TX guaranteed latency flowspec */ | ||
| 629 | BT_RX_GU_FS, /* RX guaranteed latency flowspec */ | ||
| 630 | BT_TX_BE_AGG_FS, /* TX aggregated best effort flowspec */ | ||
| 631 | BT_RX_BE_AGG_FS, /* RX aggregated best effort flowspec */ | ||
| 632 | BT_TX_GU_BW_FS, /* TX guaranteed bandwidth flowspec */ | ||
| 633 | BT_RX_GU_BW_FS, /* RX guaranteed bandwidth flowspec */ | ||
| 634 | BT_TX_GU_LARGE_FS, /* TX guaranteed latency flowspec, for testing only */ | ||
| 635 | BT_RX_GU_LARGE_FS, /* RX guaranteed latency flowspec, for testing only */ | ||
| 636 | }; | ||
| 637 | |||
| 638 | enum bt_traffic_mode { | ||
| 639 | BT_MOTOR_EXT_BE = 0x00, /* Best Effort. Default. for HCRP, PAN, SDP, RFCOMM-based profiles like FTP, OPP, SPP, DUN, etc. */ | ||
| 640 | BT_MOTOR_EXT_GUL = 0x01, /* Guaranteed Latency. This type of traffic is used e.g. for HID and AVRCP. */ | ||
| 641 | BT_MOTOR_EXT_GUB = 0X02, /* Guaranteed Bandwidth. */ | ||
| 642 | BT_MOTOR_EXT_GULB = 0X03 /* Guaranteed Latency and Bandwidth. for A2DP and VDP. */ | ||
| 643 | }; | ||
| 644 | |||
| 645 | enum bt_traffic_mode_profile { | ||
| 646 | BT_PROFILE_NONE, | ||
| 647 | BT_PROFILE_A2DP, | ||
| 648 | BT_PROFILE_PAN, | ||
| 649 | BT_PROFILE_HID, | ||
| 650 | BT_PROFILE_SCO | ||
| 651 | }; | ||
| 652 | |||
| 653 | enum bt_link_role { | ||
| 654 | BT_LINK_MASTER = 0, | ||
| 655 | BT_LINK_SLAVE = 1 | ||
| 656 | }; | ||
| 657 | |||
| 658 | enum bt_state_wpa_auth { | ||
| 659 | STATE_WPA_AUTH_UNINITIALIZED, | ||
| 660 | STATE_WPA_AUTH_WAIT_PACKET_1, /* Join */ | ||
| 661 | STATE_WPA_AUTH_WAIT_PACKET_2, /* Creat */ | ||
| 662 | STATE_WPA_AUTH_WAIT_PACKET_3, | ||
| 663 | STATE_WPA_AUTH_WAIT_PACKET_4, | ||
| 664 | STATE_WPA_AUTH_SUCCESSED | ||
| 665 | }; | ||
| 666 | |||
| 667 | #define BT_WPA_AUTH_TIMEOUT_PERIOD 1000 | ||
| 668 | #define BTMaxWPAAuthReTransmitCoun 5 | ||
| 669 | |||
| 670 | #define MAX_AMP_ASSOC_FRAG_LEN 248 | ||
| 671 | #define TOTAL_ALLOCIATE_ASSOC_LEN 1000 | ||
| 672 | |||
| 673 | struct hci_flow_spec { | ||
| 674 | u8 Identifier; | ||
| 675 | u8 ServiceType; | ||
| 676 | u16 MaximumSDUSize; | ||
| 677 | u32 SDUInterArrivalTime; | ||
| 678 | u32 AccessLatency; | ||
| 679 | u32 FlushTimeout; | ||
| 680 | }; | ||
| 681 | |||
| 682 | struct hci_log_link_cmd_data { | ||
| 683 | u8 BtPhyLinkhandle; | ||
| 684 | u16 BtLogLinkhandle; | ||
| 685 | u8 BtTxFlowSpecID; | ||
| 686 | struct hci_flow_spec Tx_Flow_Spec; | ||
| 687 | struct hci_flow_spec Rx_Flow_Spec; | ||
| 688 | u32 TxPacketCount; | ||
| 689 | u32 BestEffortFlushTimeout; | ||
| 690 | |||
| 691 | u8 bLLCompleteEventIsSet; | ||
| 692 | |||
| 693 | u8 bLLCancelCMDIsSetandComplete; | ||
| 694 | }; | ||
| 695 | |||
| 696 | struct hci_phy_link_cmd_data { | ||
| 697 | /* Physical_Link_Handle */ | ||
| 698 | u8 BtPhyLinkhandle; | ||
| 699 | |||
| 700 | u16 LinkSuperversionTimeout; | ||
| 701 | |||
| 702 | /* u16 SuperTimeOutCnt; */ | ||
| 703 | |||
| 704 | /* Dedicated_AMP_Key_Length */ | ||
| 705 | u8 BtAMPKeyLen; | ||
| 706 | /* Dedicated_AMP_Key_Type */ | ||
| 707 | u8 BtAMPKeyType; | ||
| 708 | /* Dedicated_AMP_Key */ | ||
| 709 | u8 BtAMPKey[PMK_LEN]; | ||
| 710 | }; | ||
| 711 | |||
| 712 | struct amp_assoc_structure { | ||
| 713 | /* TYPE ID */ | ||
| 714 | u8 TypeID; | ||
| 715 | /* Length */ | ||
| 716 | u16 Length; | ||
| 717 | /* Value */ | ||
| 718 | u8 Data[1]; | ||
| 719 | }; | ||
| 720 | |||
| 721 | struct amp_pref_chnl_regulatory { | ||
| 722 | u8 reXId; | ||
| 723 | u8 regulatoryClass; | ||
| 724 | u8 coverageClass; | ||
| 725 | }; | ||
| 726 | |||
| 727 | struct amp_assoc_cmd_data { | ||
| 728 | /* Physical_Link_Handle */ | ||
| 729 | u8 BtPhyLinkhandle; | ||
| 730 | /* Length_So_Far */ | ||
| 731 | u16 LenSoFar; | ||
| 732 | |||
| 733 | u16 MaxRemoteASSOCLen; | ||
| 734 | /* AMP_ASSOC_Remaining_Length */ | ||
| 735 | u16 AMPAssocRemLen; | ||
| 736 | /* AMP_ASSOC_fragment */ | ||
| 737 | void *AMPAssocfragment; | ||
| 738 | }; | ||
| 739 | |||
| 740 | struct hci_link_info { | ||
| 741 | u16 ConnectHandle; | ||
| 742 | u8 IncomingTrafficMode; | ||
| 743 | u8 OutgoingTrafficMode; | ||
| 744 | u8 BTProfile; | ||
| 745 | u8 BTCoreSpec; | ||
| 746 | s8 BT_RSSI; | ||
| 747 | u8 TrafficProfile; | ||
| 748 | u8 linkRole; | ||
| 749 | }; | ||
| 750 | |||
| 751 | struct hci_ext_config { | ||
| 752 | struct hci_link_info linkInfo[MAX_BT_ASOC_ENTRY_NUM]; | ||
| 753 | u8 btOperationCode; | ||
| 754 | u16 CurrentConnectHandle; | ||
| 755 | u8 CurrentIncomingTrafficMode; | ||
| 756 | u8 CurrentOutgoingTrafficMode; | ||
| 757 | s8 MIN_BT_RSSI; | ||
| 758 | u8 NumberOfHandle; | ||
| 759 | u8 NumberOfSCO; | ||
| 760 | u8 CurrentBTStatus; | ||
| 761 | u16 HCIExtensionVer; | ||
| 762 | |||
| 763 | /* Bt coexist related */ | ||
| 764 | u8 btProfileCase; | ||
| 765 | u8 btProfileAction; | ||
| 766 | u8 bManualControl; | ||
| 767 | u8 bBTBusy; | ||
| 768 | u8 bBTA2DPBusy; | ||
| 769 | u8 bEnableWifiScanNotify; | ||
| 770 | |||
| 771 | u8 bHoldForBtOperation; | ||
| 772 | u32 bHoldPeriodCnt; | ||
| 773 | }; | ||
| 774 | |||
| 775 | struct hci_acl_packet_data { | ||
| 776 | u16 ACLDataPacketLen; | ||
| 777 | u8 SyncDataPacketLen; | ||
| 778 | u16 TotalNumACLDataPackets; | ||
| 779 | u16 TotalSyncNumDataPackets; | ||
| 780 | }; | ||
| 781 | |||
| 782 | struct hci_phy_link_bss_info { | ||
| 783 | u16 bdCap; /* capability information */ | ||
| 784 | }; | ||
| 785 | |||
| 786 | struct packet_irp_hcicmd_data { | ||
| 787 | u16 OCF:10; | ||
| 788 | u16 OGF:6; | ||
| 789 | u8 Length; | ||
| 790 | u8 Data[20]; | ||
| 791 | }; | ||
| 792 | |||
| 793 | struct bt_asoc_entry { | ||
| 794 | u8 bUsed; | ||
| 795 | u8 mAssoc; | ||
| 796 | u8 b4waySuccess; | ||
| 797 | u8 Bssid[6]; | ||
| 798 | struct hci_phy_link_cmd_data PhyLinkCmdData; | ||
| 799 | |||
| 800 | struct hci_log_link_cmd_data LogLinkCmdData[MAX_LOGICAL_LINK_NUM]; | ||
| 801 | |||
| 802 | struct hci_acl_packet_data ACLPacketsData; | ||
| 803 | |||
| 804 | struct amp_assoc_cmd_data AmpAsocCmdData; | ||
| 805 | struct octet_string BTSsid; | ||
| 806 | u8 BTSsidBuf[33]; | ||
| 807 | |||
| 808 | enum hci_status PhyLinkDisconnectReason; | ||
| 809 | |||
| 810 | u8 bSendSupervisionPacket; | ||
| 811 | /* u8 CurrentSuervisionPacketSendNum; */ | ||
| 812 | /* u8 LastSuervisionPacketSendNum; */ | ||
| 813 | u32 NoRxPktCnt; | ||
| 814 | /* Is Creator or Joiner */ | ||
| 815 | enum amp_btap_type AMPRole; | ||
| 816 | |||
| 817 | /* BT current state */ | ||
| 818 | u8 BtCurrentState; | ||
| 819 | /* BT next state */ | ||
| 820 | u8 BtNextState; | ||
| 821 | |||
| 822 | u8 bNeedPhysLinkCompleteEvent; | ||
| 823 | |||
| 824 | enum hci_status PhysLinkCompleteStatus; | ||
| 825 | |||
| 826 | u8 BTRemoteMACAddr[6]; | ||
| 827 | |||
| 828 | u32 BTCapability; | ||
| 829 | |||
| 830 | u8 SyncDataPacketLen; | ||
| 831 | |||
| 832 | u16 TotalSyncNumDataPackets; | ||
| 833 | u16 TotalNumACLDataPackets; | ||
| 834 | |||
| 835 | u8 ShortRangeMode; | ||
| 836 | |||
| 837 | u8 PTK[PTK_LEN_TKIP]; | ||
| 838 | u8 GTK[GTK_LEN]; | ||
| 839 | u8 ANonce[KEY_NONCE_LEN]; | ||
| 840 | u8 SNonce[KEY_NONCE_LEN]; | ||
| 841 | u64 KeyReplayCounter; | ||
| 842 | u8 WPAAuthReplayCount; | ||
| 843 | u8 AESKeyBuf[AESCCMP_BLK_SIZE_TOTAL]; | ||
| 844 | u8 PMK[PMK_LEN]; | ||
| 845 | enum bt_state_wpa_auth BTWPAAuthState; | ||
| 846 | s32 UndecoratedSmoothedPWDB; | ||
| 847 | |||
| 848 | /* Add for HW security !! */ | ||
| 849 | u8 HwCAMIndex; /* Cam index */ | ||
| 850 | u8 bPeerQosSta; | ||
| 851 | |||
| 852 | u32 rxSuvpPktCnt; | ||
| 853 | }; | ||
| 854 | |||
| 855 | struct bt_traffic_statistics { | ||
| 856 | u8 bTxBusyTraffic; | ||
| 857 | u8 bRxBusyTraffic; | ||
| 858 | u8 bIdle; | ||
| 859 | u32 TxPktCntInPeriod; | ||
| 860 | u32 RxPktCntInPeriod; | ||
| 861 | u64 TxPktLenInPeriod; | ||
| 862 | u64 RxPktLenInPeriod; | ||
| 863 | }; | ||
| 864 | |||
| 865 | struct bt_mgnt { | ||
| 866 | u8 bBTConnectInProgress; | ||
| 867 | u8 bLogLinkInProgress; | ||
| 868 | u8 bPhyLinkInProgress; | ||
| 869 | u8 bPhyLinkInProgressStartLL; | ||
| 870 | u8 BtCurrentPhyLinkhandle; | ||
| 871 | u16 BtCurrentLogLinkhandle; | ||
| 872 | u8 CurrentConnectEntryNum; | ||
| 873 | u8 DisconnectEntryNum; | ||
| 874 | u8 CurrentBTConnectionCnt; | ||
| 875 | enum bt_connect_type BTCurrentConnectType; | ||
| 876 | enum bt_connect_type BTReceiveConnectPkt; | ||
| 877 | u8 BTAuthCount; | ||
| 878 | u8 BTAsocCount; | ||
| 879 | u8 bStartSendSupervisionPkt; | ||
| 880 | u8 BtOperationOn; | ||
| 881 | u8 BTNeedAMPStatusChg; | ||
| 882 | u8 JoinerNeedSendAuth; | ||
| 883 | struct hci_phy_link_bss_info bssDesc; | ||
| 884 | struct hci_ext_config ExtConfig; | ||
| 885 | u8 bNeedNotifyAMPNoCap; | ||
| 886 | u8 bCreateSpportQos; | ||
| 887 | u8 bSupportProfile; | ||
| 888 | u8 BTChannel; | ||
| 889 | u8 CheckChnlIsSuit; | ||
| 890 | u8 bBtScan; | ||
| 891 | u8 btLogoTest; | ||
| 892 | }; | ||
| 893 | |||
| 894 | struct bt_hci_dgb_info { | ||
| 895 | u32 hciCmdCnt; | ||
| 896 | u32 hciCmdCntUnknown; | ||
| 897 | u32 hciCmdCntCreatePhyLink; | ||
| 898 | u32 hciCmdCntAcceptPhyLink; | ||
| 899 | u32 hciCmdCntDisconnectPhyLink; | ||
| 900 | u32 hciCmdPhyLinkStatus; | ||
| 901 | u32 hciCmdCntCreateLogLink; | ||
| 902 | u32 hciCmdCntAcceptLogLink; | ||
| 903 | u32 hciCmdCntDisconnectLogLink; | ||
| 904 | u32 hciCmdCntReadLocalAmpAssoc; | ||
| 905 | u32 hciCmdCntWriteRemoteAmpAssoc; | ||
| 906 | u32 hciCmdCntSetAclLinkStatus; | ||
| 907 | u32 hciCmdCntSetScoLinkStatus; | ||
| 908 | u32 hciCmdCntExtensionVersionNotify; | ||
| 909 | u32 hciCmdCntLinkStatusNotify; | ||
| 910 | }; | ||
| 911 | |||
| 912 | struct bt_irp_dgb_info { | ||
| 913 | u32 irpMJCreate; | ||
| 914 | /* Io Control */ | ||
| 915 | u32 irpIoControl; | ||
| 916 | u32 irpIoCtrlHciCmd; | ||
| 917 | u32 irpIoCtrlHciEvent; | ||
| 918 | u32 irpIoCtrlHciTxData; | ||
| 919 | u32 irpIoCtrlHciRxData; | ||
| 920 | u32 irpIoCtrlUnknown; | ||
| 921 | |||
| 922 | u32 irpIoCtrlHciTxData1s; | ||
| 923 | }; | ||
| 924 | |||
| 925 | struct bt_packet_dgb_info { | ||
| 926 | u32 btPktTxProbReq; | ||
| 927 | u32 btPktRxProbReq; | ||
| 928 | u32 btPktRxProbReqFail; | ||
| 929 | u32 btPktTxProbRsp; | ||
| 930 | u32 btPktRxProbRsp; | ||
| 931 | u32 btPktTxAuth; | ||
| 932 | u32 btPktRxAuth; | ||
| 933 | u32 btPktRxAuthButDrop; | ||
| 934 | u32 btPktTxAssocReq; | ||
| 935 | u32 btPktRxAssocReq; | ||
| 936 | u32 btPktRxAssocReqButDrop; | ||
| 937 | u32 btPktTxAssocRsp; | ||
| 938 | u32 btPktRxAssocRsp; | ||
| 939 | u32 btPktTxDisassoc; | ||
| 940 | u32 btPktRxDisassoc; | ||
| 941 | u32 btPktRxDeauth; | ||
| 942 | u32 btPktTx4way1st; | ||
| 943 | u32 btPktRx4way1st; | ||
| 944 | u32 btPktTx4way2nd; | ||
| 945 | u32 btPktRx4way2nd; | ||
| 946 | u32 btPktTx4way3rd; | ||
| 947 | u32 btPktRx4way3rd; | ||
| 948 | u32 btPktTx4way4th; | ||
| 949 | u32 btPktRx4way4th; | ||
| 950 | u32 btPktTxLinkSuperReq; | ||
| 951 | u32 btPktRxLinkSuperReq; | ||
| 952 | u32 btPktTxLinkSuperRsp; | ||
| 953 | u32 btPktRxLinkSuperRsp; | ||
| 954 | u32 btPktTxData; | ||
| 955 | u32 btPktRxData; | ||
| 956 | }; | ||
| 957 | |||
| 958 | struct bt_dgb { | ||
| 959 | u8 dbgCtrl; | ||
| 960 | u32 dbgProfile; | ||
| 961 | struct bt_hci_dgb_info dbgHciInfo; | ||
| 962 | struct bt_irp_dgb_info dbgIrpInfo; | ||
| 963 | struct bt_packet_dgb_info dbgBtPkt; | ||
| 964 | }; | ||
| 965 | |||
| 966 | struct bt_hci_info { | ||
| 967 | /* 802.11 Pal version specifier */ | ||
| 968 | u8 BTPalVersion; | ||
| 969 | u16 BTPalCompanyID; | ||
| 970 | u16 BTPalsubversion; | ||
| 971 | |||
| 972 | /* Connected channel list */ | ||
| 973 | u16 BTConnectChnlListLen; | ||
| 974 | u8 BTConnectChnllist[64]; | ||
| 975 | |||
| 976 | /* Fail contact counter */ | ||
| 977 | u16 FailContactCount; | ||
| 978 | |||
| 979 | /* Event mask */ | ||
| 980 | u64 BTEventMask; | ||
| 981 | u64 BTEventMaskPage2; | ||
| 982 | |||
| 983 | /* timeout var */ | ||
| 984 | u16 ConnAcceptTimeout; | ||
| 985 | u16 LogicalAcceptTimeout; | ||
| 986 | u16 PageTimeout; | ||
| 987 | |||
| 988 | u8 LocationDomainAware; | ||
| 989 | u16 LocationDomain; | ||
| 990 | u8 LocationDomainOptions; | ||
| 991 | u8 LocationOptions; | ||
| 992 | |||
| 993 | u8 FlowControlMode; | ||
| 994 | |||
| 995 | /* Preferred channel list */ | ||
| 996 | u16 BtPreChnlListLen; | ||
| 997 | u8 BTPreChnllist[64]; | ||
| 998 | |||
| 999 | u16 enFlush_LLH; /* enhanced flush handle */ | ||
| 1000 | u16 FLTO_LLH; /* enhanced flush handle */ | ||
| 1001 | |||
| 1002 | /* */ | ||
| 1003 | /* Test command only. */ | ||
| 1004 | u8 bInTestMode; | ||
| 1005 | u8 bTestIsEnd; | ||
| 1006 | u8 bTestNeedReport; | ||
| 1007 | u8 TestScenario; | ||
| 1008 | u8 TestReportInterval; | ||
| 1009 | u8 TestCtrType; | ||
| 1010 | u32 TestEventType; | ||
| 1011 | u16 TestNumOfFrame; | ||
| 1012 | u16 TestNumOfErrFrame; | ||
| 1013 | u16 TestNumOfBits; | ||
| 1014 | u16 TestNumOfErrBits; | ||
| 1015 | /* */ | ||
| 1016 | }; | ||
| 1017 | |||
| 1018 | struct bt_traffic { | ||
| 1019 | /* Add for check replay data */ | ||
| 1020 | u8 LastRxUniFragNum; | ||
| 1021 | u16 LastRxUniSeqNum; | ||
| 1022 | |||
| 1023 | /* s32 EntryMaxUndecoratedSmoothedPWDB; */ | ||
| 1024 | /* s32 EntryMinUndecoratedSmoothedPWDB; */ | ||
| 1025 | |||
| 1026 | struct bt_traffic_statistics Bt30TrafficStatistics; | ||
| 1027 | }; | ||
| 1028 | |||
| 1029 | #define RT_WORK_ITEM struct work_struct | ||
| 1030 | |||
| 1031 | struct bt_security { | ||
| 1032 | /* WPA auth state | ||
| 1033 | * May need to remove to BTSecInfo ... | ||
| 1034 | * enum bt_state_wpa_auth BTWPAAuthState; | ||
| 1035 | */ | ||
| 1036 | struct octet_string RSNIE; | ||
| 1037 | u8 RSNIEBuf[MAXRSNIELEN]; | ||
| 1038 | u8 bRegNoEncrypt; | ||
| 1039 | u8 bUsedHwEncrypt; | ||
| 1040 | }; | ||
| 1041 | |||
| 1042 | struct bt_30info { | ||
| 1043 | struct rtw_adapter *padapter; | ||
| 1044 | struct bt_asoc_entry BtAsocEntry[MAX_BT_ASOC_ENTRY_NUM]; | ||
| 1045 | struct bt_mgnt BtMgnt; | ||
| 1046 | struct bt_dgb BtDbg; | ||
| 1047 | struct bt_hci_info BtHciInfo; | ||
| 1048 | struct bt_traffic BtTraffic; | ||
| 1049 | struct bt_security BtSec; | ||
| 1050 | RT_WORK_ITEM HCICmdWorkItem; | ||
| 1051 | struct timer_list BTHCICmdTimer; | ||
| 1052 | RT_WORK_ITEM BTPsDisableWorkItem; | ||
| 1053 | RT_WORK_ITEM BTConnectWorkItem; | ||
| 1054 | struct timer_list BTHCIDiscardAclDataTimer; | ||
| 1055 | struct timer_list BTHCIJoinTimeoutTimer; | ||
| 1056 | struct timer_list BTTestSendPacketTimer; | ||
| 1057 | struct timer_list BTDisconnectPhyLinkTimer; | ||
| 1058 | struct timer_list BTBeaconTimer; | ||
| 1059 | u8 BTBeaconTmrOn; | ||
| 1060 | |||
| 1061 | struct timer_list BTPsDisableTimer; | ||
| 1062 | |||
| 1063 | void * pBtChnlList; | ||
| 1064 | }; | ||
| 1065 | |||
| 1066 | struct packet_irp_acl_data { | ||
| 1067 | u16 Handle:12; | ||
| 1068 | u16 PB_Flag:2; | ||
| 1069 | u16 BC_Flag:2; | ||
| 1070 | u16 Length; | ||
| 1071 | u8 Data[1]; | ||
| 1072 | }; | ||
| 1073 | |||
| 1074 | struct packet_irp_hcievent_data { | ||
| 1075 | u8 EventCode; | ||
| 1076 | u8 Length; | ||
| 1077 | u8 Data[5]; | ||
| 1078 | }; | ||
| 1079 | |||
| 1080 | struct common_triple { | ||
| 1081 | u8 byte_1st; | ||
| 1082 | u8 byte_2nd; | ||
| 1083 | u8 byte_3rd; | ||
| 1084 | }; | ||
| 1085 | |||
| 1086 | #define COUNTRY_STR_LEN 3 /* country string len = 3 */ | ||
| 1087 | |||
| 1088 | #define LOCAL_PMK 0 | ||
| 1089 | |||
| 1090 | enum hci_wifi_connect_status { | ||
| 1091 | HCI_WIFI_NOT_CONNECTED = 0x0, | ||
| 1092 | HCI_WIFI_CONNECTED = 0x1, | ||
| 1093 | HCI_WIFI_CONNECT_IN_PROGRESS = 0x2, | ||
| 1094 | }; | ||
| 1095 | |||
| 1096 | enum hci_ext_bp_operation { | ||
| 1097 | HCI_BT_OP_NONE = 0x0, | ||
| 1098 | HCI_BT_OP_INQUIRY_START = 0x1, | ||
| 1099 | HCI_BT_OP_INQUIRY_FINISH = 0x2, | ||
| 1100 | HCI_BT_OP_PAGING_START = 0x3, | ||
| 1101 | HCI_BT_OP_PAGING_SUCCESS = 0x4, | ||
| 1102 | HCI_BT_OP_PAGING_UNSUCCESS = 0x5, | ||
| 1103 | HCI_BT_OP_PAIRING_START = 0x6, | ||
| 1104 | HCI_BT_OP_PAIRING_FINISH = 0x7, | ||
| 1105 | HCI_BT_OP_BT_DEV_ENABLE = 0x8, | ||
| 1106 | HCI_BT_OP_BT_DEV_DISABLE = 0x9, | ||
| 1107 | HCI_BT_OP_MAX | ||
| 1108 | }; | ||
| 1109 | |||
| 1110 | /* Function proto type */ | ||
| 1111 | struct btdata_entry { | ||
| 1112 | struct list_head List; | ||
| 1113 | void *pDataBlock; | ||
| 1114 | }; | ||
| 1115 | |||
| 1116 | #define BTHCI_SM_WITH_INFO(_Adapter, _StateToEnter, _StateCmd, _EntryNum) \ | ||
| 1117 | { \ | ||
| 1118 | RTPRINT(FIOCTL, IOCTL_STATE, ("[BT state change] caused by ""%s"", line =%d\n", __FUNCTION__, __LINE__)); \ | ||
| 1119 | BTHCI_StateMachine(_Adapter, _StateToEnter, _StateCmd, _EntryNum);\ | ||
| 1120 | } | ||
| 1121 | |||
| 1122 | void BTHCI_EventParse(struct rtw_adapter * padapter, void *pEvntData, u32 dataLen); | ||
| 1123 | #define BT_EventParse BTHCI_EventParse | ||
| 1124 | u8 BTHCI_HsConnectionEstablished(struct rtw_adapter * padapter); | ||
| 1125 | void BTHCI_UpdateBTProfileRTKToMoto(struct rtw_adapter * padapter); | ||
| 1126 | void BTHCI_WifiScanNotify(struct rtw_adapter * padapter, u8 scanType); | ||
| 1127 | void BTHCI_StateMachine(struct rtw_adapter * padapter, u8 StateToEnter, enum hci_state_with_cmd StateCmd, u8 EntryNum); | ||
| 1128 | void BTHCI_DisconnectPeer(struct rtw_adapter * padapter, u8 EntryNum); | ||
| 1129 | void BTHCI_EventNumOfCompletedDataBlocks(struct rtw_adapter * padapter); | ||
| 1130 | void BTHCI_EventAMPStatusChange(struct rtw_adapter * padapter, u8 AMP_Status); | ||
| 1131 | void BTHCI_DisconnectAll(struct rtw_adapter * padapter); | ||
| 1132 | enum hci_status BTHCI_HandleHCICMD(struct rtw_adapter * padapter, struct packet_irp_hcicmd_data *pHciCmd); | ||
| 1133 | |||
| 1134 | /* ===== End of sync from SD7 driver COMMON/bt_hci.h ===== */ | ||
| 1135 | #endif /* __BT_HCI_C__ */ | ||
| 1136 | |||
| 1137 | #ifdef __HALBTC87231ANT_C__ /* HAL/BTCoexist/HalBtc87231Ant.h */ | ||
| 1138 | /* ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtc87231Ant.h ===== */ | ||
| 1139 | #define GET_BT_INFO(padapter) (&GET_HAL_DATA(padapter)->BtInfo) | ||
| 1140 | |||
| 1141 | #define BTC_FOR_SCAN_START 1 | ||
| 1142 | #define BTC_FOR_SCAN_FINISH 0 | ||
| 1143 | |||
| 1144 | #define BT_TXRX_CNT_THRES_1 1200 | ||
| 1145 | #define BT_TXRX_CNT_THRES_2 1400 | ||
| 1146 | #define BT_TXRX_CNT_THRES_3 3000 | ||
| 1147 | #define BT_TXRX_CNT_LEVEL_0 0 /* < 1200 */ | ||
| 1148 | #define BT_TXRX_CNT_LEVEL_1 1 /* >= 1200 && < 1400 */ | ||
| 1149 | #define BT_TXRX_CNT_LEVEL_2 2 /* >= 1400 */ | ||
| 1150 | #define BT_TXRX_CNT_LEVEL_3 3 /* >= 3000 */ | ||
| 1151 | |||
| 1152 | enum bt_state_1ant { | ||
| 1153 | BT_INFO_STATE_DISABLED = 0, | ||
| 1154 | BT_INFO_STATE_NO_CONNECTION = 1, | ||
| 1155 | BT_INFO_STATE_CONNECT_IDLE = 2, | ||
| 1156 | BT_INFO_STATE_INQ_OR_PAG = 3, | ||
| 1157 | BT_INFO_STATE_ACL_ONLY_BUSY = 4, | ||
| 1158 | BT_INFO_STATE_SCO_ONLY_BUSY = 5, | ||
| 1159 | BT_INFO_STATE_ACL_SCO_BUSY = 6, | ||
| 1160 | BT_INFO_STATE_ACL_INQ_OR_PAG = 7, | ||
| 1161 | BT_INFO_STATE_MAX = 8 | ||
| 1162 | }; | ||
| 1163 | |||
| 1164 | struct btdm_8723a_1ant { | ||
| 1165 | u8 prePsTdma; | ||
| 1166 | u8 curPsTdma; | ||
| 1167 | u8 psTdmaDuAdjType; | ||
| 1168 | u8 bPrePsTdmaOn; | ||
| 1169 | u8 bCurPsTdmaOn; | ||
| 1170 | u8 preWifiPara; | ||
| 1171 | u8 curWifiPara; | ||
| 1172 | u8 preCoexWifiCon; | ||
| 1173 | u8 curCoexWifiCon; | ||
| 1174 | u8 wifiRssiThresh; | ||
| 1175 | |||
| 1176 | u32 psTdmaMonitorCnt; | ||
| 1177 | u32 psTdmaGlobalCnt; | ||
| 1178 | |||
| 1179 | /* DurationAdjust For SCO */ | ||
| 1180 | u32 psTdmaMonitorCntForSCO; | ||
| 1181 | u8 psTdmaDuAdjTypeForSCO; | ||
| 1182 | u8 RSSI_WiFi_Last; | ||
| 1183 | u8 RSSI_BT_Last; | ||
| 1184 | |||
| 1185 | u8 bWiFiHalt; | ||
| 1186 | u8 bRAChanged; | ||
| 1187 | }; | ||
| 1188 | |||
| 1189 | void BTDM_1AntSignalCompensation(struct rtw_adapter * padapter, u8 *rssi_wifi, u8 *rssi_bt); | ||
| 1190 | void BTDM_1AntForDhcp(struct rtw_adapter * padapter); | ||
| 1191 | void BTDM_1AntBtCoexist8723A(struct rtw_adapter * padapter); | ||
| 1192 | |||
| 1193 | /* ===== End of sync from SD7 driver HAL/BTCoexist/HalBtc87231Ant.h ===== */ | ||
| 1194 | #endif /* __HALBTC87231ANT_C__ */ | ||
| 1195 | |||
| 1196 | #ifdef __HALBTC87232ANT_C__ /* HAL/BTCoexist/HalBtc87232Ant.h */ | ||
| 1197 | /* ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtc87232Ant.h ===== */ | ||
| 1198 | enum bt_2ant_bt_status { | ||
| 1199 | BT_2ANT_BT_STATUS_IDLE = 0x0, | ||
| 1200 | BT_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, | ||
| 1201 | BT_2ANT_BT_STATUS_NON_IDLE = 0x2, | ||
| 1202 | BT_2ANT_BT_STATUS_MAX | ||
| 1203 | }; | ||
| 1204 | |||
| 1205 | enum bt_2ant_coex_algo { | ||
| 1206 | BT_2ANT_COEX_ALGO_UNDEFINED = 0x0, | ||
| 1207 | BT_2ANT_COEX_ALGO_SCO = 0x1, | ||
| 1208 | BT_2ANT_COEX_ALGO_HID = 0x2, | ||
| 1209 | BT_2ANT_COEX_ALGO_A2DP = 0x3, | ||
| 1210 | BT_2ANT_COEX_ALGO_PANEDR = 0x4, | ||
| 1211 | BT_2ANT_COEX_ALGO_PANHS = 0x5, | ||
| 1212 | BT_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6, | ||
| 1213 | BT_2ANT_COEX_ALGO_PANEDR_HID = 0x7, | ||
| 1214 | BT_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8, | ||
| 1215 | BT_2ANT_COEX_ALGO_HID_A2DP = 0x9, | ||
| 1216 | BT_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xA, | ||
| 1217 | BT_2ANT_COEX_ALGO_MAX = 0xB, | ||
| 1218 | }; | ||
| 1219 | |||
| 1220 | struct btdm_8723a_2ant { | ||
| 1221 | u8 bPreDecBtPwr; | ||
| 1222 | u8 bCurDecBtPwr; | ||
| 1223 | |||
| 1224 | u8 preWlanActHi; | ||
| 1225 | u8 curWlanActHi; | ||
| 1226 | u8 preWlanActLo; | ||
| 1227 | u8 curWlanActLo; | ||
| 1228 | |||
| 1229 | u8 preFwDacSwingLvl; | ||
| 1230 | u8 curFwDacSwingLvl; | ||
| 1231 | |||
| 1232 | u8 bPreRfRxLpfShrink; | ||
| 1233 | u8 bCurRfRxLpfShrink; | ||
| 1234 | |||
| 1235 | u8 bPreLowPenaltyRa; | ||
| 1236 | u8 bCurLowPenaltyRa; | ||
| 1237 | |||
| 1238 | u8 preBtRetryIndex; | ||
| 1239 | u8 curBtRetryIndex; | ||
| 1240 | |||
| 1241 | u8 bPreDacSwingOn; | ||
| 1242 | u32 preDacSwingLvl; | ||
| 1243 | u8 bCurDacSwingOn; | ||
| 1244 | u32 curDacSwingLvl; | ||
| 1245 | |||
| 1246 | u8 bPreAdcBackOff; | ||
| 1247 | u8 bCurAdcBackOff; | ||
| 1248 | |||
| 1249 | u8 bPreAgcTableEn; | ||
| 1250 | u8 bCurAgcTableEn; | ||
| 1251 | |||
| 1252 | u32 preVal0x6c0; | ||
| 1253 | u32 curVal0x6c0; | ||
| 1254 | u32 preVal0x6c8; | ||
| 1255 | u32 curVal0x6c8; | ||
| 1256 | u8 preVal0x6cc; | ||
| 1257 | u8 curVal0x6cc; | ||
| 1258 | |||
| 1259 | u8 bCurIgnoreWlanAct; | ||
| 1260 | u8 bPreIgnoreWlanAct; | ||
| 1261 | |||
| 1262 | u8 prePsTdma; | ||
| 1263 | u8 curPsTdma; | ||
| 1264 | u8 psTdmaDuAdjType; | ||
| 1265 | u8 bPrePsTdmaOn; | ||
| 1266 | u8 bCurPsTdmaOn; | ||
| 1267 | |||
| 1268 | u8 preAlgorithm; | ||
| 1269 | u8 curAlgorithm; | ||
| 1270 | u8 bResetTdmaAdjust; | ||
| 1271 | |||
| 1272 | u8 btStatus; | ||
| 1273 | }; | ||
| 1274 | |||
| 1275 | void BTDM_2AntBtCoexist8723A(struct rtw_adapter * padapter); | ||
| 1276 | /* ===== End of sync from SD7 driver HAL/BTCoexist/HalBtc87232Ant.h ===== */ | ||
| 1277 | #endif /* __HALBTC87232ANT_C__ */ | ||
| 1278 | |||
| 1279 | #ifdef __HALBTC8723_C__ /* HAL/BTCoexist/HalBtc8723.h */ | ||
| 1280 | /* ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtc8723.h ===== */ | ||
| 1281 | |||
| 1282 | #define BT_Q_PKT_OFF 0 | ||
| 1283 | #define BT_Q_PKT_ON 1 | ||
| 1284 | |||
| 1285 | #define BT_TX_PWR_OFF 0 | ||
| 1286 | #define BT_TX_PWR_ON 1 | ||
| 1287 | |||
| 1288 | /* TDMA mode definition */ | ||
| 1289 | #define TDMA_2ANT 0 | ||
| 1290 | #define TDMA_1ANT 1 | ||
| 1291 | #define TDMA_NAV_OFF 0 | ||
| 1292 | #define TDMA_NAV_ON 1 | ||
| 1293 | #define TDMA_DAC_SWING_OFF 0 | ||
| 1294 | #define TDMA_DAC_SWING_ON 1 | ||
| 1295 | |||
| 1296 | #define BT_RSSI_LEVEL_H 0 | ||
| 1297 | #define BT_RSSI_LEVEL_M 1 | ||
| 1298 | #define BT_RSSI_LEVEL_L 2 | ||
| 1299 | |||
| 1300 | /* PTA mode related definition */ | ||
| 1301 | #define BT_PTA_MODE_OFF 0 | ||
| 1302 | #define BT_PTA_MODE_ON 1 | ||
| 1303 | |||
| 1304 | /* Penalty Tx Rate Adaptive */ | ||
| 1305 | #define BT_TX_RATE_ADAPTIVE_NORMAL 0 | ||
| 1306 | #define BT_TX_RATE_ADAPTIVE_LOW_PENALTY 1 | ||
| 1307 | |||
| 1308 | /* RF Corner */ | ||
| 1309 | #define BT_RF_RX_LPF_CORNER_RESUME 0 | ||
| 1310 | #define BT_RF_RX_LPF_CORNER_SHRINK 1 | ||
| 1311 | |||
| 1312 | #define BT_INFO_ACL BIT(0) | ||
| 1313 | #define BT_INFO_SCO BIT(1) | ||
| 1314 | #define BT_INFO_INQ_PAG BIT(2) | ||
| 1315 | #define BT_INFO_ACL_BUSY BIT(3) | ||
| 1316 | #define BT_INFO_SCO_BUSY BIT(4) | ||
| 1317 | #define BT_INFO_HID BIT(5) | ||
| 1318 | #define BT_INFO_A2DP BIT(6) | ||
| 1319 | #define BT_INFO_FTP BIT(7) | ||
| 1320 | |||
| 1321 | |||
| 1322 | |||
| 1323 | struct bt_coexist_8723a { | ||
| 1324 | u32 highPriorityTx; | ||
| 1325 | u32 highPriorityRx; | ||
| 1326 | u32 lowPriorityTx; | ||
| 1327 | u32 lowPriorityRx; | ||
| 1328 | u8 btRssi; | ||
| 1329 | u8 TotalAntNum; | ||
| 1330 | u8 bC2hBtInfoSupport; | ||
| 1331 | u8 c2hBtInfo; | ||
| 1332 | u8 c2hBtInfoOriginal; | ||
| 1333 | u8 prec2hBtInfo; /* for 1Ant */ | ||
| 1334 | u8 bC2hBtInquiryPage; | ||
| 1335 | u64 btInqPageStartTime; /* for 2Ant */ | ||
| 1336 | u8 c2hBtProfile; /* for 1Ant */ | ||
| 1337 | u8 btRetryCnt; | ||
| 1338 | u8 btInfoExt; | ||
| 1339 | u8 bC2hBtInfoReqSent; | ||
| 1340 | u8 bForceFwBtInfo; | ||
| 1341 | u8 bForceA2dpSink; | ||
| 1342 | struct btdm_8723a_2ant btdm2Ant; | ||
| 1343 | struct btdm_8723a_1ant btdm1Ant; | ||
| 1344 | }; | ||
| 1345 | |||
| 1346 | void BTDM_SetFwChnlInfo(struct rtw_adapter * padapter, enum rt_media_status mstatus); | ||
| 1347 | u8 BTDM_IsWifiConnectionExist(struct rtw_adapter * padapter); | ||
| 1348 | void BTDM_SetFw3a(struct rtw_adapter * padapter, u8 byte1, u8 byte2, u8 byte3, u8 byte4, u8 byte5); | ||
| 1349 | void BTDM_QueryBtInformation(struct rtw_adapter * padapter); | ||
| 1350 | void BTDM_SetSwRfRxLpfCorner(struct rtw_adapter * padapter, u8 type); | ||
| 1351 | void BTDM_SetSwPenaltyTxRateAdaptive(struct rtw_adapter * padapter, u8 raType); | ||
| 1352 | void BTDM_SetFwDecBtPwr(struct rtw_adapter * padapter, u8 bDecBtPwr); | ||
| 1353 | u8 BTDM_BtProfileSupport(struct rtw_adapter * padapter); | ||
| 1354 | void BTDM_LpsLeave(struct rtw_adapter * padapter); | ||
| 1355 | u8 BTDM_1Ant8723A(struct rtw_adapter * padapter); | ||
| 1356 | #define BT_1Ant BTDM_1Ant8723A | ||
| 1357 | |||
| 1358 | /* ===== End of sync from SD7 driver HAL/BTCoexist/HalBtc8723.h ===== */ | ||
| 1359 | #endif /* __HALBTC8723_C__ */ | ||
| 1360 | |||
| 1361 | #ifdef __HALBTCCSR1ANT_C__ /* HAL/BTCoexist/HalBtcCsr1Ant.h */ | ||
| 1362 | /* ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtcCsr1Ant.h ===== */ | ||
| 1363 | |||
| 1364 | enum BT_A2DP_INDEX{ | ||
| 1365 | BT_A2DP_INDEX0 = 0, /* 32, 12; the most critical for BT */ | ||
| 1366 | BT_A2DP_INDEX1, /* 12, 24 */ | ||
| 1367 | BT_A2DP_INDEX2, /* 0, 0 */ | ||
| 1368 | BT_A2DP_INDEX_MAX | ||
| 1369 | }; | ||
| 1370 | |||
| 1371 | #define BT_A2DP_STATE_NOT_ENTERED 0 | ||
| 1372 | #define BT_A2DP_STATE_DETECTING 1 | ||
| 1373 | #define BT_A2DP_STATE_DETECTED 2 | ||
| 1374 | |||
| 1375 | #define BTDM_ANT_BT_IDLE 0 | ||
| 1376 | #define BTDM_ANT_WIFI 1 | ||
| 1377 | #define BTDM_ANT_BT 2 | ||
| 1378 | |||
| 1379 | |||
| 1380 | void BTDM_SingleAnt(struct rtw_adapter * padapter, u8 bSingleAntOn, u8 bInterruptOn, u8 bMultiNAVOn); | ||
| 1381 | void BTDM_CheckBTIdleChange1Ant(struct rtw_adapter * padapter); | ||
| 1382 | |||
| 1383 | /* ===== End of sync from SD7 driver HAL/BTCoexist/HalBtcCsr1Ant.h ===== */ | ||
| 1384 | #endif /* __HALBTCCSR1ANT_C__ */ | ||
| 1385 | |||
| 1386 | #ifdef __HALBTCCSR2ANT_C__ /* HAL/BTCoexist/HalBtcCsr2Ant.h */ | ||
| 1387 | /* ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtcCsr2Ant.h ===== */ | ||
| 1388 | |||
| 1389 | /* */ | ||
| 1390 | /* For old core stack before v251 */ | ||
| 1391 | /* */ | ||
| 1392 | #define BT_RSSI_STATE_NORMAL_POWER BIT0 | ||
| 1393 | #define BT_RSSI_STATE_AMDPU_OFF BIT1 | ||
| 1394 | #define BT_RSSI_STATE_SPECIAL_LOW BIT2 | ||
| 1395 | #define BT_RSSI_STATE_BG_EDCA_LOW BIT3 | ||
| 1396 | #define BT_RSSI_STATE_TXPOWER_LOW BIT4 | ||
| 1397 | |||
| 1398 | #define BT_DACSWING_OFF 0 | ||
| 1399 | #define BT_DACSWING_M4 1 | ||
| 1400 | #define BT_DACSWING_M7 2 | ||
| 1401 | #define BT_DACSWING_M10 3 | ||
| 1402 | |||
| 1403 | void BTDM_DiminishWiFi(struct rtw_adapter * Adapter, u8 bDACOn, u8 bInterruptOn, u8 DACSwingLevel, u8 bNAVOn); | ||
| 1404 | |||
| 1405 | /* ===== End of sync from SD7 driver HAL/BTCoexist/HalBtcCsr2Ant.h ===== */ | ||
| 1406 | #endif /* __HALBTCCSR2ANT_C__ */ | ||
| 1407 | |||
| 1408 | #ifdef __HALBTCOEXIST_C__ /* HAL/BTCoexist/HalBtCoexist.h */ | ||
| 1409 | |||
| 1410 | /* HEADER/TypeDef.h */ | ||
| 1411 | #define MAX_FW_SUPPORT_MACID_NUM 64 | ||
| 1412 | |||
| 1413 | /* ===== Below this line is sync from SD7 driver HAL/BTCoexist/HalBtCoexist.h ===== */ | ||
| 1414 | |||
| 1415 | #define FW_VER_BT_REG 62 | ||
| 1416 | #define FW_VER_BT_REG1 74 | ||
| 1417 | #define REG_BT_ACTIVE 0x444 | ||
| 1418 | #define REG_BT_STATE 0x448 | ||
| 1419 | #define REG_BT_POLLING1 0x44c | ||
| 1420 | #define REG_BT_POLLING 0x700 | ||
| 1421 | |||
| 1422 | #define REG_BT_ACTIVE_OLD 0x488 | ||
| 1423 | #define REG_BT_STATE_OLD 0x48c | ||
| 1424 | #define REG_BT_POLLING_OLD 0x490 | ||
| 1425 | |||
| 1426 | /* The reg define is for 8723 */ | ||
| 1427 | #define REG_HIGH_PRIORITY_TXRX 0x770 | ||
| 1428 | #define REG_LOW_PRIORITY_TXRX 0x774 | ||
| 1429 | |||
| 1430 | #define BT_FW_COEX_THRESH_TOL 6 | ||
| 1431 | #define BT_FW_COEX_THRESH_20 20 | ||
| 1432 | #define BT_FW_COEX_THRESH_23 23 | ||
| 1433 | #define BT_FW_COEX_THRESH_25 25 | ||
| 1434 | #define BT_FW_COEX_THRESH_30 30 | ||
| 1435 | #define BT_FW_COEX_THRESH_35 35 | ||
| 1436 | #define BT_FW_COEX_THRESH_40 40 | ||
| 1437 | #define BT_FW_COEX_THRESH_45 45 | ||
| 1438 | #define BT_FW_COEX_THRESH_47 47 | ||
| 1439 | #define BT_FW_COEX_THRESH_50 50 | ||
| 1440 | #define BT_FW_COEX_THRESH_55 55 | ||
| 1441 | #define BT_FW_COEX_THRESH_65 65 | ||
| 1442 | |||
| 1443 | #define BT_COEX_STATE_BT30 BIT(0) | ||
| 1444 | #define BT_COEX_STATE_WIFI_HT20 BIT(1) | ||
| 1445 | #define BT_COEX_STATE_WIFI_HT40 BIT(2) | ||
| 1446 | #define BT_COEX_STATE_WIFI_LEGACY BIT(3) | ||
| 1447 | |||
| 1448 | #define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4) | ||
| 1449 | #define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5) | ||
| 1450 | #define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6) | ||
| 1451 | #define BT_COEX_STATE_DEC_BT_POWER BIT(7) | ||
| 1452 | |||
| 1453 | #define BT_COEX_STATE_WIFI_IDLE BIT(8) | ||
| 1454 | #define BT_COEX_STATE_WIFI_UPLINK BIT(9) | ||
| 1455 | #define BT_COEX_STATE_WIFI_DOWNLINK BIT(10) | ||
| 1456 | |||
| 1457 | #define BT_COEX_STATE_BT_INQ_PAGE BIT(11) | ||
| 1458 | #define BT_COEX_STATE_BT_IDLE BIT(12) | ||
| 1459 | #define BT_COEX_STATE_BT_UPLINK BIT(13) | ||
| 1460 | #define BT_COEX_STATE_BT_DOWNLINK BIT(14) | ||
| 1461 | /* */ | ||
| 1462 | /* Todo: Remove these definitions */ | ||
| 1463 | #define BT_COEX_STATE_BT_PAN_IDLE BIT(15) | ||
| 1464 | #define BT_COEX_STATE_BT_PAN_UPLINK BIT(16) | ||
| 1465 | #define BT_COEX_STATE_BT_PAN_DOWNLINK BIT(17) | ||
| 1466 | #define BT_COEX_STATE_BT_A2DP_IDLE BIT(18) | ||
| 1467 | /* */ | ||
| 1468 | #define BT_COEX_STATE_BT_RSSI_LOW BIT(19) | ||
| 1469 | |||
| 1470 | #define BT_COEX_STATE_PROFILE_HID BIT(20) | ||
| 1471 | #define BT_COEX_STATE_PROFILE_A2DP BIT(21) | ||
| 1472 | #define BT_COEX_STATE_PROFILE_PAN BIT(22) | ||
| 1473 | #define BT_COEX_STATE_PROFILE_SCO BIT(23) | ||
| 1474 | |||
| 1475 | #define BT_COEX_STATE_WIFI_RSSI_1_LOW BIT(24) | ||
| 1476 | #define BT_COEX_STATE_WIFI_RSSI_1_MEDIUM BIT(25) | ||
| 1477 | #define BT_COEX_STATE_WIFI_RSSI_1_HIGH BIT(26) | ||
| 1478 | |||
| 1479 | #define BT_COEX_STATE_WIFI_RSSI_BEACON_LOW BIT(27) | ||
| 1480 | #define BT_COEX_STATE_WIFI_RSSI_BEACON_MEDIUM BIT(28) | ||
| 1481 | #define BT_COEX_STATE_WIFI_RSSI_BEACON_HIGH BIT(29) | ||
| 1482 | |||
| 1483 | |||
| 1484 | #define BT_COEX_STATE_BTINFO_COMMON BIT30 | ||
| 1485 | #define BT_COEX_STATE_BTINFO_B_HID_SCOESCO BIT31 | ||
| 1486 | #define BT_COEX_STATE_BTINFO_B_FTP_A2DP BIT32 | ||
| 1487 | |||
| 1488 | #define BT_COEX_STATE_BT_CNT_LEVEL_0 BIT33 | ||
| 1489 | #define BT_COEX_STATE_BT_CNT_LEVEL_1 BIT34 | ||
| 1490 | #define BT_COEX_STATE_BT_CNT_LEVEL_2 BIT35 | ||
| 1491 | #define BT_COEX_STATE_BT_CNT_LEVEL_3 BIT36 | ||
| 1492 | |||
| 1493 | #define BT_RSSI_STATE_HIGH 0 | ||
| 1494 | #define BT_RSSI_STATE_MEDIUM 1 | ||
| 1495 | #define BT_RSSI_STATE_LOW 2 | ||
| 1496 | #define BT_RSSI_STATE_STAY_HIGH 3 | ||
| 1497 | #define BT_RSSI_STATE_STAY_MEDIUM 4 | ||
| 1498 | #define BT_RSSI_STATE_STAY_LOW 5 | ||
| 1499 | |||
| 1500 | #define BT_AGCTABLE_OFF 0 | ||
| 1501 | #define BT_AGCTABLE_ON 1 | ||
| 1502 | |||
| 1503 | #define BT_BB_BACKOFF_OFF 0 | ||
| 1504 | #define BT_BB_BACKOFF_ON 1 | ||
| 1505 | |||
| 1506 | #define BT_FW_NAV_OFF 0 | ||
| 1507 | #define BT_FW_NAV_ON 1 | ||
| 1508 | |||
| 1509 | #define BT_COEX_MECH_NONE 0 | ||
| 1510 | #define BT_COEX_MECH_SCO 1 | ||
| 1511 | #define BT_COEX_MECH_HID 2 | ||
| 1512 | #define BT_COEX_MECH_A2DP 3 | ||
| 1513 | #define BT_COEX_MECH_PAN 4 | ||
| 1514 | #define BT_COEX_MECH_HID_A2DP 5 | ||
| 1515 | #define BT_COEX_MECH_HID_PAN 6 | ||
| 1516 | #define BT_COEX_MECH_PAN_A2DP 7 | ||
| 1517 | #define BT_COEX_MECH_HID_SCO_ESCO 8 | ||
| 1518 | #define BT_COEX_MECH_FTP_A2DP 9 | ||
| 1519 | #define BT_COEX_MECH_COMMON 10 | ||
| 1520 | #define BT_COEX_MECH_MAX 11 | ||
| 1521 | /* BT Dbg Ctrl */ | ||
| 1522 | #define BT_DBG_PROFILE_NONE 0 | ||
| 1523 | #define BT_DBG_PROFILE_SCO 1 | ||
| 1524 | #define BT_DBG_PROFILE_HID 2 | ||
| 1525 | #define BT_DBG_PROFILE_A2DP 3 | ||
| 1526 | #define BT_DBG_PROFILE_PAN 4 | ||
| 1527 | #define BT_DBG_PROFILE_HID_A2DP 5 | ||
| 1528 | #define BT_DBG_PROFILE_HID_PAN 6 | ||
| 1529 | #define BT_DBG_PROFILE_PAN_A2DP 7 | ||
| 1530 | #define BT_DBG_PROFILE_MAX 9 | ||
| 1531 | |||
| 1532 | struct bt_coexist_str { | ||
| 1533 | u8 BluetoothCoexist; | ||
| 1534 | u8 BT_Ant_Num; | ||
| 1535 | u8 BT_CoexistType; | ||
| 1536 | u8 BT_Ant_isolation; /* 0:good, 1:bad */ | ||
| 1537 | u8 bt_radiosharedtype; | ||
| 1538 | u32 Ratio_Tx; | ||
| 1539 | u32 Ratio_PRI; | ||
| 1540 | u8 bInitlized; | ||
| 1541 | u32 BtRfRegOrigin1E; | ||
| 1542 | u32 BtRfRegOrigin1F; | ||
| 1543 | u8 bBTBusyTraffic; | ||
| 1544 | u8 bBTTrafficModeSet; | ||
| 1545 | u8 bBTNonTrafficModeSet; | ||
| 1546 | struct bt_traffic_statistics BT21TrafficStatistics; | ||
| 1547 | u64 CurrentState; | ||
| 1548 | u64 PreviousState; | ||
| 1549 | u8 preRssiState; | ||
| 1550 | u8 preRssiState1; | ||
| 1551 | u8 preRssiStateBeacon; | ||
| 1552 | u8 bFWCoexistAllOff; | ||
| 1553 | u8 bSWCoexistAllOff; | ||
| 1554 | u8 bHWCoexistAllOff; | ||
| 1555 | u8 bBalanceOn; | ||
| 1556 | u8 bSingleAntOn; | ||
| 1557 | u8 bInterruptOn; | ||
| 1558 | u8 bMultiNAVOn; | ||
| 1559 | u8 PreWLANActH; | ||
| 1560 | u8 PreWLANActL; | ||
| 1561 | u8 WLANActH; | ||
| 1562 | u8 WLANActL; | ||
| 1563 | u8 A2DPState; | ||
| 1564 | u8 AntennaState; | ||
| 1565 | u32 lastBtEdca; | ||
| 1566 | u16 last_aggr_num; | ||
| 1567 | u8 bEDCAInitialized; | ||
| 1568 | u8 exec_cnt; | ||
| 1569 | u8 b8723aAgcTableOn; | ||
| 1570 | u8 b92DAgcTableOn; | ||
| 1571 | struct bt_coexist_8723a halCoex8723; | ||
| 1572 | u8 btActiveZeroCnt; | ||
| 1573 | u8 bCurBtDisabled; | ||
| 1574 | u8 bPreBtDisabled; | ||
| 1575 | u8 bNeedToRoamForBtDisableEnable; | ||
| 1576 | u8 fw3aVal[5]; | ||
| 1577 | }; | ||
| 1578 | |||
| 1579 | void BTDM_CheckAntSelMode(struct rtw_adapter * padapter); | ||
| 1580 | void BTDM_FwC2hBtRssi(struct rtw_adapter * padapter, u8 *tmpBuf); | ||
| 1581 | #define BT_FwC2hBtRssi BTDM_FwC2hBtRssi | ||
| 1582 | void BTDM_FwC2hBtInfo(struct rtw_adapter * padapter, u8 *tmpBuf, u8 length); | ||
| 1583 | #define BT_FwC2hBtInfo BTDM_FwC2hBtInfo | ||
| 1584 | void BTDM_DisplayBtCoexInfo(struct rtw_adapter * padapter); | ||
| 1585 | #define BT_DisplayBtCoexInfo BTDM_DisplayBtCoexInfo | ||
| 1586 | void BTDM_RejectAPAggregatedPacket(struct rtw_adapter * padapter, u8 bReject); | ||
| 1587 | u8 BTDM_IsHT40(struct rtw_adapter * padapter); | ||
| 1588 | u8 BTDM_Legacy(struct rtw_adapter * padapter); | ||
| 1589 | void BTDM_CheckWiFiState(struct rtw_adapter * padapter); | ||
| 1590 | s32 BTDM_GetRxSS(struct rtw_adapter * padapter); | ||
| 1591 | u8 BTDM_CheckCoexBcnRssiState(struct rtw_adapter * padapter, u8 levelNum, u8 RssiThresh, u8 RssiThresh1); | ||
| 1592 | u8 BTDM_CheckCoexRSSIState1(struct rtw_adapter * padapter, u8 levelNum, u8 RssiThresh, u8 RssiThresh1); | ||
| 1593 | u8 BTDM_CheckCoexRSSIState(struct rtw_adapter * padapter, u8 levelNum, u8 RssiThresh, u8 RssiThresh1); | ||
| 1594 | u8 BTDM_DisableEDCATurbo(struct rtw_adapter * padapter); | ||
| 1595 | #define BT_DisableEDCATurbo BTDM_DisableEDCATurbo | ||
| 1596 | void BTDM_Balance(struct rtw_adapter * padapter, u8 bBalanceOn, u8 ms0, u8 ms1); | ||
| 1597 | void BTDM_AGCTable(struct rtw_adapter * padapter, u8 type); | ||
| 1598 | void BTDM_BBBackOffLevel(struct rtw_adapter * padapter, u8 type); | ||
| 1599 | void BTDM_FWCoexAllOff(struct rtw_adapter * padapter); | ||
| 1600 | void BTDM_SWCoexAllOff(struct rtw_adapter * padapter); | ||
| 1601 | void BTDM_HWCoexAllOff(struct rtw_adapter * padapter); | ||
| 1602 | void BTDM_CoexAllOff(struct rtw_adapter * padapter); | ||
| 1603 | void BTDM_TurnOffBtCoexistBeforeEnterIPS(struct rtw_adapter * padapter); | ||
| 1604 | void BTDM_SignalCompensation(struct rtw_adapter * padapter, u8 *rssi_wifi, u8 *rssi_bt); | ||
| 1605 | void BTDM_Coexist(struct rtw_adapter * padapter); | ||
| 1606 | #define BT_CoexistMechanism BTDM_Coexist | ||
| 1607 | void BTDM_UpdateCoexState(struct rtw_adapter * padapter); | ||
| 1608 | u8 BTDM_IsSameCoexistState(struct rtw_adapter * padapter); | ||
| 1609 | void BTDM_PWDBMonitor(struct rtw_adapter * padapter); | ||
| 1610 | u8 BTDM_IsBTBusy(struct rtw_adapter * padapter); | ||
| 1611 | #define BT_IsBtBusy BTDM_IsBTBusy | ||
| 1612 | u8 BTDM_IsWifiBusy(struct rtw_adapter * padapter); | ||
| 1613 | u8 BTDM_IsCoexistStateChanged(struct rtw_adapter * padapter); | ||
| 1614 | u8 BTDM_IsWifiUplink(struct rtw_adapter * padapter); | ||
| 1615 | u8 BTDM_IsWifiDownlink(struct rtw_adapter * padapter); | ||
| 1616 | u8 BTDM_IsBTHSMode(struct rtw_adapter * padapter); | ||
| 1617 | u8 BTDM_IsBTUplink(struct rtw_adapter * padapter); | ||
| 1618 | u8 BTDM_IsBTDownlink(struct rtw_adapter * padapter); | ||
| 1619 | void BTDM_AdjustForBtOperation(struct rtw_adapter * padapter); | ||
| 1620 | void BTDM_ForHalt(struct rtw_adapter * padapter); | ||
| 1621 | void BTDM_WifiScanNotify(struct rtw_adapter * padapter, u8 scanType); | ||
| 1622 | void BTDM_WifiAssociateNotify(struct rtw_adapter * padapter, u8 action); | ||
| 1623 | void BTDM_MediaStatusNotify(struct rtw_adapter * padapter, enum rt_media_status mstatus); | ||
| 1624 | void BTDM_ForDhcp(struct rtw_adapter * padapter); | ||
| 1625 | void BTDM_ResetActionProfileState(struct rtw_adapter * padapter); | ||
| 1626 | void BTDM_SetBtCoexCurrAntNum(struct rtw_adapter * padapter, u8 antNum); | ||
| 1627 | #define BT_SetBtCoexCurrAntNum BTDM_SetBtCoexCurrAntNum | ||
| 1628 | u8 BTDM_IsActionSCO(struct rtw_adapter * padapter); | ||
| 1629 | u8 BTDM_IsActionHID(struct rtw_adapter * padapter); | ||
| 1630 | u8 BTDM_IsActionA2DP(struct rtw_adapter * padapter); | ||
| 1631 | u8 BTDM_IsActionPAN(struct rtw_adapter * padapter); | ||
| 1632 | u8 BTDM_IsActionHIDA2DP(struct rtw_adapter * padapter); | ||
| 1633 | u8 BTDM_IsActionHIDPAN(struct rtw_adapter * padapter); | ||
| 1634 | u8 BTDM_IsActionPANA2DP(struct rtw_adapter * padapter); | ||
| 1635 | u8 BTDM_IsBtDisabled(struct rtw_adapter * padapter); | ||
| 1636 | #define BT_IsBtDisabled BTDM_IsBtDisabled | ||
| 1637 | u32 BTDM_BtTxRxCounterH(struct rtw_adapter * padapter); | ||
| 1638 | u32 BTDM_BtTxRxCounterL(struct rtw_adapter * padapter); | ||
| 1639 | |||
| 1640 | /* ===== End of sync from SD7 driver HAL/BTCoexist/HalBtCoexist.h ===== */ | ||
| 1641 | #endif /* __HALBTCOEXIST_C__ */ | ||
| 1642 | |||
| 1643 | #ifdef __HALBT_C__ /* HAL/HalBT.h */ | ||
| 1644 | /* ===== Below this line is sync from SD7 driver HAL/HalBT.h ===== */ | ||
| 1645 | |||
| 1646 | #define RTS_CTS_NO_LEN_LIMIT 0 | ||
| 1647 | |||
| 1648 | u8 HALBT_GetPGAntNum(struct rtw_adapter * padapter); | ||
| 1649 | #define BT_GetPGAntNum HALBT_GetPGAntNum | ||
| 1650 | void HALBT_SetKey(struct rtw_adapter * padapter, u8 EntryNum); | ||
| 1651 | void HALBT_RemoveKey(struct rtw_adapter * padapter, u8 EntryNum); | ||
| 1652 | void HALBT_InitBTVars8723A(struct rtw_adapter * padapter); | ||
| 1653 | #define HALBT_InitHalVars HALBT_InitBTVars8723A | ||
| 1654 | #define BT_InitHalVars HALBT_InitHalVars | ||
| 1655 | u8 HALBT_IsBTExist(struct rtw_adapter * padapter); | ||
| 1656 | #define BT_IsBtExist HALBT_IsBTExist | ||
| 1657 | u8 HALBT_BTChipType(struct rtw_adapter * padapter); | ||
| 1658 | void HALBT_InitHwConfig(struct rtw_adapter * padapter); | ||
| 1659 | #define BT_InitHwConfig HALBT_InitHwConfig | ||
| 1660 | void HALBT_SetRtsCtsNoLenLimit(struct rtw_adapter * padapter); | ||
| 1661 | |||
| 1662 | /* ===== End of sync from SD7 driver HAL/HalBT.c ===== */ | ||
| 1663 | #endif /* __HALBT_C__ */ | ||
| 1664 | |||
| 1665 | #define _bt_dbg_off_ 0 | ||
| 1666 | #define _bt_dbg_on_ 1 | ||
| 1667 | |||
| 1668 | extern u32 BTCoexDbgLevel; | ||
| 1669 | |||
| 1670 | |||
| 1671 | |||
| 1672 | #endif /* __RTL8723A_BT_COEXIST_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_cmd.h b/drivers/staging/rtl8723au/include/rtl8723a_cmd.h new file mode 100644 index 000000000000..8fccbfc3a45c --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_cmd.h | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_CMD_H__ | ||
| 16 | #define __RTL8723A_CMD_H__ | ||
| 17 | |||
| 18 | |||
| 19 | #define H2C_BT_FW_PATCH_LEN 3 | ||
| 20 | #define H2C_BT_PWR_FORCE_LEN 3 | ||
| 21 | |||
| 22 | enum cmd_msg_element_id | ||
| 23 | { | ||
| 24 | NONE_CMDMSG_EID, | ||
| 25 | AP_OFFLOAD_EID = 0, | ||
| 26 | SET_PWRMODE_EID = 1, | ||
| 27 | JOINBSS_RPT_EID = 2, | ||
| 28 | RSVD_PAGE_EID = 3, | ||
| 29 | RSSI_4_EID = 4, | ||
| 30 | RSSI_SETTING_EID = 5, | ||
| 31 | MACID_CONFIG_EID = 6, | ||
| 32 | MACID_PS_MODE_EID = 7, | ||
| 33 | P2P_PS_OFFLOAD_EID = 8, | ||
| 34 | SELECTIVE_SUSPEND_ROF_CMD = 9, | ||
| 35 | BT_QUEUE_PKT_EID = 17, | ||
| 36 | BT_ANT_TDMA_EID = 20, | ||
| 37 | BT_2ANT_HID_EID = 21, | ||
| 38 | P2P_PS_CTW_CMD_EID = 32, | ||
| 39 | FORCE_BT_TX_PWR_EID = 33, | ||
| 40 | SET_TDMA_WLAN_ACT_TIME_EID = 34, | ||
| 41 | SET_BT_TX_RETRY_INDEX_EID = 35, | ||
| 42 | HID_PROFILE_ENABLE_EID = 36, | ||
| 43 | BT_IGNORE_WLAN_ACT_EID = 37, | ||
| 44 | BT_PTA_MANAGER_UPDATE_ENABLE_EID = 38, | ||
| 45 | DAC_SWING_VALUE_EID = 41, | ||
| 46 | TRADITIONAL_TDMA_EN_EID = 51, | ||
| 47 | H2C_BT_FW_PATCH = 54, | ||
| 48 | B_TYPE_TDMA_EID = 58, | ||
| 49 | SCAN_EN_EID = 59, | ||
| 50 | LOWPWR_LPS_EID = 71, | ||
| 51 | H2C_RESET_TSF = 75, | ||
| 52 | MAX_CMDMSG_EID | ||
| 53 | }; | ||
| 54 | |||
| 55 | struct cmd_msg_parm { | ||
| 56 | u8 eid; /* element id */ | ||
| 57 | u8 sz; /* sz */ | ||
| 58 | u8 buf[6]; | ||
| 59 | }; | ||
| 60 | |||
| 61 | struct setpwrmode_parm { | ||
| 62 | u8 Mode; | ||
| 63 | u8 SmartPS; | ||
| 64 | u8 AwakeInterval; /* unit: beacon interval */ | ||
| 65 | u8 bAllQueueUAPSD; | ||
| 66 | |||
| 67 | #define SETPM_LOWRXBCN BIT(0) | ||
| 68 | #define SETPM_AUTOANTSWITCH BIT(1) | ||
| 69 | #define SETPM_PSALLOWBTHIGHPRI BIT(2) | ||
| 70 | u8 BcnAntMode; | ||
| 71 | } __packed; | ||
| 72 | |||
| 73 | struct H2C_SS_RFOFF_PARAM{ | ||
| 74 | u8 ROFOn; /* 1: on, 0:off */ | ||
| 75 | u16 gpio_period; /* unit: 1024 us */ | ||
| 76 | }__attribute__ ((packed)); | ||
| 77 | |||
| 78 | |||
| 79 | struct joinbssrpt_parm { | ||
| 80 | u8 OpMode; /* enum rt_media_status */ | ||
| 81 | }; | ||
| 82 | |||
| 83 | struct rsvdpage_loc { | ||
| 84 | u8 LocProbeRsp; | ||
| 85 | u8 LocPsPoll; | ||
| 86 | u8 LocNullData; | ||
| 87 | u8 LocQosNull; | ||
| 88 | u8 LocBTQosNull; | ||
| 89 | }; | ||
| 90 | |||
| 91 | struct P2P_PS_Offload_t { | ||
| 92 | u8 Offload_En:1; | ||
| 93 | u8 role:1; /* 1: Owner, 0: Client */ | ||
| 94 | u8 CTWindow_En:1; | ||
| 95 | u8 NoA0_En:1; | ||
| 96 | u8 NoA1_En:1; | ||
| 97 | u8 AllStaSleep:1; /* Only valid in Owner */ | ||
| 98 | u8 discovery:1; | ||
| 99 | u8 rsvd:1; | ||
| 100 | }; | ||
| 101 | |||
| 102 | struct P2P_PS_CTWPeriod_t { | ||
| 103 | u8 CTWPeriod; /* TU */ | ||
| 104 | }; | ||
| 105 | |||
| 106 | #define B_TDMA_EN BIT(0) | ||
| 107 | #define B_TDMA_FIXANTINBT BIT(1) | ||
| 108 | #define B_TDMA_TXPSPOLL BIT(2) | ||
| 109 | #define B_TDMA_VAL870 BIT(3) | ||
| 110 | #define B_TDMA_AUTOWAKEUP BIT(4) | ||
| 111 | #define B_TDMA_NOPS BIT(5) | ||
| 112 | #define B_TDMA_WLANHIGHPRI BIT(6) | ||
| 113 | |||
| 114 | struct b_type_tdma_parm { | ||
| 115 | u8 option; | ||
| 116 | |||
| 117 | u8 TBTTOnPeriod; | ||
| 118 | u8 MedPeriod; | ||
| 119 | u8 rsvd30; | ||
| 120 | } __packed; | ||
| 121 | |||
| 122 | struct scan_en_parm { | ||
| 123 | u8 En; | ||
| 124 | } __packed; | ||
| 125 | |||
| 126 | /* BT_PWR */ | ||
| 127 | #define SET_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value) | ||
| 128 | |||
| 129 | /* BT_FW_PATCH */ | ||
| 130 | #define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 0, 8, __Value) /* SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) */ | ||
| 131 | #define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) /* SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value) */ | ||
| 132 | |||
| 133 | struct lowpwr_lps_parm{ | ||
| 134 | u8 bcn_count:4; | ||
| 135 | u8 tb_bcn_threshold:3; | ||
| 136 | u8 enable:1; | ||
| 137 | u8 bcn_interval; | ||
| 138 | u8 drop_threshold; | ||
| 139 | u8 max_early_period; | ||
| 140 | u8 max_bcn_timeout_period; | ||
| 141 | } __packed; | ||
| 142 | |||
| 143 | |||
| 144 | /* host message to firmware cmd */ | ||
| 145 | void rtl8723a_set_FwPwrMode_cmd(struct rtw_adapter * padapter, u8 Mode); | ||
| 146 | void rtl8723a_set_FwJoinBssReport_cmd(struct rtw_adapter * padapter, u8 mstatus); | ||
| 147 | #ifdef CONFIG_8723AU_BT_COEXIST | ||
| 148 | void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(struct rtw_adapter * padapter); | ||
| 149 | #endif | ||
| 150 | u8 rtl8723a_set_rssi_cmd(struct rtw_adapter * padapter, u8 *param); | ||
| 151 | u8 rtl8723a_set_raid_cmd(struct rtw_adapter * padapter, u32 mask, u8 arg); | ||
| 152 | void rtl8723a_add_rateatid(struct rtw_adapter * padapter, u32 bitmap, u8 arg, u8 rssi_level); | ||
| 153 | |||
| 154 | #ifdef CONFIG_8723AU_P2P | ||
| 155 | void rtl8723a_set_p2p_ps_offload_cmd(struct rtw_adapter * padapter, u8 p2p_ps_state); | ||
| 156 | #endif /* CONFIG_8723AU_P2P */ | ||
| 157 | |||
| 158 | void CheckFwRsvdPageContent23a(struct rtw_adapter *padapter); | ||
| 159 | |||
| 160 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_dm.h b/drivers/staging/rtl8723au/include/rtl8723a_dm.h new file mode 100644 index 000000000000..47e887f5bb26 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_dm.h | |||
| @@ -0,0 +1,144 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_DM_H__ | ||
| 16 | #define __RTL8723A_DM_H__ | ||
| 17 | /* */ | ||
| 18 | /* Description: */ | ||
| 19 | /* */ | ||
| 20 | /* This file is for 8723A dynamic mechanism only */ | ||
| 21 | /* */ | ||
| 22 | /* */ | ||
| 23 | /* */ | ||
| 24 | #define DYNAMIC_FUNC_BT BIT(0) | ||
| 25 | |||
| 26 | enum{ | ||
| 27 | UP_LINK, | ||
| 28 | DOWN_LINK, | ||
| 29 | }; | ||
| 30 | /* */ | ||
| 31 | /* structure and define */ | ||
| 32 | /* */ | ||
| 33 | |||
| 34 | /* duplicate code,will move to ODM ######### */ | ||
| 35 | #define IQK_MAC_REG_NUM 4 | ||
| 36 | #define IQK_ADDA_REG_NUM 16 | ||
| 37 | #define IQK_BB_REG_NUM 9 | ||
| 38 | #define HP_THERMAL_NUM 8 | ||
| 39 | /* duplicate code,will move to ODM ######### */ | ||
| 40 | struct dm_priv | ||
| 41 | { | ||
| 42 | u8 DM_Type; | ||
| 43 | u8 DMFlag; | ||
| 44 | u8 InitDMFlag; | ||
| 45 | u32 InitODMFlag; | ||
| 46 | |||
| 47 | /* Upper and Lower Signal threshold for Rate Adaptive*/ | ||
| 48 | int UndecoratedSmoothedPWDB; | ||
| 49 | int UndecoratedSmoothedCCK; | ||
| 50 | int EntryMinUndecoratedSmoothedPWDB; | ||
| 51 | int EntryMaxUndecoratedSmoothedPWDB; | ||
| 52 | int MinUndecoratedPWDBForDM; | ||
| 53 | int LastMinUndecoratedPWDBForDM; | ||
| 54 | |||
| 55 | s32 UndecoratedSmoothedBeacon; | ||
| 56 | #ifdef CONFIG_8723AU_BT_COEXIST | ||
| 57 | s32 BT_EntryMinUndecoratedSmoothedPWDB; | ||
| 58 | s32 BT_EntryMaxUndecoratedSmoothedPWDB; | ||
| 59 | #endif | ||
| 60 | |||
| 61 | /* for High Power */ | ||
| 62 | u8 bDynamicTxPowerEnable; | ||
| 63 | u8 LastDTPLvl; | ||
| 64 | u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */ | ||
| 65 | |||
| 66 | /* for tx power tracking */ | ||
| 67 | u8 bTXPowerTracking; | ||
| 68 | u8 TXPowercount; | ||
| 69 | u8 bTXPowerTrackingInit; | ||
| 70 | u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ | ||
| 71 | u8 TM_Trigger; | ||
| 72 | |||
| 73 | u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ | ||
| 74 | u8 ThermalValue; | ||
| 75 | u8 ThermalValue_LCK; | ||
| 76 | u8 ThermalValue_IQK; | ||
| 77 | u8 ThermalValue_DPK; | ||
| 78 | |||
| 79 | u8 bRfPiEnable; | ||
| 80 | |||
| 81 | /* for APK */ | ||
| 82 | u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ | ||
| 83 | u8 bAPKdone; | ||
| 84 | u8 bAPKThermalMeterIgnore; | ||
| 85 | u8 bDPdone; | ||
| 86 | u8 bDPPathAOK; | ||
| 87 | u8 bDPPathBOK; | ||
| 88 | |||
| 89 | /* for IQK */ | ||
| 90 | u32 RegC04; | ||
| 91 | u32 Reg874; | ||
| 92 | u32 RegC08; | ||
| 93 | u32 RegB68; | ||
| 94 | u32 RegB6C; | ||
| 95 | u32 Reg870; | ||
| 96 | u32 Reg860; | ||
| 97 | u32 Reg864; | ||
| 98 | u32 ADDA_backup[IQK_ADDA_REG_NUM]; | ||
| 99 | u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; | ||
| 100 | u32 IQK_BB_backup_recover[9]; | ||
| 101 | u32 IQK_BB_backup[IQK_BB_REG_NUM]; | ||
| 102 | u8 PowerIndex_backup[6]; | ||
| 103 | |||
| 104 | u8 bCCKinCH14; | ||
| 105 | |||
| 106 | u8 CCK_index; | ||
| 107 | u8 OFDM_index[2]; | ||
| 108 | |||
| 109 | u8 bDoneTxpower; | ||
| 110 | u8 CCK_index_HP; | ||
| 111 | u8 OFDM_index_HP[2]; | ||
| 112 | u8 ThermalValue_HP[HP_THERMAL_NUM]; | ||
| 113 | u8 ThermalValue_HP_index; | ||
| 114 | |||
| 115 | /* for TxPwrTracking */ | ||
| 116 | s32 RegE94; | ||
| 117 | s32 RegE9C; | ||
| 118 | s32 RegEB4; | ||
| 119 | s32 RegEBC; | ||
| 120 | |||
| 121 | u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ | ||
| 122 | |||
| 123 | u32 prv_traffic_idx; /* edca turbo */ | ||
| 124 | |||
| 125 | s32 OFDM_Pkt_Cnt; | ||
| 126 | u8 RSSI_Select; | ||
| 127 | /* u8 DIG_Dynamic_MIN ; */ | ||
| 128 | /* duplicate code,will move to ODM ######### */ | ||
| 129 | /* Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas */ | ||
| 130 | u8 INIDATA_RATE[32]; | ||
| 131 | }; | ||
| 132 | |||
| 133 | |||
| 134 | /* */ | ||
| 135 | /* function prototype */ | ||
| 136 | /* */ | ||
| 137 | |||
| 138 | void rtl8723a_init_dm_priv(struct rtw_adapter *padapter); | ||
| 139 | void rtl8723a_deinit_dm_priv(struct rtw_adapter *padapter); | ||
| 140 | |||
| 141 | void rtl8723a_InitHalDm(struct rtw_adapter *padapter); | ||
| 142 | void rtl8723a_HalDmWatchDog(struct rtw_adapter *padapter); | ||
| 143 | |||
| 144 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_hal.h b/drivers/staging/rtl8723au/include/rtl8723a_hal.h new file mode 100644 index 000000000000..c20248bab717 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_hal.h | |||
| @@ -0,0 +1,575 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_HAL_H__ | ||
| 16 | #define __RTL8723A_HAL_H__ | ||
| 17 | |||
| 18 | #include "rtl8723a_spec.h" | ||
| 19 | #include "rtl8723a_pg.h" | ||
| 20 | #include "Hal8723APhyReg.h" | ||
| 21 | #include "Hal8723APhyCfg.h" | ||
| 22 | #include "rtl8723a_rf.h" | ||
| 23 | #ifdef CONFIG_8723AU_BT_COEXIST | ||
| 24 | #include "rtl8723a_bt-coexist.h" | ||
| 25 | #endif | ||
| 26 | #include "rtl8723a_dm.h" | ||
| 27 | #include "rtl8723a_recv.h" | ||
| 28 | #include "rtl8723a_xmit.h" | ||
| 29 | #include "rtl8723a_cmd.h" | ||
| 30 | #include "rtl8723a_sreset.h" | ||
| 31 | #include "rtw_efuse.h" | ||
| 32 | |||
| 33 | #include "odm_precomp.h" | ||
| 34 | |||
| 35 | |||
| 36 | /* 2TODO: We should define 8192S firmware related macro settings here!! */ | ||
| 37 | #define RTL819X_DEFAULT_RF_TYPE RF_1T2R | ||
| 38 | #define RTL819X_TOTAL_RF_PATH 2 | ||
| 39 | |||
| 40 | /* TODO: The following need to check!! */ | ||
| 41 | #define RTL8723_FW_UMC_IMG "rtl8192CU\\rtl8723fw.bin" | ||
| 42 | #define RTL8723_FW_UMC_B_IMG "rtl8192CU\\rtl8723fw_B.bin" | ||
| 43 | #define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt" | ||
| 44 | #define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt" | ||
| 45 | #define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt" | ||
| 46 | #define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt" | ||
| 47 | #define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt" | ||
| 48 | #define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt" | ||
| 49 | #define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt" | ||
| 50 | |||
| 51 | /* */ | ||
| 52 | /* RTL8723S From header */ | ||
| 53 | /* */ | ||
| 54 | |||
| 55 | /* Fw Array */ | ||
| 56 | #define Rtl8723_FwImageArray Rtl8723UFwImgArray | ||
| 57 | #define Rtl8723_FwUMCBCutImageArrayWithBT Rtl8723UFwUMCBCutImgArrayWithBT | ||
| 58 | #define Rtl8723_FwUMCBCutImageArrayWithoutBT Rtl8723UFwUMCBCutImgArrayWithoutBT | ||
| 59 | |||
| 60 | #define Rtl8723_ImgArrayLength Rtl8723UImgArrayLength | ||
| 61 | #define Rtl8723_UMCBCutImgArrayWithBTLength Rtl8723UUMCBCutImgArrayWithBTLength | ||
| 62 | #define Rtl8723_UMCBCutImgArrayWithoutBTLength Rtl8723UUMCBCutImgArrayWithoutBTLength | ||
| 63 | |||
| 64 | #define Rtl8723_PHY_REG_Array_PG Rtl8723UPHY_REG_Array_PG | ||
| 65 | #define Rtl8723_PHY_REG_Array_PGLength Rtl8723UPHY_REG_Array_PGLength | ||
| 66 | |||
| 67 | #define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgAr | ||
| 68 | #define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength | ||
| 69 | |||
| 70 | #define DRVINFO_SZ 4 /* unit is 8bytes */ | ||
| 71 | #define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) | ||
| 72 | |||
| 73 | #define FW_8723A_SIZE 0x8000 | ||
| 74 | #define FW_8723A_START_ADDRESS 0x1000 | ||
| 75 | #define FW_8723A_END_ADDRESS 0x1FFF /* 0x5FFF */ | ||
| 76 | |||
| 77 | #define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */ | ||
| 78 | |||
| 79 | #define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ | ||
| 80 | (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ | ||
| 81 | (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300) | ||
| 82 | |||
| 83 | /* */ | ||
| 84 | /* This structure must be cared byte-ordering */ | ||
| 85 | /* */ | ||
| 86 | /* Added by tynli. 2009.12.04. */ | ||
| 87 | struct rt_8723a_firmware_hdr { | ||
| 88 | /* 8-byte alinment required */ | ||
| 89 | |||
| 90 | /* LONG WORD 0 ---- */ | ||
| 91 | u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ | ||
| 92 | u8 Category; /* AP/NIC and USB/PCI */ | ||
| 93 | u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ | ||
| 94 | u16 Version; /* FW Version */ | ||
| 95 | u8 Subversion; /* FW Subversion, default 0x00 */ | ||
| 96 | u16 Rsvd1; | ||
| 97 | |||
| 98 | |||
| 99 | /* LONG WORD 1 ---- */ | ||
| 100 | u8 Month; /* Release time Month field */ | ||
| 101 | u8 Date; /* Release time Date field */ | ||
| 102 | u8 Hour; /* Release time Hour field */ | ||
| 103 | u8 Minute; /* Release time Minute field */ | ||
| 104 | u16 RamCodeSize; /* The size of RAM code */ | ||
| 105 | u16 Rsvd2; | ||
| 106 | |||
| 107 | /* LONG WORD 2 ---- */ | ||
| 108 | u32 SvnIdx; /* The SVN entry index */ | ||
| 109 | u32 Rsvd3; | ||
| 110 | |||
| 111 | /* LONG WORD 3 ---- */ | ||
| 112 | u32 Rsvd4; | ||
| 113 | u32 Rsvd5; | ||
| 114 | }; | ||
| 115 | |||
| 116 | #define DRIVER_EARLY_INT_TIME 0x05 | ||
| 117 | #define BCN_DMA_ATIME_INT_TIME 0x02 | ||
| 118 | |||
| 119 | |||
| 120 | /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */ | ||
| 121 | #define MAX_TX_QUEUE 9 | ||
| 122 | |||
| 123 | #define TX_SELE_HQ BIT(0) /* High Queue */ | ||
| 124 | #define TX_SELE_LQ BIT(1) /* Low Queue */ | ||
| 125 | #define TX_SELE_NQ BIT(2) /* Normal Queue */ | ||
| 126 | |||
| 127 | /* Note: We will divide number of page equally for each queue other than public queue! */ | ||
| 128 | #define TX_TOTAL_PAGE_NUMBER 0xF8 | ||
| 129 | #define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1) | ||
| 130 | |||
| 131 | /* For Normal Chip Setting */ | ||
| 132 | /* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */ | ||
| 133 | #define NORMAL_PAGE_NUM_PUBQ 0xE7 | ||
| 134 | #define NORMAL_PAGE_NUM_HPQ 0x0C | ||
| 135 | #define NORMAL_PAGE_NUM_LPQ 0x02 | ||
| 136 | #define NORMAL_PAGE_NUM_NPQ 0x02 | ||
| 137 | |||
| 138 | /* For Test Chip Setting */ | ||
| 139 | /* (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */ | ||
| 140 | #define TEST_PAGE_NUM_PUBQ 0x7E | ||
| 141 | |||
| 142 | /* For Test Chip Setting */ | ||
| 143 | #define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5 | ||
| 144 | #define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */ | ||
| 145 | |||
| 146 | #define WMM_TEST_PAGE_NUM_PUBQ 0xA3 | ||
| 147 | #define WMM_TEST_PAGE_NUM_HPQ 0x29 | ||
| 148 | #define WMM_TEST_PAGE_NUM_LPQ 0x29 | ||
| 149 | |||
| 150 | /* Note: For Normal Chip Setting, modify later */ | ||
| 151 | #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 | ||
| 152 | #define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */ | ||
| 153 | |||
| 154 | #define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0 | ||
| 155 | #define WMM_NORMAL_PAGE_NUM_HPQ 0x29 | ||
| 156 | #define WMM_NORMAL_PAGE_NUM_LPQ 0x1C | ||
| 157 | #define WMM_NORMAL_PAGE_NUM_NPQ 0x1C | ||
| 158 | |||
| 159 | |||
| 160 | /* */ | ||
| 161 | /* Chip specific */ | ||
| 162 | /* */ | ||
| 163 | #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) | ||
| 164 | #define CHIP_BONDING_92C_1T2R 0x1 | ||
| 165 | #define CHIP_BONDING_88C_USB_MCARD 0x2 | ||
| 166 | #define CHIP_BONDING_88C_USB_HP 0x1 | ||
| 167 | |||
| 168 | #include "HalVerDef.h" | ||
| 169 | #include "hal_com.h" | ||
| 170 | |||
| 171 | /* */ | ||
| 172 | /* Channel Plan */ | ||
| 173 | /* */ | ||
| 174 | enum ChannelPlan | ||
| 175 | { | ||
| 176 | CHPL_FCC = 0, | ||
| 177 | CHPL_IC = 1, | ||
| 178 | CHPL_ETSI = 2, | ||
| 179 | CHPL_SPAIN = 3, | ||
| 180 | CHPL_FRANCE = 4, | ||
| 181 | CHPL_MKK = 5, | ||
| 182 | CHPL_MKK1 = 6, | ||
| 183 | CHPL_ISRAEL = 7, | ||
| 184 | CHPL_TELEC = 8, | ||
| 185 | CHPL_GLOBAL = 9, | ||
| 186 | CHPL_WORLD = 10, | ||
| 187 | }; | ||
| 188 | |||
| 189 | #define EFUSE_REAL_CONTENT_LEN 512 | ||
| 190 | #define EFUSE_MAP_LEN 128 | ||
| 191 | #define EFUSE_MAX_SECTION 16 | ||
| 192 | #define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ | ||
| 193 | #define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) | ||
| 194 | /* */ | ||
| 195 | /* <Roger_Notes> */ | ||
| 196 | /* To prevent out of boundary programming case, */ | ||
| 197 | /* leave 1byte and program full section */ | ||
| 198 | /* 9bytes + 1byt + 5bytes and pre 1byte. */ | ||
| 199 | /* For worst case: */ | ||
| 200 | /* | 1byte|----8bytes----|1byte|--5bytes--| */ | ||
| 201 | /* | | Reserved(14bytes) | */ | ||
| 202 | /* */ | ||
| 203 | |||
| 204 | /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ | ||
| 205 | #define EFUSE_OOB_PROTECT_BYTES 15 | ||
| 206 | |||
| 207 | #define EFUSE_REAL_CONTENT_LEN_8723A 512 | ||
| 208 | #define EFUSE_MAP_LEN_8723A 256 | ||
| 209 | #define EFUSE_MAX_SECTION_8723A 32 | ||
| 210 | |||
| 211 | /* */ | ||
| 212 | /* EFUSE for BT definition */ | ||
| 213 | /* */ | ||
| 214 | #define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 | ||
| 215 | #define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */ | ||
| 216 | #define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ | ||
| 217 | #define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ | ||
| 218 | |||
| 219 | #define EFUSE_PROTECT_BYTES_BANK 16 | ||
| 220 | |||
| 221 | /* */ | ||
| 222 | /* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */ | ||
| 223 | /* */ | ||
| 224 | enum RT_MULTI_FUNC { | ||
| 225 | RT_MULTI_FUNC_NONE = 0x00, | ||
| 226 | RT_MULTI_FUNC_WIFI = 0x01, | ||
| 227 | RT_MULTI_FUNC_BT = 0x02, | ||
| 228 | RT_MULTI_FUNC_GPS = 0x04, | ||
| 229 | }; | ||
| 230 | |||
| 231 | /* */ | ||
| 232 | /* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */ | ||
| 233 | /* */ | ||
| 234 | enum RT_POLARITY_CTL { | ||
| 235 | RT_POLARITY_LOW_ACT = 0, | ||
| 236 | RT_POLARITY_HIGH_ACT = 1, | ||
| 237 | }; | ||
| 238 | |||
| 239 | /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ | ||
| 240 | enum RT_REGULATOR_MODE { | ||
| 241 | RT_SWITCHING_REGULATOR = 0, | ||
| 242 | RT_LDO_REGULATOR = 1, | ||
| 243 | }; | ||
| 244 | |||
| 245 | /* Description: Determine the types of C2H events that are the same in driver and Fw. */ | ||
| 246 | /* Fisrt constructed by tynli. 2009.10.09. */ | ||
| 247 | enum { | ||
| 248 | C2H_DBG = 0, | ||
| 249 | C2H_TSF = 1, | ||
| 250 | C2H_AP_RPT_RSP = 2, | ||
| 251 | C2H_CCX_TX_RPT = 3, /* The FW notify the report of the specific tx packet. */ | ||
| 252 | C2H_BT_RSSI = 4, | ||
| 253 | C2H_BT_OP_MODE = 5, | ||
| 254 | C2H_EXT_RA_RPT = 6, | ||
| 255 | C2H_HW_INFO_EXCH = 10, | ||
| 256 | C2H_C2H_H2C_TEST = 11, | ||
| 257 | C2H_BT_INFO = 12, | ||
| 258 | C2H_BT_MP_INFO = 15, | ||
| 259 | MAX_C2HEVENT | ||
| 260 | }; | ||
| 261 | |||
| 262 | struct hal_data_8723a { | ||
| 263 | struct hal_version VersionID; | ||
| 264 | enum rt_customer_id CustomerID; | ||
| 265 | |||
| 266 | u16 FirmwareVersion; | ||
| 267 | u16 FirmwareVersionRev; | ||
| 268 | u16 FirmwareSubVersion; | ||
| 269 | u16 FirmwareSignature; | ||
| 270 | |||
| 271 | /* current WIFI_PHY values */ | ||
| 272 | u32 ReceiveConfig; | ||
| 273 | enum WIRELESS_MODE CurrentWirelessMode; | ||
| 274 | enum ht_channel_width CurrentChannelBW; | ||
| 275 | u8 CurrentChannel; | ||
| 276 | u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ | ||
| 277 | |||
| 278 | u16 BasicRateSet; | ||
| 279 | |||
| 280 | /* rf_ctrl */ | ||
| 281 | u8 rf_chip; | ||
| 282 | u8 rf_type; | ||
| 283 | u8 NumTotalRFPath; | ||
| 284 | |||
| 285 | u8 BoardType; | ||
| 286 | u8 CrystalCap; | ||
| 287 | /* */ | ||
| 288 | /* EEPROM setting. */ | ||
| 289 | /* */ | ||
| 290 | u8 EEPROMVersion; | ||
| 291 | u16 EEPROMVID; | ||
| 292 | u16 EEPROMPID; | ||
| 293 | u16 EEPROMSVID; | ||
| 294 | u16 EEPROMSDID; | ||
| 295 | u8 EEPROMCustomerID; | ||
| 296 | u8 EEPROMSubCustomerID; | ||
| 297 | u8 EEPROMRegulatory; | ||
| 298 | u8 EEPROMThermalMeter; | ||
| 299 | u8 EEPROMBluetoothCoexist; | ||
| 300 | u8 EEPROMBluetoothType; | ||
| 301 | u8 EEPROMBluetoothAntNum; | ||
| 302 | u8 EEPROMBluetoothAntIsolation; | ||
| 303 | u8 EEPROMBluetoothRadioShared; | ||
| 304 | |||
| 305 | u8 bTXPowerDataReadFromEEPORM; | ||
| 306 | u8 bAPKThermalMeterIgnore; | ||
| 307 | |||
| 308 | u8 bIQKInitialized; | ||
| 309 | u8 bAntennaDetected; | ||
| 310 | |||
| 311 | u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; | ||
| 312 | u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ | ||
| 313 | u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ | ||
| 314 | u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */ | ||
| 315 | u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */ | ||
| 316 | /* For power group */ | ||
| 317 | u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; | ||
| 318 | u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; | ||
| 319 | |||
| 320 | u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */ | ||
| 321 | |||
| 322 | /* Read/write are allow for following hardware information variables */ | ||
| 323 | u8 framesync; | ||
| 324 | u32 framesyncC34; | ||
| 325 | u8 framesyncMonitor; | ||
| 326 | u8 DefaultInitialGain[4]; | ||
| 327 | u8 pwrGroupCnt; | ||
| 328 | u32 MCSTxPowerLevelOriginalOffset[7][16]; | ||
| 329 | u32 CCKTxPowerLevelOriginalOffset; | ||
| 330 | |||
| 331 | u32 AntennaTxPath; /* Antenna path Tx */ | ||
| 332 | u32 AntennaRxPath; /* Antenna path Rx */ | ||
| 333 | u8 ExternalPA; | ||
| 334 | |||
| 335 | u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ | ||
| 336 | |||
| 337 | u8 b1x1RecvCombine; /* for 1T1R receive combining */ | ||
| 338 | |||
| 339 | /* For EDCA Turbo mode */ | ||
| 340 | |||
| 341 | u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ | ||
| 342 | |||
| 343 | /* vivi, for tx power tracking, 20080407 */ | ||
| 344 | /* u16 TSSI_13dBm; */ | ||
| 345 | /* u32 Pwr_Track; */ | ||
| 346 | /* The current Tx Power Level */ | ||
| 347 | u8 CurrentCckTxPwrIdx; | ||
| 348 | u8 CurrentOfdm24GTxPwrIdx; | ||
| 349 | |||
| 350 | struct bb_reg_define PHYRegDef[4]; /* Radio A/B/C/D */ | ||
| 351 | |||
| 352 | bool bRFPathRxEnable[4]; /* We support 4 RF path now. */ | ||
| 353 | |||
| 354 | u32 RfRegChnlVal[2]; | ||
| 355 | |||
| 356 | u8 bCckHighPower; | ||
| 357 | |||
| 358 | /* RDG enable */ | ||
| 359 | bool bRDGEnable; | ||
| 360 | |||
| 361 | /* for host message to fw */ | ||
| 362 | u8 LastHMEBoxNum; | ||
| 363 | |||
| 364 | u8 fw_ractrl; | ||
| 365 | u8 RegTxPause; | ||
| 366 | /* Beacon function related global variable. */ | ||
| 367 | u32 RegBcnCtrlVal; | ||
| 368 | u8 RegFwHwTxQCtrl; | ||
| 369 | u8 RegReg542; | ||
| 370 | |||
| 371 | struct dm_priv dmpriv; | ||
| 372 | struct dm_odm_t odmpriv; | ||
| 373 | struct sreset_priv srestpriv; | ||
| 374 | |||
| 375 | #ifdef CONFIG_8723AU_BT_COEXIST | ||
| 376 | u8 bBTMode; | ||
| 377 | /* BT only. */ | ||
| 378 | struct bt_30info BtInfo; | ||
| 379 | /* For bluetooth co-existance */ | ||
| 380 | struct bt_coexist_str bt_coexist; | ||
| 381 | #endif | ||
| 382 | |||
| 383 | u8 bDumpRxPkt;/* for debug */ | ||
| 384 | u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */ | ||
| 385 | |||
| 386 | /* 2010/08/09 MH Add CU power down mode. */ | ||
| 387 | u8 pwrdown; | ||
| 388 | |||
| 389 | /* Add for dual MAC 0--Mac0 1--Mac1 */ | ||
| 390 | u32 interfaceIndex; | ||
| 391 | |||
| 392 | u8 OutEpQueueSel; | ||
| 393 | u8 OutEpNumber; | ||
| 394 | |||
| 395 | /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ | ||
| 396 | bool UsbRxHighSpeedMode; | ||
| 397 | |||
| 398 | /* 2010/11/22 MH Add for slim combo debug mode selective. */ | ||
| 399 | /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */ | ||
| 400 | bool SlimComboDbg; | ||
| 401 | |||
| 402 | /* */ | ||
| 403 | /* Add For EEPROM Efuse switch and Efuse Shadow map Setting */ | ||
| 404 | /* */ | ||
| 405 | u8 EepromOrEfuse; | ||
| 406 | u16 EfuseUsedBytes; | ||
| 407 | u16 BTEfuseUsedBytes; | ||
| 408 | |||
| 409 | /* Interrupt relatd register information. */ | ||
| 410 | u32 SysIntrStatus; | ||
| 411 | u32 SysIntrMask; | ||
| 412 | |||
| 413 | /* */ | ||
| 414 | /* 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */ | ||
| 415 | /* independent file in the future. */ | ||
| 416 | /* */ | ||
| 417 | /* 8723-----------------------------------------*/ | ||
| 418 | enum RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ | ||
| 419 | enum RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ | ||
| 420 | enum RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ | ||
| 421 | /* 8723----------------------------------------- | ||
| 422 | * 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */ | ||
| 423 | /* independent file in the future. */ | ||
| 424 | |||
| 425 | bool bMACFuncEnable; | ||
| 426 | |||
| 427 | #ifdef CONFIG_8723AU_P2P | ||
| 428 | struct P2P_PS_Offload_t p2p_ps_offload; | ||
| 429 | #endif | ||
| 430 | |||
| 431 | |||
| 432 | /* */ | ||
| 433 | /* For USB Interface HAL related */ | ||
| 434 | /* */ | ||
| 435 | u32 UsbBulkOutSize; | ||
| 436 | |||
| 437 | /* Interrupt related register information. */ | ||
| 438 | u32 IntArray[2]; | ||
| 439 | u32 IntrMask[2]; | ||
| 440 | |||
| 441 | /* */ | ||
| 442 | /* For SDIO Interface HAL related */ | ||
| 443 | /* */ | ||
| 444 | |||
| 445 | /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ | ||
| 446 | u8 bMacPwrCtrlOn; | ||
| 447 | |||
| 448 | }; | ||
| 449 | |||
| 450 | #define GET_HAL_DATA(__pAdapter) ((struct hal_data_8723a *)((__pAdapter)->HalData)) | ||
| 451 | #define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) | ||
| 452 | |||
| 453 | #define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) | ||
| 454 | #define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) | ||
| 455 | |||
| 456 | struct rxreport_8723a { | ||
| 457 | u32 pktlen:14; | ||
| 458 | u32 crc32:1; | ||
| 459 | u32 icverr:1; | ||
| 460 | u32 drvinfosize:4; | ||
| 461 | u32 security:3; | ||
| 462 | u32 qos:1; | ||
| 463 | u32 shift:2; | ||
| 464 | u32 physt:1; | ||
| 465 | u32 swdec:1; | ||
| 466 | u32 ls:1; | ||
| 467 | u32 fs:1; | ||
| 468 | u32 eor:1; | ||
| 469 | u32 own:1; | ||
| 470 | |||
| 471 | u32 macid:5; | ||
| 472 | u32 tid:4; | ||
| 473 | u32 hwrsvd:4; | ||
| 474 | u32 amsdu:1; | ||
| 475 | u32 paggr:1; | ||
| 476 | u32 faggr:1; | ||
| 477 | u32 a1fit:4; | ||
| 478 | u32 a2fit:4; | ||
| 479 | u32 pam:1; | ||
| 480 | u32 pwr:1; | ||
| 481 | u32 md:1; | ||
| 482 | u32 mf:1; | ||
| 483 | u32 type:2; | ||
| 484 | u32 mc:1; | ||
| 485 | u32 bc:1; | ||
| 486 | |||
| 487 | u32 seq:12; | ||
| 488 | u32 frag:4; | ||
| 489 | u32 nextpktlen:14; | ||
| 490 | u32 nextind:1; | ||
| 491 | u32 rsvd0831:1; | ||
| 492 | |||
| 493 | u32 rxmcs:6; | ||
| 494 | u32 rxht:1; | ||
| 495 | u32 gf:1; | ||
| 496 | u32 splcp:1; | ||
| 497 | u32 bw:1; | ||
| 498 | u32 htc:1; | ||
| 499 | u32 eosp:1; | ||
| 500 | u32 bssidfit:2; | ||
| 501 | u32 rsvd1214:16; | ||
| 502 | u32 unicastwake:1; | ||
| 503 | u32 magicwake:1; | ||
| 504 | |||
| 505 | u32 pattern0match:1; | ||
| 506 | u32 pattern1match:1; | ||
| 507 | u32 pattern2match:1; | ||
| 508 | u32 pattern3match:1; | ||
| 509 | u32 pattern4match:1; | ||
| 510 | u32 pattern5match:1; | ||
| 511 | u32 pattern6match:1; | ||
| 512 | u32 pattern7match:1; | ||
| 513 | u32 pattern8match:1; | ||
| 514 | u32 pattern9match:1; | ||
| 515 | u32 patternamatch:1; | ||
| 516 | u32 patternbmatch:1; | ||
| 517 | u32 patterncmatch:1; | ||
| 518 | u32 rsvd1613:19; | ||
| 519 | |||
| 520 | u32 tsfl; | ||
| 521 | |||
| 522 | u32 bassn:12; | ||
| 523 | u32 bavld:1; | ||
| 524 | u32 rsvd2413:19; | ||
| 525 | }; | ||
| 526 | |||
| 527 | /* rtl8723a_hal_init.c */ | ||
| 528 | s32 rtl8723a_FirmwareDownload(struct rtw_adapter *padapter); | ||
| 529 | void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter); | ||
| 530 | void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter); | ||
| 531 | |||
| 532 | void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter); | ||
| 533 | void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter); | ||
| 534 | void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter); | ||
| 535 | void rtl8723a_init_default_value(struct rtw_adapter *padapter); | ||
| 536 | |||
| 537 | s32 InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary); | ||
| 538 | |||
| 539 | s32 CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU); | ||
| 540 | s32 CardDisableWithoutHWSM(struct rtw_adapter *padapter); | ||
| 541 | |||
| 542 | /* EFuse */ | ||
| 543 | u8 GetEEPROMSize8723A(struct rtw_adapter *padapter); | ||
| 544 | void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent); | ||
| 545 | void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo); | ||
| 546 | void Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter, u8 *PROMContent, bool AutoLoadFail); | ||
| 547 | void Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail); | ||
| 548 | void Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail); | ||
| 549 | void rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail); | ||
| 550 | void Hal_EfuseParseCustomerID(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail); | ||
| 551 | void Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail); | ||
| 552 | void Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail); | ||
| 553 | void Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter, u8 *hwinfo, u8 AutoLoadFail); | ||
| 554 | void Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter, u8 *hwinfo, u8 AutoLoadFail); | ||
| 555 | |||
| 556 | void Hal_InitChannelPlan23a(struct rtw_adapter *padapter); | ||
| 557 | |||
| 558 | void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc); | ||
| 559 | void SetHwReg8723A(struct rtw_adapter *padapter, u8 variable, u8 *val); | ||
| 560 | void GetHwReg8723A(struct rtw_adapter *padapter, u8 variable, u8 *val); | ||
| 561 | #ifdef CONFIG_8723AU_BT_COEXIST | ||
| 562 | void rtl8723a_SingleDualAntennaDetection(struct rtw_adapter *padapter); | ||
| 563 | #endif | ||
| 564 | |||
| 565 | /* register */ | ||
| 566 | void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits); | ||
| 567 | void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter); | ||
| 568 | |||
| 569 | void rtl8723a_clone_haldata(struct rtw_adapter *dst_adapter, struct rtw_adapter *src_adapter); | ||
| 570 | void rtl8723a_start_thread(struct rtw_adapter *padapter); | ||
| 571 | void rtl8723a_stop_thread(struct rtw_adapter *padapter); | ||
| 572 | |||
| 573 | s32 c2h_id_filter_ccx_8723a(u8 id); | ||
| 574 | |||
| 575 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_led.h b/drivers/staging/rtl8723au/include/rtl8723a_led.h new file mode 100644 index 000000000000..1623d186feb4 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_led.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_LED_H__ | ||
| 16 | #define __RTL8723A_LED_H__ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | |||
| 22 | /* */ | ||
| 23 | /* Interface to manipulate LED objects. */ | ||
| 24 | /* */ | ||
| 25 | void rtl8723au_InitSwLeds(struct rtw_adapter *padapter); | ||
| 26 | void rtl8723au_DeInitSwLeds(struct rtw_adapter *padapter); | ||
| 27 | void SwLedOn23a(struct rtw_adapter *padapter, struct led_8723a * pLed); | ||
| 28 | void SwLedOff23a(struct rtw_adapter *padapter, struct led_8723a * pLed); | ||
| 29 | |||
| 30 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_pg.h b/drivers/staging/rtl8723au/include/rtl8723a_pg.h new file mode 100644 index 000000000000..12f7a1326b4c --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_pg.h | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_PG_H__ | ||
| 16 | #define __RTL8723A_PG_H__ | ||
| 17 | |||
| 18 | /* */ | ||
| 19 | /* EEPROM/Efuse PG Offset for 8723E/8723U/8723S */ | ||
| 20 | /* */ | ||
| 21 | #define EEPROM_CCK_TX_PWR_INX_8723A 0x10 | ||
| 22 | #define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16 | ||
| 23 | #define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C | ||
| 24 | #define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F | ||
| 25 | #define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22 | ||
| 26 | #define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25 | ||
| 27 | |||
| 28 | #define EEPROM_ChannelPlan_8723A 0x28 | ||
| 29 | #define EEPROM_TSSI_A_8723A 0x29 | ||
| 30 | #define EEPROM_THERMAL_METER_8723A 0x2A | ||
| 31 | #define RF_OPTION1_8723A 0x2B | ||
| 32 | #define RF_OPTION2_8723A 0x2C | ||
| 33 | #define RF_OPTION3_8723A 0x2D | ||
| 34 | #define RF_OPTION4_8723A 0x2E | ||
| 35 | #define EEPROM_VERSION_8723A 0x30 | ||
| 36 | #define EEPROM_CustomID_8723A 0x31 | ||
| 37 | #define EEPROM_SubCustomID_8723A 0x32 | ||
| 38 | #define EEPROM_XTAL_K_8723A 0x33 | ||
| 39 | #define EEPROM_Chipset_8723A 0x34 | ||
| 40 | |||
| 41 | /* RTL8723AE */ | ||
| 42 | #define EEPROM_VID_8723AE 0x49 | ||
| 43 | #define EEPROM_DID_8723AE 0x4B | ||
| 44 | #define EEPROM_SVID_8723AE 0x4D | ||
| 45 | #define EEPROM_SMID_8723AE 0x4F | ||
| 46 | #define EEPROM_MAC_ADDR_8723AE 0x67 | ||
| 47 | |||
| 48 | /* RTL8723AU */ | ||
| 49 | #define EEPROM_MAC_ADDR_8723AU 0xC6 | ||
| 50 | #define EEPROM_VID_8723AU 0xB7 | ||
| 51 | #define EEPROM_PID_8723AU 0xB9 | ||
| 52 | |||
| 53 | /* RTL8723AS */ | ||
| 54 | #define EEPROM_MAC_ADDR_8723AS 0xAA | ||
| 55 | |||
| 56 | /* */ | ||
| 57 | /* EEPROM/Efuse Value Type */ | ||
| 58 | /* */ | ||
| 59 | #define EETYPE_TX_PWR 0x0 | ||
| 60 | |||
| 61 | /* */ | ||
| 62 | /* EEPROM/Efuse Default Value */ | ||
| 63 | /* */ | ||
| 64 | #define EEPROM_Default_CrystalCap_8723A 0x20 | ||
| 65 | |||
| 66 | |||
| 67 | /* */ | ||
| 68 | /* EEPROM/EFUSE data structure definition. */ | ||
| 69 | /* */ | ||
| 70 | #define MAX_RF_PATH_NUM 2 | ||
| 71 | #define MAX_CHNL_GROUP 3+9 | ||
| 72 | |||
| 73 | struct txpowerinfo { | ||
| 74 | u8 CCKIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; | ||
| 75 | u8 HT40_1SIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; | ||
| 76 | u8 HT40_2SIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; | ||
| 77 | u8 HT20IndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; | ||
| 78 | u8 OFDMIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; | ||
| 79 | u8 HT40MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; | ||
| 80 | u8 HT20MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP]; | ||
| 81 | u8 TSSI_A[3]; | ||
| 82 | u8 TSSI_B[3]; | ||
| 83 | u8 TSSI_A_5G[3]; /* 5GL/5GM/5GH */ | ||
| 84 | u8 TSSI_B_5G[3]; | ||
| 85 | }; | ||
| 86 | |||
| 87 | enum bt_ant_num { | ||
| 88 | Ant_x2 = 0, | ||
| 89 | Ant_x1 = 1 | ||
| 90 | }; | ||
| 91 | |||
| 92 | enum bt_cotype { | ||
| 93 | BT_2Wire = 0, | ||
| 94 | BT_ISSC_3Wire = 1, | ||
| 95 | BT_Accel = 2, | ||
| 96 | BT_CSR_BC4 = 3, | ||
| 97 | BT_CSR_BC8 = 4, | ||
| 98 | BT_RTL8756 = 5, | ||
| 99 | BT_RTL8723A = 6 | ||
| 100 | }; | ||
| 101 | |||
| 102 | enum bt_radioshared { | ||
| 103 | BT_Radio_Shared = 0, | ||
| 104 | BT_Radio_Individual = 1, | ||
| 105 | }; | ||
| 106 | |||
| 107 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_recv.h b/drivers/staging/rtl8723au/include/rtl8723a_recv.h new file mode 100644 index 000000000000..6bf6904f4d48 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_recv.h | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_RECV_H__ | ||
| 16 | #define __RTL8723A_RECV_H__ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | #define NR_RECVBUFF (4) | ||
| 22 | |||
| 23 | #define NR_PREALLOC_RECV_SKB (8) | ||
| 24 | |||
| 25 | #define RECV_BLK_SZ 512 | ||
| 26 | #define RECV_BLK_CNT 16 | ||
| 27 | #define RECV_BLK_TH RECV_BLK_CNT | ||
| 28 | |||
| 29 | #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ | ||
| 30 | |||
| 31 | #define RECV_BULK_IN_ADDR 0x80 | ||
| 32 | #define RECV_INT_IN_ADDR 0x81 | ||
| 33 | |||
| 34 | #define PHY_RSSI_SLID_WIN_MAX 100 | ||
| 35 | #define PHY_LINKQUALITY_SLID_WIN_MAX 20 | ||
| 36 | |||
| 37 | |||
| 38 | struct phy_stat | ||
| 39 | { | ||
| 40 | unsigned int phydw0; | ||
| 41 | unsigned int phydw1; | ||
| 42 | unsigned int phydw2; | ||
| 43 | unsigned int phydw3; | ||
| 44 | unsigned int phydw4; | ||
| 45 | unsigned int phydw5; | ||
| 46 | unsigned int phydw6; | ||
| 47 | unsigned int phydw7; | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* Rx smooth factor */ | ||
| 51 | #define Rx_Smooth_Factor (20) | ||
| 52 | |||
| 53 | struct interrupt_msg_format { | ||
| 54 | unsigned int C2H_MSG0; | ||
| 55 | unsigned int C2H_MSG1; | ||
| 56 | unsigned int C2H_MSG2; | ||
| 57 | unsigned int C2H_MSG3; | ||
| 58 | unsigned int HISR; /* from HISR Reg0x124, read to clear */ | ||
| 59 | unsigned int HISRE;/* from HISRE Reg0x12c, read to clear */ | ||
| 60 | unsigned int MSG_EX; | ||
| 61 | }; | ||
| 62 | |||
| 63 | void rtl8723au_init_recvbuf(struct rtw_adapter *padapter, struct recv_buf *precvbuf); | ||
| 64 | int rtl8723au_init_recv_priv(struct rtw_adapter * padapter); | ||
| 65 | void rtl8723au_free_recv_priv(struct rtw_adapter * padapter); | ||
| 66 | void rtl8723a_process_phy_info(struct rtw_adapter *padapter, void *prframe); | ||
| 67 | void update_recvframe_attrib(struct recv_frame *precvframe, struct recv_stat *prxstat); | ||
| 68 | void update_recvframe_phyinfo(struct recv_frame *precvframe, struct phy_stat *pphy_info); | ||
| 69 | |||
| 70 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_rf.h b/drivers/staging/rtl8723au/include/rtl8723a_rf.h new file mode 100644 index 000000000000..166a45fe47b1 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_rf.h | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_RF_H__ | ||
| 16 | #define __RTL8723A_RF_H__ | ||
| 17 | |||
| 18 | /*--------------------------Define Parameters-------------------------------*/ | ||
| 19 | |||
| 20 | /* */ | ||
| 21 | /* For RF 6052 Series */ | ||
| 22 | /* */ | ||
| 23 | #define RF6052_MAX_TX_PWR 0x3F | ||
| 24 | #define RF6052_MAX_REG 0x3F | ||
| 25 | #define RF6052_MAX_PATH 2 | ||
| 26 | /*--------------------------Define Parameters-------------------------------*/ | ||
| 27 | |||
| 28 | |||
| 29 | /*------------------------------Define structure----------------------------*/ | ||
| 30 | |||
| 31 | /*------------------------------Define structure----------------------------*/ | ||
| 32 | |||
| 33 | |||
| 34 | /*------------------------Export global variable----------------------------*/ | ||
| 35 | /*------------------------Export global variable----------------------------*/ | ||
| 36 | |||
| 37 | /*------------------------Export Marco Definition---------------------------*/ | ||
| 38 | |||
| 39 | /*------------------------Export Marco Definition---------------------------*/ | ||
| 40 | |||
| 41 | |||
| 42 | /*--------------------------Exported Function prototype---------------------*/ | ||
| 43 | |||
| 44 | /* */ | ||
| 45 | /* RF RL6052 Series API */ | ||
| 46 | /* */ | ||
| 47 | void rtl8723a_phy_rf6052set_bw(struct rtw_adapter *Adapter, | ||
| 48 | enum ht_channel_width Bandwidth); | ||
| 49 | void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, | ||
| 50 | u8* pPowerlevel); | ||
| 51 | void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter, | ||
| 52 | u8* pPowerLevel, u8 Channel); | ||
| 53 | |||
| 54 | /*--------------------------Exported Function prototype---------------------*/ | ||
| 55 | |||
| 56 | int PHY_RF6052_Config8723A(struct rtw_adapter *Adapter); | ||
| 57 | |||
| 58 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_spec.h b/drivers/staging/rtl8723au/include/rtl8723a_spec.h new file mode 100644 index 000000000000..3595c27907d0 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_spec.h | |||
| @@ -0,0 +1,2158 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | *******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_SPEC_H__ | ||
| 16 | #define __RTL8723A_SPEC_H__ | ||
| 17 | |||
| 18 | /* */ | ||
| 19 | /* */ | ||
| 20 | /* 0x0000h ~ 0x00FFh System Configuration */ | ||
| 21 | /* */ | ||
| 22 | /* */ | ||
| 23 | #define REG_SYS_ISO_CTRL 0x0000 | ||
| 24 | #define REG_SYS_FUNC_EN 0x0002 | ||
| 25 | #define REG_APS_FSMCO 0x0004 | ||
| 26 | #define REG_SYS_CLKR 0x0008 | ||
| 27 | #define REG_9346CR 0x000A | ||
| 28 | #define REG_EE_VPD 0x000C | ||
| 29 | #define REG_AFE_MISC 0x0010 | ||
| 30 | #define REG_SPS0_CTRL 0x0011 | ||
| 31 | #define REG_SPS_OCP_CFG 0x0018 | ||
| 32 | #define REG_RSV_CTRL 0x001C | ||
| 33 | #define REG_RF_CTRL 0x001F | ||
| 34 | #define REG_LDOA15_CTRL 0x0020 | ||
| 35 | #define REG_LDOV12D_CTRL 0x0021 | ||
| 36 | #define REG_LDOHCI12_CTRL 0x0022 | ||
| 37 | #define REG_LPLDO_CTRL 0x0023 | ||
| 38 | #define REG_AFE_XTAL_CTRL 0x0024 | ||
| 39 | #define REG_AFE_PLL_CTRL 0x0028 | ||
| 40 | #define REG_MAC_PHY_CTRL 0x002c | ||
| 41 | #define REG_EFUSE_CTRL 0x0030 | ||
| 42 | #define REG_EFUSE_TEST 0x0034 | ||
| 43 | #define REG_PWR_DATA 0x0038 | ||
| 44 | #define REG_CAL_TIMER 0x003C | ||
| 45 | #define REG_ACLK_MON 0x003E | ||
| 46 | #define REG_GPIO_MUXCFG 0x0040 | ||
| 47 | #define REG_GPIO_IO_SEL 0x0042 | ||
| 48 | #define REG_MAC_PINMUX_CFG 0x0043 | ||
| 49 | #define REG_GPIO_PIN_CTRL 0x0044 | ||
| 50 | #define REG_GPIO_INTM 0x0048 | ||
| 51 | #define REG_LEDCFG0 0x004C | ||
| 52 | #define REG_LEDCFG1 0x004D | ||
| 53 | #define REG_LEDCFG2 0x004E | ||
| 54 | #define REG_LEDCFG3 0x004F | ||
| 55 | #define REG_LEDCFG REG_LEDCFG2 | ||
| 56 | #define REG_FSIMR 0x0050 | ||
| 57 | #define REG_FSISR 0x0054 | ||
| 58 | #define REG_HSIMR 0x0058 | ||
| 59 | #define REG_HSISR 0x005c | ||
| 60 | /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ | ||
| 61 | #define REG_GPIO_PIN_CTRL_2 0x0060 | ||
| 62 | /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ | ||
| 63 | #define REG_GPIO_IO_SEL_2 0x0062 | ||
| 64 | /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ | ||
| 65 | #define REG_MULTI_FUNC_CTRL 0x0068 | ||
| 66 | #define REG_MCUFWDL 0x0080 | ||
| 67 | #define REG_HMEBOX_EXT_0 0x0088 | ||
| 68 | #define REG_HMEBOX_EXT_1 0x008A | ||
| 69 | #define REG_HMEBOX_EXT_2 0x008C | ||
| 70 | #define REG_HMEBOX_EXT_3 0x008E | ||
| 71 | /* Host suspend counter on FPGA platform */ | ||
| 72 | #define REG_HOST_SUSP_CNT 0x00BC | ||
| 73 | /* Efuse access protection for RTL8723 */ | ||
| 74 | #define REG_EFUSE_ACCESS 0x00CF | ||
| 75 | #define REG_BIST_SCAN 0x00D0 | ||
| 76 | #define REG_BIST_RPT 0x00D4 | ||
| 77 | #define REG_BIST_ROM_RPT 0x00D8 | ||
| 78 | #define REG_USB_SIE_INTF 0x00E0 | ||
| 79 | #define REG_PCIE_MIO_INTF 0x00E4 | ||
| 80 | #define REG_PCIE_MIO_INTD 0x00E8 | ||
| 81 | #define REG_HPON_FSM 0x00EC | ||
| 82 | #define REG_SYS_CFG 0x00F0 | ||
| 83 | #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ | ||
| 84 | |||
| 85 | /* */ | ||
| 86 | /* */ | ||
| 87 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ | ||
| 88 | /* */ | ||
| 89 | /* */ | ||
| 90 | #define REG_CR 0x0100 | ||
| 91 | #define REG_PBP 0x0104 | ||
| 92 | #define REG_TRXDMA_CTRL 0x010C | ||
| 93 | #define REG_TRXFF_BNDY 0x0114 | ||
| 94 | #define REG_TRXFF_STATUS 0x0118 | ||
| 95 | #define REG_RXFF_PTR 0x011C | ||
| 96 | #define REG_HIMR 0x0120 | ||
| 97 | #define REG_HISR 0x0124 | ||
| 98 | #define REG_HIMRE 0x0128 | ||
| 99 | #define REG_HISRE 0x012C | ||
| 100 | #define REG_CPWM 0x012F | ||
| 101 | #define REG_FWIMR 0x0130 | ||
| 102 | #define REG_FWISR 0x0134 | ||
| 103 | #define REG_PKTBUF_DBG_CTRL 0x0140 | ||
| 104 | #define REG_PKTBUF_DBG_DATA_L 0x0144 | ||
| 105 | #define REG_PKTBUF_DBG_DATA_H 0x0148 | ||
| 106 | |||
| 107 | #define REG_TC0_CTRL 0x0150 | ||
| 108 | #define REG_TC1_CTRL 0x0154 | ||
| 109 | #define REG_TC2_CTRL 0x0158 | ||
| 110 | #define REG_TC3_CTRL 0x015C | ||
| 111 | #define REG_TC4_CTRL 0x0160 | ||
| 112 | #define REG_TCUNIT_BASE 0x0164 | ||
| 113 | #define REG_MBIST_START 0x0174 | ||
| 114 | #define REG_MBIST_DONE 0x0178 | ||
| 115 | #define REG_MBIST_FAIL 0x017C | ||
| 116 | #define REG_C2HEVT_MSG_NORMAL 0x01A0 | ||
| 117 | #define REG_C2HEVT_CLEAR 0x01AF | ||
| 118 | #define REG_C2HEVT_MSG_TEST 0x01B8 | ||
| 119 | #define REG_MCUTST_1 0x01c0 | ||
| 120 | #define REG_FMETHR 0x01C8 | ||
| 121 | #define REG_HMETFR 0x01CC | ||
| 122 | #define REG_HMEBOX_0 0x01D0 | ||
| 123 | #define REG_HMEBOX_1 0x01D4 | ||
| 124 | #define REG_HMEBOX_2 0x01D8 | ||
| 125 | #define REG_HMEBOX_3 0x01DC | ||
| 126 | |||
| 127 | #define REG_LLT_INIT 0x01E0 | ||
| 128 | #define REG_BB_ACCEESS_CTRL 0x01E8 | ||
| 129 | #define REG_BB_ACCESS_DATA 0x01EC | ||
| 130 | |||
| 131 | |||
| 132 | /* */ | ||
| 133 | /* */ | ||
| 134 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ | ||
| 135 | /* */ | ||
| 136 | /* */ | ||
| 137 | #define REG_RQPN 0x0200 | ||
| 138 | #define REG_FIFOPAGE 0x0204 | ||
| 139 | #define REG_TDECTRL 0x0208 | ||
| 140 | #define REG_TXDMA_OFFSET_CHK 0x020C | ||
| 141 | #define REG_TXDMA_STATUS 0x0210 | ||
| 142 | #define REG_RQPN_NPQ 0x0214 | ||
| 143 | |||
| 144 | /* */ | ||
| 145 | /* */ | ||
| 146 | /* 0x0280h ~ 0x02FFh RXDMA Configuration */ | ||
| 147 | /* */ | ||
| 148 | /* */ | ||
| 149 | #define REG_RXDMA_AGG_PG_TH 0x0280 | ||
| 150 | #define REG_RXPKT_NUM 0x0284 | ||
| 151 | #define REG_RXDMA_STATUS 0x0288 | ||
| 152 | |||
| 153 | |||
| 154 | /* */ | ||
| 155 | /* */ | ||
| 156 | /* 0x0300h ~ 0x03FFh PCIe */ | ||
| 157 | /* */ | ||
| 158 | /* */ | ||
| 159 | #define REG_PCIE_CTRL_REG 0x0300 | ||
| 160 | #define REG_INT_MIG 0x0304 /* Interrupt Migration */ | ||
| 161 | /* TX Beacon Descriptor Address */ | ||
| 162 | #define REG_BCNQ_DESA 0x0308 | ||
| 163 | /* TX High Queue Descriptor Address */ | ||
| 164 | #define REG_HQ_DESA 0x0310 | ||
| 165 | /* TX Manage Queue Descriptor Address */ | ||
| 166 | #define REG_MGQ_DESA 0x0318 | ||
| 167 | /* TX VO Queue Descriptor Address */ | ||
| 168 | #define REG_VOQ_DESA 0x0320 | ||
| 169 | /* TX VI Queue Descriptor Address */ | ||
| 170 | #define REG_VIQ_DESA 0x0328 | ||
| 171 | /* TX BE Queue Descriptor Address */ | ||
| 172 | #define REG_BEQ_DESA 0x0330 | ||
| 173 | /* TX BK Queue Descriptor Address */ | ||
| 174 | #define REG_BKQ_DESA 0x0338 | ||
| 175 | /* RX Queue Descriptor Address */ | ||
| 176 | #define REG_RX_DESA 0x0340 | ||
| 177 | /* Backdoor REG for Access Configuration */ | ||
| 178 | #define REG_DBI 0x0348 | ||
| 179 | /* MDIO for Access PCIE PHY */ | ||
| 180 | #define REG_MDIO 0x0354 | ||
| 181 | /* Debug Selection Register */ | ||
| 182 | #define REG_DBG_SEL 0x0360 | ||
| 183 | /* PCIe RPWM */ | ||
| 184 | #define REG_PCIE_HRPWM 0x0361 | ||
| 185 | /* PCIe CPWM */ | ||
| 186 | #define REG_PCIE_HCPWM 0x0363 | ||
| 187 | /* UART Control */ | ||
| 188 | #define REG_UART_CTRL 0x0364 | ||
| 189 | /* UART TX Descriptor Address */ | ||
| 190 | #define REG_UART_TX_DESA 0x0370 | ||
| 191 | /* UART Rx Descriptor Address */ | ||
| 192 | #define REG_UART_RX_DESA 0x0378 | ||
| 193 | |||
| 194 | |||
| 195 | /* spec version 11 */ | ||
| 196 | /* */ | ||
| 197 | /* */ | ||
| 198 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ | ||
| 199 | /* */ | ||
| 200 | /* */ | ||
| 201 | #define REG_VOQ_INFORMATION 0x0400 | ||
| 202 | #define REG_VIQ_INFORMATION 0x0404 | ||
| 203 | #define REG_BEQ_INFORMATION 0x0408 | ||
| 204 | #define REG_BKQ_INFORMATION 0x040C | ||
| 205 | #define REG_MGQ_INFORMATION 0x0410 | ||
| 206 | #define REG_HGQ_INFORMATION 0x0414 | ||
| 207 | #define REG_BCNQ_INFORMATION 0x0418 | ||
| 208 | |||
| 209 | |||
| 210 | #define REG_CPU_MGQ_INFORMATION 0x041C | ||
| 211 | #define REG_FWHW_TXQ_CTRL 0x0420 | ||
| 212 | #define REG_HWSEQ_CTRL 0x0423 | ||
| 213 | #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 | ||
| 214 | #define REG_TXPKTBUF_MGQ_BDNY 0x0425 | ||
| 215 | #define REG_LIFETIME_EN 0x0426 | ||
| 216 | #define REG_MULTI_BCNQ_OFFSET 0x0427 | ||
| 217 | #define REG_SPEC_SIFS 0x0428 | ||
| 218 | #define REG_RL 0x042A | ||
| 219 | #define REG_DARFRC 0x0430 | ||
| 220 | #define REG_RARFRC 0x0438 | ||
| 221 | #define REG_RRSR 0x0440 | ||
| 222 | #define REG_ARFR0 0x0444 | ||
| 223 | #define REG_ARFR1 0x0448 | ||
| 224 | #define REG_ARFR2 0x044C | ||
| 225 | #define REG_ARFR3 0x0450 | ||
| 226 | #define REG_AGGLEN_LMT 0x0458 | ||
| 227 | #define REG_AMPDU_MIN_SPACE 0x045C | ||
| 228 | #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D | ||
| 229 | #define REG_FAST_EDCA_CTRL 0x0460 | ||
| 230 | #define REG_RD_RESP_PKT_TH 0x0463 | ||
| 231 | #define REG_INIRTS_RATE_SEL 0x0480 | ||
| 232 | #define REG_INIDATA_RATE_SEL 0x0484 | ||
| 233 | |||
| 234 | |||
| 235 | #define REG_POWER_STATUS 0x04A4 | ||
| 236 | #define REG_POWER_STAGE1 0x04B4 | ||
| 237 | #define REG_POWER_STAGE2 0x04B8 | ||
| 238 | #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 | ||
| 239 | #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 | ||
| 240 | #define REG_STBC_SETTING 0x04C4 | ||
| 241 | #define REG_PROT_MODE_CTRL 0x04C8 | ||
| 242 | #define REG_MAX_AGGR_NUM 0x04CA | ||
| 243 | #define REG_RTS_MAX_AGGR_NUM 0x04CB | ||
| 244 | #define REG_BAR_MODE_CTRL 0x04CC | ||
| 245 | #define REG_RA_TRY_RATE_AGG_LMT 0x04CF | ||
| 246 | #define REG_NQOS_SEQ 0x04DC | ||
| 247 | #define REG_QOS_SEQ 0x04DE | ||
| 248 | #define REG_NEED_CPU_HANDLE 0x04E0 | ||
| 249 | #define REG_PKT_LOSE_RPT 0x04E1 | ||
| 250 | #define REG_PTCL_ERR_STATUS 0x04E2 | ||
| 251 | #define REG_DUMMY 0x04FC | ||
| 252 | |||
| 253 | |||
| 254 | |||
| 255 | /* */ | ||
| 256 | /* */ | ||
| 257 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ | ||
| 258 | /* */ | ||
| 259 | /* */ | ||
| 260 | #define REG_EDCA_VO_PARAM 0x0500 | ||
| 261 | #define REG_EDCA_VI_PARAM 0x0504 | ||
| 262 | #define REG_EDCA_BE_PARAM 0x0508 | ||
| 263 | #define REG_EDCA_BK_PARAM 0x050C | ||
| 264 | #define REG_BCNTCFG 0x0510 | ||
| 265 | #define REG_PIFS 0x0512 | ||
| 266 | #define REG_RDG_PIFS 0x0513 | ||
| 267 | #define REG_SIFS_CCK 0x0514 | ||
| 268 | #define REG_SIFS_OFDM 0x0516 | ||
| 269 | #define REG_SIFS_CTX 0x0514 | ||
| 270 | #define REG_SIFS_TRX 0x0516 | ||
| 271 | #define REG_TSFTR_SYN_OFFSET 0x0518 | ||
| 272 | #define REG_AGGR_BREAK_TIME 0x051A | ||
| 273 | #define REG_SLOT 0x051B | ||
| 274 | #define REG_TX_PTCL_CTRL 0x0520 | ||
| 275 | #define REG_TXPAUSE 0x0522 | ||
| 276 | #define REG_DIS_TXREQ_CLR 0x0523 | ||
| 277 | #define REG_RD_CTRL 0x0524 | ||
| 278 | #define REG_TBTT_PROHIBIT 0x0540 | ||
| 279 | #define REG_RD_NAV_NXT 0x0544 | ||
| 280 | #define REG_NAV_PROT_LEN 0x0546 | ||
| 281 | #define REG_BCN_CTRL 0x0550 | ||
| 282 | #define REG_BCN_CTRL_1 0x0551 | ||
| 283 | #define REG_MBID_NUM 0x0552 | ||
| 284 | #define REG_DUAL_TSF_RST 0x0553 | ||
| 285 | /* The same as REG_MBSSID_BCN_SPACE */ | ||
| 286 | #define REG_BCN_INTERVAL 0x0554 | ||
| 287 | #define REG_MBSSID_BCN_SPACE 0x0554 | ||
| 288 | #define REG_DRVERLYINT 0x0558 | ||
| 289 | #define REG_BCNDMATIM 0x0559 | ||
| 290 | #define REG_ATIMWND 0x055A | ||
| 291 | #define REG_BCN_MAX_ERR 0x055D | ||
| 292 | #define REG_RXTSF_OFFSET_CCK 0x055E | ||
| 293 | #define REG_RXTSF_OFFSET_OFDM 0x055F | ||
| 294 | #define REG_TSFTR 0x0560 | ||
| 295 | #define REG_TSFTR1 0x0568 | ||
| 296 | #define REG_INIT_TSFTR 0x0564 | ||
| 297 | #define REG_ATIMWND_1 0x0570 | ||
| 298 | #define REG_PSTIMER 0x0580 | ||
| 299 | #define REG_TIMER0 0x0584 | ||
| 300 | #define REG_TIMER1 0x0588 | ||
| 301 | #define REG_ACMHWCTRL 0x05C0 | ||
| 302 | #define REG_ACMRSTCTRL 0x05C1 | ||
| 303 | #define REG_ACMAVG 0x05C2 | ||
| 304 | #define REG_VO_ADMTIME 0x05C4 | ||
| 305 | #define REG_VI_ADMTIME 0x05C6 | ||
| 306 | #define REG_BE_ADMTIME 0x05C8 | ||
| 307 | #define REG_EDCA_RANDOM_GEN 0x05CC | ||
| 308 | #define REG_SCH_TXCMD 0x05D0 | ||
| 309 | |||
| 310 | /* define REG_FW_TSF_SYNC_CNT 0x04A0 */ | ||
| 311 | #define REG_FW_RESET_TSF_CNT_1 0x05FC | ||
| 312 | #define REG_FW_RESET_TSF_CNT_0 0x05FD | ||
| 313 | #define REG_FW_BCN_DIS_CNT 0x05FE | ||
| 314 | |||
| 315 | /* */ | ||
| 316 | /* */ | ||
| 317 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ | ||
| 318 | /* */ | ||
| 319 | /* */ | ||
| 320 | #define REG_APSD_CTRL 0x0600 | ||
| 321 | #define REG_BWOPMODE 0x0603 | ||
| 322 | #define REG_TCR 0x0604 | ||
| 323 | #define REG_RCR 0x0608 | ||
| 324 | #define REG_RX_PKT_LIMIT 0x060C | ||
| 325 | #define REG_RX_DLK_TIME 0x060D | ||
| 326 | #define REG_RX_DRVINFO_SZ 0x060F | ||
| 327 | |||
| 328 | #define REG_MACID 0x0610 | ||
| 329 | #define REG_BSSID 0x0618 | ||
| 330 | #define REG_MAR 0x0620 | ||
| 331 | #define REG_MBIDCAMCFG 0x0628 | ||
| 332 | |||
| 333 | #define REG_USTIME_EDCA 0x0638 | ||
| 334 | #define REG_MAC_SPEC_SIFS 0x063A | ||
| 335 | |||
| 336 | /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ | ||
| 337 | /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ | ||
| 338 | #define REG_R2T_SIFS 0x063C | ||
| 339 | /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ | ||
| 340 | #define REG_T2T_SIFS 0x063E | ||
| 341 | #define REG_ACKTO 0x0640 | ||
| 342 | #define REG_CTS2TO 0x0641 | ||
| 343 | #define REG_EIFS 0x0642 | ||
| 344 | |||
| 345 | /* WMA, BA, CCX */ | ||
| 346 | #define REG_NAV_CTRL 0x0650 | ||
| 347 | #define REG_BACAMCMD 0x0654 | ||
| 348 | #define REG_BACAMCONTENT 0x0658 | ||
| 349 | #define REG_LBDLY 0x0660 | ||
| 350 | #define REG_FWDLY 0x0661 | ||
| 351 | #define REG_RXERR_RPT 0x0664 | ||
| 352 | #define REG_WMAC_TRXPTCL_CTL 0x0668 | ||
| 353 | |||
| 354 | |||
| 355 | /* Security */ | ||
| 356 | #define REG_CAMCMD 0x0670 | ||
| 357 | #define REG_CAMWRITE 0x0674 | ||
| 358 | #define REG_CAMREAD 0x0678 | ||
| 359 | #define REG_CAMDBG 0x067C | ||
| 360 | #define REG_SECCFG 0x0680 | ||
| 361 | |||
| 362 | /* Power */ | ||
| 363 | #define REG_WOW_CTRL 0x0690 | ||
| 364 | #define REG_PSSTATUS 0x0691 | ||
| 365 | #define REG_PS_RX_INFO 0x0692 | ||
| 366 | #define REG_LPNAV_CTRL 0x0694 | ||
| 367 | #define REG_WKFMCAM_CMD 0x0698 | ||
| 368 | #define REG_WKFMCAM_RWD 0x069C | ||
| 369 | #define REG_RXFLTMAP0 0x06A0 | ||
| 370 | #define REG_RXFLTMAP1 0x06A2 | ||
| 371 | #define REG_RXFLTMAP2 0x06A4 | ||
| 372 | #define REG_BCN_PSR_RPT 0x06A8 | ||
| 373 | #define REG_CALB32K_CTRL 0x06AC | ||
| 374 | #define REG_PKT_MON_CTRL 0x06B4 | ||
| 375 | #define REG_BT_COEX_TABLE 0x06C0 | ||
| 376 | #define REG_WMAC_RESP_TXINFO 0x06D8 | ||
| 377 | |||
| 378 | #define REG_MACID1 0x0700 | ||
| 379 | #define REG_BSSID1 0x0708 | ||
| 380 | |||
| 381 | |||
| 382 | /* */ | ||
| 383 | /* */ | ||
| 384 | /* 0xFE00h ~ 0xFE55h USB Configuration */ | ||
| 385 | /* */ | ||
| 386 | /* */ | ||
| 387 | #define REG_USB_INFO 0xFE17 | ||
| 388 | #define REG_USB_SPECIAL_OPTION 0xFE55 | ||
| 389 | #define REG_USB_DMA_AGG_TO 0xFE5B | ||
| 390 | #define REG_USB_AGG_TO 0xFE5C | ||
| 391 | #define REG_USB_AGG_TH 0xFE5D | ||
| 392 | |||
| 393 | /* For test chip */ | ||
| 394 | #define REG_TEST_USB_TXQS 0xFE48 | ||
| 395 | #define REG_TEST_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ | ||
| 396 | #define REG_TEST_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ | ||
| 397 | #define REG_TEST_SIE_OPTIONAL 0xFE64 | ||
| 398 | #define REG_TEST_SIE_CHIRP_K 0xFE65 | ||
| 399 | #define REG_TEST_SIE_PHY 0xFE66 /* 0xFE66~0xFE6B */ | ||
| 400 | #define REG_TEST_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ | ||
| 401 | #define REG_TEST_SIE_STRING 0xFE80 /* 0xFE80~0xFEB9 */ | ||
| 402 | |||
| 403 | |||
| 404 | /* For normal chip */ | ||
| 405 | #define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ | ||
| 406 | #define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ | ||
| 407 | #define REG_NORMAL_SIE_OPTIONAL 0xFE64 | ||
| 408 | #define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ | ||
| 409 | #define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ | ||
| 410 | #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C | ||
| 411 | #define REG_NORMAL_SIE_GPS_EP 0xFE6D /* RTL8723 only */ | ||
| 412 | #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ | ||
| 413 | #define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ | ||
| 414 | |||
| 415 | |||
| 416 | /* */ | ||
| 417 | /* */ | ||
| 418 | /* Redifine 8192C register definition for compatibility */ | ||
| 419 | /* */ | ||
| 420 | /* */ | ||
| 421 | |||
| 422 | /* TODO: use these definition when using REG_xxx naming rule. */ | ||
| 423 | /* NOTE: DO NOT Remove these definition. Use later. */ | ||
| 424 | |||
| 425 | /* System Isolation Interface Control. */ | ||
| 426 | #define SYS_ISO_CTRL REG_SYS_ISO_CTRL | ||
| 427 | /* System Function Enable. */ | ||
| 428 | #define SYS_FUNC_EN REG_SYS_FUNC_EN | ||
| 429 | #define SYS_CLK REG_SYS_CLKR | ||
| 430 | /* 93C46/93C56 Command Register. */ | ||
| 431 | #define CR9346 REG_9346CR | ||
| 432 | /* E-Fuse Control. */ | ||
| 433 | #define EFUSE_CTRL REG_EFUSE_CTRL | ||
| 434 | /* E-Fuse Test. */ | ||
| 435 | #define EFUSE_TEST REG_EFUSE_TEST | ||
| 436 | /* Media Status register */ | ||
| 437 | #define MSR (REG_CR + 2) | ||
| 438 | #define ISR REG_HISR | ||
| 439 | /* Timing Sync Function Timer Register. */ | ||
| 440 | #define TSFR REG_TSFTR | ||
| 441 | |||
| 442 | /* MAC ID Register, Offset 0x0050-0x0053 */ | ||
| 443 | #define MACIDR0 REG_MACID | ||
| 444 | /* MAC ID Register, Offset 0x0054-0x0055 */ | ||
| 445 | #define MACIDR4 (REG_MACID + 4) | ||
| 446 | |||
| 447 | #define PBP REG_PBP | ||
| 448 | |||
| 449 | /* Redifine MACID register, to compatible prior ICs. */ | ||
| 450 | #define IDR0 MACIDR0 | ||
| 451 | #define IDR4 MACIDR4 | ||
| 452 | |||
| 453 | |||
| 454 | /* */ | ||
| 455 | /* 9. Security Control Registers (Offset: ) */ | ||
| 456 | /* */ | ||
| 457 | /* IN 8190 Data Sheet is called CAMcmd */ | ||
| 458 | #define RWCAM REG_CAMCMD | ||
| 459 | /* Software write CAM input content */ | ||
| 460 | #define WCAMI REG_CAMWRITE | ||
| 461 | /* Software read/write CAM config */ | ||
| 462 | #define RCAMO REG_CAMREAD | ||
| 463 | #define CAMDBG REG_CAMDBG | ||
| 464 | /* Security Configuration Register */ | ||
| 465 | #define SECR REG_SECCFG | ||
| 466 | |||
| 467 | /* Unused register */ | ||
| 468 | #define UnusedRegister 0x1BF | ||
| 469 | #define DCAM UnusedRegister | ||
| 470 | #define PSR UnusedRegister | ||
| 471 | #define BBAddr UnusedRegister | ||
| 472 | #define PhyDataR UnusedRegister | ||
| 473 | |||
| 474 | #define InvalidBBRFValue 0x12345678 | ||
| 475 | |||
| 476 | /* Min Spacing related settings. */ | ||
| 477 | #define MAX_MSS_DENSITY_2T 0x13 | ||
| 478 | #define MAX_MSS_DENSITY_1T 0x0A | ||
| 479 | |||
| 480 | /* */ | ||
| 481 | /* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */ | ||
| 482 | /* */ | ||
| 483 | /* EEPROM enable when set 1 */ | ||
| 484 | #define CmdEEPROM_En BIT5 | ||
| 485 | /* System EEPROM select, 0: boot from E-FUSE, | ||
| 486 | 1: The EEPROM used is 9346 */ | ||
| 487 | #define CmdEERPOMSEL BIT4 | ||
| 488 | #define Cmd9346CR_9356SEL BIT4 | ||
| 489 | #define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) | ||
| 490 | #define AutoLoadEFUSE CmdEEPROM_En | ||
| 491 | |||
| 492 | /* */ | ||
| 493 | /* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ | ||
| 494 | /* */ | ||
| 495 | #define GPIOSEL_GPIO 0 | ||
| 496 | #define GPIOSEL_ENBT BIT5 | ||
| 497 | |||
| 498 | /* */ | ||
| 499 | /* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ | ||
| 500 | /* */ | ||
| 501 | /* GPIO pins input value */ | ||
| 502 | #define GPIO_IN REG_GPIO_PIN_CTRL | ||
| 503 | /* GPIO pins output value */ | ||
| 504 | #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) | ||
| 505 | /* GPIO pins output enable when a bit is set to "1"; | ||
| 506 | otherwise, input is configured. */ | ||
| 507 | #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) | ||
| 508 | #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) | ||
| 509 | |||
| 510 | /* */ | ||
| 511 | /* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ | ||
| 512 | /* */ | ||
| 513 | /* | ||
| 514 | Network Type | ||
| 515 | 00: No link | ||
| 516 | 01: Link in ad hoc network | ||
| 517 | 10: Link in infrastructure network | ||
| 518 | 11: AP mode | ||
| 519 | Default: 00b. | ||
| 520 | */ | ||
| 521 | #define MSR_NOLINK 0x00 | ||
| 522 | #define MSR_ADHOC 0x01 | ||
| 523 | #define MSR_INFRA 0x02 | ||
| 524 | #define MSR_AP 0x03 | ||
| 525 | |||
| 526 | /* */ | ||
| 527 | /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ | ||
| 528 | /* */ | ||
| 529 | /* */ | ||
| 530 | /* 8192C Response Rate Set Register (offset 0x181, 24bits) */ | ||
| 531 | /* */ | ||
| 532 | #define RRSR_RSC_OFFSET 21 | ||
| 533 | #define RRSR_SHORT_OFFSET 23 | ||
| 534 | #define RRSR_RSC_BW_40M 0x600000 | ||
| 535 | #define RRSR_RSC_UPSUBCHNL 0x400000 | ||
| 536 | #define RRSR_RSC_LOWSUBCHNL 0x200000 | ||
| 537 | #define RRSR_SHORT 0x800000 | ||
| 538 | #define RRSR_1M BIT0 | ||
| 539 | #define RRSR_2M BIT1 | ||
| 540 | #define RRSR_5_5M BIT2 | ||
| 541 | #define RRSR_11M BIT3 | ||
| 542 | #define RRSR_6M BIT4 | ||
| 543 | #define RRSR_9M BIT5 | ||
| 544 | #define RRSR_12M BIT6 | ||
| 545 | #define RRSR_18M BIT7 | ||
| 546 | #define RRSR_24M BIT8 | ||
| 547 | #define RRSR_36M BIT9 | ||
| 548 | #define RRSR_48M BIT10 | ||
| 549 | #define RRSR_54M BIT11 | ||
| 550 | #define RRSR_MCS0 BIT12 | ||
| 551 | #define RRSR_MCS1 BIT13 | ||
| 552 | #define RRSR_MCS2 BIT14 | ||
| 553 | #define RRSR_MCS3 BIT15 | ||
| 554 | #define RRSR_MCS4 BIT16 | ||
| 555 | #define RRSR_MCS5 BIT17 | ||
| 556 | #define RRSR_MCS6 BIT18 | ||
| 557 | #define RRSR_MCS7 BIT19 | ||
| 558 | #define BRSR_AckShortPmb BIT23 | ||
| 559 | /* CCK ACK: use Short Preamble or not */ | ||
| 560 | |||
| 561 | /* */ | ||
| 562 | /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ | ||
| 563 | /* */ | ||
| 564 | #define BW_OPMODE_20MHZ BIT2 | ||
| 565 | #define BW_OPMODE_5G BIT1 | ||
| 566 | #define BW_OPMODE_11J BIT0 | ||
| 567 | |||
| 568 | |||
| 569 | /* */ | ||
| 570 | /* 8192C CAM Config Setting (offset 0x250, 1 byte) */ | ||
| 571 | /* */ | ||
| 572 | #define CAM_VALID BIT15 | ||
| 573 | #define CAM_NOTVALID 0x0000 | ||
| 574 | #define CAM_USEDK BIT5 | ||
| 575 | |||
| 576 | #define CAM_CONTENT_COUNT 8 | ||
| 577 | |||
| 578 | #define CAM_NONE 0x0 | ||
| 579 | #define CAM_WEP40 0x01 | ||
| 580 | #define CAM_TKIP 0x02 | ||
| 581 | #define CAM_AES 0x04 | ||
| 582 | #define CAM_WEP104 0x05 | ||
| 583 | |||
| 584 | #define TOTAL_CAM_ENTRY 32 | ||
| 585 | #define HALF_CAM_ENTRY 16 | ||
| 586 | |||
| 587 | #define CAM_CONFIG_USEDK true | ||
| 588 | #define CAM_CONFIG_NO_USEDK false | ||
| 589 | |||
| 590 | #define CAM_WRITE BIT16 | ||
| 591 | #define CAM_READ 0x00000000 | ||
| 592 | #define CAM_POLLINIG BIT31 | ||
| 593 | |||
| 594 | #define SCR_UseDK 0x01 | ||
| 595 | #define SCR_TxSecEnable 0x02 | ||
| 596 | #define SCR_RxSecEnable 0x04 | ||
| 597 | |||
| 598 | |||
| 599 | /* */ | ||
| 600 | /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ | ||
| 601 | /* */ | ||
| 602 | /* */ | ||
| 603 | /* 8190 IMR/ISR bits (offset 0xfd, 8bits) */ | ||
| 604 | /* */ | ||
| 605 | #define IMR8190_DISABLED 0x0 | ||
| 606 | /* IMR DW0 Bit 0-31 */ | ||
| 607 | |||
| 608 | #define IMR_BCNDMAINT6 BIT31 /* Beacon DMA Interrupt 6 */ | ||
| 609 | #define IMR_BCNDMAINT5 BIT30 /* Beacon DMA Interrupt 5 */ | ||
| 610 | #define IMR_BCNDMAINT4 BIT29 /* Beacon DMA Interrupt 4 */ | ||
| 611 | #define IMR_BCNDMAINT3 BIT28 /* Beacon DMA Interrupt 3 */ | ||
| 612 | #define IMR_BCNDMAINT2 BIT27 /* Beacon DMA Interrupt 2 */ | ||
| 613 | #define IMR_BCNDMAINT1 BIT26 /* Beacon DMA Interrupt 1 */ | ||
| 614 | #define IMR_BCNDOK8 BIT25 /* Beacon Queue DMA OK | ||
| 615 | Interrupt 8 */ | ||
| 616 | #define IMR_BCNDOK7 BIT24 /* Beacon Queue DMA OK | ||
| 617 | Interrupt 7 */ | ||
| 618 | #define IMR_BCNDOK6 BIT23 /* Beacon Queue DMA OK | ||
| 619 | Interrupt 6 */ | ||
| 620 | #define IMR_BCNDOK5 BIT22 /* Beacon Queue DMA OK | ||
| 621 | Interrupt 5 */ | ||
| 622 | #define IMR_BCNDOK4 BIT21 /* Beacon Queue DMA OK | ||
| 623 | Interrupt 4 */ | ||
| 624 | #define IMR_BCNDOK3 BIT20 /* Beacon Queue DMA OK | ||
| 625 | Interrupt 3 */ | ||
| 626 | #define IMR_BCNDOK2 BIT19 /* Beacon Queue DMA OK | ||
| 627 | Interrupt 2 */ | ||
| 628 | #define IMR_BCNDOK1 BIT18 /* Beacon Queue DMA OK | ||
| 629 | Interrupt 1 */ | ||
| 630 | #define IMR_TIMEOUT2 BIT17 /* Timeout interrupt 2 */ | ||
| 631 | #define IMR_TIMEOUT1 BIT16 /* Timeout interrupt 1 */ | ||
| 632 | #define IMR_TXFOVW BIT15 /* Transmit FIFO Overflow */ | ||
| 633 | #define IMR_PSTIMEOUT BIT14 /* Power save time out | ||
| 634 | interrupt */ | ||
| 635 | #define IMR_BcnInt BIT13 /* Beacon DMA Interrupt 0 */ | ||
| 636 | #define IMR_RXFOVW BIT12 /* Receive FIFO Overflow */ | ||
| 637 | #define IMR_RDU BIT11 /* Receive Descriptor | ||
| 638 | Unavailable */ | ||
| 639 | #define IMR_ATIMEND BIT10 /* For 92C,ATIM Window | ||
| 640 | End Interrupt */ | ||
| 641 | #define IMR_BDOK BIT9 /* Beacon Queue DMA OK | ||
| 642 | Interrup */ | ||
| 643 | #define IMR_HIGHDOK BIT8 /* High Queue DMA OK | ||
| 644 | Interrupt */ | ||
| 645 | #define IMR_TBDOK BIT7 /* Transmit Beacon OK | ||
| 646 | interrup */ | ||
| 647 | #define IMR_MGNTDOK BIT6 /* Management Queue DMA OK | ||
| 648 | Interrupt */ | ||
| 649 | #define IMR_TBDER BIT5 /* For 92C,Transmit Beacon | ||
| 650 | Error Interrupt */ | ||
| 651 | #define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */ | ||
| 652 | #define IMR_BEDOK BIT3 /* AC_BE DMA OK Interrupt */ | ||
| 653 | #define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */ | ||
| 654 | #define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */ | ||
| 655 | #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */ | ||
| 656 | |||
| 657 | #define IMR_RX_MASK (IMR_ROK|IMR_RDU|IMR_RXFOVW) | ||
| 658 | #define IMR_TX_MASK (IMR_VODOK|IMR_VIDOK|IMR_BEDOK| \ | ||
| 659 | IMR_BKDOK|IMR_MGNTDOK|IMR_HIGHDOK| \ | ||
| 660 | IMR_BDOK) | ||
| 661 | |||
| 662 | /* 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) */ | ||
| 663 | #define IMR_BcnInt_E BIT12 | ||
| 664 | #define IMR_TXERR BIT11 | ||
| 665 | #define IMR_RXERR BIT10 | ||
| 666 | #define IMR_C2HCMD BIT9 | ||
| 667 | #define IMR_CPWM BIT8 | ||
| 668 | /* RSVD [2-7] */ | ||
| 669 | #define IMR_OCPINT BIT1 | ||
| 670 | #define IMR_WLANOFF BIT0 | ||
| 671 | |||
| 672 | |||
| 673 | /* 8192C EEPROM/EFUSE share register definition. */ | ||
| 674 | |||
| 675 | /* Default Value for EEPROM or EFUSE!!! */ | ||
| 676 | #define EEPROM_Default_TSSI 0x0 | ||
| 677 | #define EEPROM_Default_TxPowerDiff 0x0 | ||
| 678 | #define EEPROM_Default_CrystalCap 0x5 | ||
| 679 | /* Default: 2X2, RTL8192CE(QFPN68) */ | ||
| 680 | #define EEPROM_Default_BoardType 0x02 | ||
| 681 | #define EEPROM_Default_TxPower 0x1010 | ||
| 682 | #define EEPROM_Default_HT2T_TxPwr 0x10 | ||
| 683 | |||
| 684 | #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 | ||
| 685 | #define EEPROM_Default_ThermalMeter 0x12 | ||
| 686 | |||
| 687 | #define EEPROM_Default_AntTxPowerDiff 0x0 | ||
| 688 | #define EEPROM_Default_TxPwDiff_CrystalCap 0x5 | ||
| 689 | #define EEPROM_Default_TxPowerLevel 0x22 | ||
| 690 | #define EEPROM_Default_HT40_2SDiff 0x0 | ||
| 691 | /* HT20<->40 default Tx Power Index Difference */ | ||
| 692 | #define EEPROM_Default_HT20_Diff 2 | ||
| 693 | #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 | ||
| 694 | #define EEPROM_Default_HT40_PwrMaxOffset 0 | ||
| 695 | #define EEPROM_Default_HT20_PwrMaxOffset 0 | ||
| 696 | |||
| 697 | /* For debug */ | ||
| 698 | #define EEPROM_Default_PID 0x1234 | ||
| 699 | #define EEPROM_Default_VID 0x5678 | ||
| 700 | #define EEPROM_Default_CustomerID 0xAB | ||
| 701 | #define EEPROM_Default_SubCustomerID 0xCD | ||
| 702 | #define EEPROM_Default_Version 0 | ||
| 703 | |||
| 704 | #define EEPROM_CHANNEL_PLAN_FCC 0x0 | ||
| 705 | #define EEPROM_CHANNEL_PLAN_IC 0x1 | ||
| 706 | #define EEPROM_CHANNEL_PLAN_ETSI 0x2 | ||
| 707 | #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 | ||
| 708 | #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 | ||
| 709 | #define EEPROM_CHANNEL_PLAN_MKK 0x5 | ||
| 710 | #define EEPROM_CHANNEL_PLAN_MKK1 0x6 | ||
| 711 | #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 | ||
| 712 | #define EEPROM_CHANNEL_PLAN_TELEC 0x8 | ||
| 713 | #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 | ||
| 714 | #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA | ||
| 715 | #define EEPROM_CHANNEL_PLAN_NCC 0xB | ||
| 716 | #define EEPROM_USB_OPTIONAL1 0xE | ||
| 717 | #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 | ||
| 718 | |||
| 719 | |||
| 720 | #define EEPROM_CID_DEFAULT 0x0 | ||
| 721 | #define EEPROM_CID_TOSHIBA 0x4 | ||
| 722 | /* CCX test. By Bruce, 2009-02-25. */ | ||
| 723 | #define EEPROM_CID_CCX 0x10 | ||
| 724 | #define EEPROM_CID_QMI 0x0D | ||
| 725 | /* added by chiyoko for dtm, 20090108 */ | ||
| 726 | #define EEPROM_CID_WHQL 0xFE | ||
| 727 | |||
| 728 | |||
| 729 | #define RTL_EEPROM_ID 0x8129 | ||
| 730 | |||
| 731 | #define SUPPORT_HW_RADIO_DETECT(pHalData) \ | ||
| 732 | (pHalData->BoardType == BOARD_MINICARD || \ | ||
| 733 | pHalData->BoardType == BOARD_USB_SOLO || \ | ||
| 734 | pHalData->BoardType == BOARD_USB_COMBO) | ||
| 735 | |||
| 736 | /* */ | ||
| 737 | /* EEPROM address for Test chip */ | ||
| 738 | /* */ | ||
| 739 | #define EEPROM_TEST_USB_OPT 0x0E | ||
| 740 | #define EEPROM_TEST_CHIRP_K 0x0F | ||
| 741 | #define EEPROM_TEST_EP_SETTING 0x0E | ||
| 742 | #define EEPROM_TEST_USB_PHY 0x10 | ||
| 743 | |||
| 744 | |||
| 745 | /* */ | ||
| 746 | /* EEPROM address for Normal chip */ | ||
| 747 | /* */ | ||
| 748 | #define EEPROM_NORMAL_USB_OPT 0x0E | ||
| 749 | #define EEPROM_NORMAL_CHIRP_K 0x0E /* Changed */ | ||
| 750 | #define EEPROM_NORMAL_EP_SETTING 0x0F /* Changed */ | ||
| 751 | #define EEPROM_NORMAL_USB_PHY 0x12 /* Changed */ | ||
| 752 | |||
| 753 | enum { | ||
| 754 | BOARD_USB_DONGLE = 0, /* USB dongle */ | ||
| 755 | BOARD_USB_High_PA = 1, /* USB dongle with high power PA */ | ||
| 756 | BOARD_MINICARD = 2, /* Minicard */ | ||
| 757 | BOARD_USB_SOLO = 3, /* USB solo-Slim module */ | ||
| 758 | BOARD_USB_COMBO = 4, /* USB Combo-Slim module */ | ||
| 759 | }; | ||
| 760 | |||
| 761 | /* Test chip and normal chip common define */ | ||
| 762 | /* */ | ||
| 763 | /* EEPROM address for both */ | ||
| 764 | /* */ | ||
| 765 | #define EEPROM_ID0 0x00 | ||
| 766 | #define EEPROM_ID1 0x01 | ||
| 767 | #define EEPROM_RTK_RSV1 0x02 | ||
| 768 | #define EEPROM_RTK_RSV2 0x03 | ||
| 769 | #define EEPROM_RTK_RSV3 0x04 | ||
| 770 | #define EEPROM_RTK_RSV4 0x05 | ||
| 771 | #define EEPROM_RTK_RSV5 0x06 | ||
| 772 | #define EEPROM_DBG_SEL 0x07 | ||
| 773 | #define EEPROM_RTK_RSV6 0x08 | ||
| 774 | #define EEPROM_VID 0x0A | ||
| 775 | #define EEPROM_PID 0x0C | ||
| 776 | |||
| 777 | #define EEPROM_MAC_ADDR 0x16 | ||
| 778 | #define EEPROM_STRING 0x1C | ||
| 779 | #define EEPROM_SUBCUSTOMER_ID 0x59 | ||
| 780 | #define EEPROM_CCK_TX_PWR_INX 0x5A | ||
| 781 | #define EEPROM_HT40_1S_TX_PWR_INX 0x60 | ||
| 782 | #define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 | ||
| 783 | #define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 | ||
| 784 | #define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C | ||
| 785 | #define EEPROM_HT40_MAX_PWR_OFFSET 0x6F | ||
| 786 | #define EEPROM_HT20_MAX_PWR_OFFSET 0x72 | ||
| 787 | |||
| 788 | #define EEPROM_CHANNEL_PLAN 0x75 | ||
| 789 | #define EEPROM_TSSI_A 0x76 | ||
| 790 | #define EEPROM_TSSI_B 0x77 | ||
| 791 | #define EEPROM_THERMAL_METER 0x78 | ||
| 792 | #define EEPROM_RF_OPT1 0x79 | ||
| 793 | #define EEPROM_RF_OPT2 0x7A | ||
| 794 | #define EEPROM_RF_OPT3 0x7B | ||
| 795 | #define EEPROM_RF_OPT4 0x7C | ||
| 796 | #define EEPROM_VERSION 0x7E | ||
| 797 | #define EEPROM_CUSTOMER_ID 0x7F | ||
| 798 | |||
| 799 | /* 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU */ | ||
| 800 | #define EEPROM_BoardType 0x54 | ||
| 801 | /* 0x5C-0x76, Tx Power index. */ | ||
| 802 | #define EEPROM_TxPwIndex 0x5C | ||
| 803 | /* Difference of gain index between legacy and high throughput OFDM. */ | ||
| 804 | #define EEPROM_PwDiff 0x67 | ||
| 805 | /* CCK Tx Power */ | ||
| 806 | #define EEPROM_TxPowerCCK 0x5A | ||
| 807 | |||
| 808 | /* 2009/02/09 Cosa Add for SD3 requirement */ | ||
| 809 | /* HT20 Tx Power Index Difference */ | ||
| 810 | #define EEPROM_TX_PWR_HT20_DIFF 0x6e | ||
| 811 | /* HT20<->40 default Tx Power Index Difference */ | ||
| 812 | #define DEFAULT_HT20_TXPWR_DIFF 2 | ||
| 813 | /* OFDM Tx Power Index Difference */ | ||
| 814 | #define EEPROM_TX_PWR_OFDM_DIFF 0x71 | ||
| 815 | |||
| 816 | /* Power diff for channel group */ | ||
| 817 | #define EEPROM_TxPWRGroup 0x73 | ||
| 818 | /* Check if power safety is need */ | ||
| 819 | #define EEPROM_Regulatory 0x79 | ||
| 820 | |||
| 821 | /* 92cu, 0x7E[4] */ | ||
| 822 | #define EEPROM_BLUETOOTH_COEXIST 0x7E | ||
| 823 | #define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 /* 7:5] */ | ||
| 824 | #define BOARD_TYPE_NORMAL_MASK 0xE0 | ||
| 825 | #define BOARD_TYPE_TEST_MASK 0x0F | ||
| 826 | /* BIT0 1 for build-in module, 0 for external dongle */ | ||
| 827 | #define EEPROM_EASY_REPLACEMENT 0x50 | ||
| 828 | /* */ | ||
| 829 | /* EPROM content definitions */ | ||
| 830 | /* */ | ||
| 831 | #define OS_LINK_SPEED BIT(5) | ||
| 832 | |||
| 833 | #define BOARD_TYPE_MASK 0xF | ||
| 834 | |||
| 835 | #define BT_COEXISTENCE BIT(4) | ||
| 836 | #define BT_CO_SHIFT 4 | ||
| 837 | |||
| 838 | #define EP_NUMBER_MASK 0x30 /* bit 4:5 0Eh */ | ||
| 839 | #define EP_NUMBER_SHIFT 4 | ||
| 840 | |||
| 841 | |||
| 842 | #define USB_PHY_PARA_SIZE 5 | ||
| 843 | |||
| 844 | |||
| 845 | /* */ | ||
| 846 | /* EEPROM default value definitions */ | ||
| 847 | /* */ | ||
| 848 | /* Use 0xABCD instead of 0x8192 for debug */ | ||
| 849 | #define EEPROM_DEF_ID_0 0xCD /* Byte 0x00 */ | ||
| 850 | #define EEPROM_DEF_ID_1 0xAB /* Byte 0x01 */ | ||
| 851 | |||
| 852 | #define EEPROM_DEF_RTK_RSV_A3 0x74 /* Byte 0x03 */ | ||
| 853 | #define EEPROM_DEF_RTK_RSV_A4 0x6D /* Byte 0x04 */ | ||
| 854 | #define EEPROM_DEF_RTK_RSV_A8 0xFF /* Byte 0x08 */ | ||
| 855 | |||
| 856 | #define EEPROM_DEF_VID_0 0x0A /* Byte 0x0A */ | ||
| 857 | #define EEPROM_DEF_VID_1 0x0B | ||
| 858 | |||
| 859 | #define EEPROM_DEF_PID_0 0x92 /* Byte 0x0C */ | ||
| 860 | #define EEPROM_DEF_PID_1 0x81 | ||
| 861 | |||
| 862 | |||
| 863 | #define EEPROM_TEST_DEF_USB_OPT 0x80 /* Byte 0x0E */ | ||
| 864 | #define EEPROM_NORMAL_DEF_USB_OPT 0x00 /* Byte 0x0E */ | ||
| 865 | |||
| 866 | #define EEPROM_DEF_CHIRPK 0x15 /* Byte 0x0F */ | ||
| 867 | |||
| 868 | #define EEPROM_DEF_USB_PHY_0 0x85 /* Byte 0x10 */ | ||
| 869 | #define EEPROM_DEF_USB_PHY_1 0x62 /* Byte 0x11 */ | ||
| 870 | #define EEPROM_DEF_USB_PHY_2 0x9E /* Byte 0x12 */ | ||
| 871 | #define EEPROM_DEF_USB_PHY_3 0x06 /* Byte 0x13 */ | ||
| 872 | |||
| 873 | #define EEPROM_DEF_TSSI_A 0x09 /* Byte 0x78 */ | ||
| 874 | #define EEPROM_DEF_TSSI_B 0x09 /* Byte 0x79 */ | ||
| 875 | |||
| 876 | |||
| 877 | #define EEPROM_DEF_THERMAL_METER 0x12 /* Byte 0x7A */ | ||
| 878 | |||
| 879 | /* Check if power safety spec is need */ | ||
| 880 | #define RF_OPTION1 0x79 | ||
| 881 | #define RF_OPTION2 0x7A | ||
| 882 | #define RF_OPTION3 0x7B | ||
| 883 | #define RF_OPTION4 0x7C | ||
| 884 | |||
| 885 | |||
| 886 | #define EEPROM_USB_SN BIT(0) | ||
| 887 | #define EEPROM_USB_REMOTE_WAKEUP BIT(1) | ||
| 888 | #define EEPROM_USB_DEVICE_PWR BIT(2) | ||
| 889 | #define EEPROM_EP_NUMBER (BIT(3)|BIT(4)) | ||
| 890 | |||
| 891 | /*=================================================================== | ||
| 892 | ===================================================================== | ||
| 893 | Here the register defines are for 92C. When the define is as same with 92C, | ||
| 894 | we will use the 92C's define for the consistency | ||
| 895 | So the following defines for 92C is not entire!!!!!! | ||
| 896 | ===================================================================== | ||
| 897 | =====================================================================*/ | ||
| 898 | /* | ||
| 899 | Based on Datasheet V33---090401 | ||
| 900 | Register Summary | ||
| 901 | Current IOREG MAP | ||
| 902 | 0x0000h ~ 0x00FFh System Configuration (256 Bytes) | ||
| 903 | 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) | ||
| 904 | 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) | ||
| 905 | 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) | ||
| 906 | 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) | ||
| 907 | 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) | ||
| 908 | 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) | ||
| 909 | 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) | ||
| 910 | 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) | ||
| 911 | */ | ||
| 912 | |||
| 913 | /* */ | ||
| 914 | /* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ | ||
| 915 | /* */ | ||
| 916 | #define RCR_APPFCS BIT31 /* WMAC append FCS after payload*/ | ||
| 917 | #define RCR_APP_MIC BIT30 | ||
| 918 | #define RCR_APP_PHYSTS BIT28 | ||
| 919 | #define RCR_APP_ICV BIT29 | ||
| 920 | #define RCR_APP_PHYST_RXFF BIT28 | ||
| 921 | #define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */ | ||
| 922 | #define RCR_ENMBID BIT24 /* Enable Multiple BssId. */ | ||
| 923 | #define RCR_LSIGEN BIT23 | ||
| 924 | #define RCR_MFBEN BIT22 | ||
| 925 | #define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */ | ||
| 926 | #define RCR_AMF BIT13 /* Accept management type frame */ | ||
| 927 | #define RCR_ACF BIT12 /* Accept control type frame */ | ||
| 928 | #define RCR_ADF BIT11 /* Accept data type frame */ | ||
| 929 | #define RCR_AICV BIT9 /* Accept ICV error packet */ | ||
| 930 | #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ | ||
| 931 | #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet | ||
| 932 | (Rx beacon, probe rsp) */ | ||
| 933 | #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet | ||
| 934 | (Data) */ | ||
| 935 | #define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match | ||
| 936 | packet */ | ||
| 937 | #define RCR_APWRMGT BIT5 /* Accept power management | ||
| 938 | packet */ | ||
| 939 | #define RCR_ADD3 BIT4 /* Accept address 3 match | ||
| 940 | packet */ | ||
| 941 | #define RCR_AB BIT3 /* Accept broadcast packet */ | ||
| 942 | #define RCR_AM BIT2 /* Accept multicast packet */ | ||
| 943 | #define RCR_APM BIT1 /* Accept physical match packet */ | ||
| 944 | #define RCR_AAP BIT0 /* Accept all unicast packet */ | ||
| 945 | #define RCR_MXDMA_OFFSET 8 | ||
| 946 | #define RCR_FIFO_OFFSET 13 | ||
| 947 | |||
| 948 | |||
| 949 | |||
| 950 | /* */ | ||
| 951 | /* 8192c USB specific Regsiter Offset and Content definition, */ | ||
| 952 | /* 2009.08.18, added by vivi. for merge 92c and 92C into one driver */ | ||
| 953 | /* */ | ||
| 954 | /* define APS_FSMCO 0x0004 same with 92Ce */ | ||
| 955 | #define RSV_CTRL 0x001C | ||
| 956 | #define RD_CTRL 0x0524 | ||
| 957 | |||
| 958 | /* */ | ||
| 959 | /* */ | ||
| 960 | /* 0xFE00h ~ 0xFE55h USB Configuration */ | ||
| 961 | /* */ | ||
| 962 | /* */ | ||
| 963 | #define REG_USB_INFO 0xFE17 | ||
| 964 | #define REG_USB_SPECIAL_OPTION 0xFE55 | ||
| 965 | #define REG_USB_DMA_AGG_TO 0xFE5B | ||
| 966 | #define REG_USB_AGG_TO 0xFE5C | ||
| 967 | #define REG_USB_AGG_TH 0xFE5D | ||
| 968 | |||
| 969 | #define REG_USB_VID 0xFE60 | ||
| 970 | #define REG_USB_PID 0xFE62 | ||
| 971 | #define REG_USB_OPTIONAL 0xFE64 | ||
| 972 | #define REG_USB_CHIRP_K 0xFE65 | ||
| 973 | #define REG_USB_PHY 0xFE66 | ||
| 974 | #define REG_USB_MAC_ADDR 0xFE70 | ||
| 975 | |||
| 976 | #define REG_USB_HRPWM 0xFE58 | ||
| 977 | #define REG_USB_HCPWM 0xFE57 | ||
| 978 | |||
| 979 | #define InvalidBBRFValue 0x12345678 | ||
| 980 | |||
| 981 | /* */ | ||
| 982 | /* 8192C Regsiter Bit and Content definition */ | ||
| 983 | /* */ | ||
| 984 | /* */ | ||
| 985 | /* */ | ||
| 986 | /* 0x0000h ~ 0x00FFh System Configuration */ | ||
| 987 | /* */ | ||
| 988 | /* */ | ||
| 989 | |||
| 990 | /* 2 SPS0_CTRL */ | ||
| 991 | #define SW18_FPWM BIT(3) | ||
| 992 | |||
| 993 | |||
| 994 | /* 2 SYS_ISO_CTRL */ | ||
| 995 | #define ISO_MD2PP BIT(0) | ||
| 996 | #define ISO_UA2USB BIT(1) | ||
| 997 | #define ISO_UD2CORE BIT(2) | ||
| 998 | #define ISO_PA2PCIE BIT(3) | ||
| 999 | #define ISO_PD2CORE BIT(4) | ||
| 1000 | #define ISO_IP2MAC BIT(5) | ||
| 1001 | #define ISO_DIOP BIT(6) | ||
| 1002 | #define ISO_DIOE BIT(7) | ||
| 1003 | #define ISO_EB2CORE BIT(8) | ||
| 1004 | #define ISO_DIOR BIT(9) | ||
| 1005 | |||
| 1006 | #define PWC_EV25V BIT(14) | ||
| 1007 | #define PWC_EV12V BIT(15) | ||
| 1008 | |||
| 1009 | |||
| 1010 | /* 2 SYS_FUNC_EN */ | ||
| 1011 | #define FEN_BBRSTB BIT(0) | ||
| 1012 | #define FEN_BB_GLB_RSTn BIT(1) | ||
| 1013 | #define FEN_USBA BIT(2) | ||
| 1014 | #define FEN_UPLL BIT(3) | ||
| 1015 | #define FEN_USBD BIT(4) | ||
| 1016 | #define FEN_DIO_PCIE BIT(5) | ||
| 1017 | #define FEN_PCIEA BIT(6) | ||
| 1018 | #define FEN_PPLL BIT(7) | ||
| 1019 | #define FEN_PCIED BIT(8) | ||
| 1020 | #define FEN_DIOE BIT(9) | ||
| 1021 | #define FEN_CPUEN BIT(10) | ||
| 1022 | #define FEN_DCORE BIT(11) | ||
| 1023 | #define FEN_ELDR BIT(12) | ||
| 1024 | #define FEN_DIO_RF BIT(13) | ||
| 1025 | #define FEN_HWPDN BIT(14) | ||
| 1026 | #define FEN_MREGEN BIT(15) | ||
| 1027 | |||
| 1028 | /* 2 APS_FSMCO */ | ||
| 1029 | #define PFM_LDALL BIT(0) | ||
| 1030 | #define PFM_ALDN BIT(1) | ||
| 1031 | #define PFM_LDKP BIT(2) | ||
| 1032 | #define PFM_WOWL BIT(3) | ||
| 1033 | #define EnPDN BIT(4) | ||
| 1034 | #define PDN_PL BIT(5) | ||
| 1035 | #define APFM_ONMAC BIT(8) | ||
| 1036 | #define APFM_OFF BIT(9) | ||
| 1037 | #define APFM_RSM BIT(10) | ||
| 1038 | #define AFSM_HSUS BIT(11) | ||
| 1039 | #define AFSM_PCIE BIT(12) | ||
| 1040 | #define APDM_MAC BIT(13) | ||
| 1041 | #define APDM_HOST BIT(14) | ||
| 1042 | #define APDM_HPDN BIT(15) | ||
| 1043 | #define RDY_MACON BIT(16) | ||
| 1044 | #define SUS_HOST BIT(17) | ||
| 1045 | #define ROP_ALD BIT(20) | ||
| 1046 | #define ROP_PWR BIT(21) | ||
| 1047 | #define ROP_SPS BIT(22) | ||
| 1048 | #define SOP_MRST BIT(25) | ||
| 1049 | #define SOP_FUSE BIT(26) | ||
| 1050 | #define SOP_ABG BIT(27) | ||
| 1051 | #define SOP_AMB BIT(28) | ||
| 1052 | #define SOP_RCK BIT(29) | ||
| 1053 | #define SOP_A8M BIT(30) | ||
| 1054 | #define XOP_BTCK BIT(31) | ||
| 1055 | |||
| 1056 | /* 2 SYS_CLKR */ | ||
| 1057 | #define ANAD16V_EN BIT(0) | ||
| 1058 | #define ANA8M BIT(1) | ||
| 1059 | #define MACSLP BIT(4) | ||
| 1060 | #define LOADER_CLK_EN BIT(5) | ||
| 1061 | #define _80M_SSC_DIS BIT(7) | ||
| 1062 | #define _80M_SSC_EN_HO BIT(8) | ||
| 1063 | #define PHY_SSC_RSTB BIT(9) | ||
| 1064 | #define SEC_CLK_EN BIT(10) | ||
| 1065 | #define MAC_CLK_EN BIT(11) | ||
| 1066 | #define SYS_CLK_EN BIT(12) | ||
| 1067 | #define RING_CLK_EN BIT(13) | ||
| 1068 | |||
| 1069 | |||
| 1070 | /* 2 9346CR */ | ||
| 1071 | |||
| 1072 | |||
| 1073 | #define EEDO BIT(0) | ||
| 1074 | #define EEDI BIT(1) | ||
| 1075 | #define EESK BIT(2) | ||
| 1076 | #define EECS BIT(3) | ||
| 1077 | /* define EERPROMSEL BIT(4) */ | ||
| 1078 | /* define EEPROM_EN BIT(5) */ | ||
| 1079 | #define BOOT_FROM_EEPROM BIT(4) | ||
| 1080 | #define EEPROM_EN BIT(5) | ||
| 1081 | #define EEM0 BIT(6) | ||
| 1082 | #define EEM1 BIT(7) | ||
| 1083 | |||
| 1084 | |||
| 1085 | /* 2 AFE_MISC */ | ||
| 1086 | #define AFE_BGEN BIT(0) | ||
| 1087 | #define AFE_MBEN BIT(1) | ||
| 1088 | #define MAC_ID_EN BIT(7) | ||
| 1089 | |||
| 1090 | |||
| 1091 | /* 2 SPS0_CTRL */ | ||
| 1092 | |||
| 1093 | |||
| 1094 | /* 2 SPS_OCP_CFG */ | ||
| 1095 | |||
| 1096 | |||
| 1097 | /* 2 RSV_CTRL */ | ||
| 1098 | #define WLOCK_ALL BIT(0) | ||
| 1099 | #define WLOCK_00 BIT(1) | ||
| 1100 | #define WLOCK_04 BIT(2) | ||
| 1101 | #define WLOCK_08 BIT(3) | ||
| 1102 | #define WLOCK_40 BIT(4) | ||
| 1103 | #define R_DIS_PRST_0 BIT(5) | ||
| 1104 | #define R_DIS_PRST_1 BIT(6) | ||
| 1105 | #define LOCK_ALL_EN BIT(7) | ||
| 1106 | |||
| 1107 | /* 2 RF_CTRL */ | ||
| 1108 | #define RF_EN BIT(0) | ||
| 1109 | #define RF_RSTB BIT(1) | ||
| 1110 | #define RF_SDMRSTB BIT(2) | ||
| 1111 | |||
| 1112 | |||
| 1113 | |||
| 1114 | /* 2 LDOA15_CTRL */ | ||
| 1115 | #define LDA15_EN BIT(0) | ||
| 1116 | #define LDA15_STBY BIT(1) | ||
| 1117 | #define LDA15_OBUF BIT(2) | ||
| 1118 | #define LDA15_REG_VOS BIT(3) | ||
| 1119 | #define _LDA15_VOADJ(x) (((x) & 0x7) << 4) | ||
| 1120 | |||
| 1121 | |||
| 1122 | |||
| 1123 | /* 2 LDOV12D_CTRL */ | ||
| 1124 | #define LDV12_EN BIT(0) | ||
| 1125 | #define LDV12_SDBY BIT(1) | ||
| 1126 | #define LPLDO_HSM BIT(2) | ||
| 1127 | #define LPLDO_LSM_DIS BIT(3) | ||
| 1128 | #define _LDV12_VADJ(x) (((x) & 0xF) << 4) | ||
| 1129 | |||
| 1130 | |||
| 1131 | /* 2 AFE_XTAL_CTRL */ | ||
| 1132 | #define XTAL_EN BIT(0) | ||
| 1133 | #define XTAL_BSEL BIT(1) | ||
| 1134 | #define _XTAL_BOSC(x) (((x) & 0x3) << 2) | ||
| 1135 | #define _XTAL_CADJ(x) (((x) & 0xF) << 4) | ||
| 1136 | #define XTAL_GATE_USB BIT(8) | ||
| 1137 | #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) | ||
| 1138 | #define XTAL_GATE_AFE BIT(11) | ||
| 1139 | #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) | ||
| 1140 | #define XTAL_RF_GATE BIT(14) | ||
| 1141 | #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) | ||
| 1142 | #define XTAL_GATE_DIG BIT(17) | ||
| 1143 | #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) | ||
| 1144 | #define XTAL_BT_GATE BIT(20) | ||
| 1145 | #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) | ||
| 1146 | #define _XTAL_GPIO(x) (((x) & 0x7) << 23) | ||
| 1147 | |||
| 1148 | |||
| 1149 | #define CKDLY_AFE BIT(26) | ||
| 1150 | #define CKDLY_USB BIT(27) | ||
| 1151 | #define CKDLY_DIG BIT(28) | ||
| 1152 | #define CKDLY_BT BIT(29) | ||
| 1153 | |||
| 1154 | |||
| 1155 | /* 2 AFE_PLL_CTRL */ | ||
| 1156 | #define APLL_EN BIT(0) | ||
| 1157 | #define APLL_320_EN BIT(1) | ||
| 1158 | #define APLL_FREF_SEL BIT(2) | ||
| 1159 | #define APLL_EDGE_SEL BIT(3) | ||
| 1160 | #define APLL_WDOGB BIT(4) | ||
| 1161 | #define APLL_LPFEN BIT(5) | ||
| 1162 | |||
| 1163 | #define APLL_REF_CLK_13MHZ 0x1 | ||
| 1164 | #define APLL_REF_CLK_19_2MHZ 0x2 | ||
| 1165 | #define APLL_REF_CLK_20MHZ 0x3 | ||
| 1166 | #define APLL_REF_CLK_25MHZ 0x4 | ||
| 1167 | #define APLL_REF_CLK_26MHZ 0x5 | ||
| 1168 | #define APLL_REF_CLK_38_4MHZ 0x6 | ||
| 1169 | #define APLL_REF_CLK_40MHZ 0x7 | ||
| 1170 | |||
| 1171 | #define APLL_320EN BIT(14) | ||
| 1172 | #define APLL_80EN BIT(15) | ||
| 1173 | #define APLL_1MEN BIT(24) | ||
| 1174 | |||
| 1175 | |||
| 1176 | /* 2 EFUSE_CTRL */ | ||
| 1177 | #define ALD_EN BIT(18) | ||
| 1178 | #define EF_PD BIT(19) | ||
| 1179 | #define EF_FLAG BIT(31) | ||
| 1180 | |||
| 1181 | /* 2 EFUSE_TEST (For RTL8723 partially) */ | ||
| 1182 | #define EF_TRPT BIT(7) | ||
| 1183 | /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ | ||
| 1184 | #define EF_CELL_SEL (BIT(8)|BIT(9)) | ||
| 1185 | #define LDOE25_EN BIT(31) | ||
| 1186 | #define EFUSE_SEL(x) (((x) & 0x3) << 8) | ||
| 1187 | #define EFUSE_SEL_MASK 0x300 | ||
| 1188 | #define EFUSE_WIFI_SEL_0 0x0 | ||
| 1189 | #define EFUSE_BT_SEL_0 0x1 | ||
| 1190 | #define EFUSE_BT_SEL_1 0x2 | ||
| 1191 | #define EFUSE_BT_SEL_2 0x3 | ||
| 1192 | |||
| 1193 | #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ | ||
| 1194 | #define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ | ||
| 1195 | |||
| 1196 | /* 2 PWR_DATA */ | ||
| 1197 | |||
| 1198 | /* 2 CAL_TIMER */ | ||
| 1199 | |||
| 1200 | /* 2 ACLK_MON */ | ||
| 1201 | #define RSM_EN BIT(0) | ||
| 1202 | #define Timer_EN BIT(4) | ||
| 1203 | |||
| 1204 | |||
| 1205 | /* 2 GPIO_MUXCFG */ | ||
| 1206 | #define TRSW0EN BIT(2) | ||
| 1207 | #define TRSW1EN BIT(3) | ||
| 1208 | #define EROM_EN BIT(4) | ||
| 1209 | #define EnBT BIT(5) | ||
| 1210 | #define EnUart BIT(8) | ||
| 1211 | #define Uart_910 BIT(9) | ||
| 1212 | #define EnPMAC BIT(10) | ||
| 1213 | #define SIC_SWRST BIT(11) | ||
| 1214 | #define EnSIC BIT(12) | ||
| 1215 | #define SIC_23 BIT(13) | ||
| 1216 | #define EnHDP BIT(14) | ||
| 1217 | #define SIC_LBK BIT(15) | ||
| 1218 | |||
| 1219 | /* 2 GPIO_PIN_CTRL */ | ||
| 1220 | |||
| 1221 | /* GPIO BIT */ | ||
| 1222 | #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) | ||
| 1223 | |||
| 1224 | /* 2 GPIO_INTM */ | ||
| 1225 | |||
| 1226 | /* 2 LEDCFG */ | ||
| 1227 | #define LED0PL BIT(4) | ||
| 1228 | #define LED0DIS BIT(7) | ||
| 1229 | #define LED1DIS BIT(15) | ||
| 1230 | #define LED1PL BIT(12) | ||
| 1231 | |||
| 1232 | #define SECCAM_CLR BIT(30) | ||
| 1233 | |||
| 1234 | |||
| 1235 | /* 2 FSIMR */ | ||
| 1236 | |||
| 1237 | /* 2 FSISR */ | ||
| 1238 | |||
| 1239 | |||
| 1240 | /* 2 8051FWDL */ | ||
| 1241 | /* 2 MCUFWDL */ | ||
| 1242 | #define MCUFWDL_EN BIT(0) | ||
| 1243 | #define MCUFWDL_RDY BIT(1) | ||
| 1244 | #define FWDL_ChkSum_rpt BIT(2) | ||
| 1245 | #define MACINI_RDY BIT(3) | ||
| 1246 | #define BBINI_RDY BIT(4) | ||
| 1247 | #define RFINI_RDY BIT(5) | ||
| 1248 | #define WINTINI_RDY BIT(6) | ||
| 1249 | #define CPRST BIT(23) | ||
| 1250 | |||
| 1251 | /* 2REG_HPON_FSM */ | ||
| 1252 | #define BOND92CE_1T2R_CFG BIT(22) | ||
| 1253 | |||
| 1254 | |||
| 1255 | /* 2 REG_SYS_CFG */ | ||
| 1256 | #define XCLK_VLD BIT(0) | ||
| 1257 | #define ACLK_VLD BIT(1) | ||
| 1258 | #define UCLK_VLD BIT(2) | ||
| 1259 | #define PCLK_VLD BIT(3) | ||
| 1260 | #define PCIRSTB BIT(4) | ||
| 1261 | #define V15_VLD BIT(5) | ||
| 1262 | #define TRP_B15V_EN BIT(7) | ||
| 1263 | #define SIC_IDLE BIT(8) | ||
| 1264 | #define BD_MAC2 BIT(9) | ||
| 1265 | #define BD_MAC1 BIT(10) | ||
| 1266 | #define IC_MACPHY_MODE BIT(11) | ||
| 1267 | #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) | ||
| 1268 | #define BT_FUNC BIT(16) | ||
| 1269 | #define VENDOR_ID BIT(19) | ||
| 1270 | #define PAD_HWPD_IDN BIT(22) | ||
| 1271 | #define TRP_VAUX_EN BIT(23) | ||
| 1272 | #define TRP_BT_EN BIT(24) | ||
| 1273 | #define BD_PKG_SEL BIT(25) | ||
| 1274 | #define BD_HCI_SEL BIT(26) | ||
| 1275 | #define TYPE_ID BIT(27) | ||
| 1276 | |||
| 1277 | #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ | ||
| 1278 | #define CHIP_VER_RTL_SHIFT 12 | ||
| 1279 | |||
| 1280 | /* 2REG_GPIO_OUTSTS (For RTL8723 only) */ | ||
| 1281 | #define EFS_HCI_SEL (BIT(0)|BIT(1)) | ||
| 1282 | #define PAD_HCI_SEL (BIT(2)|BIT(3)) | ||
| 1283 | #define HCI_SEL (BIT(4)|BIT(5)) | ||
| 1284 | #define PKG_SEL_HCI BIT(6) | ||
| 1285 | #define FEN_GPS BIT(7) | ||
| 1286 | #define FEN_BT BIT(8) | ||
| 1287 | #define FEN_WL BIT(9) | ||
| 1288 | #define FEN_PCI BIT(10) | ||
| 1289 | #define FEN_USB BIT(11) | ||
| 1290 | #define BTRF_HWPDN_N BIT(12) | ||
| 1291 | #define WLRF_HWPDN_N BIT(13) | ||
| 1292 | #define PDN_BT_N BIT(14) | ||
| 1293 | #define PDN_GPS_N BIT(15) | ||
| 1294 | #define BT_CTL_HWPDN BIT(16) | ||
| 1295 | #define GPS_CTL_HWPDN BIT(17) | ||
| 1296 | #define PPHY_SUSB BIT(20) | ||
| 1297 | #define UPHY_SUSB BIT(21) | ||
| 1298 | #define PCI_SUSEN BIT(22) | ||
| 1299 | #define USB_SUSEN BIT(23) | ||
| 1300 | #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) | ||
| 1301 | |||
| 1302 | /* */ | ||
| 1303 | /* */ | ||
| 1304 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ | ||
| 1305 | /* */ | ||
| 1306 | /* */ | ||
| 1307 | |||
| 1308 | |||
| 1309 | /* 2 Function Enable Registers */ | ||
| 1310 | /* 2 CR */ | ||
| 1311 | |||
| 1312 | #define REG_LBMODE (REG_CR + 3) | ||
| 1313 | |||
| 1314 | |||
| 1315 | #define HCI_TXDMA_EN BIT(0) | ||
| 1316 | #define HCI_RXDMA_EN BIT(1) | ||
| 1317 | #define TXDMA_EN BIT(2) | ||
| 1318 | #define RXDMA_EN BIT(3) | ||
| 1319 | #define PROTOCOL_EN BIT(4) | ||
| 1320 | #define SCHEDULE_EN BIT(5) | ||
| 1321 | #define MACTXEN BIT(6) | ||
| 1322 | #define MACRXEN BIT(7) | ||
| 1323 | #define ENSWBCN BIT(8) | ||
| 1324 | #define ENSEC BIT(9) | ||
| 1325 | |||
| 1326 | /* Network type */ | ||
| 1327 | #define _NETTYPE(x) (((x) & 0x3) << 16) | ||
| 1328 | #define MASK_NETTYPE 0x30000 | ||
| 1329 | #define NT_NO_LINK 0x0 | ||
| 1330 | #define NT_LINK_AD_HOC 0x1 | ||
| 1331 | #define NT_LINK_AP 0x2 | ||
| 1332 | #define NT_AS_AP 0x3 | ||
| 1333 | |||
| 1334 | #define _LBMODE(x) (((x) & 0xF) << 24) | ||
| 1335 | #define MASK_LBMODE 0xF000000 | ||
| 1336 | #define LOOPBACK_NORMAL 0x0 | ||
| 1337 | #define LOOPBACK_IMMEDIATELY 0xB | ||
| 1338 | #define LOOPBACK_MAC_DELAY 0x3 | ||
| 1339 | #define LOOPBACK_PHY 0x1 | ||
| 1340 | #define LOOPBACK_DMA 0x7 | ||
| 1341 | |||
| 1342 | |||
| 1343 | /* 2 PBP - Page Size Register */ | ||
| 1344 | #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) | ||
| 1345 | #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) | ||
| 1346 | #define _PSRX_MASK 0xF | ||
| 1347 | #define _PSTX_MASK 0xF0 | ||
| 1348 | #define _PSRX(x) (x) | ||
| 1349 | #define _PSTX(x) ((x) << 4) | ||
| 1350 | |||
| 1351 | #define PBP_64 0x0 | ||
| 1352 | #define PBP_128 0x1 | ||
| 1353 | #define PBP_256 0x2 | ||
| 1354 | #define PBP_512 0x3 | ||
| 1355 | #define PBP_1024 0x4 | ||
| 1356 | |||
| 1357 | |||
| 1358 | /* 2 TX/RXDMA */ | ||
| 1359 | #define RXDMA_ARBBW_EN BIT(0) | ||
| 1360 | #define RXSHFT_EN BIT(1) | ||
| 1361 | #define RXDMA_AGG_EN BIT(2) | ||
| 1362 | #define QS_VO_QUEUE BIT(8) | ||
| 1363 | #define QS_VI_QUEUE BIT(9) | ||
| 1364 | #define QS_BE_QUEUE BIT(10) | ||
| 1365 | #define QS_BK_QUEUE BIT(11) | ||
| 1366 | #define QS_MANAGER_QUEUE BIT(12) | ||
| 1367 | #define QS_HIGH_QUEUE BIT(13) | ||
| 1368 | |||
| 1369 | #define HQSEL_VOQ BIT(0) | ||
| 1370 | #define HQSEL_VIQ BIT(1) | ||
| 1371 | #define HQSEL_BEQ BIT(2) | ||
| 1372 | #define HQSEL_BKQ BIT(3) | ||
| 1373 | #define HQSEL_MGTQ BIT(4) | ||
| 1374 | #define HQSEL_HIQ BIT(5) | ||
| 1375 | |||
| 1376 | /* For normal driver, 0x10C */ | ||
| 1377 | #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) | ||
| 1378 | #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) | ||
| 1379 | #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) | ||
| 1380 | #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) | ||
| 1381 | #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) | ||
| 1382 | #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) | ||
| 1383 | |||
| 1384 | #define QUEUE_LOW 1 | ||
| 1385 | #define QUEUE_NORMAL 2 | ||
| 1386 | #define QUEUE_HIGH 3 | ||
| 1387 | |||
| 1388 | |||
| 1389 | |||
| 1390 | /* 2 TRXFF_BNDY */ | ||
| 1391 | |||
| 1392 | |||
| 1393 | /* 2 LLT_INIT */ | ||
| 1394 | #define _LLT_NO_ACTIVE 0x0 | ||
| 1395 | #define _LLT_WRITE_ACCESS 0x1 | ||
| 1396 | #define _LLT_READ_ACCESS 0x2 | ||
| 1397 | |||
| 1398 | #define _LLT_INIT_DATA(x) ((x) & 0xFF) | ||
| 1399 | #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) | ||
| 1400 | #define _LLT_OP(x) (((x) & 0x3) << 30) | ||
| 1401 | #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) | ||
| 1402 | |||
| 1403 | |||
| 1404 | /* 2 BB_ACCESS_CTRL */ | ||
| 1405 | #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) | ||
| 1406 | #define BB_WRITE_EN BIT(30) | ||
| 1407 | #define BB_READ_EN BIT(31) | ||
| 1408 | /* define BB_ADDR_MASK 0xFFF */ | ||
| 1409 | /* define _BB_ADDR(x) ((x) & BB_ADDR_MASK) */ | ||
| 1410 | |||
| 1411 | /* */ | ||
| 1412 | /* */ | ||
| 1413 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ | ||
| 1414 | /* */ | ||
| 1415 | /* */ | ||
| 1416 | /* 2 RQPN */ | ||
| 1417 | #define _HPQ(x) ((x) & 0xFF) | ||
| 1418 | #define _LPQ(x) (((x) & 0xFF) << 8) | ||
| 1419 | #define _PUBQ(x) (((x) & 0xFF) << 16) | ||
| 1420 | /* NOTE: in RQPN_NPQ register */ | ||
| 1421 | #define _NPQ(x) ((x) & 0xFF) | ||
| 1422 | |||
| 1423 | |||
| 1424 | #define HPQ_PUBLIC_DIS BIT(24) | ||
| 1425 | #define LPQ_PUBLIC_DIS BIT(25) | ||
| 1426 | #define LD_RQPN BIT(31) | ||
| 1427 | |||
| 1428 | |||
| 1429 | /* 2 TDECTRL */ | ||
| 1430 | #define BCN_VALID BIT(16) | ||
| 1431 | #define BCN_HEAD(x) (((x) & 0xFF) << 8) | ||
| 1432 | #define BCN_HEAD_MASK 0xFF00 | ||
| 1433 | |||
| 1434 | /* 2 TDECTL */ | ||
| 1435 | #define BLK_DESC_NUM_SHIFT 4 | ||
| 1436 | #define BLK_DESC_NUM_MASK 0xF | ||
| 1437 | |||
| 1438 | |||
| 1439 | /* 2 TXDMA_OFFSET_CHK */ | ||
| 1440 | #define DROP_DATA_EN BIT(9) | ||
| 1441 | |||
| 1442 | /* */ | ||
| 1443 | /* */ | ||
| 1444 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ | ||
| 1445 | /* */ | ||
| 1446 | /* */ | ||
| 1447 | /* 2 FWHW_TXQ_CTRL */ | ||
| 1448 | #define EN_AMPDU_RTY_NEW BIT(7) | ||
| 1449 | |||
| 1450 | /* 2 INIRTSMCS_SEL */ | ||
| 1451 | #define _INIRTSMCS_SEL(x) ((x) & 0x3F) | ||
| 1452 | |||
| 1453 | |||
| 1454 | /* 2 SPEC SIFS */ | ||
| 1455 | #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) | ||
| 1456 | #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) | ||
| 1457 | |||
| 1458 | |||
| 1459 | /* 2 RRSR */ | ||
| 1460 | |||
| 1461 | #define RATE_REG_BITMAP_ALL 0xFFFFF | ||
| 1462 | |||
| 1463 | #define _RRSC_BITMAP(x) ((x) & 0xFFFFF) | ||
| 1464 | |||
| 1465 | #define _RRSR_RSC(x) (((x) & 0x3) << 21) | ||
| 1466 | #define RRSR_RSC_RESERVED 0x0 | ||
| 1467 | #define RRSR_RSC_UPPER_SUBCHANNEL 0x1 | ||
| 1468 | #define RRSR_RSC_LOWER_SUBCHANNEL 0x2 | ||
| 1469 | #define RRSR_RSC_DUPLICATE_MODE 0x3 | ||
| 1470 | |||
| 1471 | |||
| 1472 | /* 2 ARFR */ | ||
| 1473 | #define USE_SHORT_G1 BIT(20) | ||
| 1474 | |||
| 1475 | /* 2 AGGLEN_LMT_L */ | ||
| 1476 | #define _AGGLMT_MCS0(x) ((x) & 0xF) | ||
| 1477 | #define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) | ||
| 1478 | #define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) | ||
| 1479 | #define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) | ||
| 1480 | #define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) | ||
| 1481 | #define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) | ||
| 1482 | #define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) | ||
| 1483 | #define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) | ||
| 1484 | |||
| 1485 | |||
| 1486 | /* 2 RL */ | ||
| 1487 | #define RETRY_LIMIT_SHORT_SHIFT 8 | ||
| 1488 | #define RETRY_LIMIT_LONG_SHIFT 0 | ||
| 1489 | |||
| 1490 | |||
| 1491 | /* 2 DARFRC */ | ||
| 1492 | #define _DARF_RC1(x) ((x) & 0x1F) | ||
| 1493 | #define _DARF_RC2(x) (((x) & 0x1F) << 8) | ||
| 1494 | #define _DARF_RC3(x) (((x) & 0x1F) << 16) | ||
| 1495 | #define _DARF_RC4(x) (((x) & 0x1F) << 24) | ||
| 1496 | /* NOTE: shift starting from address (DARFRC + 4) */ | ||
| 1497 | #define _DARF_RC5(x) ((x) & 0x1F) | ||
| 1498 | #define _DARF_RC6(x) (((x) & 0x1F) << 8) | ||
| 1499 | #define _DARF_RC7(x) (((x) & 0x1F) << 16) | ||
| 1500 | #define _DARF_RC8(x) (((x) & 0x1F) << 24) | ||
| 1501 | |||
| 1502 | |||
| 1503 | /* 2 RARFRC */ | ||
| 1504 | #define _RARF_RC1(x) ((x) & 0x1F) | ||
| 1505 | #define _RARF_RC2(x) (((x) & 0x1F) << 8) | ||
| 1506 | #define _RARF_RC3(x) (((x) & 0x1F) << 16) | ||
| 1507 | #define _RARF_RC4(x) (((x) & 0x1F) << 24) | ||
| 1508 | /* NOTE: shift starting from address (RARFRC + 4) */ | ||
| 1509 | #define _RARF_RC5(x) ((x) & 0x1F) | ||
| 1510 | #define _RARF_RC6(x) (((x) & 0x1F) << 8) | ||
| 1511 | #define _RARF_RC7(x) (((x) & 0x1F) << 16) | ||
| 1512 | #define _RARF_RC8(x) (((x) & 0x1F) << 24) | ||
| 1513 | |||
| 1514 | |||
| 1515 | /* */ | ||
| 1516 | /* */ | ||
| 1517 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ | ||
| 1518 | /* */ | ||
| 1519 | /* */ | ||
| 1520 | |||
| 1521 | |||
| 1522 | |||
| 1523 | /* 2 EDCA setting */ | ||
| 1524 | #define AC_PARAM_TXOP_LIMIT_OFFSET 16 | ||
| 1525 | #define AC_PARAM_ECW_MAX_OFFSET 12 | ||
| 1526 | #define AC_PARAM_ECW_MIN_OFFSET 8 | ||
| 1527 | #define AC_PARAM_AIFS_OFFSET 0 | ||
| 1528 | |||
| 1529 | |||
| 1530 | /* 2 EDCA_VO_PARAM */ | ||
| 1531 | #define _AIFS(x) (x) | ||
| 1532 | #define _ECW_MAX_MIN(x) ((x) << 8) | ||
| 1533 | #define _TXOP_LIMIT(x) ((x) << 16) | ||
| 1534 | |||
| 1535 | |||
| 1536 | #define _BCNIFS(x) ((x) & 0xFF) | ||
| 1537 | #define _BCNECW(x) (((x) & 0xF))<< 8) | ||
| 1538 | |||
| 1539 | |||
| 1540 | #define _LRL(x) ((x) & 0x3F) | ||
| 1541 | #define _SRL(x) (((x) & 0x3F) << 8) | ||
| 1542 | |||
| 1543 | |||
| 1544 | /* 2 SIFS_CCK */ | ||
| 1545 | #define _SIFS_CCK_CTX(x) ((x) & 0xFF) | ||
| 1546 | #define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); | ||
| 1547 | |||
| 1548 | |||
| 1549 | /* 2 SIFS_OFDM */ | ||
| 1550 | #define _SIFS_OFDM_CTX(x) ((x) & 0xFF) | ||
| 1551 | #define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); | ||
| 1552 | |||
| 1553 | |||
| 1554 | /* 2 TBTT PROHIBIT */ | ||
| 1555 | #define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) | ||
| 1556 | |||
| 1557 | |||
| 1558 | /* 2 REG_RD_CTRL */ | ||
| 1559 | #define DIS_EDCA_CNT_DWN BIT(11) | ||
| 1560 | |||
| 1561 | |||
| 1562 | /* 2 BCN_CTRL */ | ||
| 1563 | #define EN_MBSSID BIT(1) | ||
| 1564 | #define EN_TXBCN_RPT BIT(2) | ||
| 1565 | #define EN_BCN_FUNCTION BIT(3) | ||
| 1566 | #define DIS_TSF_UPDATE BIT(3) | ||
| 1567 | |||
| 1568 | /* The same function but different bit field. */ | ||
| 1569 | #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) | ||
| 1570 | #define DIS_TSF_UDT0_TEST_CHIP BIT(5) | ||
| 1571 | |||
| 1572 | /* 2 ACMHWCTRL */ | ||
| 1573 | #define AcmHw_HwEn BIT(0) | ||
| 1574 | #define AcmHw_BeqEn BIT(1) | ||
| 1575 | #define AcmHw_ViqEn BIT(2) | ||
| 1576 | #define AcmHw_VoqEn BIT(3) | ||
| 1577 | #define AcmHw_BeqStatus BIT(4) | ||
| 1578 | #define AcmHw_ViqStatus BIT(5) | ||
| 1579 | #define AcmHw_VoqStatus BIT(6) | ||
| 1580 | |||
| 1581 | |||
| 1582 | |||
| 1583 | /* */ | ||
| 1584 | /* */ | ||
| 1585 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ | ||
| 1586 | /* */ | ||
| 1587 | /* */ | ||
| 1588 | |||
| 1589 | /* 2 APSD_CTRL */ | ||
| 1590 | #define APSDOFF BIT(6) | ||
| 1591 | #define APSDOFF_STATUS BIT(7) | ||
| 1592 | |||
| 1593 | |||
| 1594 | /* 2 BWOPMODE */ | ||
| 1595 | #define BW_20MHZ BIT(2) | ||
| 1596 | |||
| 1597 | |||
| 1598 | #define RATE_BITMAP_ALL 0xFFFFF | ||
| 1599 | |||
| 1600 | /* Only use CCK 1M rate for ACK */ | ||
| 1601 | #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 | ||
| 1602 | |||
| 1603 | /* 2 TCR */ | ||
| 1604 | #define TSFRST BIT(0) | ||
| 1605 | #define DIS_GCLK BIT(1) | ||
| 1606 | #define PAD_SEL BIT(2) | ||
| 1607 | #define PWR_ST BIT(6) | ||
| 1608 | #define PWRBIT_OW_EN BIT(7) | ||
| 1609 | #define ACRC BIT(8) | ||
| 1610 | #define CFENDFORM BIT(9) | ||
| 1611 | #define ICV BIT(10) | ||
| 1612 | |||
| 1613 | |||
| 1614 | |||
| 1615 | /* 2 RCR */ | ||
| 1616 | #define AAP BIT(0) | ||
| 1617 | #define APM BIT(1) | ||
| 1618 | #define AM BIT(2) | ||
| 1619 | #define AB BIT(3) | ||
| 1620 | #define ADD3 BIT(4) | ||
| 1621 | #define APWRMGT BIT(5) | ||
| 1622 | #define CBSSID BIT(6) | ||
| 1623 | #define CBSSID_BCN BIT(7) | ||
| 1624 | #define ACRC32 BIT(8) | ||
| 1625 | #define AICV BIT(9) | ||
| 1626 | #define ADF BIT(11) | ||
| 1627 | #define ACF BIT(12) | ||
| 1628 | #define AMF BIT(13) | ||
| 1629 | #define HTC_LOC_CTRL BIT(14) | ||
| 1630 | #define UC_DATA_EN BIT(16) | ||
| 1631 | #define BM_DATA_EN BIT(17) | ||
| 1632 | #define MFBEN BIT(22) | ||
| 1633 | #define LSIGEN BIT(23) | ||
| 1634 | #define EnMBID BIT(24) | ||
| 1635 | #define APP_BASSN BIT(27) | ||
| 1636 | #define APP_PHYSTS BIT(28) | ||
| 1637 | #define APP_ICV BIT(29) | ||
| 1638 | #define APP_MIC BIT(30) | ||
| 1639 | #define APP_FCS BIT(31) | ||
| 1640 | |||
| 1641 | /* 2 RX_PKT_LIMIT */ | ||
| 1642 | |||
| 1643 | /* 2 RX_DLK_TIME */ | ||
| 1644 | |||
| 1645 | /* 2 MBIDCAMCFG */ | ||
| 1646 | |||
| 1647 | |||
| 1648 | |||
| 1649 | /* 2 AMPDU_MIN_SPACE */ | ||
| 1650 | #define _MIN_SPACE(x) ((x) & 0x7) | ||
| 1651 | #define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) | ||
| 1652 | |||
| 1653 | |||
| 1654 | /* 2 RXERR_RPT */ | ||
| 1655 | #define RXERR_TYPE_OFDM_PPDU 0 | ||
| 1656 | #define RXERR_TYPE_OFDMfalse_ALARM 1 | ||
| 1657 | #define RXERR_TYPE_OFDM_MPDU_OK 2 | ||
| 1658 | #define RXERR_TYPE_OFDM_MPDU_FAIL 3 | ||
| 1659 | #define RXERR_TYPE_CCK_PPDU 4 | ||
| 1660 | #define RXERR_TYPE_CCKfalse_ALARM 5 | ||
| 1661 | #define RXERR_TYPE_CCK_MPDU_OK 6 | ||
| 1662 | #define RXERR_TYPE_CCK_MPDU_FAIL 7 | ||
| 1663 | #define RXERR_TYPE_HT_PPDU 8 | ||
| 1664 | #define RXERR_TYPE_HTfalse_ALARM 9 | ||
| 1665 | #define RXERR_TYPE_HT_MPDU_TOTAL 10 | ||
| 1666 | #define RXERR_TYPE_HT_MPDU_OK 11 | ||
| 1667 | #define RXERR_TYPE_HT_MPDU_FAIL 12 | ||
| 1668 | #define RXERR_TYPE_RX_FULL_DROP 15 | ||
| 1669 | |||
| 1670 | #define RXERR_COUNTER_MASK 0xFFFFF | ||
| 1671 | #define RXERR_RPT_RST BIT(27) | ||
| 1672 | #define _RXERR_RPT_SEL(type) ((type) << 28) | ||
| 1673 | |||
| 1674 | |||
| 1675 | /* 2 SECCFG */ | ||
| 1676 | #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ | ||
| 1677 | #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ | ||
| 1678 | #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ | ||
| 1679 | #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ | ||
| 1680 | #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ | ||
| 1681 | #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ | ||
| 1682 | |||
| 1683 | |||
| 1684 | |||
| 1685 | /* */ | ||
| 1686 | /* */ | ||
| 1687 | /* 0xFE00h ~ 0xFE55h USB Configuration */ | ||
| 1688 | /* */ | ||
| 1689 | /* */ | ||
| 1690 | |||
| 1691 | /* 2 USB Information (0xFE17) */ | ||
| 1692 | #define USB_IS_HIGH_SPEED 0 | ||
| 1693 | #define USB_IS_FULL_SPEED 1 | ||
| 1694 | #define USB_SPEED_MASK BIT(5) | ||
| 1695 | |||
| 1696 | #define USB_NORMAL_SIE_EP_MASK 0xF | ||
| 1697 | #define USB_NORMAL_SIE_EP_SHIFT 4 | ||
| 1698 | |||
| 1699 | #define USB_TEST_EP_MASK 0x30 | ||
| 1700 | #define USB_TEST_EP_SHIFT 4 | ||
| 1701 | |||
| 1702 | /* 2 Special Option */ | ||
| 1703 | #define USB_AGG_EN BIT(3) | ||
| 1704 | |||
| 1705 | |||
| 1706 | /* 2REG_C2HEVT_CLEAR */ | ||
| 1707 | /* Set by driver and notify FW that the driver has read the | ||
| 1708 | C2H command message */ | ||
| 1709 | #define C2H_EVT_HOST_CLOSE 0x00 | ||
| 1710 | /* Set by FW indicating that FW had set the C2H command message | ||
| 1711 | and it's not yet read by driver. */ | ||
| 1712 | #define C2H_EVT_FW_CLOSE 0xFF | ||
| 1713 | |||
| 1714 | |||
| 1715 | /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ | ||
| 1716 | /* Enable GPIO[9] as WiFi HW PDn source */ | ||
| 1717 | #define WL_HWPDN_EN BIT0 | ||
| 1718 | /* WiFi HW PDn polarity control */ | ||
| 1719 | #define WL_HWPDN_SL BIT1 | ||
| 1720 | /* WiFi function enable */ | ||
| 1721 | #define WL_FUNC_EN BIT2 | ||
| 1722 | /* Enable GPIO[9] as WiFi RF HW PDn source */ | ||
| 1723 | #define WL_HWROF_EN BIT3 | ||
| 1724 | /* Enable GPIO[11] as BT HW PDn source */ | ||
| 1725 | #define BT_HWPDN_EN BIT16 | ||
| 1726 | /* BT HW PDn polarity control */ | ||
| 1727 | #define BT_HWPDN_SL BIT17 | ||
| 1728 | /* BT function enable */ | ||
| 1729 | #define BT_FUNC_EN BIT18 | ||
| 1730 | /* Enable GPIO[11] as BT/GPS RF HW PDn source */ | ||
| 1731 | #define BT_HWROF_EN BIT19 | ||
| 1732 | /* Enable GPIO[10] as GPS HW PDn source */ | ||
| 1733 | #define GPS_HWPDN_EN BIT20 | ||
| 1734 | /* GPS HW PDn polarity control */ | ||
| 1735 | #define GPS_HWPDN_SL BIT21 | ||
| 1736 | /* GPS function enable */ | ||
| 1737 | #define GPS_FUNC_EN BIT22 | ||
| 1738 | |||
| 1739 | /* 3 REG_LIFECTRL_CTRL */ | ||
| 1740 | #define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 | ||
| 1741 | #define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 | ||
| 1742 | #define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 | ||
| 1743 | #define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 | ||
| 1744 | |||
| 1745 | #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ | ||
| 1746 | |||
| 1747 | /* */ | ||
| 1748 | /* General definitions */ | ||
| 1749 | /* */ | ||
| 1750 | |||
| 1751 | #define LAST_ENTRY_OF_TX_PKT_BUFFER 255 | ||
| 1752 | |||
| 1753 | #define POLLING_LLT_THRESHOLD 20 | ||
| 1754 | #define POLLING_READY_TIMEOUT_COUNT 1000 | ||
| 1755 | |||
| 1756 | /* Min Spacing related settings. */ | ||
| 1757 | #define MAX_MSS_DENSITY_2T 0x13 | ||
| 1758 | #define MAX_MSS_DENSITY_1T 0x0A | ||
| 1759 | |||
| 1760 | /* */ | ||
| 1761 | /* 8723A Regsiter offset definition */ | ||
| 1762 | /* */ | ||
| 1763 | #define HAL_8723A_NAV_UPPER_UNIT 128 /* micro-second */ | ||
| 1764 | |||
| 1765 | /* */ | ||
| 1766 | /* */ | ||
| 1767 | /* 0x0000h ~ 0x00FFh System Configuration */ | ||
| 1768 | /* */ | ||
| 1769 | /* */ | ||
| 1770 | #define REG_SYSON_REG_LOCK 0x001C | ||
| 1771 | |||
| 1772 | |||
| 1773 | /* */ | ||
| 1774 | /* */ | ||
| 1775 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ | ||
| 1776 | /* */ | ||
| 1777 | /* */ | ||
| 1778 | #define REG_FTIMR 0x0138 | ||
| 1779 | |||
| 1780 | |||
| 1781 | /* */ | ||
| 1782 | /* */ | ||
| 1783 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ | ||
| 1784 | /* */ | ||
| 1785 | /* */ | ||
| 1786 | |||
| 1787 | |||
| 1788 | /* */ | ||
| 1789 | /* */ | ||
| 1790 | /* 0x0280h ~ 0x02FFh RXDMA Configuration */ | ||
| 1791 | /* */ | ||
| 1792 | /* */ | ||
| 1793 | |||
| 1794 | |||
| 1795 | /* */ | ||
| 1796 | /* */ | ||
| 1797 | /* 0x0300h ~ 0x03FFh PCIe */ | ||
| 1798 | /* */ | ||
| 1799 | /* */ | ||
| 1800 | |||
| 1801 | |||
| 1802 | /* */ | ||
| 1803 | /* */ | ||
| 1804 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ | ||
| 1805 | /* */ | ||
| 1806 | /* */ | ||
| 1807 | #define REG_EARLY_MODE_CONTROL 0x4D0 | ||
| 1808 | |||
| 1809 | |||
| 1810 | /* */ | ||
| 1811 | /* */ | ||
| 1812 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ | ||
| 1813 | /* */ | ||
| 1814 | /* */ | ||
| 1815 | |||
| 1816 | /* 2 BCN_CTRL */ | ||
| 1817 | #define DIS_ATIM BIT(0) | ||
| 1818 | #define DIS_BCNQ_SUB BIT(1) | ||
| 1819 | #define DIS_TSF_UDT BIT(4) | ||
| 1820 | |||
| 1821 | |||
| 1822 | /* */ | ||
| 1823 | /* */ | ||
| 1824 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ | ||
| 1825 | /* */ | ||
| 1826 | /* */ | ||
| 1827 | /* */ | ||
| 1828 | /* Note: */ | ||
| 1829 | /* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. | ||
| 1830 | * The default value is always too small, but the WiFi TestPlan test | ||
| 1831 | * by 25,000 microseconds of NAV through sending CTS in the air. We | ||
| 1832 | * must update this value greater than 25,000 microseconds to pass the | ||
| 1833 | * item. | ||
| 1834 | * The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset | ||
| 1835 | * should be 0x0652. Commented by SD1 Scott. */ | ||
| 1836 | /* By Bruce, 2011-07-18. */ | ||
| 1837 | /* */ | ||
| 1838 | #define REG_NAV_UPPER 0x0652 /* unit of 128 */ | ||
| 1839 | |||
| 1840 | |||
| 1841 | /* */ | ||
| 1842 | /* 8723 Regsiter Bit and Content definition */ | ||
| 1843 | /* */ | ||
| 1844 | |||
| 1845 | /* */ | ||
| 1846 | /* */ | ||
| 1847 | /* 0x0000h ~ 0x00FFh System Configuration */ | ||
| 1848 | /* */ | ||
| 1849 | /* */ | ||
| 1850 | |||
| 1851 | /* 2 SPS0_CTRL */ | ||
| 1852 | |||
| 1853 | /* 2 SYS_ISO_CTRL */ | ||
| 1854 | |||
| 1855 | /* 2 SYS_FUNC_EN */ | ||
| 1856 | |||
| 1857 | /* 2 APS_FSMCO */ | ||
| 1858 | #define EN_WLON BIT(16) | ||
| 1859 | |||
| 1860 | /* 2 SYS_CLKR */ | ||
| 1861 | |||
| 1862 | /* 2 9346CR */ | ||
| 1863 | |||
| 1864 | /* 2 AFE_MISC */ | ||
| 1865 | |||
| 1866 | /* 2 SPS0_CTRL */ | ||
| 1867 | |||
| 1868 | /* 2 SPS_OCP_CFG */ | ||
| 1869 | |||
| 1870 | /* 2 SYSON_REG_LOCK */ | ||
| 1871 | #define WLOCK_ALL BIT(0) | ||
| 1872 | #define WLOCK_00 BIT(1) | ||
| 1873 | #define WLOCK_04 BIT(2) | ||
| 1874 | #define WLOCK_08 BIT(3) | ||
| 1875 | #define WLOCK_40 BIT(4) | ||
| 1876 | #define WLOCK_1C_B6 BIT(5) | ||
| 1877 | #define R_DIS_PRST_1 BIT(6) | ||
| 1878 | #define LOCK_ALL_EN BIT(7) | ||
| 1879 | |||
| 1880 | /* 2 RF_CTRL */ | ||
| 1881 | |||
| 1882 | /* 2 LDOA15_CTRL */ | ||
| 1883 | |||
| 1884 | /* 2 LDOV12D_CTRL */ | ||
| 1885 | |||
| 1886 | /* 2 AFE_XTAL_CTRL */ | ||
| 1887 | |||
| 1888 | /* 2 AFE_PLL_CTRL */ | ||
| 1889 | |||
| 1890 | /* 2 EFUSE_CTRL */ | ||
| 1891 | |||
| 1892 | /* 2 EFUSE_TEST (For RTL8723 partially) */ | ||
| 1893 | |||
| 1894 | /* 2 PWR_DATA */ | ||
| 1895 | |||
| 1896 | /* 2 CAL_TIMER */ | ||
| 1897 | |||
| 1898 | /* 2 ACLK_MON */ | ||
| 1899 | |||
| 1900 | /* 2 GPIO_MUXCFG */ | ||
| 1901 | |||
| 1902 | /* 2 GPIO_PIN_CTRL */ | ||
| 1903 | |||
| 1904 | /* 2 GPIO_INTM */ | ||
| 1905 | |||
| 1906 | /* 2 LEDCFG */ | ||
| 1907 | |||
| 1908 | /* 2 FSIMR */ | ||
| 1909 | |||
| 1910 | /* 2 FSISR */ | ||
| 1911 | |||
| 1912 | /* 2 HSIMR */ | ||
| 1913 | /* 8723 Host System Interrupt Mask Register (offset 0x58, 32 byte) */ | ||
| 1914 | #define HSIMR_GPIO12_0_INT_EN BIT(0) | ||
| 1915 | #define HSIMR_SPS_OCP_INT_EN BIT(5) | ||
| 1916 | #define HSIMR_RON_INT_EN BIT(6) | ||
| 1917 | #define HSIMR_PDNINT_EN BIT(7) | ||
| 1918 | #define HSIMR_GPIO9_INT_EN BIT(25) | ||
| 1919 | |||
| 1920 | /* 2 HSISR */ | ||
| 1921 | /* 8723 Host System Interrupt Status Register (offset 0x5C, 32 byte) */ | ||
| 1922 | #define HSISR_GPIO12_0_INT BIT(0) | ||
| 1923 | #define HSISR_SPS_OCP_INT BIT(5) | ||
| 1924 | #define HSISR_RON_INT BIT(6) | ||
| 1925 | #define HSISR_PDNINT BIT(7) | ||
| 1926 | #define HSISR_GPIO9_INT BIT(25) | ||
| 1927 | |||
| 1928 | /* interrupt mask which needs to clear */ | ||
| 1929 | #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT | \ | ||
| 1930 | HSISR_SPS_OCP_INT | \ | ||
| 1931 | HSISR_RON_INT | \ | ||
| 1932 | HSISR_PDNINT | \ | ||
| 1933 | HSISR_GPIO9_INT) | ||
| 1934 | |||
| 1935 | /* 2 MCUFWDL */ | ||
| 1936 | #define RAM_DL_SEL BIT7 /* 1:RAM, 0:ROM */ | ||
| 1937 | |||
| 1938 | /* 2 HPON_FSM */ | ||
| 1939 | |||
| 1940 | /* 2 SYS_CFG */ | ||
| 1941 | #define RTL_ID BIT(23) /* TestChip ID, | ||
| 1942 | 1:Test(RLE); 0:MP(RL) */ | ||
| 1943 | #define SPS_SEL BIT(24) /* 1:LDO regulator mode; | ||
| 1944 | 0:Switching regulator mode*/ | ||
| 1945 | |||
| 1946 | |||
| 1947 | /* */ | ||
| 1948 | /* */ | ||
| 1949 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ | ||
| 1950 | /* */ | ||
| 1951 | /* */ | ||
| 1952 | |||
| 1953 | /* 2 Function Enable Registers */ | ||
| 1954 | |||
| 1955 | /* 2 CR */ | ||
| 1956 | #define CALTMR_EN BIT(10) | ||
| 1957 | |||
| 1958 | /* 2 PBP - Page Size Register */ | ||
| 1959 | |||
| 1960 | /* 2 TX/RXDMA */ | ||
| 1961 | |||
| 1962 | /* 2 TRXFF_BNDY */ | ||
| 1963 | |||
| 1964 | /* 2 LLT_INIT */ | ||
| 1965 | |||
| 1966 | /* 2 BB_ACCESS_CTRL */ | ||
| 1967 | |||
| 1968 | |||
| 1969 | /* */ | ||
| 1970 | /* */ | ||
| 1971 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ | ||
| 1972 | /* */ | ||
| 1973 | /* */ | ||
| 1974 | |||
| 1975 | /* 2 RQPN */ | ||
| 1976 | |||
| 1977 | /* 2 TDECTRL */ | ||
| 1978 | |||
| 1979 | /* 2 TDECTL */ | ||
| 1980 | |||
| 1981 | /* 2 TXDMA_OFFSET_CHK */ | ||
| 1982 | |||
| 1983 | |||
| 1984 | /* */ | ||
| 1985 | /* */ | ||
| 1986 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ | ||
| 1987 | /* */ | ||
| 1988 | /* */ | ||
| 1989 | |||
| 1990 | /* 2 FWHW_TXQ_CTRL */ | ||
| 1991 | |||
| 1992 | /* 2 INIRTSMCS_SEL */ | ||
| 1993 | |||
| 1994 | /* 2 SPEC SIFS */ | ||
| 1995 | |||
| 1996 | /* 2 RRSR */ | ||
| 1997 | |||
| 1998 | /* 2 ARFR */ | ||
| 1999 | |||
| 2000 | /* 2 AGGLEN_LMT_L */ | ||
| 2001 | |||
| 2002 | /* 2 RL */ | ||
| 2003 | |||
| 2004 | /* 2 DARFRC */ | ||
| 2005 | |||
| 2006 | /* 2 RARFRC */ | ||
| 2007 | |||
| 2008 | |||
| 2009 | /* */ | ||
| 2010 | /* */ | ||
| 2011 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ | ||
| 2012 | /* */ | ||
| 2013 | /* */ | ||
| 2014 | |||
| 2015 | /* 2 EDCA setting */ | ||
| 2016 | |||
| 2017 | /* 2 EDCA_VO_PARAM */ | ||
| 2018 | |||
| 2019 | /* 2 SIFS_CCK */ | ||
| 2020 | |||
| 2021 | /* 2 SIFS_OFDM */ | ||
| 2022 | |||
| 2023 | /* 2 TBTT PROHIBIT */ | ||
| 2024 | |||
| 2025 | /* 2 REG_RD_CTRL */ | ||
| 2026 | |||
| 2027 | /* 2 BCN_CTRL */ | ||
| 2028 | |||
| 2029 | /* 2 ACMHWCTRL */ | ||
| 2030 | |||
| 2031 | |||
| 2032 | /* */ | ||
| 2033 | /* */ | ||
| 2034 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ | ||
| 2035 | /* */ | ||
| 2036 | /* */ | ||
| 2037 | |||
| 2038 | /* 2 APSD_CTRL */ | ||
| 2039 | |||
| 2040 | /* 2 BWOPMODE */ | ||
| 2041 | |||
| 2042 | /* 2 TCR */ | ||
| 2043 | |||
| 2044 | /* 2 RCR */ | ||
| 2045 | |||
| 2046 | /* 2 RX_PKT_LIMIT */ | ||
| 2047 | |||
| 2048 | /* 2 RX_DLK_TIME */ | ||
| 2049 | |||
| 2050 | /* 2 MBIDCAMCFG */ | ||
| 2051 | |||
| 2052 | /* 2 AMPDU_MIN_SPACE */ | ||
| 2053 | |||
| 2054 | /* 2 RXERR_RPT */ | ||
| 2055 | |||
| 2056 | /* 2 SECCFG */ | ||
| 2057 | |||
| 2058 | |||
| 2059 | /* */ | ||
| 2060 | /* */ | ||
| 2061 | /* 0xFE00h ~ 0xFE55h RTL8723 SDIO Configuration */ | ||
| 2062 | /* */ | ||
| 2063 | /* */ | ||
| 2064 | |||
| 2065 | /* I/O bus domain address mapping */ | ||
| 2066 | #define WLAN_IOREG_BASE 0x10260000 | ||
| 2067 | #define FIRMWARE_FIFO_BASE 0x10270000 | ||
| 2068 | #define TX_HIQ_BASE 0x10310000 | ||
| 2069 | #define TX_MIQ_BASE 0x10320000 | ||
| 2070 | #define TX_LOQ_BASE 0x10330000 | ||
| 2071 | #define RX_RX0FF_BASE 0x10340000 | ||
| 2072 | |||
| 2073 | /* SDIO host local register space mapping. */ | ||
| 2074 | #define WLAN_IOREG_MSK 0x7FFF | ||
| 2075 | #define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ | ||
| 2076 | #define WLAN_RX0FF_MSK 0x0003 | ||
| 2077 | |||
| 2078 | #define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ | ||
| 2079 | #define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ | ||
| 2080 | |||
| 2081 | /* 8723 EFUSE */ | ||
| 2082 | #define HWSET_MAX_SIZE 256 | ||
| 2083 | |||
| 2084 | |||
| 2085 | /* USB interrupt */ | ||
| 2086 | #define UHIMR_TIMEOUT2 BIT31 | ||
| 2087 | #define UHIMR_TIMEOUT1 BIT30 | ||
| 2088 | #define UHIMR_PSTIMEOUT BIT29 | ||
| 2089 | #define UHIMR_GTINT4 BIT28 | ||
| 2090 | #define UHIMR_GTINT3 BIT27 | ||
| 2091 | #define UHIMR_TXBCNERR BIT26 | ||
| 2092 | #define UHIMR_TXBCNOK BIT25 | ||
| 2093 | #define UHIMR_TSF_BIT32_TOGGLE BIT24 | ||
| 2094 | #define UHIMR_BCNDMAINT3 BIT23 | ||
| 2095 | #define UHIMR_BCNDMAINT2 BIT22 | ||
| 2096 | #define UHIMR_BCNDMAINT1 BIT21 | ||
| 2097 | #define UHIMR_BCNDMAINT0 BIT20 | ||
| 2098 | #define UHIMR_BCNDOK3 BIT19 | ||
| 2099 | #define UHIMR_BCNDOK2 BIT18 | ||
| 2100 | #define UHIMR_BCNDOK1 BIT17 | ||
| 2101 | #define UHIMR_BCNDOK0 BIT16 | ||
| 2102 | #define UHIMR_HSISR_IND BIT15 | ||
| 2103 | #define UHIMR_BCNDMAINT_E BIT14 | ||
| 2104 | /* RSVD BIT13 */ | ||
| 2105 | #define UHIMR_CTW_END BIT12 | ||
| 2106 | /* RSVD BIT11 */ | ||
| 2107 | #define UHIMR_C2HCMD BIT10 | ||
| 2108 | #define UHIMR_CPWM2 BIT9 | ||
| 2109 | #define UHIMR_CPWM BIT8 | ||
| 2110 | #define UHIMR_HIGHDOK BIT7 /* High Queue DMA OK | ||
| 2111 | Interrupt */ | ||
| 2112 | #define UHIMR_MGNTDOK BIT6 /* Management Queue DMA OK | ||
| 2113 | Interrupt */ | ||
| 2114 | #define UHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ | ||
| 2115 | #define UHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ | ||
| 2116 | #define UHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ | ||
| 2117 | #define UHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ | ||
| 2118 | #define UHIMR_RDU BIT1 /* Receive Descriptor | ||
| 2119 | Unavailable */ | ||
| 2120 | #define UHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ | ||
| 2121 | |||
| 2122 | /* USB Host Interrupt Status Extension bit */ | ||
| 2123 | #define UHIMR_BCNDMAINT7 BIT23 | ||
| 2124 | #define UHIMR_BCNDMAINT6 BIT22 | ||
| 2125 | #define UHIMR_BCNDMAINT5 BIT21 | ||
| 2126 | #define UHIMR_BCNDMAINT4 BIT20 | ||
| 2127 | #define UHIMR_BCNDOK7 BIT19 | ||
| 2128 | #define UHIMR_BCNDOK6 BIT18 | ||
| 2129 | #define UHIMR_BCNDOK5 BIT17 | ||
| 2130 | #define UHIMR_BCNDOK4 BIT16 | ||
| 2131 | /* bit14-15: RSVD */ | ||
| 2132 | #define UHIMR_ATIMEND_E BIT13 | ||
| 2133 | #define UHIMR_ATIMEND BIT12 | ||
| 2134 | #define UHIMR_TXERR BIT11 | ||
| 2135 | #define UHIMR_RXERR BIT10 | ||
| 2136 | #define UHIMR_TXFOVW BIT9 | ||
| 2137 | #define UHIMR_RXFOVW BIT8 | ||
| 2138 | /* bit2-7: RSVD */ | ||
| 2139 | #define UHIMR_OCPINT BIT1 | ||
| 2140 | /* bit0: RSVD */ | ||
| 2141 | |||
| 2142 | #define REG_USB_HIMR 0xFE38 | ||
| 2143 | #define REG_USB_HIMRE 0xFE3C | ||
| 2144 | #define REG_USB_HISR 0xFE78 | ||
| 2145 | #define REG_USB_HISRE 0xFE7C | ||
| 2146 | |||
| 2147 | #define USB_INTR_CPWM_OFFSET 16 | ||
| 2148 | #define USB_INTR_CONTENT_HISR_OFFSET 48 | ||
| 2149 | #define USB_INTR_CONTENT_HISRE_OFFSET 52 | ||
| 2150 | #define USB_INTR_CONTENT_LENGTH 56 | ||
| 2151 | #define USB_C2H_CMDID_OFFSET 0 | ||
| 2152 | #define USB_C2H_SEQ_OFFSET 1 | ||
| 2153 | #define USB_C2H_EVENT_OFFSET 2 | ||
| 2154 | /* */ | ||
| 2155 | /* General definitions */ | ||
| 2156 | /* */ | ||
| 2157 | |||
| 2158 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_sreset.h b/drivers/staging/rtl8723au/include/rtl8723a_sreset.h new file mode 100644 index 000000000000..82af6a2704ed --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_sreset.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _RTL8723A_SRESET_H_ | ||
| 16 | #define _RTL8723A_SRESET_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | #include <rtw_sreset.h> | ||
| 21 | |||
| 22 | void rtl8723a_sreset_xmit_status_check(struct rtw_adapter *padapter); | ||
| 23 | void rtl8723a_sreset_linked_status_check(struct rtw_adapter *padapter); | ||
| 24 | |||
| 25 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtl8723a_xmit.h b/drivers/staging/rtl8723au/include/rtl8723a_xmit.h new file mode 100644 index 000000000000..3b6fdc3a9b7b --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtl8723a_xmit.h | |||
| @@ -0,0 +1,229 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTL8723A_XMIT_H__ | ||
| 16 | #define __RTL8723A_XMIT_H__ | ||
| 17 | |||
| 18 | /* */ | ||
| 19 | /* Queue Select Value in TxDesc */ | ||
| 20 | /* */ | ||
| 21 | #define QSLT_BK 0x2/* 0x01 */ | ||
| 22 | #define QSLT_BE 0x0 | ||
| 23 | #define QSLT_VI 0x5/* 0x4 */ | ||
| 24 | #define QSLT_VO 0x7/* 0x6 */ | ||
| 25 | #define QSLT_BEACON 0x10 | ||
| 26 | #define QSLT_HIGH 0x11 | ||
| 27 | #define QSLT_MGNT 0x12 | ||
| 28 | #define QSLT_CMD 0x13 | ||
| 29 | |||
| 30 | /* */ | ||
| 31 | /* defined for TX DESC Operation */ | ||
| 32 | /* */ | ||
| 33 | |||
| 34 | #define MAX_TID (15) | ||
| 35 | |||
| 36 | /* OFFSET 0 */ | ||
| 37 | #define OFFSET_SZ 0 | ||
| 38 | #define OFFSET_SHT 16 | ||
| 39 | #define BMC BIT(24) | ||
| 40 | #define LSG BIT(26) | ||
| 41 | #define FSG BIT(27) | ||
| 42 | #define OWN BIT(31) | ||
| 43 | |||
| 44 | |||
| 45 | /* OFFSET 4 */ | ||
| 46 | #define PKT_OFFSET_SZ 0 | ||
| 47 | #define BK BIT(6) | ||
| 48 | #define QSEL_SHT 8 | ||
| 49 | #define Rate_ID_SHT 16 | ||
| 50 | #define NAVUSEHDR BIT(20) | ||
| 51 | #define PKT_OFFSET_SHT 26 | ||
| 52 | #define HWPC BIT(31) | ||
| 53 | |||
| 54 | /* OFFSET 8 */ | ||
| 55 | #define AGG_EN BIT(29) | ||
| 56 | |||
| 57 | /* OFFSET 12 */ | ||
| 58 | #define SEQ_SHT 16 | ||
| 59 | |||
| 60 | /* OFFSET 16 */ | ||
| 61 | #define QoS BIT(6) | ||
| 62 | #define HW_SEQ_EN BIT(7) | ||
| 63 | #define USERATE BIT(8) | ||
| 64 | #define DISDATAFB BIT(10) | ||
| 65 | #define DATA_SHORT BIT(24) | ||
| 66 | #define DATA_BW BIT(25) | ||
| 67 | |||
| 68 | /* OFFSET 20 */ | ||
| 69 | #define SGI BIT(6) | ||
| 70 | |||
| 71 | struct txdesc_8723a { | ||
| 72 | u32 pktlen:16; | ||
| 73 | u32 offset:8; | ||
| 74 | u32 bmc:1; | ||
| 75 | u32 htc:1; | ||
| 76 | u32 ls:1; | ||
| 77 | u32 fs:1; | ||
| 78 | u32 linip:1; | ||
| 79 | u32 noacm:1; | ||
| 80 | u32 gf:1; | ||
| 81 | u32 own:1; | ||
| 82 | |||
| 83 | u32 macid:5; | ||
| 84 | u32 agg_en:1; | ||
| 85 | u32 bk:1; | ||
| 86 | u32 rd_en:1; | ||
| 87 | u32 qsel:5; | ||
| 88 | u32 rd_nav_ext:1; | ||
| 89 | u32 lsig_txop_en:1; | ||
| 90 | u32 pifs:1; | ||
| 91 | u32 rate_id:4; | ||
| 92 | u32 navusehdr:1; | ||
| 93 | u32 en_desc_id:1; | ||
| 94 | u32 sectype:2; | ||
| 95 | u32 rsvd0424:2; | ||
| 96 | u32 pkt_offset:5; /* unit: 8 bytes */ | ||
| 97 | u32 rsvd0431:1; | ||
| 98 | |||
| 99 | u32 rts_rc:6; | ||
| 100 | u32 data_rc:6; | ||
| 101 | u32 rsvd0812:2; | ||
| 102 | u32 bar_rty_th:2; | ||
| 103 | u32 rsvd0816:1; | ||
| 104 | u32 morefrag:1; | ||
| 105 | u32 raw:1; | ||
| 106 | u32 ccx:1; | ||
| 107 | u32 ampdu_density:3; | ||
| 108 | u32 bt_null:1; | ||
| 109 | u32 ant_sel_a:1; | ||
| 110 | u32 ant_sel_b:1; | ||
| 111 | u32 tx_ant_cck:2; | ||
| 112 | u32 tx_antl:2; | ||
| 113 | u32 tx_ant_ht:2; | ||
| 114 | |||
| 115 | u32 nextheadpage:8; | ||
| 116 | u32 tailpage:8; | ||
| 117 | u32 seq:12; | ||
| 118 | u32 cpu_handle:1; | ||
| 119 | u32 tag1:1; | ||
| 120 | u32 trigger_int:1; | ||
| 121 | u32 hwseq_en:1; | ||
| 122 | |||
| 123 | u32 rtsrate:5; | ||
| 124 | u32 ap_dcfe:1; | ||
| 125 | u32 hwseq_sel:2; | ||
| 126 | u32 userate:1; | ||
| 127 | u32 disrtsfb:1; | ||
| 128 | u32 disdatafb:1; | ||
| 129 | u32 cts2self:1; | ||
| 130 | u32 rtsen:1; | ||
| 131 | u32 hw_rts_en:1; | ||
| 132 | u32 port_id:1; | ||
| 133 | u32 rsvd1615:3; | ||
| 134 | u32 wait_dcts:1; | ||
| 135 | u32 cts2ap_en:1; | ||
| 136 | u32 data_sc:2; | ||
| 137 | u32 data_stbc:2; | ||
| 138 | u32 data_short:1; | ||
| 139 | u32 data_bw:1; | ||
| 140 | u32 rts_short:1; | ||
| 141 | u32 rts_bw:1; | ||
| 142 | u32 rts_sc:2; | ||
| 143 | u32 vcs_stbc:2; | ||
| 144 | |||
| 145 | u32 datarate:6; | ||
| 146 | u32 sgi:1; | ||
| 147 | u32 try_rate:1; | ||
| 148 | u32 data_ratefb_lmt:5; | ||
| 149 | u32 rts_ratefb_lmt:4; | ||
| 150 | u32 rty_lmt_en:1; | ||
| 151 | u32 data_rt_lmt:6; | ||
| 152 | u32 usb_txagg_num:8; | ||
| 153 | |||
| 154 | u32 txagg_a:5; | ||
| 155 | u32 txagg_b:5; | ||
| 156 | u32 use_max_len:1; | ||
| 157 | u32 max_agg_num:5; | ||
| 158 | u32 mcsg1_max_len:4; | ||
| 159 | u32 mcsg2_max_len:4; | ||
| 160 | u32 mcsg3_max_len:4; | ||
| 161 | u32 mcs7_sgi_max_len:4; | ||
| 162 | |||
| 163 | u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */ | ||
| 164 | u32 mcsg4_max_len:4; | ||
| 165 | u32 mcsg5_max_len:4; | ||
| 166 | u32 mcsg6_max_len:4; | ||
| 167 | u32 mcs15_sgi_max_len:4; | ||
| 168 | }; | ||
| 169 | |||
| 170 | #define txdesc_set_ccx_sw_8723a(txdesc, value) \ | ||
| 171 | do { \ | ||
| 172 | ((struct txdesc_8723a *)(txdesc))->mcsg4_max_len = (((value)>>8) & 0x0f); \ | ||
| 173 | ((struct txdesc_8723a *)(txdesc))->mcs15_sgi_max_len= (((value)>>4) & 0x0f); \ | ||
| 174 | ((struct txdesc_8723a *)(txdesc))->mcsg6_max_len = ((value) & 0x0f); \ | ||
| 175 | } while (0) | ||
| 176 | |||
| 177 | struct txrpt_ccx_8723a { | ||
| 178 | /* offset 0 */ | ||
| 179 | u8 tag1:1; | ||
| 180 | u8 rsvd:4; | ||
| 181 | u8 int_bt:1; | ||
| 182 | u8 int_tri:1; | ||
| 183 | u8 int_ccx:1; | ||
| 184 | |||
| 185 | /* offset 1 */ | ||
| 186 | u8 mac_id:5; | ||
| 187 | u8 pkt_drop:1; | ||
| 188 | u8 pkt_ok:1; | ||
| 189 | u8 bmc:1; | ||
| 190 | |||
| 191 | /* offset 2 */ | ||
| 192 | u8 retry_cnt:6; | ||
| 193 | u8 lifetime_over:1; | ||
| 194 | u8 retry_over:1; | ||
| 195 | |||
| 196 | /* offset 3 */ | ||
| 197 | u8 ccx_qtime0; | ||
| 198 | u8 ccx_qtime1; | ||
| 199 | |||
| 200 | /* offset 5 */ | ||
| 201 | u8 final_data_rate; | ||
| 202 | |||
| 203 | /* offset 6 */ | ||
| 204 | u8 sw1:4; | ||
| 205 | u8 qsel:4; | ||
| 206 | |||
| 207 | /* offset 7 */ | ||
| 208 | u8 sw0; | ||
| 209 | }; | ||
| 210 | |||
| 211 | #define txrpt_ccx_sw_8723a(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8)) | ||
| 212 | #define txrpt_ccx_qtime_8723a(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) | ||
| 213 | |||
| 214 | void dump_txrpt_ccx_8723a(void *buf); | ||
| 215 | void handle_txrpt_ccx_8723a(struct rtw_adapter *adapter, void *buf); | ||
| 216 | void rtl8723a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); | ||
| 217 | void rtl8723a_fill_fake_txdesc(struct rtw_adapter *padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull); | ||
| 218 | |||
| 219 | s32 rtl8723au_hal_xmitframe_enqueue(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe); | ||
| 220 | s32 rtl8723au_xmit_buf_handler(struct rtw_adapter *padapter); | ||
| 221 | #define hal_xmit_handler rtl8723au_xmit_buf_handler | ||
| 222 | s32 rtl8723au_init_xmit_priv(struct rtw_adapter * padapter); | ||
| 223 | void rtl8723au_free_xmit_priv(struct rtw_adapter * padapter); | ||
| 224 | s32 rtl8723au_hal_xmit(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe); | ||
| 225 | s32 rtl8723au_mgnt_xmit(struct rtw_adapter *padapter, struct xmit_frame *pmgntframe); | ||
| 226 | s32 rtl8723au_xmitframe_complete(struct rtw_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); | ||
| 227 | |||
| 228 | |||
| 229 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_ap.h b/drivers/staging/rtl8723au/include/rtw_ap.h new file mode 100644 index 000000000000..76f82d68f633 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_ap.h | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_AP_H_ | ||
| 16 | #define __RTW_AP_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | |||
| 22 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 23 | |||
| 24 | /* external function */ | ||
| 25 | void rtw_indicate_sta_assoc_event23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 26 | void rtw_indicate_sta_disassoc_event23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 27 | |||
| 28 | void init_mlme_ap_info23a(struct rtw_adapter *padapter); | ||
| 29 | void free_mlme_ap_info23a(struct rtw_adapter *padapter); | ||
| 30 | /* void update_BCNTIM(struct rtw_adapter *padapter); */ | ||
| 31 | void rtw_add_bcn_ie(struct rtw_adapter *padapter, struct wlan_bssid_ex *pnetwork, u8 index, u8 *data, u8 len); | ||
| 32 | void rtw_remove_bcn_ie(struct rtw_adapter *padapter, struct wlan_bssid_ex *pnetwork, u8 index); | ||
| 33 | void update_beacon23a(struct rtw_adapter *padapter, u8 ie_id, u8 *oui, u8 tx); | ||
| 34 | void add_RATid23a(struct rtw_adapter *padapter, struct sta_info *psta, u8 rssi_level); | ||
| 35 | void expire_timeout_chk23a(struct rtw_adapter *padapter); | ||
| 36 | void update_sta_info23a_apmode23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 37 | int rtw_check_beacon_data23a(struct rtw_adapter *padapter, u8 *pbuf, int len); | ||
| 38 | void rtw_ap_restore_network(struct rtw_adapter *padapter); | ||
| 39 | void rtw_set_macaddr_acl23a(struct rtw_adapter *padapter, int mode); | ||
| 40 | int rtw_acl_add_sta23a(struct rtw_adapter *padapter, u8 *addr); | ||
| 41 | int rtw_acl_remove_sta23a(struct rtw_adapter *padapter, u8 *addr); | ||
| 42 | |||
| 43 | void associated_clients_update23a(struct rtw_adapter *padapter, u8 updated); | ||
| 44 | void bss_cap_update_on_sta_join23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 45 | u8 bss_cap_update_on_sta_leave23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 46 | void sta_info_update23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 47 | void ap_sta_info_defer_update23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 48 | u8 ap_free_sta23a(struct rtw_adapter *padapter, struct sta_info *psta, bool active, u16 reason); | ||
| 49 | int rtw_sta_flush23a(struct rtw_adapter *padapter); | ||
| 50 | int rtw_ap_inform_ch_switch23a(struct rtw_adapter *padapter, u8 new_ch, u8 ch_offset); | ||
| 51 | void start_ap_mode23a(struct rtw_adapter *padapter); | ||
| 52 | void stop_ap_mode23a(struct rtw_adapter *padapter); | ||
| 53 | #endif /* end of CONFIG_8723AU_AP_MODE */ | ||
| 54 | |||
| 55 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_cmd.h b/drivers/staging/rtl8723au/include/rtw_cmd.h new file mode 100644 index 000000000000..f9caa3e35f57 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_cmd.h | |||
| @@ -0,0 +1,835 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_CMD_H_ | ||
| 16 | #define __RTW_CMD_H_ | ||
| 17 | |||
| 18 | #include <wlan_bssdef.h> | ||
| 19 | #include <rtw_rf.h> | ||
| 20 | #include <rtw_led.h> | ||
| 21 | |||
| 22 | #define C2H_MEM_SZ (16*1024) | ||
| 23 | |||
| 24 | #include <osdep_service.h> | ||
| 25 | #include <ieee80211.h> /* <ieee80211/ieee80211.h> */ | ||
| 26 | |||
| 27 | |||
| 28 | #define FREE_CMDOBJ_SZ 128 | ||
| 29 | |||
| 30 | #define MAX_CMDSZ 1024 | ||
| 31 | #define MAX_RSPSZ 512 | ||
| 32 | #define MAX_EVTSZ 1024 | ||
| 33 | |||
| 34 | #define CMDBUFF_ALIGN_SZ 512 | ||
| 35 | |||
| 36 | struct cmd_obj { | ||
| 37 | struct rtw_adapter *padapter; | ||
| 38 | u16 cmdcode; | ||
| 39 | u8 res; | ||
| 40 | u8 *parmbuf; | ||
| 41 | u32 cmdsz; | ||
| 42 | u8 *rsp; | ||
| 43 | u32 rspsz; | ||
| 44 | /* struct semaphore cmd_sem; */ | ||
| 45 | struct list_head list; | ||
| 46 | }; | ||
| 47 | |||
| 48 | struct cmd_priv { | ||
| 49 | struct semaphore cmd_queue_sema; | ||
| 50 | /* struct semaphore cmd_done_sema; */ | ||
| 51 | struct semaphore terminate_cmdthread_sema; | ||
| 52 | struct rtw_queue cmd_queue; | ||
| 53 | u8 cmd_seq; | ||
| 54 | u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */ | ||
| 55 | u8 *cmd_allocated_buf; | ||
| 56 | u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */ | ||
| 57 | u8 *rsp_allocated_buf; | ||
| 58 | u32 cmd_issued_cnt; | ||
| 59 | u32 cmd_done_cnt; | ||
| 60 | u32 rsp_cnt; | ||
| 61 | u8 cmdthd_running; | ||
| 62 | struct rtw_adapter *padapter; | ||
| 63 | }; | ||
| 64 | |||
| 65 | #define C2H_QUEUE_MAX_LEN 10 | ||
| 66 | |||
| 67 | struct evt_priv { | ||
| 68 | struct work_struct c2h_wk; | ||
| 69 | bool c2h_wk_alive; | ||
| 70 | struct rtw_cbuf *c2h_queue; | ||
| 71 | |||
| 72 | atomic_t event_seq; | ||
| 73 | u8 *evt_buf; /* shall be non-paged, and 4 bytes aligned */ | ||
| 74 | u8 *evt_allocated_buf; | ||
| 75 | u32 evt_done_cnt; | ||
| 76 | }; | ||
| 77 | |||
| 78 | #define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \ | ||
| 79 | do {\ | ||
| 80 | INIT_LIST_HEAD(&pcmd->list);\ | ||
| 81 | pcmd->cmdcode = code;\ | ||
| 82 | pcmd->parmbuf = (u8 *)(pparm);\ | ||
| 83 | pcmd->cmdsz = sizeof (*pparm);\ | ||
| 84 | pcmd->rsp = NULL;\ | ||
| 85 | pcmd->rspsz = 0;\ | ||
| 86 | } while(0) | ||
| 87 | |||
| 88 | struct c2h_evt_hdr { | ||
| 89 | u8 id:4; | ||
| 90 | u8 plen:4; | ||
| 91 | u8 seq; | ||
| 92 | u8 payload[0]; | ||
| 93 | }; | ||
| 94 | |||
| 95 | #define c2h_evt_exist(c2h_evt) ((c2h_evt)->id || (c2h_evt)->plen) | ||
| 96 | |||
| 97 | u32 rtw_enqueue_cmd23a(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); | ||
| 98 | void rtw_free_cmd_obj23a(struct cmd_obj *pcmd); | ||
| 99 | |||
| 100 | int rtw_cmd_thread23a(void *context); | ||
| 101 | |||
| 102 | int rtw_init_cmd_priv23a(struct cmd_priv *pcmdpriv); | ||
| 103 | void rtw_free_cmd_priv23a (struct cmd_priv *pcmdpriv); | ||
| 104 | |||
| 105 | u32 rtw_init_evt_priv23a (struct evt_priv *pevtpriv); | ||
| 106 | void rtw_free_evt_priv23a (struct evt_priv *pevtpriv); | ||
| 107 | void rtw_cmd_clr_isr23a(struct cmd_priv *pcmdpriv); | ||
| 108 | void rtw_evt_notify_isr(struct evt_priv *pevtpriv); | ||
| 109 | #ifdef CONFIG_8723AU_P2P | ||
| 110 | u8 p2p_protocol_wk_cmd23a(struct rtw_adapter*padapter, int intCmdType ); | ||
| 111 | #endif /* CONFIG_8723AU_P2P */ | ||
| 112 | |||
| 113 | enum rtw_drvextra_cmd_id | ||
| 114 | { | ||
| 115 | NONE_WK_CID, | ||
| 116 | DYNAMIC_CHK_WK_CID, | ||
| 117 | DM_CTRL_WK_CID, | ||
| 118 | PBC_POLLING_WK_CID, | ||
| 119 | POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */ | ||
| 120 | LPS_CTRL_WK_CID, | ||
| 121 | ANT_SELECT_WK_CID, | ||
| 122 | P2P_PS_WK_CID, | ||
| 123 | P2P_PROTO_WK_CID, | ||
| 124 | CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */ | ||
| 125 | C2H_WK_CID, | ||
| 126 | RTP_TIMER_CFG_WK_CID, | ||
| 127 | MAX_WK_CID | ||
| 128 | }; | ||
| 129 | |||
| 130 | enum LPS_CTRL_TYPE | ||
| 131 | { | ||
| 132 | LPS_CTRL_SCAN=0, | ||
| 133 | LPS_CTRL_JOINBSS=1, | ||
| 134 | LPS_CTRL_CONNECT=2, | ||
| 135 | LPS_CTRL_DISCONNECT=3, | ||
| 136 | LPS_CTRL_SPECIAL_PACKET=4, | ||
| 137 | LPS_CTRL_LEAVE=5, | ||
| 138 | }; | ||
| 139 | |||
| 140 | enum RFINTFS { | ||
| 141 | SWSI, | ||
| 142 | HWSI, | ||
| 143 | HWPI, | ||
| 144 | }; | ||
| 145 | |||
| 146 | /* | ||
| 147 | Caller Mode: Infra, Ad-HoC(C) | ||
| 148 | |||
| 149 | Notes: To enter USB suspend mode | ||
| 150 | |||
| 151 | Command Mode | ||
| 152 | |||
| 153 | */ | ||
| 154 | struct usb_suspend_parm { | ||
| 155 | u32 action;/* 1: sleep, 0:resume */ | ||
| 156 | }; | ||
| 157 | |||
| 158 | /* | ||
| 159 | Caller Mode: Infra, Ad-HoC | ||
| 160 | |||
| 161 | Notes: To join a known BSS. | ||
| 162 | |||
| 163 | Command-Event Mode | ||
| 164 | |||
| 165 | */ | ||
| 166 | |||
| 167 | /* | ||
| 168 | Caller Mode: Infra, Ad-HoC(C) | ||
| 169 | |||
| 170 | Notes: To disconnect the current associated BSS | ||
| 171 | |||
| 172 | Command Mode | ||
| 173 | |||
| 174 | */ | ||
| 175 | struct disconnect_parm { | ||
| 176 | u32 deauth_timeout_ms; | ||
| 177 | }; | ||
| 178 | |||
| 179 | struct setopmode_parm { | ||
| 180 | u8 mode; | ||
| 181 | u8 rsvd[3]; | ||
| 182 | }; | ||
| 183 | |||
| 184 | /* | ||
| 185 | Caller Mode: AP, Ad-HoC, Infra | ||
| 186 | |||
| 187 | Notes: To ask RTL8711 performing site-survey | ||
| 188 | |||
| 189 | Command-Event Mode | ||
| 190 | |||
| 191 | */ | ||
| 192 | |||
| 193 | #define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */ | ||
| 194 | #define RTW_CHANNEL_SCAN_AMOUNT (14+37) | ||
| 195 | struct sitesurvey_parm { | ||
| 196 | int scan_mode; /* active: 1, passive: 0 */ | ||
| 197 | u8 ssid_num; | ||
| 198 | u8 ch_num; | ||
| 199 | struct cfg80211_ssid ssid[RTW_SSID_SCAN_AMOUNT]; | ||
| 200 | struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; | ||
| 201 | }; | ||
| 202 | |||
| 203 | /* | ||
| 204 | Caller Mode: Any | ||
| 205 | |||
| 206 | Notes: To set the auth type of RTL8711. open/shared/802.1x | ||
| 207 | |||
| 208 | Command Mode | ||
| 209 | |||
| 210 | */ | ||
| 211 | struct setauth_parm { | ||
| 212 | u8 mode; /* 0: legacy open, 1: legacy shared 2: 802.1x */ | ||
| 213 | u8 _1x; /* 0: PSK, 1: TLS */ | ||
| 214 | u8 rsvd[2]; | ||
| 215 | }; | ||
| 216 | |||
| 217 | /* | ||
| 218 | Caller Mode: Infra | ||
| 219 | |||
| 220 | a. algorithm: wep40, wep104, tkip & aes | ||
| 221 | b. keytype: grp key/unicast key | ||
| 222 | c. key contents | ||
| 223 | |||
| 224 | when shared key ==> keyid is the camid | ||
| 225 | when 802.1x ==> keyid [0:1] ==> grp key | ||
| 226 | when 802.1x ==> keyid > 2 ==> unicast key | ||
| 227 | |||
| 228 | */ | ||
| 229 | struct setkey_parm { | ||
| 230 | u8 algorithm; /* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */ | ||
| 231 | u8 keyid; | ||
| 232 | u8 grpkey; /* 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x */ | ||
| 233 | u8 set_tx; /* 1: main tx key for wep. 0: other key. */ | ||
| 234 | u8 key[16]; /* this could be 40 or 104 */ | ||
| 235 | }; | ||
| 236 | |||
| 237 | /* | ||
| 238 | When in AP or Ad-Hoc mode, this is used to | ||
| 239 | allocate an sw/hw entry for a newly associated sta. | ||
| 240 | |||
| 241 | Command | ||
| 242 | |||
| 243 | when shared key ==> algorithm/keyid | ||
| 244 | |||
| 245 | */ | ||
| 246 | struct set_stakey_parm { | ||
| 247 | u8 addr[ETH_ALEN]; | ||
| 248 | u8 algorithm; | ||
| 249 | u8 id;/* currently for erasing cam entry if algorithm == _NO_PRIVACY_ */ | ||
| 250 | u8 key[16]; | ||
| 251 | }; | ||
| 252 | |||
| 253 | struct set_stakey_rsp { | ||
| 254 | u8 addr[ETH_ALEN]; | ||
| 255 | u8 keyid; | ||
| 256 | u8 rsvd; | ||
| 257 | }; | ||
| 258 | |||
| 259 | /* | ||
| 260 | Caller Ad-Hoc/AP | ||
| 261 | |||
| 262 | Command -Rsp(AID == CAMID) mode | ||
| 263 | |||
| 264 | This is to force fw to add an sta_data entry per driver's request. | ||
| 265 | |||
| 266 | FW will write an cam entry associated with it. | ||
| 267 | |||
| 268 | */ | ||
| 269 | struct set_assocsta_parm { | ||
| 270 | u8 addr[ETH_ALEN]; | ||
| 271 | }; | ||
| 272 | |||
| 273 | struct set_assocsta_rsp { | ||
| 274 | u8 cam_id; | ||
| 275 | u8 rsvd[3]; | ||
| 276 | }; | ||
| 277 | |||
| 278 | /* | ||
| 279 | Caller Ad-Hoc/AP | ||
| 280 | |||
| 281 | Command mode | ||
| 282 | |||
| 283 | This is to force fw to del an sta_data entry per driver's request | ||
| 284 | |||
| 285 | FW will invalidate the cam entry associated with it. | ||
| 286 | |||
| 287 | */ | ||
| 288 | struct del_assocsta_parm { | ||
| 289 | u8 addr[ETH_ALEN]; | ||
| 290 | }; | ||
| 291 | |||
| 292 | /* | ||
| 293 | Caller Mode: AP/Ad-HoC(M) | ||
| 294 | |||
| 295 | Notes: To notify fw that given staid has changed its power state | ||
| 296 | |||
| 297 | Command Mode | ||
| 298 | |||
| 299 | */ | ||
| 300 | struct setstapwrstate_parm { | ||
| 301 | u8 staid; | ||
| 302 | u8 status; | ||
| 303 | u8 hwaddr[6]; | ||
| 304 | }; | ||
| 305 | |||
| 306 | /* | ||
| 307 | Caller Mode: Any | ||
| 308 | |||
| 309 | Notes: To setup the basic rate of RTL8711 | ||
| 310 | |||
| 311 | Command Mode | ||
| 312 | |||
| 313 | */ | ||
| 314 | struct setbasicrate_parm { | ||
| 315 | u8 basicrates[NumRates]; | ||
| 316 | }; | ||
| 317 | |||
| 318 | /* | ||
| 319 | Caller Mode: Any | ||
| 320 | |||
| 321 | Notes: To read the current basic rate | ||
| 322 | |||
| 323 | Command-Rsp Mode | ||
| 324 | |||
| 325 | */ | ||
| 326 | struct getbasicrate_parm { | ||
| 327 | u32 rsvd; | ||
| 328 | }; | ||
| 329 | |||
| 330 | struct getbasicrate_rsp { | ||
| 331 | u8 basicrates[NumRates]; | ||
| 332 | }; | ||
| 333 | |||
| 334 | /* | ||
| 335 | Caller Mode: Any | ||
| 336 | |||
| 337 | Notes: To setup the data rate of RTL8711 | ||
| 338 | |||
| 339 | Command Mode | ||
| 340 | |||
| 341 | */ | ||
| 342 | struct setdatarate_parm { | ||
| 343 | u8 mac_id; | ||
| 344 | u8 datarates[NumRates]; | ||
| 345 | }; | ||
| 346 | |||
| 347 | /* | ||
| 348 | Caller Mode: Any | ||
| 349 | |||
| 350 | Notes: To read the current data rate | ||
| 351 | |||
| 352 | Command-Rsp Mode | ||
| 353 | |||
| 354 | */ | ||
| 355 | struct getdatarate_parm { | ||
| 356 | u32 rsvd; | ||
| 357 | }; | ||
| 358 | |||
| 359 | struct getdatarate_rsp { | ||
| 360 | u8 datarates[NumRates]; | ||
| 361 | }; | ||
| 362 | |||
| 363 | |||
| 364 | /* | ||
| 365 | Caller Mode: Any | ||
| 366 | AP: AP can use the info for the contents of beacon frame | ||
| 367 | Infra: STA can use the info when sitesurveying | ||
| 368 | Ad-HoC(M): Like AP | ||
| 369 | Ad-HoC(C): Like STA | ||
| 370 | |||
| 371 | |||
| 372 | Notes: To set the phy capability of the NIC | ||
| 373 | |||
| 374 | Command Mode | ||
| 375 | |||
| 376 | */ | ||
| 377 | |||
| 378 | struct setphyinfo_parm { | ||
| 379 | struct regulatory_class class_sets[NUM_REGULATORYS]; | ||
| 380 | u8 status; | ||
| 381 | }; | ||
| 382 | |||
| 383 | struct getphyinfo_parm { | ||
| 384 | u32 rsvd; | ||
| 385 | }; | ||
| 386 | |||
| 387 | struct getphyinfo_rsp { | ||
| 388 | struct regulatory_class class_sets[NUM_REGULATORYS]; | ||
| 389 | u8 status; | ||
| 390 | }; | ||
| 391 | |||
| 392 | /* | ||
| 393 | Caller Mode: Any | ||
| 394 | |||
| 395 | Notes: To set the channel/modem/band | ||
| 396 | This command will be used when channel/modem/band is changed. | ||
| 397 | |||
| 398 | Command Mode | ||
| 399 | |||
| 400 | */ | ||
| 401 | struct setphy_parm { | ||
| 402 | u8 rfchannel; | ||
| 403 | u8 modem; | ||
| 404 | }; | ||
| 405 | |||
| 406 | /* | ||
| 407 | Caller Mode: Any | ||
| 408 | |||
| 409 | Notes: To get the current setting of channel/modem/band | ||
| 410 | |||
| 411 | Command-Rsp Mode | ||
| 412 | |||
| 413 | */ | ||
| 414 | struct getphy_parm { | ||
| 415 | u32 rsvd; | ||
| 416 | }; | ||
| 417 | |||
| 418 | struct getphy_rsp { | ||
| 419 | u8 rfchannel; | ||
| 420 | u8 modem; | ||
| 421 | }; | ||
| 422 | |||
| 423 | struct readBB_parm { | ||
| 424 | u8 offset; | ||
| 425 | }; | ||
| 426 | |||
| 427 | struct readBB_rsp { | ||
| 428 | u8 value; | ||
| 429 | }; | ||
| 430 | |||
| 431 | struct readTSSI_parm { | ||
| 432 | u8 offset; | ||
| 433 | }; | ||
| 434 | |||
| 435 | struct readTSSI_rsp { | ||
| 436 | u8 value; | ||
| 437 | }; | ||
| 438 | |||
| 439 | struct writeBB_parm { | ||
| 440 | u8 offset; | ||
| 441 | u8 value; | ||
| 442 | }; | ||
| 443 | |||
| 444 | struct readRF_parm { | ||
| 445 | u8 offset; | ||
| 446 | }; | ||
| 447 | |||
| 448 | struct readRF_rsp { | ||
| 449 | u32 value; | ||
| 450 | }; | ||
| 451 | |||
| 452 | struct writeRF_parm { | ||
| 453 | u32 offset; | ||
| 454 | u32 value; | ||
| 455 | }; | ||
| 456 | |||
| 457 | struct getrfintfs_parm { | ||
| 458 | u8 rfintfs; | ||
| 459 | }; | ||
| 460 | |||
| 461 | struct Tx_Beacon_param | ||
| 462 | { | ||
| 463 | struct wlan_bssid_ex network; | ||
| 464 | }; | ||
| 465 | |||
| 466 | /* CMD param Formart for driver extra cmd handler */ | ||
| 467 | struct drvextra_cmd_parm { | ||
| 468 | int ec_id; /* extra cmd id */ | ||
| 469 | int type_size; /* Can use this field as the type id or command size */ | ||
| 470 | unsigned char *pbuf; | ||
| 471 | }; | ||
| 472 | |||
| 473 | /*------------------- Below are used for RF/BB tunning ---------------------*/ | ||
| 474 | |||
| 475 | struct setantenna_parm { | ||
| 476 | u8 tx_antset; | ||
| 477 | u8 rx_antset; | ||
| 478 | u8 tx_antenna; | ||
| 479 | u8 rx_antenna; | ||
| 480 | }; | ||
| 481 | |||
| 482 | struct enrateadaptive_parm { | ||
| 483 | u32 en; | ||
| 484 | }; | ||
| 485 | |||
| 486 | struct settxagctbl_parm { | ||
| 487 | u32 txagc[MAX_RATES_LENGTH]; | ||
| 488 | }; | ||
| 489 | |||
| 490 | struct gettxagctbl_parm { | ||
| 491 | u32 rsvd; | ||
| 492 | }; | ||
| 493 | |||
| 494 | struct gettxagctbl_rsp { | ||
| 495 | u32 txagc[MAX_RATES_LENGTH]; | ||
| 496 | }; | ||
| 497 | |||
| 498 | struct setagcctrl_parm { | ||
| 499 | u32 agcctrl; /* 0: pure hw, 1: fw */ | ||
| 500 | }; | ||
| 501 | |||
| 502 | struct setssup_parm { | ||
| 503 | u32 ss_ForceUp[MAX_RATES_LENGTH]; | ||
| 504 | }; | ||
| 505 | |||
| 506 | struct getssup_parm { | ||
| 507 | u32 rsvd; | ||
| 508 | }; | ||
| 509 | |||
| 510 | struct getssup_rsp { | ||
| 511 | u8 ss_ForceUp[MAX_RATES_LENGTH]; | ||
| 512 | }; | ||
| 513 | |||
| 514 | struct setssdlevel_parm { | ||
| 515 | u8 ss_DLevel[MAX_RATES_LENGTH]; | ||
| 516 | }; | ||
| 517 | |||
| 518 | struct getssdlevel_parm { | ||
| 519 | u32 rsvd; | ||
| 520 | }; | ||
| 521 | |||
| 522 | struct getssdlevel_rsp { | ||
| 523 | u8 ss_DLevel[MAX_RATES_LENGTH]; | ||
| 524 | }; | ||
| 525 | |||
| 526 | struct setssulevel_parm { | ||
| 527 | u8 ss_ULevel[MAX_RATES_LENGTH]; | ||
| 528 | }; | ||
| 529 | |||
| 530 | struct getssulevel_parm { | ||
| 531 | u32 rsvd; | ||
| 532 | }; | ||
| 533 | |||
| 534 | struct getssulevel_rsp { | ||
| 535 | u8 ss_ULevel[MAX_RATES_LENGTH]; | ||
| 536 | }; | ||
| 537 | |||
| 538 | struct setcountjudge_parm { | ||
| 539 | u8 count_judge[MAX_RATES_LENGTH]; | ||
| 540 | }; | ||
| 541 | |||
| 542 | struct getcountjudge_parm { | ||
| 543 | u32 rsvd; | ||
| 544 | }; | ||
| 545 | |||
| 546 | struct getcountjudge_rsp { | ||
| 547 | u8 count_judge[MAX_RATES_LENGTH]; | ||
| 548 | }; | ||
| 549 | |||
| 550 | struct setratable_parm { | ||
| 551 | u8 ss_ForceUp[NumRates]; | ||
| 552 | u8 ss_ULevel[NumRates]; | ||
| 553 | u8 ss_DLevel[NumRates]; | ||
| 554 | u8 count_judge[NumRates]; | ||
| 555 | }; | ||
| 556 | |||
| 557 | struct getratable_parm { | ||
| 558 | uint rsvd; | ||
| 559 | }; | ||
| 560 | |||
| 561 | struct getratable_rsp { | ||
| 562 | u8 ss_ForceUp[NumRates]; | ||
| 563 | u8 ss_ULevel[NumRates]; | ||
| 564 | u8 ss_DLevel[NumRates]; | ||
| 565 | u8 count_judge[NumRates]; | ||
| 566 | }; | ||
| 567 | |||
| 568 | /* to get TX,RX retry count */ | ||
| 569 | struct gettxretrycnt_parm{ | ||
| 570 | unsigned int rsvd; | ||
| 571 | }; | ||
| 572 | struct gettxretrycnt_rsp{ | ||
| 573 | unsigned long tx_retrycnt; | ||
| 574 | }; | ||
| 575 | |||
| 576 | struct getrxretrycnt_parm{ | ||
| 577 | unsigned int rsvd; | ||
| 578 | }; | ||
| 579 | struct getrxretrycnt_rsp{ | ||
| 580 | unsigned long rx_retrycnt; | ||
| 581 | }; | ||
| 582 | |||
| 583 | /* to get BCNOK,BCNERR count */ | ||
| 584 | struct getbcnokcnt_parm{ | ||
| 585 | unsigned int rsvd; | ||
| 586 | }; | ||
| 587 | struct getbcnokcnt_rsp{ | ||
| 588 | unsigned long bcnokcnt; | ||
| 589 | }; | ||
| 590 | |||
| 591 | struct getbcnerrcnt_parm{ | ||
| 592 | unsigned int rsvd; | ||
| 593 | }; | ||
| 594 | struct getbcnerrcnt_rsp{ | ||
| 595 | unsigned long bcnerrcnt; | ||
| 596 | }; | ||
| 597 | |||
| 598 | /* to get current TX power level */ | ||
| 599 | struct getcurtxpwrlevel_parm{ | ||
| 600 | unsigned int rsvd; | ||
| 601 | }; | ||
| 602 | |||
| 603 | struct getcurtxpwrlevel_rsp{ | ||
| 604 | unsigned short tx_power; | ||
| 605 | }; | ||
| 606 | |||
| 607 | struct setprobereqextraie_parm { | ||
| 608 | unsigned char e_id; | ||
| 609 | unsigned char ie_len; | ||
| 610 | unsigned char ie[0]; | ||
| 611 | }; | ||
| 612 | |||
| 613 | struct setassocreqextraie_parm { | ||
| 614 | unsigned char e_id; | ||
| 615 | unsigned char ie_len; | ||
| 616 | unsigned char ie[0]; | ||
| 617 | }; | ||
| 618 | |||
| 619 | struct setproberspextraie_parm { | ||
| 620 | unsigned char e_id; | ||
| 621 | unsigned char ie_len; | ||
| 622 | unsigned char ie[0]; | ||
| 623 | }; | ||
| 624 | |||
| 625 | struct setassocrspextraie_parm { | ||
| 626 | unsigned char e_id; | ||
| 627 | unsigned char ie_len; | ||
| 628 | unsigned char ie[0]; | ||
| 629 | }; | ||
| 630 | |||
| 631 | struct addBaReq_parm { | ||
| 632 | unsigned int tid; | ||
| 633 | u8 addr[ETH_ALEN]; | ||
| 634 | }; | ||
| 635 | |||
| 636 | /*H2C Handler index: 46 */ | ||
| 637 | struct set_ch_parm { | ||
| 638 | u8 ch; | ||
| 639 | u8 bw; | ||
| 640 | u8 ch_offset; | ||
| 641 | }; | ||
| 642 | |||
| 643 | /*H2C Handler index: 59 */ | ||
| 644 | struct SetChannelPlan_param { | ||
| 645 | u8 channel_plan; | ||
| 646 | }; | ||
| 647 | |||
| 648 | /*H2C Handler index: 60 */ | ||
| 649 | struct LedBlink_param { | ||
| 650 | struct led_8723a *pLed; | ||
| 651 | }; | ||
| 652 | |||
| 653 | /*H2C Handler index: 61 */ | ||
| 654 | struct SetChannelSwitch_param { | ||
| 655 | u8 new_ch_no; | ||
| 656 | }; | ||
| 657 | |||
| 658 | /*H2C Handler index: 62 */ | ||
| 659 | struct TDLSoption_param { | ||
| 660 | u8 addr[ETH_ALEN]; | ||
| 661 | u8 option; | ||
| 662 | }; | ||
| 663 | |||
| 664 | #define GEN_CMD_CODE(cmd) cmd ## _CMD_ | ||
| 665 | |||
| 666 | |||
| 667 | /* | ||
| 668 | |||
| 669 | Result: | ||
| 670 | 0x00: success | ||
| 671 | 0x01: sucess, and check Response. | ||
| 672 | 0x02: cmd ignored due to duplicated sequcne number | ||
| 673 | 0x03: cmd dropped due to invalid cmd code | ||
| 674 | 0x04: reserved. | ||
| 675 | |||
| 676 | */ | ||
| 677 | |||
| 678 | #define H2C_RSP_OFFSET 512 | ||
| 679 | |||
| 680 | #define H2C_SUCCESS 0x00 | ||
| 681 | #define H2C_SUCCESS_RSP 0x01 | ||
| 682 | #define H2C_DUPLICATED 0x02 | ||
| 683 | #define H2C_DROPPED 0x03 | ||
| 684 | #define H2C_PARAMETERS_ERROR 0x04 | ||
| 685 | #define H2C_REJECTED 0x05 | ||
| 686 | #define H2C_CMD_OVERFLOW 0x06 | ||
| 687 | #define H2C_RESERVED 0x07 | ||
| 688 | |||
| 689 | u8 rtw_setassocsta_cmd(struct rtw_adapter *padapter, u8 *mac_addr); | ||
| 690 | u8 rtw_setstandby_cmd(struct rtw_adapter *padapter, uint action); | ||
| 691 | u8 rtw_sitesurvey_cmd23a(struct rtw_adapter *padapter, struct cfg80211_ssid *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num); | ||
| 692 | u8 rtw_createbss_cmd23a(struct rtw_adapter *padapter); | ||
| 693 | u8 rtw_createbss_cmd23a_ex(struct rtw_adapter *padapter, unsigned char *pbss, unsigned int sz); | ||
| 694 | u8 rtw_setphy_cmd(struct rtw_adapter *padapter, u8 modem, u8 ch); | ||
| 695 | u8 rtw_setstakey_cmd23a(struct rtw_adapter *padapter, u8 *psta, u8 unicast_key); | ||
| 696 | u8 rtw_clearstakey_cmd23a(struct rtw_adapter *padapter, u8 *psta, u8 entry, u8 enqueue); | ||
| 697 | u8 rtw_joinbss_cmd23a(struct rtw_adapter *padapter, struct wlan_network* pnetwork); | ||
| 698 | u8 rtw_disassoc_cmd23a(struct rtw_adapter *padapter, u32 deauth_timeout_ms, bool enqueue); | ||
| 699 | u8 rtw_setopmode_cmd23a(struct rtw_adapter *padapter, enum ndis_802_11_net_infra networktype); | ||
| 700 | u8 rtw_setdatarate_cmd(struct rtw_adapter *padapter, u8 *rateset); | ||
| 701 | u8 rtw_setbasicrate_cmd(struct rtw_adapter *padapter, u8 *rateset); | ||
| 702 | u8 rtw_setbbreg_cmd(struct rtw_adapter * padapter, u8 offset, u8 val); | ||
| 703 | u8 rtw_setrfreg_cmd(struct rtw_adapter * padapter, u8 offset, u32 val); | ||
| 704 | u8 rtw_getbbreg_cmd(struct rtw_adapter * padapter, u8 offset, u8 * pval); | ||
| 705 | u8 rtw_getrfreg_cmd(struct rtw_adapter * padapter, u8 offset, u8 * pval); | ||
| 706 | u8 rtw_setrfintfs_cmd(struct rtw_adapter *padapter, u8 mode); | ||
| 707 | u8 rtw_setrttbl_cmd(struct rtw_adapter *padapter, struct setratable_parm *prate_table); | ||
| 708 | u8 rtw_getrttbl_cmd(struct rtw_adapter *padapter, struct getratable_rsp *pval); | ||
| 709 | |||
| 710 | u8 rtw_gettssi_cmd(struct rtw_adapter *padapter, u8 offset,u8 *pval); | ||
| 711 | u8 rtw_setfwdig_cmd(struct rtw_adapter*padapter, u8 type); | ||
| 712 | u8 rtw_setfwra_cmd(struct rtw_adapter*padapter, u8 type); | ||
| 713 | |||
| 714 | u8 rtw_addbareq_cmd23a(struct rtw_adapter*padapter, u8 tid, u8 *addr); | ||
| 715 | |||
| 716 | u8 rtw_dynamic_chk_wk_cmd23a(struct rtw_adapter *adapter); | ||
| 717 | |||
| 718 | u8 rtw_lps_ctrl_wk_cmd23a(struct rtw_adapter*padapter, u8 lps_ctrl_type, u8 enqueue); | ||
| 719 | |||
| 720 | u8 rtw_ps_cmd23a(struct rtw_adapter*padapter); | ||
| 721 | |||
| 722 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 723 | u8 rtw_chk_hi_queue_cmd23a(struct rtw_adapter*padapter); | ||
| 724 | #endif | ||
| 725 | |||
| 726 | u8 rtw_set_ch_cmd23a(struct rtw_adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue); | ||
| 727 | u8 rtw_set_chplan_cmd(struct rtw_adapter*padapter, u8 chplan, u8 enqueue); | ||
| 728 | u8 rtw_led_blink_cmd(struct rtw_adapter*padapter, struct led_8723a *pLed); | ||
| 729 | u8 rtw_set_csa_cmd(struct rtw_adapter*padapter, u8 new_ch_no); | ||
| 730 | u8 rtw_tdls_cmd(struct rtw_adapter*padapter, u8 *addr, u8 option); | ||
| 731 | |||
| 732 | u8 rtw_c2h_wk_cmd23a(struct rtw_adapter *padapter, u8 *c2h_evt); | ||
| 733 | |||
| 734 | u8 rtw_drvextra_cmd_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); | ||
| 735 | |||
| 736 | void rtw_survey_cmd_callback23a(struct rtw_adapter *padapter, struct cmd_obj *pcmd); | ||
| 737 | void rtw_disassoc_cmd23a_callback(struct rtw_adapter *padapter, struct cmd_obj *pcmd); | ||
| 738 | void rtw_joinbss_cmd23a_callback(struct rtw_adapter *padapter, struct cmd_obj *pcmd); | ||
| 739 | void rtw_createbss_cmd23a_callback(struct rtw_adapter *padapter, struct cmd_obj *pcmd); | ||
| 740 | void rtw_getbbrfreg_cmdrsp_callback23a(struct rtw_adapter *padapter, struct cmd_obj *pcmd); | ||
| 741 | void rtw_readtssi_cmdrsp_callback(struct rtw_adapter* padapter, struct cmd_obj *pcmd); | ||
| 742 | |||
| 743 | void rtw_setstaKey_cmdrsp_callback23a(struct rtw_adapter *padapter, struct cmd_obj *pcmd); | ||
| 744 | void rtw_setassocsta_cmdrsp_callback23a(struct rtw_adapter *padapter, struct cmd_obj *pcmd); | ||
| 745 | void rtw_getrttbl_cmdrsp_callback(struct rtw_adapter *padapter, struct cmd_obj *pcmd); | ||
| 746 | |||
| 747 | struct _cmd_callback { | ||
| 748 | u32 cmd_code; | ||
| 749 | void (*callback)(struct rtw_adapter *padapter, struct cmd_obj *cmd); | ||
| 750 | }; | ||
| 751 | |||
| 752 | enum rtw_h2c_cmd { | ||
| 753 | GEN_CMD_CODE(_Read_MACREG) , /*0*/ | ||
| 754 | GEN_CMD_CODE(_Write_MACREG) , | ||
| 755 | GEN_CMD_CODE(_Read_BBREG) , | ||
| 756 | GEN_CMD_CODE(_Write_BBREG) , | ||
| 757 | GEN_CMD_CODE(_Read_RFREG) , | ||
| 758 | GEN_CMD_CODE(_Write_RFREG) , /*5*/ | ||
| 759 | GEN_CMD_CODE(_Read_EEPROM) , | ||
| 760 | GEN_CMD_CODE(_Write_EEPROM) , | ||
| 761 | GEN_CMD_CODE(_Read_EFUSE) , | ||
| 762 | GEN_CMD_CODE(_Write_EFUSE) , | ||
| 763 | |||
| 764 | GEN_CMD_CODE(_Read_CAM) , /*10*/ | ||
| 765 | GEN_CMD_CODE(_Write_CAM) , | ||
| 766 | GEN_CMD_CODE(_setBCNITV), | ||
| 767 | GEN_CMD_CODE(_setMBIDCFG), | ||
| 768 | GEN_CMD_CODE(_JoinBss), /*14*/ | ||
| 769 | GEN_CMD_CODE(_DisConnect) , /*15*/ | ||
| 770 | GEN_CMD_CODE(_CreateBss) , | ||
| 771 | GEN_CMD_CODE(_SetOpMode) , | ||
| 772 | GEN_CMD_CODE(_SiteSurvey), /*18*/ | ||
| 773 | GEN_CMD_CODE(_SetAuth) , | ||
| 774 | |||
| 775 | GEN_CMD_CODE(_SetKey) , /*20*/ | ||
| 776 | GEN_CMD_CODE(_SetStaKey) , | ||
| 777 | GEN_CMD_CODE(_SetAssocSta) , | ||
| 778 | GEN_CMD_CODE(_DelAssocSta) , | ||
| 779 | GEN_CMD_CODE(_SetStaPwrState) , | ||
| 780 | GEN_CMD_CODE(_SetBasicRate) , /*25*/ | ||
| 781 | GEN_CMD_CODE(_GetBasicRate) , | ||
| 782 | GEN_CMD_CODE(_SetDataRate) , | ||
| 783 | GEN_CMD_CODE(_GetDataRate) , | ||
| 784 | GEN_CMD_CODE(_SetPhyInfo) , | ||
| 785 | |||
| 786 | GEN_CMD_CODE(_GetPhyInfo) , /*30*/ | ||
| 787 | GEN_CMD_CODE(_SetPhy) , | ||
| 788 | GEN_CMD_CODE(_GetPhy) , | ||
| 789 | GEN_CMD_CODE(_readRssi) , | ||
| 790 | GEN_CMD_CODE(_readGain) , | ||
| 791 | GEN_CMD_CODE(_SetAtim) , /*35*/ | ||
| 792 | GEN_CMD_CODE(_SetPwrMode) , | ||
| 793 | GEN_CMD_CODE(_JoinbssRpt), | ||
| 794 | GEN_CMD_CODE(_SetRaTable) , | ||
| 795 | GEN_CMD_CODE(_GetRaTable) , | ||
| 796 | |||
| 797 | GEN_CMD_CODE(_GetCCXReport), /*40*/ | ||
| 798 | GEN_CMD_CODE(_GetDTMReport), | ||
| 799 | GEN_CMD_CODE(_GetTXRateStatistics), | ||
| 800 | GEN_CMD_CODE(_SetUsbSuspend), | ||
| 801 | GEN_CMD_CODE(_SetH2cLbk), | ||
| 802 | GEN_CMD_CODE(_AddBAReq) , /*45*/ | ||
| 803 | GEN_CMD_CODE(_SetChannel), /*46*/ | ||
| 804 | GEN_CMD_CODE(_SetTxPower), | ||
| 805 | GEN_CMD_CODE(_SwitchAntenna), | ||
| 806 | GEN_CMD_CODE(_SetCrystalCap), | ||
| 807 | GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/ | ||
| 808 | |||
| 809 | GEN_CMD_CODE(_SetSingleToneTx),/*51*/ | ||
| 810 | GEN_CMD_CODE(_SetCarrierSuppressionTx), | ||
| 811 | GEN_CMD_CODE(_SetContinuousTx), | ||
| 812 | GEN_CMD_CODE(_SwitchBandwidth), /*54*/ | ||
| 813 | GEN_CMD_CODE(_TX_Beacon), /*55*/ | ||
| 814 | |||
| 815 | GEN_CMD_CODE(_Set_MLME_EVT), /*56*/ | ||
| 816 | GEN_CMD_CODE(_Set_Drv_Extra), /*57*/ | ||
| 817 | GEN_CMD_CODE(_Set_H2C_MSG), /*58*/ | ||
| 818 | |||
| 819 | GEN_CMD_CODE(_SetChannelPlan), /*59*/ | ||
| 820 | GEN_CMD_CODE(_LedBlink), /*60*/ | ||
| 821 | |||
| 822 | GEN_CMD_CODE(_SetChannelSwitch), /*61*/ | ||
| 823 | GEN_CMD_CODE(_TDLS), /*62*/ | ||
| 824 | |||
| 825 | MAX_H2CCMD | ||
| 826 | }; | ||
| 827 | |||
| 828 | #define _GetBBReg_CMD_ _Read_BBREG_CMD_ | ||
| 829 | #define _SetBBReg_CMD_ _Write_BBREG_CMD_ | ||
| 830 | #define _GetRFReg_CMD_ _Read_RFREG_CMD_ | ||
| 831 | #define _SetRFReg_CMD_ _Write_RFREG_CMD_ | ||
| 832 | |||
| 833 | extern struct _cmd_callback rtw_cmd_callback[]; | ||
| 834 | |||
| 835 | #endif /* _CMD_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_debug.h b/drivers/staging/rtl8723au/include/rtw_debug.h new file mode 100644 index 000000000000..a69d6e215b8b --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_debug.h | |||
| @@ -0,0 +1,192 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | #ifndef __RTW_DEBUG_H__ | ||
| 17 | #define __RTW_DEBUG_H__ | ||
| 18 | |||
| 19 | #include <osdep_service.h> | ||
| 20 | #include <drv_types.h> | ||
| 21 | |||
| 22 | #define _drv_always_ 1 | ||
| 23 | #define _drv_emerg_ 2 | ||
| 24 | #define _drv_alert_ 3 | ||
| 25 | #define _drv_err_ 4 | ||
| 26 | #define _drv_warning_ 5 | ||
| 27 | #define _drv_notice_ 6 | ||
| 28 | #define _drv_info_ 7 | ||
| 29 | #define _drv_debug_ 8 | ||
| 30 | |||
| 31 | #define _module_rtl871x_xmit_c_ BIT(0) | ||
| 32 | #define _module_xmit_osdep_c_ BIT(1) | ||
| 33 | #define _module_rtl871x_recv_c_ BIT(2) | ||
| 34 | #define _module_recv_osdep_c_ BIT(3) | ||
| 35 | #define _module_rtl871x_mlme_c_ BIT(4) | ||
| 36 | #define _module_mlme_osdep_c_ BIT(5) | ||
| 37 | #define _module_rtl871x_sta_mgt_c_ BIT(6) | ||
| 38 | #define _module_rtl871x_cmd_c_ BIT(7) | ||
| 39 | #define _module_cmd_osdep_c_ BIT(8) | ||
| 40 | #define _module_rtl871x_io_c_ BIT(9) | ||
| 41 | #define _module_io_osdep_c_ BIT(10) | ||
| 42 | #define _module_os_intfs_c_ BIT(11) | ||
| 43 | #define _module_rtl871x_security_c_ BIT(12) | ||
| 44 | #define _module_rtl871x_eeprom_c_ BIT(13) | ||
| 45 | #define _module_hal_init_c_ BIT(14) | ||
| 46 | #define _module_hci_hal_init_c_ BIT(15) | ||
| 47 | #define _module_rtl871x_ioctl_c_ BIT(16) | ||
| 48 | #define _module_rtl871x_ioctl_set_c_ BIT(17) | ||
| 49 | #define _module_rtl871x_ioctl_query_c_ BIT(18) | ||
| 50 | #define _module_rtl871x_pwrctrl_c_ BIT(19) | ||
| 51 | #define _module_hci_intfs_c_ BIT(20) | ||
| 52 | #define _module_hci_ops_c_ BIT(21) | ||
| 53 | #define _module_osdep_service_c_ BIT(22) | ||
| 54 | #define _module_mp_ BIT(23) | ||
| 55 | #define _module_hci_ops_os_c_ BIT(24) | ||
| 56 | #define _module_rtl871x_ioctl_os_c BIT(25) | ||
| 57 | #define _module_rtl8712_cmd_c_ BIT(26) | ||
| 58 | #define _module_rtl8192c_xmit_c_ BIT(28) | ||
| 59 | #define _module_hal_xmit_c_ BIT(28) /* duplication intentional */ | ||
| 60 | #define _module_efuse_ BIT(29) | ||
| 61 | #define _module_rtl8712_recv_c_ BIT(30) | ||
| 62 | #define _module_rtl8712_led_c_ BIT(31) | ||
| 63 | |||
| 64 | #undef _MODULE_DEFINE_ | ||
| 65 | |||
| 66 | #if defined _RTW_XMIT_C_ | ||
| 67 | #define _MODULE_DEFINE_ _module_rtl871x_xmit_c_ | ||
| 68 | #elif defined _XMIT_OSDEP_C_ | ||
| 69 | #define _MODULE_DEFINE_ _module_xmit_osdep_c_ | ||
| 70 | #elif defined _RTW_RECV_C_ | ||
| 71 | #define _MODULE_DEFINE_ _module_rtl871x_recv_c_ | ||
| 72 | #elif defined _RECV_OSDEP_C_ | ||
| 73 | #define _MODULE_DEFINE_ _module_recv_osdep_c_ | ||
| 74 | #elif defined _RTW_MLME_C_ | ||
| 75 | #define _MODULE_DEFINE_ _module_rtl871x_mlme_c_ | ||
| 76 | #elif defined _MLME_OSDEP_C_ | ||
| 77 | #define _MODULE_DEFINE_ _module_mlme_osdep_c_ | ||
| 78 | #elif defined _RTW_MLME_EXT_C_ | ||
| 79 | #define _MODULE_DEFINE_ 1 | ||
| 80 | #elif defined _RTW_STA_MGT_C_ | ||
| 81 | #define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_ | ||
| 82 | #elif defined _RTW_CMD_C_ | ||
| 83 | #define _MODULE_DEFINE_ _module_rtl871x_cmd_c_ | ||
| 84 | #elif defined _CMD_OSDEP_C_ | ||
| 85 | #define _MODULE_DEFINE_ _module_cmd_osdep_c_ | ||
| 86 | #elif defined _RTW_IO_C_ | ||
| 87 | #define _MODULE_DEFINE_ _module_rtl871x_io_c_ | ||
| 88 | #elif defined _IO_OSDEP_C_ | ||
| 89 | #define _MODULE_DEFINE_ _module_io_osdep_c_ | ||
| 90 | #elif defined _OS_INTFS_C_ | ||
| 91 | #define _MODULE_DEFINE_ _module_os_intfs_c_ | ||
| 92 | #elif defined _RTW_SECURITY_C_ | ||
| 93 | #define _MODULE_DEFINE_ _module_rtl871x_security_c_ | ||
| 94 | #elif defined _RTW_EEPROM_C_ | ||
| 95 | #define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_ | ||
| 96 | #elif defined _HAL_INTF_C_ | ||
| 97 | #define _MODULE_DEFINE_ _module_hal_init_c_ | ||
| 98 | #elif (defined _HCI_HAL_INIT_C_) || (defined _SDIO_HALINIT_C_) | ||
| 99 | #define _MODULE_DEFINE_ _module_hci_hal_init_c_ | ||
| 100 | #elif defined _RTL871X_IOCTL_C_ | ||
| 101 | #define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_ | ||
| 102 | #elif defined _RTL871X_IOCTL_SET_C_ | ||
| 103 | #define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_ | ||
| 104 | #elif defined _RTL871X_IOCTL_QUERY_C_ | ||
| 105 | #define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_ | ||
| 106 | #elif defined _RTL871X_PWRCTRL_C_ | ||
| 107 | #define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_ | ||
| 108 | #elif defined _RTW_PWRCTRL_C_ | ||
| 109 | #define _MODULE_DEFINE_ 1 | ||
| 110 | #elif defined _HCI_INTF_C_ | ||
| 111 | #define _MODULE_DEFINE_ _module_hci_intfs_c_ | ||
| 112 | #elif defined _HCI_OPS_C_ | ||
| 113 | #define _MODULE_DEFINE_ _module_hci_ops_c_ | ||
| 114 | #elif defined _SDIO_OPS_C_ | ||
| 115 | #define _MODULE_DEFINE_ 1 | ||
| 116 | #elif defined _OSDEP_HCI_INTF_C_ | ||
| 117 | #define _MODULE_DEFINE_ _module_hci_intfs_c_ | ||
| 118 | #elif defined _OSDEP_SERVICE_C_ | ||
| 119 | #define _MODULE_DEFINE_ _module_osdep_service_c_ | ||
| 120 | #elif defined _HCI_OPS_OS_C_ | ||
| 121 | #define _MODULE_DEFINE_ _module_hci_ops_os_c_ | ||
| 122 | #elif defined _RTL871X_IOCTL_LINUX_C_ | ||
| 123 | #define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c | ||
| 124 | #elif defined _RTL8712_CMD_C_ | ||
| 125 | #define _MODULE_DEFINE_ _module_rtl8712_cmd_c_ | ||
| 126 | #elif defined _RTL8192C_XMIT_C_ | ||
| 127 | #define _MODULE_DEFINE_ 1 | ||
| 128 | #elif defined _RTL8723AS_XMIT_C_ | ||
| 129 | #define _MODULE_DEFINE_ 1 | ||
| 130 | #elif defined _RTL8712_RECV_C_ | ||
| 131 | #define _MODULE_DEFINE_ _module_rtl8712_recv_c_ | ||
| 132 | #elif defined _RTL8192CU_RECV_C_ | ||
| 133 | #define _MODULE_DEFINE_ _module_rtl8712_recv_c_ | ||
| 134 | #elif defined _RTL871X_MLME_EXT_C_ | ||
| 135 | #define _MODULE_DEFINE_ _module_mlme_osdep_c_ | ||
| 136 | #elif defined _RTW_MP_C_ | ||
| 137 | #define _MODULE_DEFINE_ _module_mp_ | ||
| 138 | #elif defined _RTW_MP_IOCTL_C_ | ||
| 139 | #define _MODULE_DEFINE_ _module_mp_ | ||
| 140 | #elif defined _RTW_EFUSE_C_ | ||
| 141 | #define _MODULE_DEFINE_ _module_efuse_ | ||
| 142 | #endif | ||
| 143 | |||
| 144 | #define DRIVER_PREFIX "RTL8723AU: " | ||
| 145 | #define DEBUG_LEVEL (_drv_err_) | ||
| 146 | #define DBG_8723A_LEVEL(_level, fmt, arg...) \ | ||
| 147 | do { \ | ||
| 148 | if (_level <= GlobalDebugLevel23A) \ | ||
| 149 | pr_info(DRIVER_PREFIX"ERROR " fmt, ##arg);\ | ||
| 150 | } while (0) | ||
| 151 | |||
| 152 | #define DBG_8723A(...) \ | ||
| 153 | do { \ | ||
| 154 | if (_drv_err_ <= GlobalDebugLevel23A) \ | ||
| 155 | pr_info(DRIVER_PREFIX __VA_ARGS__); \ | ||
| 156 | } while (0) | ||
| 157 | |||
| 158 | #define MSG_8723A(...) \ | ||
| 159 | do { \ | ||
| 160 | if (_drv_err_ <= GlobalDebugLevel23A) \ | ||
| 161 | pr_info(DRIVER_PREFIX __VA_ARGS__); \ | ||
| 162 | } while (0) | ||
| 163 | |||
| 164 | extern u32 GlobalDebugLevel23A; | ||
| 165 | |||
| 166 | |||
| 167 | #define RT_TRACE(_Comp, _Level, Fmt) \ | ||
| 168 | do { \ | ||
| 169 | if (_Level <= GlobalDebugLevel23A) { \ | ||
| 170 | pr_info("%s [0x%08x,%d]", DRIVER_PREFIX, \ | ||
| 171 | (unsigned int)_Comp, _Level); \ | ||
| 172 | pr_info Fmt; \ | ||
| 173 | } \ | ||
| 174 | } while (0) | ||
| 175 | |||
| 176 | #define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, \ | ||
| 177 | _HexDataLen) \ | ||
| 178 | if (_Level <= GlobalDebugLevel23A) { \ | ||
| 179 | int __i; \ | ||
| 180 | u8 *ptr = (u8 *)_HexData; \ | ||
| 181 | pr_info("%s", DRIVER_PREFIX); \ | ||
| 182 | pr_info(_TitleString); \ | ||
| 183 | for (__i = 0; __i < (int)_HexDataLen; __i++) { \ | ||
| 184 | printk("%02X%s", ptr[__i], \ | ||
| 185 | (((__i + 1) % 4) == 0) ? " " : " "); \ | ||
| 186 | if (((__i + 1) % 16) == 0) \ | ||
| 187 | printk("\n"); \ | ||
| 188 | } \ | ||
| 189 | printk("\n"); \ | ||
| 190 | } | ||
| 191 | |||
| 192 | #endif /* __RTW_DEBUG_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_eeprom.h b/drivers/staging/rtl8723au/include/rtw_eeprom.h new file mode 100644 index 000000000000..d008f032181b --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_eeprom.h | |||
| @@ -0,0 +1,135 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_EEPROM_H__ | ||
| 16 | #define __RTW_EEPROM_H__ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | #define RTL8712_EEPROM_ID 0x8712 | ||
| 22 | /* define EEPROM_MAX_SIZE 256 */ | ||
| 23 | |||
| 24 | #define HWSET_MAX_SIZE_512 512 | ||
| 25 | #define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512 | ||
| 26 | |||
| 27 | #define CLOCK_RATE 50 /* 100us */ | ||
| 28 | |||
| 29 | /* EEPROM opcodes */ | ||
| 30 | #define EEPROM_READ_OPCODE 06 | ||
| 31 | #define EEPROM_WRITE_OPCODE 05 | ||
| 32 | #define EEPROM_ERASE_OPCODE 07 | ||
| 33 | #define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */ | ||
| 34 | #define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */ | ||
| 35 | |||
| 36 | /* Country codes */ | ||
| 37 | #define USA 0x555320 | ||
| 38 | #define EUROPE 0x1 /* temp, should be provided later */ | ||
| 39 | #define JAPAN 0x2 /* temp, should be provided later */ | ||
| 40 | |||
| 41 | #define EEPROM_CID_DEFAULT 0x0 | ||
| 42 | #define EEPROM_CID_ALPHA 0x1 | ||
| 43 | #define EEPROM_CID_Senao 0x3 | ||
| 44 | #define EEPROM_CID_NetCore 0x5 | ||
| 45 | #define EEPROM_CID_CAMEO 0X8 | ||
| 46 | #define EEPROM_CID_SITECOM 0x9 | ||
| 47 | #define EEPROM_CID_COREGA 0xB | ||
| 48 | #define EEPROM_CID_EDIMAX_BELKIN 0xC | ||
| 49 | #define EEPROM_CID_SERCOMM_BELKIN 0xE | ||
| 50 | #define EEPROM_CID_CAMEO1 0xF | ||
| 51 | #define EEPROM_CID_WNC_COREGA 0x12 | ||
| 52 | #define EEPROM_CID_CLEVO 0x13 | ||
| 53 | #define EEPROM_CID_WHQL 0xFE /* added by chiyoko for dtm, 20090108 */ | ||
| 54 | |||
| 55 | /* */ | ||
| 56 | /* Customer ID, note that: */ | ||
| 57 | /* This variable is initiailzed through EEPROM or registry, */ | ||
| 58 | /* however, its definition may be different with that in EEPROM for */ | ||
| 59 | /* EEPROM size consideration. So, we have to perform proper translation between them. */ | ||
| 60 | /* Besides, CustomerID of registry has precedence of that of EEPROM. */ | ||
| 61 | /* defined below. 060703, by rcnjko. */ | ||
| 62 | /* */ | ||
| 63 | enum rt_customer_id | ||
| 64 | { | ||
| 65 | RT_CID_DEFAULT = 0, | ||
| 66 | RT_CID_8187_ALPHA0 = 1, | ||
| 67 | RT_CID_8187_SERCOMM_PS = 2, | ||
| 68 | RT_CID_8187_HW_LED = 3, | ||
| 69 | RT_CID_8187_NETGEAR = 4, | ||
| 70 | RT_CID_WHQL = 5, | ||
| 71 | RT_CID_819x_CAMEO = 6, | ||
| 72 | RT_CID_819x_RUNTOP = 7, | ||
| 73 | RT_CID_819x_Senao = 8, | ||
| 74 | RT_CID_TOSHIBA = 9, /* Merge by Jacken, 2008/01/31. */ | ||
| 75 | RT_CID_819x_Netcore = 10, | ||
| 76 | RT_CID_Nettronix = 11, | ||
| 77 | RT_CID_DLINK = 12, | ||
| 78 | RT_CID_PRONET = 13, | ||
| 79 | RT_CID_COREGA = 14, | ||
| 80 | RT_CID_CHINA_MOBILE = 15, | ||
| 81 | RT_CID_819x_ALPHA = 16, | ||
| 82 | RT_CID_819x_Sitecom = 17, | ||
| 83 | RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */ | ||
| 84 | RT_CID_819x_Lenovo = 19, | ||
| 85 | RT_CID_819x_QMI = 20, | ||
| 86 | RT_CID_819x_Edimax_Belkin = 21, | ||
| 87 | RT_CID_819x_Sercomm_Belkin = 22, | ||
| 88 | RT_CID_819x_CAMEO1 = 23, | ||
| 89 | RT_CID_819x_MSI = 24, | ||
| 90 | RT_CID_819x_Acer = 25, | ||
| 91 | RT_CID_819x_AzWave_ASUS = 26, | ||
| 92 | RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */ | ||
| 93 | RT_CID_819x_HP = 28, | ||
| 94 | RT_CID_819x_WNC_COREGA = 29, | ||
| 95 | RT_CID_819x_Arcadyan_Belkin = 30, | ||
| 96 | RT_CID_819x_SAMSUNG = 31, | ||
| 97 | RT_CID_819x_CLEVO = 32, | ||
| 98 | RT_CID_819x_DELL = 33, | ||
| 99 | RT_CID_819x_PRONETS = 34, | ||
| 100 | RT_CID_819x_Edimax_ASUS = 35, | ||
| 101 | RT_CID_819x_CAMEO_NETGEAR = 36, | ||
| 102 | RT_CID_PLANEX = 37, | ||
| 103 | RT_CID_CC_C = 38, | ||
| 104 | RT_CID_819x_Xavi = 39, | ||
| 105 | RT_CID_819x_FUNAI_TV = 40, | ||
| 106 | RT_CID_819x_ALPHA_WD=41, | ||
| 107 | }; | ||
| 108 | |||
| 109 | struct eeprom_priv { | ||
| 110 | u8 bautoload_fail_flag; | ||
| 111 | u8 bloadfile_fail_flag; | ||
| 112 | u8 bloadmac_fail_flag; | ||
| 113 | /* u8 bempty; */ | ||
| 114 | /* u8 sys_config; */ | ||
| 115 | u8 mac_addr[6]; /* PermanentAddress */ | ||
| 116 | /* u8 config0; */ | ||
| 117 | u16 channel_plan; | ||
| 118 | /* u8 country_string[3]; */ | ||
| 119 | /* u8 tx_power_b[15]; */ | ||
| 120 | /* u8 tx_power_g[15]; */ | ||
| 121 | /* u8 tx_power_a[201]; */ | ||
| 122 | |||
| 123 | u8 EepromOrEfuse; | ||
| 124 | |||
| 125 | u8 efuse_eeprom_data[HWSET_MAX_SIZE_512]; /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */ | ||
| 126 | }; | ||
| 127 | |||
| 128 | void eeprom_write16(struct rtw_adapter *padapter, u16 reg, u16 data); | ||
| 129 | u16 eeprom_read16(struct rtw_adapter *padapter, u16 reg); | ||
| 130 | void read_eeprom_content(struct rtw_adapter *padapter); | ||
| 131 | void eeprom_read_sz(struct rtw_adapter * padapter, u16 reg,u8* data, u32 sz); | ||
| 132 | |||
| 133 | void read_eeprom_content_by_attrib(struct rtw_adapter *padapter); | ||
| 134 | |||
| 135 | #endif /* __RTL871X_EEPROM_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_efuse.h b/drivers/staging/rtl8723au/include/rtw_efuse.h new file mode 100644 index 000000000000..a7755056163f --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_efuse.h | |||
| @@ -0,0 +1,109 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | #ifndef __RTW_EFUSE_H__ | ||
| 17 | #define __RTW_EFUSE_H__ | ||
| 18 | |||
| 19 | #include <osdep_service.h> | ||
| 20 | |||
| 21 | #define EFUSE_ERROE_HANDLE 1 | ||
| 22 | |||
| 23 | #define PG_STATE_HEADER 0x01 | ||
| 24 | #define PG_STATE_WORD_0 0x02 | ||
| 25 | #define PG_STATE_WORD_1 0x04 | ||
| 26 | #define PG_STATE_WORD_2 0x08 | ||
| 27 | #define PG_STATE_WORD_3 0x10 | ||
| 28 | #define PG_STATE_DATA 0x20 | ||
| 29 | |||
| 30 | #define PG_SWBYTE_H 0x01 | ||
| 31 | #define PG_SWBYTE_L 0x02 | ||
| 32 | |||
| 33 | #define PGPKT_DATA_SIZE 8 | ||
| 34 | |||
| 35 | #define EFUSE_WIFI 0 | ||
| 36 | #define EFUSE_BT 1 | ||
| 37 | |||
| 38 | enum _EFUSE_DEF_TYPE { | ||
| 39 | TYPE_EFUSE_MAX_SECTION = 0, | ||
| 40 | TYPE_EFUSE_REAL_CONTENT_LEN = 1, | ||
| 41 | TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, | ||
| 42 | TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, | ||
| 43 | TYPE_EFUSE_MAP_LEN = 4, | ||
| 44 | TYPE_EFUSE_PROTECT_BYTES_BANK = 5, | ||
| 45 | TYPE_EFUSE_CONTENT_LEN_BANK = 6, | ||
| 46 | }; | ||
| 47 | |||
| 48 | /* E-Fuse */ | ||
| 49 | #define EFUSE_MAP_SIZE 256 | ||
| 50 | |||
| 51 | #define EFUSE_MAX_SIZE 512 | ||
| 52 | /* end of E-Fuse */ | ||
| 53 | |||
| 54 | #define EFUSE_MAX_MAP_LEN 256 | ||
| 55 | #define EFUSE_MAX_HW_SIZE 512 | ||
| 56 | #define EFUSE_MAX_SECTION_BASE 16 | ||
| 57 | |||
| 58 | #define EXT_HEADER(header) ((header & 0x1F ) == 0x0F) | ||
| 59 | #define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) | ||
| 60 | #define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5) | ||
| 61 | |||
| 62 | #define EFUSE_REPEAT_THRESHOLD_ 3 | ||
| 63 | |||
| 64 | /* */ | ||
| 65 | /* The following is for BT Efuse definition */ | ||
| 66 | /* */ | ||
| 67 | #define EFUSE_BT_MAX_MAP_LEN 1024 | ||
| 68 | #define EFUSE_MAX_BANK 4 | ||
| 69 | #define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) | ||
| 70 | /* */ | ||
| 71 | /*--------------------------Define Parameters-------------------------------*/ | ||
| 72 | #define EFUSE_MAX_WORD_UNIT 4 | ||
| 73 | |||
| 74 | /*------------------------------Define structure----------------------------*/ | ||
| 75 | struct pg_pkt_struct { | ||
| 76 | u8 offset; | ||
| 77 | u8 word_en; | ||
| 78 | u8 data[8]; | ||
| 79 | u8 word_cnts; | ||
| 80 | }; | ||
| 81 | |||
| 82 | /*------------------------Export global variable----------------------------*/ | ||
| 83 | |||
| 84 | u8 efuse_GetCurrentSize23a(struct rtw_adapter *padapter, u16 *size); | ||
| 85 | u16 efuse_GetMaxSize23a(struct rtw_adapter *padapter); | ||
| 86 | u8 rtw_efuse_access23a(struct rtw_adapter *padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data); | ||
| 87 | u8 rtw_efuse_map_read23a(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data); | ||
| 88 | u8 rtw_efuse_map_write(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data); | ||
| 89 | u8 rtw_BT_efuse_map_read23a(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data); | ||
| 90 | u8 rtw_BT_efuse_map_write(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data); | ||
| 91 | |||
| 92 | u16 Efuse_GetCurrentSize23a(struct rtw_adapter *pAdapter, u8 efuseType); | ||
| 93 | u8 Efuse_CalculateWordCnts23a(u8 word_en); | ||
| 94 | void ReadEFuseByte23a(struct rtw_adapter *Adapter, u16 _offset, u8 *pbuf); | ||
| 95 | void EFUSE_GetEfuseDefinition23a(struct rtw_adapter *pAdapter, u8 efuseType, u8 type, void *pOut); | ||
| 96 | u8 efuse_OneByteRead23a(struct rtw_adapter *pAdapter, u16 addr, u8 *data); | ||
| 97 | u8 efuse_OneByteWrite23a(struct rtw_adapter *pAdapter, u16 addr, u8 data); | ||
| 98 | |||
| 99 | void Efuse_PowerSwitch23a(struct rtw_adapter *pAdapter,u8 bWrite,u8 PwrState); | ||
| 100 | int Efuse_PgPacketRead23a(struct rtw_adapter *pAdapter, u8 offset, u8 *data); | ||
| 101 | int Efuse_PgPacketWrite23a(struct rtw_adapter *pAdapter, u8 offset, u8 word_en, u8 *data); | ||
| 102 | void efuse_WordEnableDataRead23a(u8 word_en, u8 *sourdata, u8 *targetdata); | ||
| 103 | u8 Efuse_WordEnableDataWrite23a(struct rtw_adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data); | ||
| 104 | |||
| 105 | u8 EFUSE_Read1Byte23a(struct rtw_adapter *pAdapter, u16 Address); | ||
| 106 | void EFUSE_ShadowMapUpdate23a(struct rtw_adapter *pAdapter, u8 efuseType); | ||
| 107 | void EFUSE_ShadowRead23a(struct rtw_adapter *pAdapter, u8 Type, u16 Offset, u32 *Value); | ||
| 108 | |||
| 109 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_event.h b/drivers/staging/rtl8723au/include/rtw_event.h new file mode 100644 index 000000000000..bb20640e6855 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_event.h | |||
| @@ -0,0 +1,114 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _RTW_EVENT_H_ | ||
| 16 | #define _RTW_EVENT_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | |||
| 20 | #include <wlan_bssdef.h> | ||
| 21 | |||
| 22 | /* | ||
| 23 | Used to report a bss has been scanned | ||
| 24 | |||
| 25 | */ | ||
| 26 | struct survey_event { | ||
| 27 | struct wlan_bssid_ex bss; | ||
| 28 | }; | ||
| 29 | |||
| 30 | /* | ||
| 31 | Used to report that the requested site survey has been done. | ||
| 32 | |||
| 33 | bss_cnt indicates the number of bss that has been reported. | ||
| 34 | |||
| 35 | |||
| 36 | */ | ||
| 37 | struct surveydone_event { | ||
| 38 | unsigned int bss_cnt; | ||
| 39 | |||
| 40 | }; | ||
| 41 | |||
| 42 | /* | ||
| 43 | Used to report the link result of joinning the given bss | ||
| 44 | |||
| 45 | |||
| 46 | join_res: | ||
| 47 | -1: authentication fail | ||
| 48 | -2: association fail | ||
| 49 | > 0: TID | ||
| 50 | |||
| 51 | */ | ||
| 52 | struct joinbss_event { | ||
| 53 | struct wlan_network network; | ||
| 54 | }; | ||
| 55 | |||
| 56 | /* | ||
| 57 | Used to report a given STA has joinned the created BSS. | ||
| 58 | It is used in AP/Ad-HoC(M) mode. | ||
| 59 | |||
| 60 | |||
| 61 | */ | ||
| 62 | struct stassoc_event { | ||
| 63 | unsigned char macaddr[6]; | ||
| 64 | unsigned char rsvd[2]; | ||
| 65 | int cam_id; | ||
| 66 | |||
| 67 | }; | ||
| 68 | |||
| 69 | struct stadel_event { | ||
| 70 | unsigned char macaddr[6]; | ||
| 71 | unsigned char rsvd[2]; /* for reason */ | ||
| 72 | int mac_id; | ||
| 73 | }; | ||
| 74 | |||
| 75 | struct addba_event | ||
| 76 | { | ||
| 77 | unsigned int tid; | ||
| 78 | }; | ||
| 79 | |||
| 80 | #define GEN_EVT_CODE(event) event ## _EVT_ | ||
| 81 | |||
| 82 | struct fwevent { | ||
| 83 | u32 parmsize; | ||
| 84 | void (*event_callback)(struct rtw_adapter *dev, u8 *pbuf); | ||
| 85 | }; | ||
| 86 | |||
| 87 | |||
| 88 | #define C2HEVENT_SZ 32 | ||
| 89 | |||
| 90 | struct event_node{ | ||
| 91 | unsigned char *node; | ||
| 92 | unsigned char evt_code; | ||
| 93 | unsigned short evt_sz; | ||
| 94 | volatile int *caller_ff_tail; | ||
| 95 | int caller_ff_sz; | ||
| 96 | }; | ||
| 97 | |||
| 98 | struct c2hevent_queue { | ||
| 99 | volatile int head; | ||
| 100 | volatile int tail; | ||
| 101 | struct event_node nodes[C2HEVENT_SZ]; | ||
| 102 | unsigned char seq; | ||
| 103 | }; | ||
| 104 | |||
| 105 | #define NETWORK_QUEUE_SZ 4 | ||
| 106 | |||
| 107 | struct network_queue { | ||
| 108 | volatile int head; | ||
| 109 | volatile int tail; | ||
| 110 | struct wlan_bssid_ex networks[NETWORK_QUEUE_SZ]; | ||
| 111 | }; | ||
| 112 | |||
| 113 | |||
| 114 | #endif /* _WLANEVENT_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_ht.h b/drivers/staging/rtl8723au/include/rtw_ht.h new file mode 100644 index 000000000000..7fe0aa46f707 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_ht.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _RTW_HT_H_ | ||
| 16 | #define _RTW_HT_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include "linux/ieee80211.h" | ||
| 20 | #include "wifi.h" | ||
| 21 | |||
| 22 | struct ht_priv | ||
| 23 | { | ||
| 24 | u32 ht_option; | ||
| 25 | u32 ampdu_enable;/* for enable Tx A-MPDU */ | ||
| 26 | /* u8 baddbareq_issued[16]; */ | ||
| 27 | u32 tx_amsdu_enable;/* for enable Tx A-MSDU */ | ||
| 28 | u32 tx_amdsu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */ | ||
| 29 | u32 rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */ | ||
| 30 | |||
| 31 | u8 bwmode;/* */ | ||
| 32 | u8 ch_offset;/* PRIME_CHNL_OFFSET */ | ||
| 33 | u8 sgi;/* short GI */ | ||
| 34 | |||
| 35 | /* for processing Tx A-MPDU */ | ||
| 36 | u8 agg_enable_bitmap; | ||
| 37 | /* u8 ADDBA_retry_count; */ | ||
| 38 | u8 candidate_tid_bitmap; | ||
| 39 | |||
| 40 | struct ieee80211_ht_cap ht_cap; | ||
| 41 | }; | ||
| 42 | |||
| 43 | #endif /* _RTL871X_HT_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_io.h b/drivers/staging/rtl8723au/include/rtw_io.h new file mode 100644 index 000000000000..8d39d800267d --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_io.h | |||
| @@ -0,0 +1,416 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef _RTW_IO_H_ | ||
| 17 | #define _RTW_IO_H_ | ||
| 18 | |||
| 19 | #include <osdep_service.h> | ||
| 20 | #include <osdep_intf.h> | ||
| 21 | |||
| 22 | #include <asm/byteorder.h> | ||
| 23 | #include <linux/semaphore.h> | ||
| 24 | #include <linux/list.h> | ||
| 25 | /* include <linux/smp_lock.h> */ | ||
| 26 | #include <linux/spinlock.h> | ||
| 27 | #include <asm/atomic.h> | ||
| 28 | |||
| 29 | #include <linux/usb.h> | ||
| 30 | #include <linux/usb/ch9.h> | ||
| 31 | |||
| 32 | #define rtw_usb_buffer_alloc(dev, size, dma) usb_alloc_coherent((dev), (size), (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), (dma)) | ||
| 33 | #define rtw_usb_buffer_free(dev, size, addr, dma) usb_free_coherent((dev), (size), (addr), (dma)) | ||
| 34 | |||
| 35 | #define NUM_IOREQ 8 | ||
| 36 | |||
| 37 | #define MAX_PROT_SZ (64-16) | ||
| 38 | |||
| 39 | #define _IOREADY 0 | ||
| 40 | #define _IO_WAIT_COMPLETE 1 | ||
| 41 | #define _IO_WAIT_RSP 2 | ||
| 42 | |||
| 43 | /* IO COMMAND TYPE */ | ||
| 44 | #define _IOSZ_MASK_ (0x7F) | ||
| 45 | #define _IO_WRITE_ BIT(7) | ||
| 46 | #define _IO_FIXED_ BIT(8) | ||
| 47 | #define _IO_BURST_ BIT(9) | ||
| 48 | #define _IO_BYTE_ BIT(10) | ||
| 49 | #define _IO_HW_ BIT(11) | ||
| 50 | #define _IO_WORD_ BIT(12) | ||
| 51 | #define _IO_SYNC_ BIT(13) | ||
| 52 | #define _IO_CMDMASK_ (0x1F80) | ||
| 53 | |||
| 54 | |||
| 55 | /* | ||
| 56 | For prompt mode accessing, caller shall free io_req | ||
| 57 | Otherwise, io_handler will free io_req | ||
| 58 | */ | ||
| 59 | |||
| 60 | |||
| 61 | |||
| 62 | /* IO STATUS TYPE */ | ||
| 63 | #define _IO_ERR_ BIT(2) | ||
| 64 | #define _IO_SUCCESS_ BIT(1) | ||
| 65 | #define _IO_DONE_ BIT(0) | ||
| 66 | |||
| 67 | |||
| 68 | #define IO_RD32 (_IO_SYNC_ | _IO_WORD_) | ||
| 69 | #define IO_RD16 (_IO_SYNC_ | _IO_HW_) | ||
| 70 | #define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) | ||
| 71 | |||
| 72 | #define IO_RD32_ASYNC (_IO_WORD_) | ||
| 73 | #define IO_RD16_ASYNC (_IO_HW_) | ||
| 74 | #define IO_RD8_ASYNC (_IO_BYTE_) | ||
| 75 | |||
| 76 | #define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) | ||
| 77 | #define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) | ||
| 78 | #define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) | ||
| 79 | |||
| 80 | #define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) | ||
| 81 | #define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) | ||
| 82 | #define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) | ||
| 83 | |||
| 84 | /* | ||
| 85 | |||
| 86 | Only Sync. burst accessing is provided. | ||
| 87 | |||
| 88 | */ | ||
| 89 | |||
| 90 | #define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_)) | ||
| 91 | #define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_)) | ||
| 92 | |||
| 93 | |||
| 94 | |||
| 95 | /* below is for the intf_option bit defition... */ | ||
| 96 | |||
| 97 | #define _INTF_ASYNC_ BIT(0) /* support async io */ | ||
| 98 | |||
| 99 | struct intf_priv; | ||
| 100 | struct intf_hdl; | ||
| 101 | struct io_queue; | ||
| 102 | |||
| 103 | struct _io_ops | ||
| 104 | { | ||
| 105 | u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr); | ||
| 106 | u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr); | ||
| 107 | u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr); | ||
| 108 | |||
| 109 | int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); | ||
| 110 | int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); | ||
| 111 | int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); | ||
| 112 | int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); | ||
| 113 | |||
| 114 | int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); | ||
| 115 | int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); | ||
| 116 | int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); | ||
| 117 | |||
| 118 | void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); | ||
| 119 | void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); | ||
| 120 | |||
| 121 | void (*_sync_irp_protocol_rw)(struct io_queue *pio_q); | ||
| 122 | |||
| 123 | u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); | ||
| 124 | |||
| 125 | u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, struct recv_buf *rbuf); | ||
| 126 | u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, struct xmit_buf *pmem); | ||
| 127 | |||
| 128 | u32 (*_write_scsi)(struct intf_hdl *pintfhdl,u32 cnt, u8 *pmem); | ||
| 129 | |||
| 130 | void (*_read_port_cancel)(struct intf_hdl *pintfhdl); | ||
| 131 | void (*_write_port_cancel)(struct intf_hdl *pintfhdl); | ||
| 132 | |||
| 133 | }; | ||
| 134 | |||
| 135 | struct io_req { | ||
| 136 | struct list_head list; | ||
| 137 | u32 addr; | ||
| 138 | volatile u32 val; | ||
| 139 | u32 command; | ||
| 140 | u32 status; | ||
| 141 | u8 *pbuf; | ||
| 142 | struct semaphore sema; | ||
| 143 | |||
| 144 | void (*_async_io_callback)(struct rtw_adapter *padater, struct io_req *pio_req, u8 *cnxt); | ||
| 145 | u8 *cnxt; | ||
| 146 | }; | ||
| 147 | |||
| 148 | struct intf_hdl { | ||
| 149 | struct rtw_adapter *padapter; | ||
| 150 | struct dvobj_priv *pintf_dev;/* pointer to &(padapter->dvobjpriv); */ | ||
| 151 | |||
| 152 | struct _io_ops io_ops; | ||
| 153 | |||
| 154 | }; | ||
| 155 | |||
| 156 | struct reg_protocol_rd { | ||
| 157 | |||
| 158 | #ifdef __LITTLE_ENDIAN | ||
| 159 | |||
| 160 | /* DW1 */ | ||
| 161 | u32 NumOfTrans:4; | ||
| 162 | u32 Reserved1:4; | ||
| 163 | u32 Reserved2:24; | ||
| 164 | /* DW2 */ | ||
| 165 | u32 ByteCount:7; | ||
| 166 | u32 WriteEnable:1; /* 0:read, 1:write */ | ||
| 167 | u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */ | ||
| 168 | u32 BurstMode:1; | ||
| 169 | u32 Byte1Access:1; | ||
| 170 | u32 Byte2Access:1; | ||
| 171 | u32 Byte4Access:1; | ||
| 172 | u32 Reserved3:3; | ||
| 173 | u32 Reserved4:16; | ||
| 174 | /* DW3 */ | ||
| 175 | u32 BusAddress; | ||
| 176 | /* DW4 */ | ||
| 177 | /* u32 Value; */ | ||
| 178 | #else | ||
| 179 | |||
| 180 | |||
| 181 | /* DW1 */ | ||
| 182 | u32 Reserved1 :4; | ||
| 183 | u32 NumOfTrans :4; | ||
| 184 | |||
| 185 | u32 Reserved2 :24; | ||
| 186 | |||
| 187 | /* DW2 */ | ||
| 188 | u32 WriteEnable : 1; | ||
| 189 | u32 ByteCount :7; | ||
| 190 | |||
| 191 | |||
| 192 | u32 Reserved3 : 3; | ||
| 193 | u32 Byte4Access : 1; | ||
| 194 | |||
| 195 | u32 Byte2Access : 1; | ||
| 196 | u32 Byte1Access : 1; | ||
| 197 | u32 BurstMode :1 ; | ||
| 198 | u32 FixOrContinuous : 1; | ||
| 199 | |||
| 200 | u32 Reserved4 : 16; | ||
| 201 | |||
| 202 | /* DW3 */ | ||
| 203 | u32 BusAddress; | ||
| 204 | |||
| 205 | /* DW4 */ | ||
| 206 | /* u32 Value; */ | ||
| 207 | |||
| 208 | #endif | ||
| 209 | |||
| 210 | }; | ||
| 211 | |||
| 212 | |||
| 213 | struct reg_protocol_wt { | ||
| 214 | |||
| 215 | |||
| 216 | #ifdef __LITTLE_ENDIAN | ||
| 217 | |||
| 218 | /* DW1 */ | ||
| 219 | u32 NumOfTrans:4; | ||
| 220 | u32 Reserved1:4; | ||
| 221 | u32 Reserved2:24; | ||
| 222 | /* DW2 */ | ||
| 223 | u32 ByteCount:7; | ||
| 224 | u32 WriteEnable:1; /* 0:read, 1:write */ | ||
| 225 | u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */ | ||
| 226 | u32 BurstMode:1; | ||
| 227 | u32 Byte1Access:1; | ||
| 228 | u32 Byte2Access:1; | ||
| 229 | u32 Byte4Access:1; | ||
| 230 | u32 Reserved3:3; | ||
| 231 | u32 Reserved4:16; | ||
| 232 | /* DW3 */ | ||
| 233 | u32 BusAddress; | ||
| 234 | /* DW4 */ | ||
| 235 | u32 Value; | ||
| 236 | |||
| 237 | #else | ||
| 238 | /* DW1 */ | ||
| 239 | u32 Reserved1 :4; | ||
| 240 | u32 NumOfTrans :4; | ||
| 241 | |||
| 242 | u32 Reserved2 :24; | ||
| 243 | |||
| 244 | /* DW2 */ | ||
| 245 | u32 WriteEnable : 1; | ||
| 246 | u32 ByteCount :7; | ||
| 247 | |||
| 248 | u32 Reserved3 : 3; | ||
| 249 | u32 Byte4Access : 1; | ||
| 250 | |||
| 251 | u32 Byte2Access : 1; | ||
| 252 | u32 Byte1Access : 1; | ||
| 253 | u32 BurstMode :1 ; | ||
| 254 | u32 FixOrContinuous : 1; | ||
| 255 | |||
| 256 | u32 Reserved4 : 16; | ||
| 257 | |||
| 258 | /* DW3 */ | ||
| 259 | u32 BusAddress; | ||
| 260 | |||
| 261 | /* DW4 */ | ||
| 262 | u32 Value; | ||
| 263 | |||
| 264 | #endif | ||
| 265 | |||
| 266 | }; | ||
| 267 | |||
| 268 | |||
| 269 | |||
| 270 | /* | ||
| 271 | Below is the data structure used by _io_handler | ||
| 272 | |||
| 273 | */ | ||
| 274 | |||
| 275 | struct io_queue { | ||
| 276 | spinlock_t lock; | ||
| 277 | struct list_head free_ioreqs; | ||
| 278 | struct list_head pending; /* The io_req list that will be served in the single protocol read/write. */ | ||
| 279 | struct list_head processing; | ||
| 280 | u8 *free_ioreqs_buf; /* 4-byte aligned */ | ||
| 281 | u8 *pallocated_free_ioreqs_buf; | ||
| 282 | struct intf_hdl intf; | ||
| 283 | }; | ||
| 284 | |||
| 285 | struct io_priv{ | ||
| 286 | |||
| 287 | struct rtw_adapter *padapter; | ||
| 288 | |||
| 289 | struct intf_hdl intf; | ||
| 290 | |||
| 291 | }; | ||
| 292 | |||
| 293 | uint ioreq_flush(struct rtw_adapter *adapter, struct io_queue *ioqueue); | ||
| 294 | void sync_ioreq_enqueue(struct io_req *preq,struct io_queue *ioqueue); | ||
| 295 | uint sync_ioreq_flush(struct rtw_adapter *adapter, struct io_queue *ioqueue); | ||
| 296 | |||
| 297 | uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue); | ||
| 298 | struct io_req *alloc_ioreq(struct io_queue *pio_q); | ||
| 299 | |||
| 300 | uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl); | ||
| 301 | void unregister_intf_hdl(struct intf_hdl *pintfhdl); | ||
| 302 | |||
| 303 | void _rtw_attrib_read(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); | ||
| 304 | void _rtw_attrib_write(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); | ||
| 305 | |||
| 306 | u8 _rtw_read823a(struct rtw_adapter *adapter, u32 addr); | ||
| 307 | u16 _rtw_read1623a(struct rtw_adapter *adapter, u32 addr); | ||
| 308 | u32 _rtw_read3223a(struct rtw_adapter *adapter, u32 addr); | ||
| 309 | void _rtw_read_mem23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); | ||
| 310 | void _rtw_read_port23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, struct recv_buf *rbuf); | ||
| 311 | void _rtw_read_port23a_cancel(struct rtw_adapter *adapter); | ||
| 312 | |||
| 313 | int _rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val); | ||
| 314 | int _rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val); | ||
| 315 | int _rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val); | ||
| 316 | int _rtw_writeN23a(struct rtw_adapter *adapter, u32 addr, u32 length, u8 *pdata); | ||
| 317 | |||
| 318 | int _rtw_write823a_async23a(struct rtw_adapter *adapter, u32 addr, u8 val); | ||
| 319 | int _rtw_write1623a_async(struct rtw_adapter *adapter, u32 addr, u16 val); | ||
| 320 | int _rtw_write3223a_async23a(struct rtw_adapter *adapter, u32 addr, u32 val); | ||
| 321 | |||
| 322 | void _rtw_write_mem23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); | ||
| 323 | u32 _rtw_write_port23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, struct xmit_buf *pmem); | ||
| 324 | u32 _rtw_write_port23a_and_wait23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, struct xmit_buf *pmem, int timeout_ms); | ||
| 325 | void _rtw_write_port23a_cancel(struct rtw_adapter *adapter); | ||
| 326 | |||
| 327 | #ifdef DBG_IO | ||
| 328 | bool match_read_sniff_ranges(u16 addr, u16 len); | ||
| 329 | bool match_write_sniff_ranges(u16 addr, u16 len); | ||
| 330 | |||
| 331 | u8 dbg_rtw_read823a(struct rtw_adapter *adapter, u32 addr, const char *caller, const int line); | ||
| 332 | u16 dbg_rtw_read1623a(struct rtw_adapter *adapter, u32 addr, const char *caller, const int line); | ||
| 333 | u32 dbg_rtw_read3223a(struct rtw_adapter *adapter, u32 addr, const char *caller, const int line); | ||
| 334 | |||
| 335 | int dbg_rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); | ||
| 336 | int dbg_rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); | ||
| 337 | int dbg_rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); | ||
| 338 | int dbg_rtw_writeN23a(struct rtw_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line); | ||
| 339 | |||
| 340 | #define rtw_read8(adapter, addr) dbg_rtw_read823a((adapter), (addr), __FUNCTION__, __LINE__) | ||
| 341 | #define rtw_read16(adapter, addr) dbg_rtw_read1623a((adapter), (addr), __FUNCTION__, __LINE__) | ||
| 342 | #define rtw_read32(adapter, addr) dbg_rtw_read3223a((adapter), (addr), __FUNCTION__, __LINE__) | ||
| 343 | #define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem23a((adapter), (addr), (cnt), (mem)) | ||
| 344 | #define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port23a((adapter), (addr), (cnt), (mem)) | ||
| 345 | #define rtw_read_port_cancel(adapter) _rtw_read_port23a_cancel((adapter)) | ||
| 346 | |||
| 347 | #define rtw_write8(adapter, addr, val) dbg_rtw_write823a((adapter), (addr), (val), __FUNCTION__, __LINE__) | ||
| 348 | #define rtw_write16(adapter, addr, val) dbg_rtw_write1623a((adapter), (addr), (val), __FUNCTION__, __LINE__) | ||
| 349 | #define rtw_write32(adapter, addr, val) dbg_rtw_write3223a((adapter), (addr), (val), __FUNCTION__, __LINE__) | ||
| 350 | #define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN23a((adapter), (addr), (length), (data), __FUNCTION__, __LINE__) | ||
| 351 | |||
| 352 | #define rtw_write8_async(adapter, addr, val) _rtw_write823a_async23a((adapter), (addr), (val)) | ||
| 353 | #define rtw_write16_async(adapter, addr, val) _rtw_write1623a_async((adapter), (addr), (val)) | ||
| 354 | #define rtw_write32_async(adapter, addr, val) _rtw_write3223a_async23a((adapter), (addr), (val)) | ||
| 355 | |||
| 356 | #define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem23a((adapter), addr, cnt, mem) | ||
| 357 | #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port23a(adapter, addr, cnt, mem) | ||
| 358 | #define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port23a_and_wait23a((adapter), (addr), (cnt), (mem), (timeout_ms)) | ||
| 359 | #define rtw_write_port_cancel(adapter) _rtw_write_port23a_cancel(adapter) | ||
| 360 | #else /* DBG_IO */ | ||
| 361 | #define rtw_read8(adapter, addr) _rtw_read823a((adapter), (addr)) | ||
| 362 | #define rtw_read16(adapter, addr) _rtw_read1623a((adapter), (addr)) | ||
| 363 | #define rtw_read32(adapter, addr) _rtw_read3223a((adapter), (addr)) | ||
| 364 | #define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem23a((adapter), (addr), (cnt), (mem)) | ||
| 365 | #define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port23a((adapter), (addr), (cnt), (mem)) | ||
| 366 | #define rtw_read_port_cancel(adapter) _rtw_read_port23a_cancel((adapter)) | ||
| 367 | |||
| 368 | #define rtw_write8(adapter, addr, val) _rtw_write823a((adapter), (addr), (val)) | ||
| 369 | #define rtw_write16(adapter, addr, val) _rtw_write1623a((adapter), (addr), (val)) | ||
| 370 | #define rtw_write32(adapter, addr, val) _rtw_write3223a((adapter), (addr), (val)) | ||
| 371 | #define rtw_writeN(adapter, addr, length, data) _rtw_writeN23a((adapter), (addr), (length), (data)) | ||
| 372 | |||
| 373 | #define rtw_write8_async(adapter, addr, val) _rtw_write823a_async23a((adapter), (addr), (val)) | ||
| 374 | #define rtw_write16_async(adapter, addr, val) _rtw_write1623a_async((adapter), (addr), (val)) | ||
| 375 | #define rtw_write32_async(adapter, addr, val) _rtw_write3223a_async23a((adapter), (addr), (val)) | ||
| 376 | |||
| 377 | #define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem23a((adapter), (addr), (cnt), (mem)) | ||
| 378 | #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port23a((adapter), (addr), (cnt), (mem)) | ||
| 379 | #define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port23a_and_wait23a((adapter), (addr), (cnt), (mem), (timeout_ms)) | ||
| 380 | #define rtw_write_port_cancel(adapter) _rtw_write_port23a_cancel((adapter)) | ||
| 381 | #endif /* DBG_IO */ | ||
| 382 | |||
| 383 | void rtw_write_scsi(struct rtw_adapter *adapter, u32 cnt, u8 *pmem); | ||
| 384 | |||
| 385 | /* ioreq */ | ||
| 386 | void ioreq_read8(struct rtw_adapter *adapter, u32 addr, u8 *pval); | ||
| 387 | void ioreq_read16(struct rtw_adapter *adapter, u32 addr, u16 *pval); | ||
| 388 | void ioreq_read32(struct rtw_adapter *adapter, u32 addr, u32 *pval); | ||
| 389 | void ioreq_write8(struct rtw_adapter *adapter, u32 addr, u8 val); | ||
| 390 | void ioreq_write16(struct rtw_adapter *adapter, u32 addr, u16 val); | ||
| 391 | void ioreq_write32(struct rtw_adapter *adapter, u32 addr, u32 val); | ||
| 392 | |||
| 393 | int rtw_init_io_priv23a(struct rtw_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops)); | ||
| 394 | |||
| 395 | uint alloc_io_queue(struct rtw_adapter *adapter); | ||
| 396 | void free_io_queue(struct rtw_adapter *adapter); | ||
| 397 | void async_bus_io(struct io_queue *pio_q); | ||
| 398 | void bus_sync_io(struct io_queue *pio_q); | ||
| 399 | u32 _ioreq2rwmem(struct io_queue *pio_q); | ||
| 400 | void dev_power_down(struct rtw_adapter * Adapter, u8 bpwrup); | ||
| 401 | |||
| 402 | #define PlatformEFIOWrite1Byte(_a,_b,_c) \ | ||
| 403 | rtw_write8(_a,_b,_c) | ||
| 404 | #define PlatformEFIOWrite2Byte(_a,_b,_c) \ | ||
| 405 | rtw_write16(_a,_b,_c) | ||
| 406 | #define PlatformEFIOWrite4Byte(_a,_b,_c) \ | ||
| 407 | rtw_write32(_a,_b,_c) | ||
| 408 | |||
| 409 | #define PlatformEFIORead1Byte(_a,_b) \ | ||
| 410 | rtw_read8(_a,_b) | ||
| 411 | #define PlatformEFIORead2Byte(_a,_b) \ | ||
| 412 | rtw_read16(_a,_b) | ||
| 413 | #define PlatformEFIORead4Byte(_a,_b) \ | ||
| 414 | rtw_read32(_a,_b) | ||
| 415 | |||
| 416 | #endif /* _RTL8711_IO_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_ioctl.h b/drivers/staging/rtl8723au/include/rtw_ioctl.h new file mode 100644 index 000000000000..629eec8a7023 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_ioctl.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _RTW_IOCTL_H_ | ||
| 16 | #define _RTW_IOCTL_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | |||
| 22 | #if defined(CONFIG_WIRELESS_EXT) | ||
| 23 | extern struct iw_handler_def rtw_handlers_def; | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #endif /* #ifndef __INC_CEINFO_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_ioctl_set.h b/drivers/staging/rtl8723au/include/rtw_ioctl_set.h new file mode 100644 index 000000000000..18ad2a873350 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_ioctl_set.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_IOCTL_SET_H_ | ||
| 16 | #define __RTW_IOCTL_SET_H_ | ||
| 17 | |||
| 18 | #include <drv_types.h> | ||
| 19 | |||
| 20 | |||
| 21 | struct bssid_info { | ||
| 22 | unsigned char BSSID[6]; | ||
| 23 | u8 PMKID[16]; | ||
| 24 | }; | ||
| 25 | |||
| 26 | u8 rtw_set_802_11_authentication_mode23a(struct rtw_adapter *pdapter, | ||
| 27 | enum ndis_802_11_auth_mode authmode); | ||
| 28 | u8 rtw_set_802_11_add_wep23a(struct rtw_adapter * padapter, | ||
| 29 | struct ndis_802_11_wep *wep); | ||
| 30 | u8 rtw_set_802_11_bssid23a_list_scan(struct rtw_adapter *padapter, | ||
| 31 | struct cfg80211_ssid *pssid, int ssid_max_num); | ||
| 32 | u8 rtw_set_802_11_infrastructure_mode23a(struct rtw_adapter *padapter, | ||
| 33 | enum ndis_802_11_net_infra networktype); | ||
| 34 | u8 rtw_set_802_11_ssid23a(struct rtw_adapter * padapter, struct cfg80211_ssid * ssid); | ||
| 35 | |||
| 36 | u16 rtw_get_cur_max_rate23a(struct rtw_adapter *adapter); | ||
| 37 | s32 FillH2CCmd(struct rtw_adapter *padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_led.h b/drivers/staging/rtl8723au/include/rtw_led.h new file mode 100644 index 000000000000..c071da587efd --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_led.h | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_LED_H_ | ||
| 16 | #define __RTW_LED_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | #define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) | ||
| 22 | |||
| 23 | #define LED_BLINK_NORMAL_INTERVAL 100 | ||
| 24 | #define LED_BLINK_SLOWLY_INTERVAL 200 | ||
| 25 | #define LED_BLINK_LONG_INTERVAL 400 | ||
| 26 | |||
| 27 | #define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 | ||
| 28 | #define LED_BLINK_LINK_INTERVAL_ALPHA 500 /* 500 */ | ||
| 29 | #define LED_BLINK_SCAN_INTERVAL_ALPHA 180 /* 150 */ | ||
| 30 | #define LED_BLINK_FASTER_INTERVAL_ALPHA 50 | ||
| 31 | #define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 | ||
| 32 | |||
| 33 | #define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100 | ||
| 34 | #define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000 | ||
| 35 | |||
| 36 | #define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000 | ||
| 37 | #define LED_BLINK_NORMAL_INTERVAL_PORNET 100 | ||
| 38 | |||
| 39 | #define LED_BLINK_FAST_INTERVAL_BITLAND 30 | ||
| 40 | |||
| 41 | /* 060403, rcnjko: Customized for AzWave. */ | ||
| 42 | #define LED_CM2_BLINK_ON_INTERVAL 250 | ||
| 43 | #define LED_CM2_BLINK_OFF_INTERVAL 4750 | ||
| 44 | |||
| 45 | #define LED_CM8_BLINK_INTERVAL 500 /* for QMI */ | ||
| 46 | #define LED_CM8_BLINK_OFF_INTERVAL 3750 /* for QMI */ | ||
| 47 | |||
| 48 | /* 080124, lanhsin: Customized for RunTop */ | ||
| 49 | #define LED_RunTop_BLINK_INTERVAL 300 | ||
| 50 | |||
| 51 | /* 060421, rcnjko: Customized for Sercomm Printer Server case. */ | ||
| 52 | #define LED_CM3_BLINK_INTERVAL 1500 | ||
| 53 | |||
| 54 | enum led_ctl_mode { | ||
| 55 | LED_CTL_POWER_ON = 1, | ||
| 56 | LED_CTL_LINK = 2, | ||
| 57 | LED_CTL_NO_LINK = 3, | ||
| 58 | LED_CTL_TX = 4, | ||
| 59 | LED_CTL_RX = 5, | ||
| 60 | LED_CTL_SITE_SURVEY = 6, | ||
| 61 | LED_CTL_POWER_OFF = 7, | ||
| 62 | LED_CTL_START_TO_LINK = 8, | ||
| 63 | LED_CTL_START_WPS = 9, | ||
| 64 | LED_CTL_STOP_WPS = 10, | ||
| 65 | LED_CTL_START_WPS_BOTTON = 11, /* added for runtop */ | ||
| 66 | LED_CTL_STOP_WPS_FAIL = 12, /* added for ALPHA */ | ||
| 67 | LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, /* added for BELKIN */ | ||
| 68 | LED_CTL_CONNECTION_NO_TRANSFER = 14, | ||
| 69 | }; | ||
| 70 | |||
| 71 | enum led_state_872x { | ||
| 72 | LED_UNKNOWN = 0, | ||
| 73 | RTW_LED_ON = 1, | ||
| 74 | RTW_LED_OFF = 2, | ||
| 75 | LED_BLINK_NORMAL = 3, | ||
| 76 | LED_BLINK_SLOWLY = 4, | ||
| 77 | LED_BLINK_POWER_ON = 5, | ||
| 78 | LED_BLINK_SCAN = 6, /* LED is blinking during scanning period, the # of times to blink is depend on time for scanning. */ | ||
| 79 | LED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */ | ||
| 80 | LED_BLINK_StartToBlink = 8,/* Customzied for Sercomm Printer Server case */ | ||
| 81 | LED_BLINK_TXRX = 9, | ||
| 82 | LED_BLINK_WPS = 10, /* LED is blinkg during WPS communication */ | ||
| 83 | LED_BLINK_WPS_STOP = 11, /* for ALPHA */ | ||
| 84 | LED_BLINK_WPS_STOP_OVERLAP = 12, /* for BELKIN */ | ||
| 85 | LED_BLINK_RUNTOP = 13, /* Customized for RunTop */ | ||
| 86 | LED_BLINK_CAMEO = 14, | ||
| 87 | LED_BLINK_XAVI = 15, | ||
| 88 | LED_BLINK_ALWAYS_ON = 16, | ||
| 89 | }; | ||
| 90 | |||
| 91 | enum led_pin_8723a { | ||
| 92 | LED_PIN_NULL = 0, | ||
| 93 | LED_PIN_LED0 = 1, | ||
| 94 | LED_PIN_LED1 = 2, | ||
| 95 | LED_PIN_LED2 = 3, | ||
| 96 | LED_PIN_GPIO0 = 4, | ||
| 97 | }; | ||
| 98 | |||
| 99 | struct led_8723a { | ||
| 100 | struct rtw_adapter *padapter; | ||
| 101 | |||
| 102 | enum led_pin_8723a LedPin; /* Identify how to implement this SW led. */ | ||
| 103 | enum led_state_872x CurrLedState; /* Current LED state. */ | ||
| 104 | enum led_state_872x BlinkingLedState; /* Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. */ | ||
| 105 | |||
| 106 | u8 bLedOn; /* true if LED is ON, false if LED is OFF. */ | ||
| 107 | |||
| 108 | u8 bLedBlinkInProgress; /* true if it is blinking, false o.w.. */ | ||
| 109 | |||
| 110 | u8 bLedWPSBlinkInProgress; | ||
| 111 | |||
| 112 | u32 BlinkTimes; /* Number of times to toggle led state for blinking. */ | ||
| 113 | |||
| 114 | struct timer_list BlinkTimer; /* Timer object for led blinking. */ | ||
| 115 | |||
| 116 | u8 bSWLedCtrl; | ||
| 117 | |||
| 118 | /* ALPHA, added by chiyoko, 20090106 */ | ||
| 119 | u8 bLedNoLinkBlinkInProgress; | ||
| 120 | u8 bLedLinkBlinkInProgress; | ||
| 121 | u8 bLedStartToLinkBlinkInProgress; | ||
| 122 | u8 bLedScanBlinkInProgress; | ||
| 123 | |||
| 124 | struct work_struct BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED. */ | ||
| 125 | }; | ||
| 126 | |||
| 127 | #define IS_LED_WPS_BLINKING(_LED_871x) (((struct led_8723a *)_LED_871x)->CurrLedState==LED_BLINK_WPS \ | ||
| 128 | || ((struct led_8723a *)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \ | ||
| 129 | || ((struct led_8723a *)_LED_871x)->bLedWPSBlinkInProgress) | ||
| 130 | |||
| 131 | #define IS_LED_BLINKING(_LED_871x) (((struct led_8723a *)_LED_871x)->bLedWPSBlinkInProgress \ | ||
| 132 | ||((struct led_8723a *)_LED_871x)->bLedScanBlinkInProgress) | ||
| 133 | |||
| 134 | /* */ | ||
| 135 | /* LED customization. */ | ||
| 136 | /* */ | ||
| 137 | |||
| 138 | enum led_strategy_8723a { | ||
| 139 | SW_LED_MODE0 = 0, /* SW control 1 LED via GPIO0. It is default option. */ | ||
| 140 | SW_LED_MODE1= 1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */ | ||
| 141 | SW_LED_MODE2 = 2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */ | ||
| 142 | SW_LED_MODE3 = 3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */ | ||
| 143 | SW_LED_MODE4 = 4, /* for Edimax / Belkin */ | ||
| 144 | SW_LED_MODE5 = 5, /* for Sercomm / Belkin */ | ||
| 145 | SW_LED_MODE6 = 6, /* for 88CU minicard, porting from ce SW_LED_MODE7 */ | ||
| 146 | HW_LED = 50, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) */ | ||
| 147 | LED_ST_NONE = 99, | ||
| 148 | }; | ||
| 149 | |||
| 150 | void LedControl871x23a(struct rtw_adapter *padapter, enum led_ctl_mode LedAction); | ||
| 151 | |||
| 152 | struct led_priv{ | ||
| 153 | /* add for led controll */ | ||
| 154 | struct led_8723a SwLed0; | ||
| 155 | struct led_8723a SwLed1; | ||
| 156 | enum led_strategy_8723a LedStrategy; | ||
| 157 | u8 bRegUseLed; | ||
| 158 | void (*LedControlHandler)(struct rtw_adapter *padapter, enum led_ctl_mode LedAction); | ||
| 159 | /* add for led controll */ | ||
| 160 | }; | ||
| 161 | |||
| 162 | #define rtw_led_control(adapter, LedAction) | ||
| 163 | |||
| 164 | void BlinkWorkItemCallback23a(struct work_struct *work); | ||
| 165 | |||
| 166 | void ResetLedStatus23a(struct led_8723a *pLed); | ||
| 167 | |||
| 168 | void | ||
| 169 | InitLed871x23a( | ||
| 170 | struct rtw_adapter *padapter, | ||
| 171 | struct led_8723a *pLed, | ||
| 172 | enum led_pin_8723a LedPin | ||
| 173 | ); | ||
| 174 | |||
| 175 | void | ||
| 176 | DeInitLed871x23a(struct led_8723a *pLed); | ||
| 177 | |||
| 178 | /* hal... */ | ||
| 179 | void BlinkHandler23a(struct led_8723a *pLed); | ||
| 180 | |||
| 181 | #endif /* __RTW_LED_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_mlme.h b/drivers/staging/rtl8723au/include/rtw_mlme.h new file mode 100644 index 000000000000..adbea44d601f --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_mlme.h | |||
| @@ -0,0 +1,632 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * | ||
| 15 | ******************************************************************************/ | ||
| 16 | #ifndef __RTW_MLME_H_ | ||
| 17 | #define __RTW_MLME_H_ | ||
| 18 | |||
| 19 | #include <osdep_service.h> | ||
| 20 | #include <mlme_osdep.h> | ||
| 21 | #include <drv_types.h> | ||
| 22 | #include <wlan_bssdef.h> | ||
| 23 | |||
| 24 | #define MAX_BSS_CNT 128 | ||
| 25 | #define MAX_JOIN_TIMEOUT 6500 | ||
| 26 | |||
| 27 | /* Increase the scanning timeout because of increasing the SURVEY_TO value. */ | ||
| 28 | |||
| 29 | #define SCANNING_TIMEOUT 8000 | ||
| 30 | |||
| 31 | #define SCAN_INTERVAL (30) /* unit:2sec, 30*2 = 60sec */ | ||
| 32 | |||
| 33 | #define SCANQUEUE_LIFETIME 20 /* unit:sec */ | ||
| 34 | |||
| 35 | #define WIFI_NULL_STATE 0x00000000 | ||
| 36 | |||
| 37 | #define WIFI_ASOC_STATE 0x00000001 /* Under Linked state.*/ | ||
| 38 | #define WIFI_REASOC_STATE 0x00000002 | ||
| 39 | #define WIFI_SLEEP_STATE 0x00000004 | ||
| 40 | #define WIFI_STATION_STATE 0x00000008 | ||
| 41 | |||
| 42 | #define WIFI_AP_STATE 0x00000010 | ||
| 43 | #define WIFI_ADHOC_STATE 0x00000020 | ||
| 44 | #define WIFI_ADHOC_MASTER_STATE 0x00000040 | ||
| 45 | #define WIFI_UNDER_LINKING 0x00000080 | ||
| 46 | |||
| 47 | #define WIFI_UNDER_WPS 0x00000100 | ||
| 48 | #define WIFI_STA_ALIVE_CHK_STATE 0x00000400 | ||
| 49 | /* to indicate the station is under site surveying */ | ||
| 50 | #define WIFI_SITE_MONITOR 0x00000800 | ||
| 51 | |||
| 52 | #define WIFI_MP_STATE 0x00010000 | ||
| 53 | #define WIFI_MP_CTX_BACKGROUND 0x00020000 /* in continous tx background */ | ||
| 54 | #define WIFI_MP_CTX_ST 0x00040000 /* in continous tx with single-tone */ | ||
| 55 | #define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 /* pending in continous tx background due to out of skb */ | ||
| 56 | #define WIFI_MP_CTX_CCK_HW 0x00100000 /* in continous tx */ | ||
| 57 | #define WIFI_MP_CTX_CCK_CS 0x00200000 /* in continous tx with carrier suppression */ | ||
| 58 | #define WIFI_MP_LPBK_STATE 0x00400000 | ||
| 59 | |||
| 60 | #define _FW_UNDER_LINKING WIFI_UNDER_LINKING | ||
| 61 | #define _FW_LINKED WIFI_ASOC_STATE | ||
| 62 | #define _FW_UNDER_SURVEY WIFI_SITE_MONITOR | ||
| 63 | |||
| 64 | |||
| 65 | enum dot11AuthAlgrthmNum { | ||
| 66 | dot11AuthAlgrthm_Open = 0, | ||
| 67 | dot11AuthAlgrthm_Shared, | ||
| 68 | dot11AuthAlgrthm_8021X, | ||
| 69 | dot11AuthAlgrthm_Auto, | ||
| 70 | dot11AuthAlgrthm_MaxNum | ||
| 71 | }; | ||
| 72 | |||
| 73 | /* Scan type including active and passive scan. */ | ||
| 74 | enum rt_scan_type { | ||
| 75 | SCAN_PASSIVE, | ||
| 76 | SCAN_ACTIVE, | ||
| 77 | SCAN_MIX, | ||
| 78 | }; | ||
| 79 | |||
| 80 | enum { | ||
| 81 | GHZ24_50 = 0, | ||
| 82 | GHZ_50, | ||
| 83 | GHZ_24, | ||
| 84 | }; | ||
| 85 | |||
| 86 | enum SCAN_RESULT_TYPE { | ||
| 87 | SCAN_RESULT_P2P_ONLY = 0, /* Will return all the P2P devices. */ | ||
| 88 | SCAN_RESULT_ALL = 1, /* Will return all the scanned device, include AP. */ | ||
| 89 | SCAN_RESULT_WFD_TYPE = 2 /* Will just return the correct WFD device. */ | ||
| 90 | /* If this device is Miracast sink device, it will just return all the Miracast source devices. */ | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* | ||
| 94 | |||
| 95 | there are several "locks" in mlme_priv, | ||
| 96 | since mlme_priv is a shared resource between many threads, | ||
| 97 | like ISR/Call-Back functions, the OID handlers, and even timer functions. | ||
| 98 | |||
| 99 | |||
| 100 | Each _queue has its own locks, already. | ||
| 101 | Other items are protected by mlme_priv.lock. | ||
| 102 | |||
| 103 | To avoid possible dead lock, any thread trying to modifiying mlme_priv | ||
| 104 | SHALL not lock up more than one locks at a time! | ||
| 105 | */ | ||
| 106 | |||
| 107 | #define traffic_threshold 10 | ||
| 108 | #define traffic_scan_period 500 | ||
| 109 | |||
| 110 | struct sitesurvey_ctrl { | ||
| 111 | u64 last_tx_pkts; | ||
| 112 | uint last_rx_pkts; | ||
| 113 | int traffic_busy; | ||
| 114 | struct timer_list sitesurvey_ctrl_timer; | ||
| 115 | }; | ||
| 116 | |||
| 117 | struct rt_link_detect { | ||
| 118 | u32 NumTxOkInPeriod; | ||
| 119 | u32 NumRxOkInPeriod; | ||
| 120 | u32 NumRxUnicastOkInPeriod; | ||
| 121 | bool bBusyTraffic; | ||
| 122 | bool bTxBusyTraffic; | ||
| 123 | bool bRxBusyTraffic; | ||
| 124 | bool bHigherBusyTraffic; /* For interrupt migration purpose. */ | ||
| 125 | bool bHigherBusyRxTraffic; /* We may disable Tx interrupt according as Rx traffic. */ | ||
| 126 | bool bHigherBusyTxTraffic; /* We may disable Tx interrupt according as Tx traffic. */ | ||
| 127 | }; | ||
| 128 | |||
| 129 | struct profile_info { | ||
| 130 | u8 ssidlen; | ||
| 131 | u8 ssid[IEEE80211_MAX_SSID_LEN]; | ||
| 132 | u8 peermac[ETH_ALEN]; | ||
| 133 | }; | ||
| 134 | |||
| 135 | struct tx_invite_req_info { | ||
| 136 | u8 token; | ||
| 137 | u8 benable; | ||
| 138 | u8 go_ssid[IEEE80211_MAX_SSID_LEN]; | ||
| 139 | u8 ssidlen; | ||
| 140 | u8 go_bssid[ETH_ALEN]; | ||
| 141 | u8 peer_macaddr[ETH_ALEN]; | ||
| 142 | u8 operating_ch; /* This information will be set by using the p2p_set op_ch = x */ | ||
| 143 | u8 peer_ch; /* The listen channel for peer P2P device */ | ||
| 144 | |||
| 145 | }; | ||
| 146 | |||
| 147 | struct tx_invite_resp_info { | ||
| 148 | u8 token; /* Used to record the dialog token of p2p invitation request frame. */ | ||
| 149 | }; | ||
| 150 | |||
| 151 | #ifdef CONFIG_8723AU_P2P | ||
| 152 | |||
| 153 | struct wifi_display_info { | ||
| 154 | u16 wfd_enable; /* Enable/Disable the WFD function. */ | ||
| 155 | u16 rtsp_ctrlport; /* TCP port number at which the this WFD device listens for RTSP messages */ | ||
| 156 | u16 peer_rtsp_ctrlport; /* TCP port number at which the peer WFD device listens for RTSP messages */ | ||
| 157 | /* This filed should be filled when receiving the gropu negotiation request */ | ||
| 158 | |||
| 159 | u8 peer_session_avail; /* WFD session is available or not for the peer wfd device. */ | ||
| 160 | /* This variable will be set when sending the provisioning discovery request to peer WFD device. */ | ||
| 161 | /* And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */ | ||
| 162 | u8 ip_address[4]; | ||
| 163 | u8 peer_ip_address[4]; | ||
| 164 | u8 wfd_pc; /* WFD preferred connection */ | ||
| 165 | /* 0 -> Prefer to use the P2P for WFD connection on peer side. */ | ||
| 166 | /* 1 -> Prefer to use the TDLS for WFD connection on peer side. */ | ||
| 167 | |||
| 168 | u8 wfd_device_type;/* WFD Device Type */ | ||
| 169 | /* 0 -> WFD Source Device */ | ||
| 170 | /* 1 -> WFD Primary Sink Device */ | ||
| 171 | enum SCAN_RESULT_TYPE scan_result_type; /* Used when P2P is enable. This parameter will impact the scan result. */ | ||
| 172 | }; | ||
| 173 | #endif /* CONFIG_8723AU_P2P */ | ||
| 174 | |||
| 175 | struct tx_provdisc_req_info { | ||
| 176 | u16 wps_config_method_request; /* Used when sending the provisioning request frame */ | ||
| 177 | u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ | ||
| 178 | struct cfg80211_ssid ssid; | ||
| 179 | u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ | ||
| 180 | u8 peerIFAddr[ETH_ALEN]; /* Peer interface address */ | ||
| 181 | u8 benable; /* This provision discovery request frame is trigger to send or not */ | ||
| 182 | }; | ||
| 183 | |||
| 184 | struct rx_provdisc_req_info { /* When peer device issue prov_disc_req first, we should store the following informations */ | ||
| 185 | u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ | ||
| 186 | u8 strconfig_method_desc_of_prov_disc_req[4]; /* description for the config method located in the provisioning discovery request frame. */ | ||
| 187 | /* The UI must know this information to know which config method the remote p2p device is requiring. */ | ||
| 188 | }; | ||
| 189 | |||
| 190 | struct tx_nego_req_info { | ||
| 191 | u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ | ||
| 192 | u8 peerDevAddr[ETH_ALEN];/* Peer device address */ | ||
| 193 | u8 benable; /* This negoitation request frame is trigger to send or not */ | ||
| 194 | }; | ||
| 195 | |||
| 196 | struct group_id_info { | ||
| 197 | u8 go_device_addr[ETH_ALEN]; /*The GO's device address of P2P group */ | ||
| 198 | u8 ssid[IEEE80211_MAX_SSID_LEN]; /* The SSID of this P2P group */ | ||
| 199 | }; | ||
| 200 | |||
| 201 | struct scan_limit_info { | ||
| 202 | u8 scan_op_ch_only; /* When this flag is set, the driver should just scan the operation channel */ | ||
| 203 | u8 operation_ch[2]; /* Store the operation channel of invitation request frame */ | ||
| 204 | }; | ||
| 205 | |||
| 206 | struct cfg80211_wifidirect_info { | ||
| 207 | struct timer_list remain_on_ch_timer; | ||
| 208 | u8 restore_channel; | ||
| 209 | struct ieee80211_channel remain_on_ch_channel; | ||
| 210 | enum nl80211_channel_type remain_on_ch_type; | ||
| 211 | u64 remain_on_ch_cookie; | ||
| 212 | bool is_ro_ch; | ||
| 213 | }; | ||
| 214 | |||
| 215 | struct wifidirect_info { | ||
| 216 | struct rtw_adapter *padapter; | ||
| 217 | struct timer_list find_phase_timer; | ||
| 218 | struct timer_list restore_p2p_state_timer; | ||
| 219 | |||
| 220 | /* Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */ | ||
| 221 | struct timer_list pre_tx_scan_timer; | ||
| 222 | struct timer_list reset_ch_sitesurvey; | ||
| 223 | struct timer_list reset_ch_sitesurvey2; /* Just for resetting the scan limit function by using p2p nego */ | ||
| 224 | struct tx_provdisc_req_info tx_prov_disc_info; | ||
| 225 | struct rx_provdisc_req_info rx_prov_disc_info; | ||
| 226 | struct tx_invite_req_info invitereq_info; | ||
| 227 | struct profile_info profileinfo[P2P_MAX_PERSISTENT_GROUP_NUM]; /* Store the profile information of persistent group */ | ||
| 228 | struct tx_invite_resp_info inviteresp_info; | ||
| 229 | struct tx_nego_req_info nego_req_info; | ||
| 230 | struct group_id_info groupid_info; /* Store the group id information when doing the group negotiation handshake. */ | ||
| 231 | struct scan_limit_info rx_invitereq_info; /* Used for get the limit scan channel from the Invitation procedure */ | ||
| 232 | struct scan_limit_info p2p_info; /* Used for get the limit scan channel from the P2P negotiation handshake */ | ||
| 233 | #ifdef CONFIG_8723AU_P2P | ||
| 234 | struct wifi_display_info *wfd_info; | ||
| 235 | #endif | ||
| 236 | enum P2P_ROLE role; | ||
| 237 | enum P2P_STATE pre_p2p_state; | ||
| 238 | enum P2P_STATE p2p_state; | ||
| 239 | u8 device_addr[ETH_ALEN]; /* The device address should be the mac address of this device. */ | ||
| 240 | u8 interface_addr[ETH_ALEN]; | ||
| 241 | u8 social_chan[4]; | ||
| 242 | u8 listen_channel; | ||
| 243 | u8 operating_channel; | ||
| 244 | u8 listen_dwell; /* This value should be between 1 and 3 */ | ||
| 245 | u8 support_rate[8]; | ||
| 246 | u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; | ||
| 247 | u8 intent; /* should only include the intent value. */ | ||
| 248 | u8 p2p_peer_interface_addr[ETH_ALEN]; | ||
| 249 | u8 p2p_peer_device_addr[ETH_ALEN]; | ||
| 250 | u8 peer_intent; /* Included the intent value and tie breaker value. */ | ||
| 251 | u8 device_name[WPS_MAX_DEVICE_NAME_LEN]; /* Device name for displaying on searching device screen */ | ||
| 252 | u8 device_name_len; | ||
| 253 | u8 profileindex; /* Used to point to the index of profileinfo array */ | ||
| 254 | u8 peer_operating_ch; | ||
| 255 | u8 find_phase_state_exchange_cnt; | ||
| 256 | u16 device_password_id_for_nego; /* The device password ID for group negotation */ | ||
| 257 | u8 negotiation_dialog_token; | ||
| 258 | /* SSID information for group negotitation */ | ||
| 259 | u8 nego_ssid[IEEE80211_MAX_SSID_LEN]; | ||
| 260 | u8 nego_ssidlen; | ||
| 261 | u8 p2p_group_ssid[IEEE80211_MAX_SSID_LEN]; | ||
| 262 | u8 p2p_group_ssid_len; | ||
| 263 | u8 persistent_supported; /* Flag to know the persistent function should be supported or not. */ | ||
| 264 | /* In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */ | ||
| 265 | /* 0: disable */ | ||
| 266 | /* 1: enable */ | ||
| 267 | u8 session_available; /* Flag to set the WFD session available to enable or disable "by Sigma" */ | ||
| 268 | /* In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */ | ||
| 269 | /* 0: disable */ | ||
| 270 | /* 1: enable */ | ||
| 271 | |||
| 272 | u8 wfd_tdls_enable; /* Flag to enable or disable the TDLS by WFD Sigma */ | ||
| 273 | /* 0: disable */ | ||
| 274 | /* 1: enable */ | ||
| 275 | u8 wfd_tdls_weaksec; /* Flag to enable or disable the weak security function for TDLS by WFD Sigma */ | ||
| 276 | /* 0: disable */ | ||
| 277 | /* In this case, the driver can't issue the tdsl setup request frame. */ | ||
| 278 | /* 1: enable */ | ||
| 279 | /* In this case, the driver can issue the tdls setup request frame */ | ||
| 280 | /* even the current security is weak security. */ | ||
| 281 | |||
| 282 | enum P2P_WPSINFO ui_got_wps_info; /* This field will store the WPS value (PIN value or PBC) that UI had got from the user. */ | ||
| 283 | u16 supported_wps_cm; /* This field describes the WPS config method which this driver supported. */ | ||
| 284 | /* The value should be the combination of config method defined in page104 of WPS v2.0 spec. */ | ||
| 285 | uint channel_list_attr_len; /* This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */ | ||
| 286 | u8 channel_list_attr[100]; /* This field will contain the body of P2P Channel List attribute of group negotitation response frame. */ | ||
| 287 | /* We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */ | ||
| 288 | #ifdef CONFIG_8723AU_P2P | ||
| 289 | enum P2P_PS_MODE p2p_ps_mode; /* indicate p2p ps mode */ | ||
| 290 | enum P2P_PS_STATE p2p_ps_state; /* indicate p2p ps state */ | ||
| 291 | u8 noa_index; /* Identifies and instance of Notice of Absence timing. */ | ||
| 292 | u8 ctwindow; /* Client traffic window. A period of time in TU after TBTT. */ | ||
| 293 | u8 opp_ps; /* opportunistic power save. */ | ||
| 294 | u8 noa_num; /* number of NoA descriptor in P2P IE. */ | ||
| 295 | u8 noa_count[P2P_MAX_NOA_NUM]; /* Count for owner, Type of client. */ | ||
| 296 | u32 noa_duration[P2P_MAX_NOA_NUM]; /* Max duration for owner, preferred or min acceptable duration for client. */ | ||
| 297 | u32 noa_interval[P2P_MAX_NOA_NUM]; /* Length of interval for owner, preferred or max acceptable interval of client. */ | ||
| 298 | u32 noa_start_time[P2P_MAX_NOA_NUM]; /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */ | ||
| 299 | #endif /* CONFIG_8723AU_P2P */ | ||
| 300 | }; | ||
| 301 | |||
| 302 | struct tdls_ss_record { /* signal strength record */ | ||
| 303 | u8 macaddr[ETH_ALEN]; | ||
| 304 | u8 RxPWDBAll; | ||
| 305 | u8 is_tdls_sta; /* true: direct link sta, false: else */ | ||
| 306 | }; | ||
| 307 | |||
| 308 | struct tdls_info { | ||
| 309 | u8 ap_prohibited; | ||
| 310 | uint setup_state; | ||
| 311 | u8 sta_cnt; | ||
| 312 | /* 1:tdls sta == (NUM_STA-1), reach max direct link no; 0: else; */ | ||
| 313 | u8 sta_maximum; | ||
| 314 | struct tdls_ss_record ss_record; | ||
| 315 | u8 macid_index; /* macid entry that is ready to write */ | ||
| 316 | /* cam entry that is trying to clear, using it in direct link teardown*/ | ||
| 317 | u8 clear_cam; | ||
| 318 | u8 ch_sensing; | ||
| 319 | u8 cur_channel; | ||
| 320 | u8 candidate_ch; | ||
| 321 | u8 collect_pkt_num[MAX_CHANNEL_NUM]; | ||
| 322 | spinlock_t cmd_lock; | ||
| 323 | spinlock_t hdl_lock; | ||
| 324 | u8 watchdog_count; | ||
| 325 | u8 dev_discovered; /* WFD_TDLS: for sigma test */ | ||
| 326 | u8 enable; | ||
| 327 | #ifdef CONFIG_8723AU_P2P | ||
| 328 | struct wifi_display_info *wfd_info; | ||
| 329 | #endif | ||
| 330 | }; | ||
| 331 | |||
| 332 | struct mlme_priv { | ||
| 333 | spinlock_t lock; | ||
| 334 | int fw_state; | ||
| 335 | u8 bScanInProcess; | ||
| 336 | u8 to_join; /* flag */ | ||
| 337 | u8 to_roaming; /* roaming trying times */ | ||
| 338 | |||
| 339 | struct rtw_adapter *nic_hdl; | ||
| 340 | |||
| 341 | u8 not_indic_disco; | ||
| 342 | struct rtw_queue scanned_queue; | ||
| 343 | |||
| 344 | struct cfg80211_ssid assoc_ssid; | ||
| 345 | u8 assoc_bssid[6]; | ||
| 346 | |||
| 347 | struct wlan_network cur_network; | ||
| 348 | |||
| 349 | /* uint wireless_mode; no used, remove it */ | ||
| 350 | |||
| 351 | u32 scan_interval; | ||
| 352 | |||
| 353 | struct timer_list assoc_timer; | ||
| 354 | |||
| 355 | uint assoc_by_bssid; | ||
| 356 | uint assoc_by_rssi; | ||
| 357 | |||
| 358 | struct timer_list scan_to_timer; | ||
| 359 | |||
| 360 | struct timer_list set_scan_deny_timer; | ||
| 361 | atomic_t set_scan_deny; /* 0: allowed, 1: deny */ | ||
| 362 | |||
| 363 | struct qos_priv qospriv; | ||
| 364 | |||
| 365 | /* Number of non-HT AP/stations */ | ||
| 366 | int num_sta_no_ht; | ||
| 367 | |||
| 368 | int num_FortyMHzIntolerant; | ||
| 369 | |||
| 370 | struct ht_priv htpriv; | ||
| 371 | |||
| 372 | struct rt_link_detect LinkDetectInfo; | ||
| 373 | struct timer_list dynamic_chk_timer; /* dynamic/periodic check timer */ | ||
| 374 | |||
| 375 | u8 key_mask; /* use for ips to set wep key after ips_leave23a */ | ||
| 376 | u8 acm_mask; /* for wmm acm mask */ | ||
| 377 | u8 ChannelPlan; | ||
| 378 | enum rt_scan_type scan_mode; /* active: 1, passive: 0 */ | ||
| 379 | |||
| 380 | u8 *wps_probe_req_ie; | ||
| 381 | u32 wps_probe_req_ie_len; | ||
| 382 | |||
| 383 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 384 | /* Number of associated Non-ERP stations (i.e., stations using 802.11b | ||
| 385 | * in 802.11g BSS) */ | ||
| 386 | int num_sta_non_erp; | ||
| 387 | |||
| 388 | /* Number of associated stations that do not support Short Slot Time */ | ||
| 389 | int num_sta_no_short_slot_time; | ||
| 390 | |||
| 391 | /* Number of associated stations that do not support Short Preamble */ | ||
| 392 | int num_sta_no_short_preamble; | ||
| 393 | |||
| 394 | int olbc; /* Overlapping Legacy BSS Condition */ | ||
| 395 | |||
| 396 | /* Number of HT associated stations that do not support greenfield */ | ||
| 397 | int num_sta_ht_no_gf; | ||
| 398 | |||
| 399 | /* Number of associated non-HT stations */ | ||
| 400 | /* int num_sta_no_ht; */ | ||
| 401 | |||
| 402 | /* Number of HT associated stations 20 MHz */ | ||
| 403 | int num_sta_ht_20mhz; | ||
| 404 | |||
| 405 | /* Overlapping BSS information */ | ||
| 406 | int olbc_ht; | ||
| 407 | |||
| 408 | u16 ht_op_mode; | ||
| 409 | |||
| 410 | u8 *assoc_req; | ||
| 411 | u32 assoc_req_len; | ||
| 412 | u8 *assoc_rsp; | ||
| 413 | u32 assoc_rsp_len; | ||
| 414 | |||
| 415 | u8 *wps_beacon_ie; | ||
| 416 | /* u8 *wps_probe_req_ie; */ | ||
| 417 | u8 *wps_probe_resp_ie; | ||
| 418 | u8 *wps_assoc_resp_ie; | ||
| 419 | |||
| 420 | u32 wps_beacon_ie_len; | ||
| 421 | /* u32 wps_probe_req_ie_len; */ | ||
| 422 | u32 wps_probe_resp_ie_len; | ||
| 423 | u32 wps_assoc_resp_ie_len; | ||
| 424 | |||
| 425 | u8 *p2p_beacon_ie; | ||
| 426 | u8 *p2p_probe_req_ie; | ||
| 427 | u8 *p2p_probe_resp_ie; | ||
| 428 | u8 *p2p_go_probe_resp_ie; /* for GO */ | ||
| 429 | u8 *p2p_assoc_req_ie; | ||
| 430 | |||
| 431 | u32 p2p_beacon_ie_len; | ||
| 432 | u32 p2p_probe_req_ie_len; | ||
| 433 | u32 p2p_probe_resp_ie_len; | ||
| 434 | u32 p2p_go_probe_resp_ie_len; /* for GO */ | ||
| 435 | u32 p2p_assoc_req_ie_len; | ||
| 436 | spinlock_t bcn_update_lock; | ||
| 437 | u8 update_bcn; | ||
| 438 | |||
| 439 | #endif /* ifdef CONFIG_8723AU_AP_MODE */ | ||
| 440 | |||
| 441 | #if defined(CONFIG_8723AU_P2P) | ||
| 442 | u8 *wfd_beacon_ie; | ||
| 443 | u8 *wfd_probe_req_ie; | ||
| 444 | u8 *wfd_probe_resp_ie; | ||
| 445 | u8 *wfd_go_probe_resp_ie; /* for GO */ | ||
| 446 | u8 *wfd_assoc_req_ie; | ||
| 447 | |||
| 448 | u32 wfd_beacon_ie_len; | ||
| 449 | u32 wfd_probe_req_ie_len; | ||
| 450 | u32 wfd_probe_resp_ie_len; | ||
| 451 | u32 wfd_go_probe_resp_ie_len; /* for GO */ | ||
| 452 | u32 wfd_assoc_req_ie_len; | ||
| 453 | #endif | ||
| 454 | }; | ||
| 455 | |||
| 456 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 457 | |||
| 458 | struct hostapd_priv { | ||
| 459 | struct rtw_adapter *padapter; | ||
| 460 | }; | ||
| 461 | |||
| 462 | int hostapd_mode_init(struct rtw_adapter *padapter); | ||
| 463 | void hostapd_mode_unload(struct rtw_adapter *padapter); | ||
| 464 | #endif | ||
| 465 | |||
| 466 | void rtw_joinbss_event_prehandle23a(struct rtw_adapter *adapter, u8 *pbuf); | ||
| 467 | void rtw_survey_event_cb23a(struct rtw_adapter *adapter, u8 *pbuf); | ||
| 468 | void rtw_surveydone_event_callback23a(struct rtw_adapter *adapter, u8 *pbuf); | ||
| 469 | void rtw23a_joinbss_event_cb(struct rtw_adapter *adapter, u8 *pbuf); | ||
| 470 | void rtw_stassoc_event_callback23a(struct rtw_adapter *adapter, u8 *pbuf); | ||
| 471 | void rtw_stadel_event_callback23a(struct rtw_adapter *adapter, u8 *pbuf); | ||
| 472 | void rtw_atimdone_event_callback23a(struct rtw_adapter *adapter, u8 *pbuf); | ||
| 473 | void rtw_cpwm_event_callback23a(struct rtw_adapter *adapter, u8 *pbuf); | ||
| 474 | |||
| 475 | |||
| 476 | int event_thread(void *context); | ||
| 477 | void rtw23a_join_to_handler(unsigned long); | ||
| 478 | |||
| 479 | void rtw_free_network_queue23a(struct rtw_adapter *adapter, u8 isfreeall); | ||
| 480 | int rtw_init_mlme_priv23a(struct rtw_adapter *adapter); | ||
| 481 | |||
| 482 | void rtw_free_mlme_priv23a(struct mlme_priv *pmlmepriv); | ||
| 483 | |||
| 484 | int rtw_select_and_join_from_scanned_queue23a(struct mlme_priv *pmlmepriv); | ||
| 485 | int rtw_set_key23a(struct rtw_adapter *adapter, | ||
| 486 | struct security_priv *psecuritypriv, int keyid, u8 set_tx); | ||
| 487 | int rtw_set_auth23a(struct rtw_adapter *adapter, | ||
| 488 | struct security_priv *psecuritypriv); | ||
| 489 | |||
| 490 | static inline u8 *get_bssid(struct mlme_priv *pmlmepriv) | ||
| 491 | { /* if sta_mode:pmlmepriv->cur_network.network.MacAddress => bssid */ | ||
| 492 | /* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress => ibss mac address */ | ||
| 493 | return pmlmepriv->cur_network.network.MacAddress; | ||
| 494 | } | ||
| 495 | |||
| 496 | static inline int check_fwstate(struct mlme_priv *pmlmepriv, int state) | ||
| 497 | { | ||
| 498 | if (pmlmepriv->fw_state & state) | ||
| 499 | return true; | ||
| 500 | |||
| 501 | return false; | ||
| 502 | } | ||
| 503 | |||
| 504 | static inline int get_fwstate(struct mlme_priv *pmlmepriv) | ||
| 505 | { | ||
| 506 | return pmlmepriv->fw_state; | ||
| 507 | } | ||
| 508 | |||
| 509 | /* | ||
| 510 | * No Limit on the calling context, | ||
| 511 | * therefore set it to be the critical section... | ||
| 512 | * | ||
| 513 | * ### NOTE:#### (!!!!) | ||
| 514 | * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock | ||
| 515 | */ | ||
| 516 | static inline void set_fwstate(struct mlme_priv *pmlmepriv, int state) | ||
| 517 | { | ||
| 518 | pmlmepriv->fw_state |= state; | ||
| 519 | /* FOR HW integration */ | ||
| 520 | if (_FW_UNDER_SURVEY == state) | ||
| 521 | pmlmepriv->bScanInProcess = true; | ||
| 522 | } | ||
| 523 | |||
| 524 | static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, int state) | ||
| 525 | { | ||
| 526 | pmlmepriv->fw_state &= ~state; | ||
| 527 | /* FOR HW integration */ | ||
| 528 | if (_FW_UNDER_SURVEY == state) | ||
| 529 | pmlmepriv->bScanInProcess = false; | ||
| 530 | } | ||
| 531 | |||
| 532 | /* | ||
| 533 | * No Limit on the calling context, | ||
| 534 | * therefore set it to be the critical section... | ||
| 535 | */ | ||
| 536 | static inline void clr_fwstate(struct mlme_priv *pmlmepriv, int state) | ||
| 537 | { | ||
| 538 | spin_lock_bh(&pmlmepriv->lock); | ||
| 539 | if (check_fwstate(pmlmepriv, state) == true) | ||
| 540 | pmlmepriv->fw_state ^= state; | ||
| 541 | spin_unlock_bh(&pmlmepriv->lock); | ||
| 542 | } | ||
| 543 | |||
| 544 | static inline void clr_fwstate_ex(struct mlme_priv *pmlmepriv, int state) | ||
| 545 | { | ||
| 546 | spin_lock_bh(&pmlmepriv->lock); | ||
| 547 | _clr_fwstate_(pmlmepriv, state); | ||
| 548 | spin_unlock_bh(&pmlmepriv->lock); | ||
| 549 | } | ||
| 550 | |||
| 551 | u16 rtw_get_capability23a(struct wlan_bssid_ex *bss); | ||
| 552 | void rtw_update_scanned_network23a(struct rtw_adapter *adapter, | ||
| 553 | struct wlan_bssid_ex *target); | ||
| 554 | void rtw_disconnect_hdl23a_under_linked(struct rtw_adapter *adapter, | ||
| 555 | struct sta_info *psta, u8 free_assoc); | ||
| 556 | void rtw_generate_random_ibss23a(u8 *pibss); | ||
| 557 | struct wlan_network *rtw_find_network23a(struct rtw_queue *scanned_queue, u8 *addr); | ||
| 558 | struct wlan_network *rtw_get_oldest_wlan_network23a(struct rtw_queue *scanned_queue); | ||
| 559 | |||
| 560 | void rtw_free_assoc_resources23a(struct rtw_adapter *adapter, | ||
| 561 | int lock_scanned_queue); | ||
| 562 | void rtw_indicate_disconnect23a(struct rtw_adapter *adapter); | ||
| 563 | void rtw_indicate_connect23a(struct rtw_adapter *adapter); | ||
| 564 | void rtw_indicate_scan_done23a(struct rtw_adapter *padapter, bool aborted); | ||
| 565 | void rtw_scan_abort23a(struct rtw_adapter *adapter); | ||
| 566 | |||
| 567 | int rtw_restruct_sec_ie23a(struct rtw_adapter *adapter, u8 *in_ie, u8 *out_ie, | ||
| 568 | uint in_len); | ||
| 569 | int rtw_restruct_wmm_ie23a(struct rtw_adapter *adapter, u8 *in_ie, u8 *out_ie, | ||
| 570 | uint in_len, uint initial_out_len); | ||
| 571 | void rtw_init_registrypriv_dev_network23a(struct rtw_adapter *adapter); | ||
| 572 | |||
| 573 | void rtw_update_registrypriv_dev_network23a(struct rtw_adapter *adapter); | ||
| 574 | |||
| 575 | void rtw_get_encrypt_decrypt_from_registrypriv23a(struct rtw_adapter *adapter); | ||
| 576 | |||
| 577 | void rtw_scan_timeout_handler23a(unsigned long data); | ||
| 578 | |||
| 579 | void rtw_dynamic_check_timer_handler(unsigned long data); | ||
| 580 | bool rtw_is_scan_deny(struct rtw_adapter *adapter); | ||
| 581 | void rtw_clear_scan_deny(struct rtw_adapter *adapter); | ||
| 582 | void rtw_set_scan_deny_timer_hdl(unsigned long data); | ||
| 583 | void rtw_set_scan_deny(struct rtw_adapter *adapter, u32 ms); | ||
| 584 | |||
| 585 | int _rtw_init_mlme_priv23a(struct rtw_adapter *padapter); | ||
| 586 | |||
| 587 | void rtw23a_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); | ||
| 588 | |||
| 589 | void _rtw_free_mlme_priv23a(struct mlme_priv *pmlmepriv); | ||
| 590 | |||
| 591 | struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv); | ||
| 592 | |||
| 593 | void _rtw_free_network23a(struct mlme_priv *pmlmepriv, | ||
| 594 | struct wlan_network *pnetwork, u8 isfreeall); | ||
| 595 | void _rtw_free_network23a_nolock23a(struct mlme_priv *pmlmepriv, | ||
| 596 | struct wlan_network *pnetwork); | ||
| 597 | |||
| 598 | struct wlan_network *_rtw_find_network23a(struct rtw_queue *scanned_queue, u8 *addr); | ||
| 599 | |||
| 600 | void _rtw_free_network23a_queue23a(struct rtw_adapter *padapter, u8 isfreeall); | ||
| 601 | |||
| 602 | int rtw_if_up23a(struct rtw_adapter *padapter); | ||
| 603 | |||
| 604 | int rtw_linked_check(struct rtw_adapter *padapter); | ||
| 605 | |||
| 606 | u8 *rtw_get_capability23a_from_ie(u8 *ie); | ||
| 607 | u8 *rtw_get_timestampe_from_ie23a(u8 *ie); | ||
| 608 | u8 *rtw_get_beacon_interval23a_from_ie(u8 *ie); | ||
| 609 | |||
| 610 | |||
| 611 | void rtw_joinbss_reset23a(struct rtw_adapter *padapter); | ||
| 612 | |||
| 613 | unsigned int rtw_restructure_ht_ie23a(struct rtw_adapter *padapter, u8 *in_ie, | ||
| 614 | u8 *out_ie, uint in_len, uint *pout_len); | ||
| 615 | void rtw_update_ht_cap23a(struct rtw_adapter *padapter, | ||
| 616 | u8 *pie, uint ie_len); | ||
| 617 | void rtw_issue_addbareq_cmd23a(struct rtw_adapter *padapter, | ||
| 618 | struct xmit_frame *pxmitframe); | ||
| 619 | |||
| 620 | int rtw_is_same_ibss23a(struct rtw_adapter *adapter, | ||
| 621 | struct wlan_network *pnetwork); | ||
| 622 | int is_same_network23a(struct wlan_bssid_ex *src, struct wlan_bssid_ex *dst); | ||
| 623 | |||
| 624 | void _rtw23a_roaming(struct rtw_adapter *adapter, | ||
| 625 | struct wlan_network *tgt_network); | ||
| 626 | void rtw23a_roaming(struct rtw_adapter *adapter, | ||
| 627 | struct wlan_network *tgt_network); | ||
| 628 | void rtw_set_roaming(struct rtw_adapter *adapter, u8 to_roaming); | ||
| 629 | u8 rtw_to_roaming(struct rtw_adapter *adapter); | ||
| 630 | void rtw_stassoc_hw_rpt23a(struct rtw_adapter *adapter, struct sta_info *psta); | ||
| 631 | |||
| 632 | #endif /* __RTL871X_MLME_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_mlme_ext.h b/drivers/staging/rtl8723au/include/rtw_mlme_ext.h new file mode 100644 index 000000000000..d1c2d71295e5 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_mlme_ext.h | |||
| @@ -0,0 +1,782 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_MLME_EXT_H_ | ||
| 16 | #define __RTW_MLME_EXT_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | #include <wlan_bssdef.h> | ||
| 21 | |||
| 22 | |||
| 23 | /* Commented by Albert 20101105 */ | ||
| 24 | /* Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) */ | ||
| 25 | /* The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. */ | ||
| 26 | /* So, this driver tried to extend the dwell time for each scanning channel. */ | ||
| 27 | /* This will increase the chance to receive the probe response from SoftAP. */ | ||
| 28 | |||
| 29 | #define SURVEY_TO (100) | ||
| 30 | #define REAUTH_TO (300) /* 50) */ | ||
| 31 | #define REASSOC_TO (300) /* 50) */ | ||
| 32 | /* define DISCONNECT_TO (3000) */ | ||
| 33 | #define ADDBA_TO (2000) | ||
| 34 | |||
| 35 | #define LINKED_TO (1) /* unit:2 sec, 1x2=2 sec */ | ||
| 36 | |||
| 37 | #define REAUTH_LIMIT (4) | ||
| 38 | #define REASSOC_LIMIT (4) | ||
| 39 | #define READDBA_LIMIT (2) | ||
| 40 | |||
| 41 | #define ROAMING_LIMIT 8 | ||
| 42 | |||
| 43 | #define DYNAMIC_FUNC_DISABLE (0x0) | ||
| 44 | |||
| 45 | /* ====== enum odm_ability ======== */ | ||
| 46 | /* BB ODM section BIT 0-15 */ | ||
| 47 | #define DYNAMIC_BB_DIG BIT(0) | ||
| 48 | #define DYNAMIC_BB_RA_MASK BIT(1) | ||
| 49 | #define DYNAMIC_BB_DYNAMIC_TXPWR BIT(2) | ||
| 50 | #define DYNAMIC_BB_BB_FA_CNT BIT(3) | ||
| 51 | |||
| 52 | #define DYNAMIC_BB_RSSI_MONITOR BIT(4) | ||
| 53 | #define DYNAMIC_BB_CCK_PD BIT(5) | ||
| 54 | #define DYNAMIC_BB_ANT_DIV BIT(6) | ||
| 55 | #define DYNAMIC_BB_PWR_SAVE BIT(7) | ||
| 56 | #define DYNAMIC_BB_PWR_TRAIN BIT(8) | ||
| 57 | #define DYNAMIC_BB_RATE_ADAPTIVE BIT(9) | ||
| 58 | #define DYNAMIC_BB_PATH_DIV BIT(10) | ||
| 59 | #define DYNAMIC_BB_PSD BIT(11) | ||
| 60 | |||
| 61 | /* MAC DM section BIT 16-23 */ | ||
| 62 | #define DYNAMIC_MAC_struct edca_turboURBO BIT(16) | ||
| 63 | #define DYNAMIC_MAC_EARLY_MODE BIT(17) | ||
| 64 | |||
| 65 | /* RF ODM section BIT 24-31 */ | ||
| 66 | #define DYNAMIC_RF_TX_PWR_TRACK BIT(24) | ||
| 67 | #define DYNAMIC_RF_RX_GAIN_TRACK BIT(25) | ||
| 68 | #define DYNAMIC_RF_CALIBRATION BIT(26) | ||
| 69 | |||
| 70 | #define DYNAMIC_ALL_FUNC_ENABLE 0xFFFFFFF | ||
| 71 | |||
| 72 | #define _HW_STATE_NOLINK_ 0x00 | ||
| 73 | #define _HW_STATE_ADHOC_ 0x01 | ||
| 74 | #define _HW_STATE_STATION_ 0x02 | ||
| 75 | #define _HW_STATE_AP_ 0x03 | ||
| 76 | |||
| 77 | |||
| 78 | #define _1M_RATE_ 0 | ||
| 79 | #define _2M_RATE_ 1 | ||
| 80 | #define _5M_RATE_ 2 | ||
| 81 | #define _11M_RATE_ 3 | ||
| 82 | #define _6M_RATE_ 4 | ||
| 83 | #define _9M_RATE_ 5 | ||
| 84 | #define _12M_RATE_ 6 | ||
| 85 | #define _18M_RATE_ 7 | ||
| 86 | #define _24M_RATE_ 8 | ||
| 87 | #define _36M_RATE_ 9 | ||
| 88 | #define _48M_RATE_ 10 | ||
| 89 | #define _54M_RATE_ 11 | ||
| 90 | |||
| 91 | |||
| 92 | extern unsigned char RTW_WPA_OUI23A[]; | ||
| 93 | extern unsigned char WMM_OUI23A[]; | ||
| 94 | extern unsigned char WPS_OUI23A[]; | ||
| 95 | extern unsigned char WFD_OUI23A[]; | ||
| 96 | extern unsigned char P2P_OUI23A[]; | ||
| 97 | |||
| 98 | extern unsigned char WMM_INFO_OUI23A[]; | ||
| 99 | extern unsigned char WMM_PARA_OUI23A[]; | ||
| 100 | |||
| 101 | |||
| 102 | /* */ | ||
| 103 | /* Channel Plan Type. */ | ||
| 104 | /* Note: */ | ||
| 105 | /* We just add new channel plan when the new channel plan is different from any of the following */ | ||
| 106 | /* channel plan. */ | ||
| 107 | /* If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan, */ | ||
| 108 | /* customize them in struct rt_channel_info in the RT_CHANNEL_LIST. */ | ||
| 109 | /* */ | ||
| 110 | enum { /* _RT_CHANNEL_DOMAIN */ | ||
| 111 | /* old channel plan mapping ===== */ | ||
| 112 | RT_CHANNEL_DOMAIN_FCC = 0x00, | ||
| 113 | RT_CHANNEL_DOMAIN_IC = 0x01, | ||
| 114 | RT_CHANNEL_DOMAIN_ETSI = 0x02, | ||
| 115 | RT_CHANNEL_DOMAIN_SPAIN = 0x03, | ||
| 116 | RT_CHANNEL_DOMAIN_FRANCE = 0x04, | ||
| 117 | RT_CHANNEL_DOMAIN_MKK = 0x05, | ||
| 118 | RT_CHANNEL_DOMAIN_MKK1 = 0x06, | ||
| 119 | RT_CHANNEL_DOMAIN_ISRAEL = 0x07, | ||
| 120 | RT_CHANNEL_DOMAIN_TELEC = 0x08, | ||
| 121 | RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x09, | ||
| 122 | RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0x0A, | ||
| 123 | RT_CHANNEL_DOMAIN_TAIWAN = 0x0B, | ||
| 124 | RT_CHANNEL_DOMAIN_CHINA = 0x0C, | ||
| 125 | RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0x0D, | ||
| 126 | RT_CHANNEL_DOMAIN_KOREA = 0x0E, | ||
| 127 | RT_CHANNEL_DOMAIN_TURKEY = 0x0F, | ||
| 128 | RT_CHANNEL_DOMAIN_JAPAN = 0x10, | ||
| 129 | RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11, | ||
| 130 | RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12, | ||
| 131 | RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13, | ||
| 132 | RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14, | ||
| 133 | |||
| 134 | /* new channel plan mapping, (2GDOMAIN_5GDOMAIN) ===== */ | ||
| 135 | RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20, | ||
| 136 | RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21, | ||
| 137 | RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22, | ||
| 138 | RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23, | ||
| 139 | RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24, | ||
| 140 | RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25, | ||
| 141 | RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26, | ||
| 142 | RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27, | ||
| 143 | RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28, | ||
| 144 | RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29, | ||
| 145 | RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30, | ||
| 146 | RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31, | ||
| 147 | RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32, | ||
| 148 | RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33, | ||
| 149 | RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34, | ||
| 150 | RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35, | ||
| 151 | RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36, | ||
| 152 | RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37, | ||
| 153 | RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38, | ||
| 154 | RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39, | ||
| 155 | RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40, | ||
| 156 | RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN_2G = 0x41, | ||
| 157 | /* Add new channel plan above this line=============== */ | ||
| 158 | RT_CHANNEL_DOMAIN_MAX, | ||
| 159 | RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F, | ||
| 160 | }; | ||
| 161 | |||
| 162 | enum { /* _RT_CHANNEL_DOMAIN_2G */ | ||
| 163 | RT_CHANNEL_DOMAIN_2G_WORLD = 0x00, /* Worldwird 13 */ | ||
| 164 | RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, /* Europe */ | ||
| 165 | RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, /* US */ | ||
| 166 | RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, /* Japan */ | ||
| 167 | RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, /* France */ | ||
| 168 | RT_CHANNEL_DOMAIN_2G_NULL = 0x05, | ||
| 169 | /* Add new channel plan above this line=============== */ | ||
| 170 | RT_CHANNEL_DOMAIN_2G_MAX, | ||
| 171 | }; | ||
| 172 | |||
| 173 | enum { /* _RT_CHANNEL_DOMAIN_5G */ | ||
| 174 | RT_CHANNEL_DOMAIN_5G_NULL = 0x00, | ||
| 175 | RT_CHANNEL_DOMAIN_5G_ETSI1 = 0x01, /* Europe */ | ||
| 176 | RT_CHANNEL_DOMAIN_5G_ETSI2 = 0x02, /* Australia, New Zealand */ | ||
| 177 | RT_CHANNEL_DOMAIN_5G_ETSI3 = 0x03, /* Russia */ | ||
| 178 | RT_CHANNEL_DOMAIN_5G_FCC1 = 0x04, /* US */ | ||
| 179 | RT_CHANNEL_DOMAIN_5G_FCC2 = 0x05, /* FCC o/w DFS Channels */ | ||
| 180 | RT_CHANNEL_DOMAIN_5G_FCC3 = 0x06, /* India, Mexico */ | ||
| 181 | RT_CHANNEL_DOMAIN_5G_FCC4 = 0x07, /* Venezuela */ | ||
| 182 | RT_CHANNEL_DOMAIN_5G_FCC5 = 0x08, /* China */ | ||
| 183 | RT_CHANNEL_DOMAIN_5G_FCC6 = 0x09, /* Israel */ | ||
| 184 | RT_CHANNEL_DOMAIN_5G_FCC7_IC1 = 0x0A, /* US, Canada */ | ||
| 185 | RT_CHANNEL_DOMAIN_5G_KCC1 = 0x0B, /* Korea */ | ||
| 186 | RT_CHANNEL_DOMAIN_5G_MKK1 = 0x0C, /* Japan */ | ||
| 187 | RT_CHANNEL_DOMAIN_5G_MKK2 = 0x0D, /* Japan (W52, W53) */ | ||
| 188 | RT_CHANNEL_DOMAIN_5G_MKK3 = 0x0E, /* Japan (W56) */ | ||
| 189 | RT_CHANNEL_DOMAIN_5G_NCC1 = 0x0F, /* Taiwan */ | ||
| 190 | RT_CHANNEL_DOMAIN_5G_NCC2 = 0x10, /* Taiwan o/w DFS */ | ||
| 191 | /* Add new channel plan above this line=============== */ | ||
| 192 | /* Driver Self Defined ===== */ | ||
| 193 | RT_CHANNEL_DOMAIN_5G_FCC = 0x11, | ||
| 194 | RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS = 0x12, | ||
| 195 | RT_CHANNEL_DOMAIN_5G_FCC4_NO_DFS = 0x13, | ||
| 196 | RT_CHANNEL_DOMAIN_5G_MAX, | ||
| 197 | }; | ||
| 198 | |||
| 199 | #define rtw_is_channel_plan_valid(chplan) (chplan<RT_CHANNEL_DOMAIN_MAX || chplan == RT_CHANNEL_DOMAIN_REALTEK_DEFINE) | ||
| 200 | |||
| 201 | struct rt_channel_plan { | ||
| 202 | unsigned char Channel[MAX_CHANNEL_NUM]; | ||
| 203 | unsigned char Len; | ||
| 204 | }; | ||
| 205 | |||
| 206 | struct rt_channel_plan_2g { | ||
| 207 | unsigned char Channel[MAX_CHANNEL_NUM_2G]; | ||
| 208 | unsigned char Len; | ||
| 209 | }; | ||
| 210 | |||
| 211 | struct rt_channel_plan_5g { | ||
| 212 | unsigned char Channel[MAX_CHANNEL_NUM_5G]; | ||
| 213 | unsigned char Len; | ||
| 214 | }; | ||
| 215 | |||
| 216 | struct rt_channel_plan_map { | ||
| 217 | unsigned char Index2G; | ||
| 218 | unsigned char Index5G; | ||
| 219 | }; | ||
| 220 | |||
| 221 | enum Associated_AP { | ||
| 222 | atherosAP = 0, | ||
| 223 | broadcomAP = 1, | ||
| 224 | ciscoAP = 2, | ||
| 225 | marvellAP = 3, | ||
| 226 | ralinkAP = 4, | ||
| 227 | realtekAP = 5, | ||
| 228 | airgocapAP = 6, | ||
| 229 | unknownAP = 7, | ||
| 230 | maxAP, | ||
| 231 | }; | ||
| 232 | |||
| 233 | enum { /* HT_IOT_PEER_E */ | ||
| 234 | HT_IOT_PEER_UNKNOWN = 0, | ||
| 235 | HT_IOT_PEER_REALTEK = 1, | ||
| 236 | HT_IOT_PEER_REALTEK_92SE = 2, | ||
| 237 | HT_IOT_PEER_BROADCOM = 3, | ||
| 238 | HT_IOT_PEER_RALINK = 4, | ||
| 239 | HT_IOT_PEER_ATHEROS = 5, | ||
| 240 | HT_IOT_PEER_CISCO = 6, | ||
| 241 | HT_IOT_PEER_MERU = 7, | ||
| 242 | HT_IOT_PEER_MARVELL = 8, | ||
| 243 | HT_IOT_PEER_REALTEK_SOFTAP = 9,/* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */ | ||
| 244 | HT_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */ | ||
| 245 | HT_IOT_PEER_AIRGO = 11, | ||
| 246 | HT_IOT_PEER_INTEL = 12, | ||
| 247 | HT_IOT_PEER_RTK_APCLIENT = 13, | ||
| 248 | HT_IOT_PEER_REALTEK_81XX = 14, | ||
| 249 | HT_IOT_PEER_REALTEK_WOW = 15, | ||
| 250 | HT_IOT_PEER_TENDA = 16, | ||
| 251 | HT_IOT_PEER_MAX = 17 | ||
| 252 | }; | ||
| 253 | |||
| 254 | enum SCAN_STATE { | ||
| 255 | SCAN_DISABLE = 0, | ||
| 256 | SCAN_START = 1, | ||
| 257 | SCAN_TXNULL = 2, | ||
| 258 | SCAN_PROCESS = 3, | ||
| 259 | SCAN_COMPLETE = 4, | ||
| 260 | SCAN_STATE_MAX, | ||
| 261 | }; | ||
| 262 | |||
| 263 | struct mlme_handler { | ||
| 264 | char *str; | ||
| 265 | unsigned int (*func)(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 266 | }; | ||
| 267 | |||
| 268 | struct action_handler { | ||
| 269 | unsigned int num; | ||
| 270 | char* str; | ||
| 271 | unsigned int (*func)(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 272 | }; | ||
| 273 | |||
| 274 | struct ss_res | ||
| 275 | { | ||
| 276 | int state; | ||
| 277 | int bss_cnt; | ||
| 278 | int channel_idx; | ||
| 279 | int scan_mode; | ||
| 280 | u8 ssid_num; | ||
| 281 | u8 ch_num; | ||
| 282 | struct cfg80211_ssid ssid[RTW_SSID_SCAN_AMOUNT]; | ||
| 283 | struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; | ||
| 284 | }; | ||
| 285 | |||
| 286 | /* define AP_MODE 0x0C */ | ||
| 287 | /* define STATION_MODE 0x08 */ | ||
| 288 | /* define AD_HOC_MODE 0x04 */ | ||
| 289 | /* define NO_LINK_MODE 0x00 */ | ||
| 290 | |||
| 291 | #define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_ | ||
| 292 | #define WIFI_FW_STATION_STATE _HW_STATE_STATION_ | ||
| 293 | #define WIFI_FW_AP_STATE _HW_STATE_AP_ | ||
| 294 | #define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_ | ||
| 295 | |||
| 296 | #define WIFI_FW_AUTH_NULL 0x00000100 | ||
| 297 | #define WIFI_FW_AUTH_STATE 0x00000200 | ||
| 298 | #define WIFI_FW_AUTH_SUCCESS 0x00000400 | ||
| 299 | |||
| 300 | #define WIFI_FW_ASSOC_STATE 0x00002000 | ||
| 301 | #define WIFI_FW_ASSOC_SUCCESS 0x00004000 | ||
| 302 | |||
| 303 | #define WIFI_FW_LINKING_STATE (WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE | WIFI_FW_AUTH_SUCCESS |WIFI_FW_ASSOC_STATE) | ||
| 304 | |||
| 305 | struct FW_Sta_Info { | ||
| 306 | struct sta_info *psta; | ||
| 307 | u32 status; | ||
| 308 | u32 rx_pkt; | ||
| 309 | u32 retry; | ||
| 310 | unsigned char SupportedRates[NDIS_802_11_LENGTH_RATES_EX]; | ||
| 311 | }; | ||
| 312 | |||
| 313 | /* | ||
| 314 | * Usage: | ||
| 315 | * When one iface acted as AP mode and the other iface is STA mode and scanning, | ||
| 316 | * it should switch back to AP's operating channel periodically. | ||
| 317 | * Parameters info: | ||
| 318 | * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for | ||
| 319 | * RTW_STAY_AP_CH_MILLISECOND * SURVEY_TO milliseconds. | ||
| 320 | * Example: | ||
| 321 | * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1, | ||
| 322 | * RTW_SCAN_NUM_OF_CH is 8, RTW_STAY_AP_CH_MILLISECOND is 3 and SURVEY_TO is 100. | ||
| 323 | * When it's STA mode gets set_scan command, | ||
| 324 | * it would | ||
| 325 | * 1. Doing the scan on channel 1.2.3.4.5.6.7.8 | ||
| 326 | * 2. Back to channel 1 for 300 milliseconds | ||
| 327 | * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52 | ||
| 328 | * 4. Back to channel 1 for 300 milliseconds | ||
| 329 | * 5. ... and so on, till survey done. | ||
| 330 | */ | ||
| 331 | |||
| 332 | struct mlme_ext_info | ||
| 333 | { | ||
| 334 | u32 state; | ||
| 335 | u32 reauth_count; | ||
| 336 | u32 reassoc_count; | ||
| 337 | u32 link_count; | ||
| 338 | u32 auth_seq; | ||
| 339 | u32 auth_algo; /* 802.11 auth, could be open, shared, auto */ | ||
| 340 | u32 authModeToggle; | ||
| 341 | u32 enc_algo;/* encrypt algorithm; */ | ||
| 342 | u32 key_index; /* this is only valid for legendary wep, 0~3 for key id. */ | ||
| 343 | u32 iv; | ||
| 344 | u8 chg_txt[128]; | ||
| 345 | u16 aid; | ||
| 346 | u16 bcn_interval; | ||
| 347 | u16 capability; | ||
| 348 | u8 assoc_AP_vendor; | ||
| 349 | u8 slotTime; | ||
| 350 | u8 preamble_mode; | ||
| 351 | u8 WMM_enable; | ||
| 352 | u8 ERP_enable; | ||
| 353 | u8 ERP_IE; | ||
| 354 | u8 HT_enable; | ||
| 355 | u8 HT_caps_enable; | ||
| 356 | u8 HT_info_enable; | ||
| 357 | u8 HT_protection; | ||
| 358 | u8 turboMode_cts2self; | ||
| 359 | u8 turboMode_rtsen; | ||
| 360 | u8 SM_PS; | ||
| 361 | u8 agg_enable_bitmap; | ||
| 362 | u8 ADDBA_retry_count; | ||
| 363 | u8 candidate_tid_bitmap; | ||
| 364 | u8 dialogToken; | ||
| 365 | /* Accept ADDBA Request */ | ||
| 366 | bool bAcceptAddbaReq; | ||
| 367 | u8 bwmode_updated; | ||
| 368 | u8 hidden_ssid_mode; | ||
| 369 | |||
| 370 | struct ADDBA_request ADDBA_req; | ||
| 371 | struct WMM_para_element WMM_param; | ||
| 372 | struct HT_caps_element HT_caps; | ||
| 373 | struct HT_info_element HT_info; | ||
| 374 | struct wlan_bssid_ex network;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */ | ||
| 375 | struct FW_Sta_Info FW_sta_info[NUM_STA]; | ||
| 376 | }; | ||
| 377 | |||
| 378 | /* The channel information about this channel including joining, scanning, and power constraints. */ | ||
| 379 | struct rt_channel_info { | ||
| 380 | u8 ChannelNum; /* The channel number. */ | ||
| 381 | enum rt_scan_type ScanType; /* Scan type such as passive or active scan. */ | ||
| 382 | }; | ||
| 383 | |||
| 384 | int rtw_ch_set_search_ch23a(struct rt_channel_info *ch_set, const u32 ch); | ||
| 385 | |||
| 386 | /* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */ | ||
| 387 | #define P2P_MAX_REG_CLASSES 10 | ||
| 388 | |||
| 389 | /* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class */ | ||
| 390 | #define P2P_MAX_REG_CLASS_CHANNELS 20 | ||
| 391 | |||
| 392 | /* struct p2p_channels - List of supported channels */ | ||
| 393 | struct p2p_channels { | ||
| 394 | /* struct p2p_reg_class - Supported regulatory class */ | ||
| 395 | struct p2p_reg_class { | ||
| 396 | /* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */ | ||
| 397 | u8 reg_class; | ||
| 398 | |||
| 399 | /* channel - Supported channels */ | ||
| 400 | u8 channel[P2P_MAX_REG_CLASS_CHANNELS]; | ||
| 401 | |||
| 402 | /* channels - Number of channel entries in use */ | ||
| 403 | size_t channels; | ||
| 404 | } reg_class[P2P_MAX_REG_CLASSES]; | ||
| 405 | |||
| 406 | /* reg_classes - Number of reg_class entries in use */ | ||
| 407 | size_t reg_classes; | ||
| 408 | }; | ||
| 409 | |||
| 410 | struct p2p_oper_class_map { | ||
| 411 | enum hw_mode {IEEE80211G,IEEE80211A} mode; | ||
| 412 | u8 op_class; | ||
| 413 | u8 min_chan; | ||
| 414 | u8 max_chan; | ||
| 415 | u8 inc; | ||
| 416 | enum { | ||
| 417 | BW20, BW40PLUS, BW40MINUS | ||
| 418 | } bw; | ||
| 419 | }; | ||
| 420 | |||
| 421 | struct mlme_ext_priv { | ||
| 422 | struct rtw_adapter *padapter; | ||
| 423 | u8 mlmeext_init; | ||
| 424 | atomic_t event_seq; | ||
| 425 | u16 mgnt_seq; | ||
| 426 | |||
| 427 | /* struct fw_priv fwpriv; */ | ||
| 428 | |||
| 429 | unsigned char cur_channel; | ||
| 430 | unsigned char cur_bwmode; | ||
| 431 | unsigned char cur_ch_offset;/* PRIME_CHNL_OFFSET */ | ||
| 432 | unsigned char cur_wireless_mode; /* NETWORK_TYPE */ | ||
| 433 | |||
| 434 | unsigned char max_chan_nums; | ||
| 435 | struct rt_channel_info channel_set[MAX_CHANNEL_NUM]; | ||
| 436 | struct p2p_channels channel_list; | ||
| 437 | unsigned char basicrate[NumRates]; | ||
| 438 | unsigned char datarate[NumRates]; | ||
| 439 | |||
| 440 | struct ss_res sitesurvey_res; | ||
| 441 | struct mlme_ext_info mlmext_info;/* for sta/adhoc mode, including current scanning/connecting/connected related info. */ | ||
| 442 | /* for ap mode, network includes ap's cap_info */ | ||
| 443 | struct timer_list survey_timer; | ||
| 444 | struct timer_list link_timer; | ||
| 445 | u16 chan_scan_time; | ||
| 446 | |||
| 447 | u8 scan_abort; | ||
| 448 | u8 tx_rate; /* TXRATE when USERATE is set. */ | ||
| 449 | |||
| 450 | u32 retry; /* retry for issue probereq */ | ||
| 451 | |||
| 452 | u64 TSFValue; | ||
| 453 | |||
| 454 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 455 | unsigned char bstart_bss; | ||
| 456 | #endif | ||
| 457 | u8 update_channel_plan_by_ap_done; | ||
| 458 | /* recv_decache check for Action_public frame */ | ||
| 459 | u8 action_public_dialog_token; | ||
| 460 | u16 action_public_rxseq; | ||
| 461 | u8 active_keep_alive_check; | ||
| 462 | }; | ||
| 463 | |||
| 464 | int init_mlme_ext_priv23a(struct rtw_adapter* padapter); | ||
| 465 | int init_hw_mlme_ext23a(struct rtw_adapter *padapter); | ||
| 466 | void free_mlme_ext_priv23a (struct mlme_ext_priv *pmlmeext); | ||
| 467 | void init_mlme_ext_timer23a(struct rtw_adapter *padapter); | ||
| 468 | void init_addba_retry_timer23a(struct sta_info *psta); | ||
| 469 | struct xmit_frame *alloc_mgtxmitframe23a(struct xmit_priv *pxmitpriv); | ||
| 470 | |||
| 471 | unsigned char networktype_to_raid23a(unsigned char network_type); | ||
| 472 | u8 judge_network_type23a(struct rtw_adapter *padapter, unsigned char *rate, | ||
| 473 | int ratelen); | ||
| 474 | void get_rate_set23a(struct rtw_adapter *padapter, unsigned char *pbssrate, | ||
| 475 | int *bssrate_len); | ||
| 476 | void UpdateBrateTbl23a(struct rtw_adapter *padapter,u8 *mBratesOS); | ||
| 477 | void Update23aTblForSoftAP(u8 *bssrateset, u32 bssratelen); | ||
| 478 | |||
| 479 | void Save_DM_Func_Flag23a(struct rtw_adapter *padapter); | ||
| 480 | void Restore_DM_Func_Flag23a(struct rtw_adapter *padapter); | ||
| 481 | void Switch_DM_Func23a(struct rtw_adapter *padapter, unsigned long mode, u8 enable); | ||
| 482 | |||
| 483 | void Set_MSR23a(struct rtw_adapter *padapter, u8 type); | ||
| 484 | |||
| 485 | u8 rtw_get_oper_ch23a(struct rtw_adapter *adapter); | ||
| 486 | void rtw_set_oper_ch23a(struct rtw_adapter *adapter, u8 ch); | ||
| 487 | u8 rtw_get_oper_bw23a(struct rtw_adapter *adapter); | ||
| 488 | void rtw_set_oper_bw23a(struct rtw_adapter *adapter, u8 bw); | ||
| 489 | u8 rtw_get_oper_ch23aoffset(struct rtw_adapter *adapter); | ||
| 490 | void rtw_set_oper_ch23aoffset23a(struct rtw_adapter *adapter, u8 offset); | ||
| 491 | |||
| 492 | void set_channel_bwmode23a(struct rtw_adapter *padapter, unsigned char channel, | ||
| 493 | unsigned char channel_offset, unsigned short bwmode); | ||
| 494 | void SelectChannel23a(struct rtw_adapter *padapter, unsigned char channel); | ||
| 495 | void SetBWMode23a(struct rtw_adapter *padapter, unsigned short bwmode, | ||
| 496 | unsigned char channel_offset); | ||
| 497 | |||
| 498 | unsigned int decide_wait_for_beacon_timeout23a(unsigned int bcn_interval); | ||
| 499 | |||
| 500 | void write_cam23a(struct rtw_adapter *padapter, u8 entry, u16 ctrl, | ||
| 501 | u8 *mac, u8 *key); | ||
| 502 | void clear_cam_entry23a(struct rtw_adapter *padapter, u8 entry); | ||
| 503 | |||
| 504 | void invalidate_cam_all23a(struct rtw_adapter *padapter); | ||
| 505 | void CAM_empty_entry23a(struct rtw_adapter *Adapter, u8 ucIndex); | ||
| 506 | |||
| 507 | int allocate_fw_sta_entry23a(struct rtw_adapter *padapter); | ||
| 508 | void flush_all_cam_entry23a(struct rtw_adapter *padapter); | ||
| 509 | |||
| 510 | bool IsLegal5GChannel(struct rtw_adapter *Adapter, u8 channel); | ||
| 511 | |||
| 512 | void site_survey23a(struct rtw_adapter *padapter); | ||
| 513 | u8 collect_bss_info23a(struct rtw_adapter *padapter, | ||
| 514 | struct recv_frame *precv_frame, | ||
| 515 | struct wlan_bssid_ex *bssid); | ||
| 516 | void update_network23a(struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src, | ||
| 517 | struct rtw_adapter *padapter, bool update_ie); | ||
| 518 | |||
| 519 | int get_bsstype23a(unsigned short capability); | ||
| 520 | u8 *get_my_bssid23a(struct wlan_bssid_ex *pnetwork); | ||
| 521 | u16 get_beacon_interval23a(struct wlan_bssid_ex *bss); | ||
| 522 | |||
| 523 | int is_client_associated_to_ap23a(struct rtw_adapter *padapter); | ||
| 524 | int is_client_associated_to_ibss23a(struct rtw_adapter *padapter); | ||
| 525 | int is_IBSS_empty23a(struct rtw_adapter *padapter); | ||
| 526 | |||
| 527 | unsigned char check_assoc_AP23a(u8 *pframe, uint len); | ||
| 528 | |||
| 529 | int WMM_param_handler23a(struct rtw_adapter *padapter, | ||
| 530 | struct ndis_802_11_var_ies *pIE); | ||
| 531 | #ifdef CONFIG_8723AU_P2P | ||
| 532 | int WFD_info_handler(struct rtw_adapter *padapter, | ||
| 533 | struct ndis_802_11_var_ies *pIE); | ||
| 534 | #endif | ||
| 535 | void WMMOnAssocRsp23a(struct rtw_adapter *padapter); | ||
| 536 | |||
| 537 | void HT_caps_handler23a(struct rtw_adapter *padapter, | ||
| 538 | struct ndis_802_11_var_ies *pIE); | ||
| 539 | void HT_info_handler23a(struct rtw_adapter *padapter, | ||
| 540 | struct ndis_802_11_var_ies *pIE); | ||
| 541 | void HTOnAssocRsp23a(struct rtw_adapter *padapter); | ||
| 542 | |||
| 543 | void ERP_IE_handler23a(struct rtw_adapter *padapter, | ||
| 544 | struct ndis_802_11_var_ies *pIE); | ||
| 545 | void VCS_update23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 546 | |||
| 547 | void update_beacon23a_info(struct rtw_adapter *padapter, u8 *pframe, uint len, | ||
| 548 | struct sta_info *psta); | ||
| 549 | int rtw_check_bcn_info23a(struct rtw_adapter *Adapter, u8 *pframe, u32 packet_len); | ||
| 550 | void update_IOT_info23a(struct rtw_adapter *padapter); | ||
| 551 | void update_capinfo23a(struct rtw_adapter *Adapter, u16 updateCap); | ||
| 552 | void update_wireless_mode23a(struct rtw_adapter * padapter); | ||
| 553 | void update_tx_basic_rate23a(struct rtw_adapter *padapter, u8 modulation); | ||
| 554 | void update_bmc_sta_support_rate23a(struct rtw_adapter *padapter, u32 mac_id); | ||
| 555 | int update_sta_support_rate23a(struct rtw_adapter *padapter, u8* pvar_ie, | ||
| 556 | uint var_ie_len, int cam_idx); | ||
| 557 | |||
| 558 | /* for sta/adhoc mode */ | ||
| 559 | void update_sta_info23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 560 | unsigned int update_basic_rate23a(unsigned char *ptn, unsigned int ptn_sz); | ||
| 561 | unsigned int update_supported_rate23a(unsigned char *ptn, unsigned int ptn_sz); | ||
| 562 | unsigned int update_MSC_rate23a(struct HT_caps_element *pHT_caps); | ||
| 563 | void Update_RA_Entry23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 564 | void set_sta_rate23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 565 | |||
| 566 | unsigned int receive_disconnect23a(struct rtw_adapter *padapter, | ||
| 567 | unsigned char *MacAddr, unsigned short reason); | ||
| 568 | |||
| 569 | unsigned char get_highest_rate_idx23a(u32 mask); | ||
| 570 | int support_short_GI23a(struct rtw_adapter *padapter, | ||
| 571 | struct HT_caps_element *pHT_caps); | ||
| 572 | unsigned int is_ap_in_tkip23a(struct rtw_adapter *padapter); | ||
| 573 | unsigned int is_ap_in_wep23a(struct rtw_adapter *padapter); | ||
| 574 | unsigned int should_forbid_n_rate23a(struct rtw_adapter *padapter); | ||
| 575 | |||
| 576 | void report_join_res23a(struct rtw_adapter *padapter, int res); | ||
| 577 | void report_survey_event23a(struct rtw_adapter *padapter, | ||
| 578 | struct recv_frame *precv_frame); | ||
| 579 | void report_surveydone_event23a(struct rtw_adapter *padapter); | ||
| 580 | void report_del_sta_event23a(struct rtw_adapter *padapter, | ||
| 581 | unsigned char *MacAddr, unsigned short reason); | ||
| 582 | void report_add_sta_event23a(struct rtw_adapter *padapter, | ||
| 583 | unsigned char *MacAddr, int cam_idx); | ||
| 584 | |||
| 585 | void beacon_timing_control23a(struct rtw_adapter *padapter); | ||
| 586 | u8 set_tx_beacon_cmd23a(struct rtw_adapter*padapter); | ||
| 587 | unsigned int setup_beacon_frame(struct rtw_adapter *padapter, | ||
| 588 | unsigned char *beacon_frame); | ||
| 589 | void update_mgnt_tx_rate23a(struct rtw_adapter *padapter, u8 rate); | ||
| 590 | void update_mgntframe_attrib23a(struct rtw_adapter *padapter, | ||
| 591 | struct pkt_attrib *pattrib); | ||
| 592 | void dump_mgntframe23a(struct rtw_adapter *padapter, | ||
| 593 | struct xmit_frame *pmgntframe); | ||
| 594 | s32 dump_mgntframe23a_and_wait(struct rtw_adapter *padapter, | ||
| 595 | struct xmit_frame *pmgntframe, int timeout_ms); | ||
| 596 | s32 dump_mgntframe23a_and_wait_ack23a(struct rtw_adapter *padapter, | ||
| 597 | struct xmit_frame *pmgntframe); | ||
| 598 | |||
| 599 | #ifdef CONFIG_8723AU_P2P | ||
| 600 | void issue_probersp23a_p2p23a(struct rtw_adapter *padapter, unsigned char *da); | ||
| 601 | void issue_p2p_provision_request23a(struct rtw_adapter *padapter, u8 *pssid, | ||
| 602 | u8 ussidlen, u8* pdev_raddr); | ||
| 603 | void issue_p2p_GO_request23a(struct rtw_adapter *padapter, u8* raddr); | ||
| 604 | void issue23a_probereq_p2p(struct rtw_adapter *padapter, u8 *da); | ||
| 605 | int issue23a_probereq_p2p_ex(struct rtw_adapter *adapter, u8 *da, int try_cnt, | ||
| 606 | int wait_ms); | ||
| 607 | void issue_p2p_invitation_response23a(struct rtw_adapter *padapter, u8* raddr, | ||
| 608 | u8 dialogToken, u8 success); | ||
| 609 | void issue_p2p_invitation_request23a(struct rtw_adapter *padapter, u8* raddr); | ||
| 610 | #endif /* CONFIG_8723AU_P2P */ | ||
| 611 | void issue_beacon23a(struct rtw_adapter *padapter, int timeout_ms); | ||
| 612 | void issue_probersp23a(struct rtw_adapter *padapter, unsigned char *da, | ||
| 613 | u8 is_valid_p2p_probereq); | ||
| 614 | void issue_assocreq23a(struct rtw_adapter *padapter); | ||
| 615 | void issue_asocrsp23a(struct rtw_adapter *padapter, unsigned short status, | ||
| 616 | struct sta_info *pstat, int pkt_type); | ||
| 617 | void issue_auth23a(struct rtw_adapter *padapter, struct sta_info *psta, | ||
| 618 | unsigned short status); | ||
| 619 | void issue_probereq23a(struct rtw_adapter *padapter, struct cfg80211_ssid *pssid, | ||
| 620 | u8 *da); | ||
| 621 | s32 issue_probereq23a_ex23a(struct rtw_adapter *padapter, struct cfg80211_ssid *pssid, | ||
| 622 | u8 *da, int try_cnt, int wait_ms); | ||
| 623 | int issue_nulldata23a(struct rtw_adapter *padapter, unsigned char *da, | ||
| 624 | unsigned int power_mode, int try_cnt, int wait_ms); | ||
| 625 | int issue_qos_nulldata23a(struct rtw_adapter *padapter, unsigned char *da, u16 tid, | ||
| 626 | int try_cnt, int wait_ms); | ||
| 627 | int issue_deauth23a(struct rtw_adapter *padapter, unsigned char *da, | ||
| 628 | unsigned short reason); | ||
| 629 | int issue_deauth23a_ex23a(struct rtw_adapter *padapter, u8 *da, unsigned short reason, | ||
| 630 | int try_cnt, int wait_ms); | ||
| 631 | void issue_action_spct_ch_switch23a(struct rtw_adapter *padapter, u8 *ra, | ||
| 632 | u8 new_ch, u8 ch_offset); | ||
| 633 | void issue_action_BA23a(struct rtw_adapter *padapter, unsigned char *raddr, | ||
| 634 | unsigned char action, unsigned short status); | ||
| 635 | unsigned int send_delba23a(struct rtw_adapter *padapter, u8 initiator, u8 *addr); | ||
| 636 | unsigned int send_beacon23a(struct rtw_adapter *padapter); | ||
| 637 | |||
| 638 | void start_clnt_assoc23a(struct rtw_adapter *padapter); | ||
| 639 | void start_clnt_auth23a(struct rtw_adapter *padapter); | ||
| 640 | void start_clnt_join23a(struct rtw_adapter *padapter); | ||
| 641 | void start_create_ibss23a(struct rtw_adapter *padapter); | ||
| 642 | |||
| 643 | unsigned int OnAssocReq23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 644 | unsigned int OnAssocRsp23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 645 | unsigned int OnProbeReq23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 646 | unsigned int OnProbeRsp23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 647 | unsigned int DoReserved23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 648 | unsigned int OnBeacon23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 649 | unsigned int OnAtim23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 650 | unsigned int OnDisassoc23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 651 | unsigned int OnAuth23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 652 | unsigned int OnAuth23aClient23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 653 | unsigned int OnDeAuth23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 654 | unsigned int OnAction23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 655 | |||
| 656 | unsigned int on_action_spct23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 657 | unsigned int OnAction23a_qos(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 658 | unsigned int OnAction23a_dls(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 659 | unsigned int OnAction23a_back23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 660 | unsigned int on_action_public23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 661 | unsigned int OnAction23a_ht(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 662 | unsigned int OnAction23a_wmm(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 663 | unsigned int OnAction23a_p2p(struct rtw_adapter *padapter, struct recv_frame *precv_frame); | ||
| 664 | |||
| 665 | |||
| 666 | void mlmeext_joinbss_event_callback23a(struct rtw_adapter *padapter, int join_res); | ||
| 667 | void mlmeext_sta_del_event_callback23a(struct rtw_adapter *padapter); | ||
| 668 | void mlmeext_sta_add_event_callback23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 669 | |||
| 670 | void linked_status_chk23a(struct rtw_adapter *padapter); | ||
| 671 | |||
| 672 | #define set_survey_timer(mlmeext, ms) \ | ||
| 673 | /*DBG_8723A("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ | ||
| 674 | mod_timer(&mlmeext->survey_timer, jiffies + msecs_to_jiffies(ms)); | ||
| 675 | |||
| 676 | #define set_link_timer(mlmeext, ms) \ | ||
| 677 | /*DBG_8723A("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ | ||
| 678 | mod_timer(&mlmeext->link_timer, jiffies + msecs_to_jiffies(ms)); | ||
| 679 | |||
| 680 | int cckrates_included23a(unsigned char *rate, int ratelen); | ||
| 681 | int cckratesonly_included23a(unsigned char *rate, int ratelen); | ||
| 682 | |||
| 683 | void process_addba_req23a(struct rtw_adapter *padapter, u8 *paddba_req, u8 *addr); | ||
| 684 | |||
| 685 | void update_TSF23a(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); | ||
| 686 | void correct_TSF23a(struct rtw_adapter *padapter, struct mlme_ext_priv *pmlmeext); | ||
| 687 | |||
| 688 | struct cmd_hdl { | ||
| 689 | uint parmsize; | ||
| 690 | u8 (*h2cfuns)(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 691 | }; | ||
| 692 | |||
| 693 | |||
| 694 | u8 read_macreg_hdl(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 695 | u8 write_macreg_hdl(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 696 | u8 read_bbreg_hdl(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 697 | u8 write_bbreg_hdl(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 698 | u8 read_rfreg_hdl(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 699 | u8 write_rfreg_hdl(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 700 | |||
| 701 | |||
| 702 | u8 NULL_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 703 | u8 join_cmd_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 704 | u8 disconnect_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 705 | u8 createbss_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 706 | u8 setopmode_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 707 | u8 sitesurvey_cmd_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 708 | u8 setauth_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 709 | u8 setkey_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 710 | u8 set_stakey_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 711 | u8 set_assocsta_hdl(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 712 | u8 del_assocsta_hdl(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 713 | u8 add_ba_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); | ||
| 714 | |||
| 715 | u8 mlme_evt_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); | ||
| 716 | u8 h2c_msg_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); | ||
| 717 | u8 tx_beacon_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); | ||
| 718 | u8 set_ch_hdl23a(struct rtw_adapter *padapter, u8 *pbuf); | ||
| 719 | u8 set_chplan_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); | ||
| 720 | u8 led_blink_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); | ||
| 721 | u8 set_csa_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); /* Kurt: Handling DFS channel switch announcement ie. */ | ||
| 722 | u8 tdls_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf); | ||
| 723 | |||
| 724 | #define GEN_DRV_CMD_HANDLER(size, cmd) {size, &cmd ## _hdl23a}, | ||
| 725 | #define GEN_MLME_EXT_HANDLER(size, cmd) {size, cmd}, | ||
| 726 | |||
| 727 | struct C2HEvent_Header { | ||
| 728 | #ifdef __LITTLE_ENDIAN | ||
| 729 | |||
| 730 | unsigned int len:16; | ||
| 731 | unsigned int ID:8; | ||
| 732 | unsigned int seq:8; | ||
| 733 | |||
| 734 | #elif defined(__BIG_ENDIAN) | ||
| 735 | |||
| 736 | unsigned int seq:8; | ||
| 737 | unsigned int ID:8; | ||
| 738 | unsigned int len:16; | ||
| 739 | |||
| 740 | #else | ||
| 741 | |||
| 742 | # error "Must be LITTLE or BIG Endian" | ||
| 743 | |||
| 744 | #endif | ||
| 745 | |||
| 746 | unsigned int rsvd; | ||
| 747 | }; | ||
| 748 | |||
| 749 | void rtw_dummy_event_callback23a(struct rtw_adapter *adapter , u8 *pbuf); | ||
| 750 | void rtw23a_fwdbg_event_callback(struct rtw_adapter *adapter , u8 *pbuf); | ||
| 751 | |||
| 752 | enum rtw_c2h_event { | ||
| 753 | GEN_EVT_CODE(_Read_MACREG) = 0, /*0*/ | ||
| 754 | GEN_EVT_CODE(_Read_BBREG), | ||
| 755 | GEN_EVT_CODE(_Read_RFREG), | ||
| 756 | GEN_EVT_CODE(_Read_EEPROM), | ||
| 757 | GEN_EVT_CODE(_Read_EFUSE), | ||
| 758 | GEN_EVT_CODE(_Read_CAM), /*5*/ | ||
| 759 | GEN_EVT_CODE(_Get_BasicRate), | ||
| 760 | GEN_EVT_CODE(_Get_DataRate), | ||
| 761 | GEN_EVT_CODE(_Survey), /*8*/ | ||
| 762 | GEN_EVT_CODE(_SurveyDone), /*9*/ | ||
| 763 | |||
| 764 | GEN_EVT_CODE(_JoinBss) , /*10*/ | ||
| 765 | GEN_EVT_CODE(_AddSTA), | ||
| 766 | GEN_EVT_CODE(_DelSTA), | ||
| 767 | GEN_EVT_CODE(_AtimDone) , | ||
| 768 | GEN_EVT_CODE(_TX_Report), | ||
| 769 | GEN_EVT_CODE(_CCX_Report), /*15*/ | ||
| 770 | GEN_EVT_CODE(_DTM_Report), | ||
| 771 | GEN_EVT_CODE(_TX_Rate_Statistics), | ||
| 772 | GEN_EVT_CODE(_C2HLBK), | ||
| 773 | GEN_EVT_CODE(_FWDBG), | ||
| 774 | GEN_EVT_CODE(_C2HFEEDBACK), /*20*/ | ||
| 775 | GEN_EVT_CODE(_ADDBA), | ||
| 776 | GEN_EVT_CODE(_C2HBCN), | ||
| 777 | GEN_EVT_CODE(_ReportPwrState), /* filen: only for PCIE, USB */ | ||
| 778 | GEN_EVT_CODE(_CloseRF), /* filen: only for PCIE, work around ASPM */ | ||
| 779 | MAX_C2HEVT | ||
| 780 | }; | ||
| 781 | |||
| 782 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_p2p.h b/drivers/staging/rtl8723au/include/rtw_p2p.h new file mode 100644 index 000000000000..93fdc658ff4d --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_p2p.h | |||
| @@ -0,0 +1,158 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_P2P_H_ | ||
| 16 | #define __RTW_P2P_H_ | ||
| 17 | |||
| 18 | #include <drv_types.h> | ||
| 19 | |||
| 20 | u32 build_beacon_p2p_ie23a(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 21 | u32 build_probe_resp_p2p_ie23a(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 22 | u32 build_prov_disc_request_p2p_ie23a(struct wifidirect_info *pwdinfo, u8 *pbuf, | ||
| 23 | u8 *pssid, u8 ussidlen, u8 *pdev_raddr); | ||
| 24 | u32 build_assoc_resp_p2p_ie23a(struct wifidirect_info *pwdinfo, u8 *pbuf, | ||
| 25 | u8 status_code); | ||
| 26 | u32 build_deauth_p2p_ie23a(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 27 | #ifdef CONFIG_8723AU_P2P | ||
| 28 | u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 29 | u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, | ||
| 30 | u8 tunneled); | ||
| 31 | u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 32 | u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 33 | u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 34 | u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 35 | u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 36 | u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 37 | u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 38 | u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 39 | u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 40 | u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); | ||
| 41 | #endif /* CONFIG_8723AU_P2P */ | ||
| 42 | |||
| 43 | u32 process_probe_req_p2p_ie23a(struct wifidirect_info *pwdinfo, u8 *pframe, | ||
| 44 | uint len); | ||
| 45 | u32 process_assoc_req_p2p_ie23a(struct wifidirect_info *pwdinfo, u8 *pframe, | ||
| 46 | uint len, struct sta_info *psta); | ||
| 47 | u32 process_p2p_devdisc_req23a(struct wifidirect_info *pwdinfo, u8 *pframe, | ||
| 48 | uint len); | ||
| 49 | u32 process_p2p_devdisc_resp23a(struct wifidirect_info *pwdinfo, u8 *pframe, | ||
| 50 | uint len); | ||
| 51 | u8 process_p2p_provdisc_req23a(struct wifidirect_info *pwdinfo, u8 *pframe, | ||
| 52 | uint len); | ||
| 53 | u8 process_p2p_provdisc_resp23a(struct wifidirect_info *pwdinfo, u8 *pframe); | ||
| 54 | u8 process_p2p_group_negotation_req23a(struct wifidirect_info *pwdinfo, | ||
| 55 | u8 *pframe, uint len); | ||
| 56 | u8 process_p2p_group_negotation_resp23a(struct wifidirect_info *pwdinfo, | ||
| 57 | u8 *pframe, uint len); | ||
| 58 | u8 process_p2p_group_negotation_confirm23a(struct wifidirect_info *pwdinfo, | ||
| 59 | u8 *pframe, uint len); | ||
| 60 | u8 process_p2p_presence_req23a(struct wifidirect_info *pwdinfo, | ||
| 61 | u8 *pframe, uint len); | ||
| 62 | |||
| 63 | void p2p_protocol_wk_hdl23a(struct rtw_adapter *padapter, int cmdtype); | ||
| 64 | |||
| 65 | #ifdef CONFIG_8723AU_P2P | ||
| 66 | void process_p2p_ps_ie23a(struct rtw_adapter *padapter, u8 *IEs, u32 IELength); | ||
| 67 | void p2p_ps_wk_hdl23a(struct rtw_adapter *padapter, u8 p2p_ps_state); | ||
| 68 | u8 p2p_ps_wk_cmd23a(struct rtw_adapter *padapter, u8 p2p_ps_state, u8 enqueue); | ||
| 69 | #endif /* CONFIG_8723AU_P2P */ | ||
| 70 | |||
| 71 | void rtw_init_cfg80211_wifidirect_info(struct rtw_adapter *padapter); | ||
| 72 | int rtw_p2p_check_frames(struct rtw_adapter *padapter, const u8 *buf, | ||
| 73 | u32 len, u8 tx); | ||
| 74 | void rtw_append_wfd_ie(struct rtw_adapter *padapter, u8 *buf, u32 *len); | ||
| 75 | |||
| 76 | void reset_global_wifidirect_info23a(struct rtw_adapter *padapter); | ||
| 77 | int rtw_init_wifi_display_info(struct rtw_adapter *padapter); | ||
| 78 | void rtw_init_wifidirect_timers23a(struct rtw_adapter *padapter); | ||
| 79 | void rtw_init_wifidirect_addrs23a(struct rtw_adapter *padapter, u8 *dev_addr, | ||
| 80 | u8 *iface_addr); | ||
| 81 | void init_wifidirect_info23a(struct rtw_adapter *padapter, enum P2P_ROLE role); | ||
| 82 | int rtw_p2p_enable23a(struct rtw_adapter *padapter, enum P2P_ROLE role); | ||
| 83 | |||
| 84 | static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, | ||
| 85 | enum P2P_STATE state) | ||
| 86 | { | ||
| 87 | if (wdinfo->p2p_state != state) { | ||
| 88 | /* wdinfo->pre_p2p_state = wdinfo->p2p_state; */ | ||
| 89 | wdinfo->p2p_state = state; | ||
| 90 | } | ||
| 91 | } | ||
| 92 | |||
| 93 | static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, | ||
| 94 | enum P2P_STATE state) | ||
| 95 | { | ||
| 96 | if (wdinfo->pre_p2p_state != state) | ||
| 97 | wdinfo->pre_p2p_state = state; | ||
| 98 | } | ||
| 99 | |||
| 100 | static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, | ||
| 101 | enum P2P_ROLE role) | ||
| 102 | { | ||
| 103 | if (wdinfo->role != role) | ||
| 104 | wdinfo->role = role; | ||
| 105 | } | ||
| 106 | |||
| 107 | static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo) | ||
| 108 | { | ||
| 109 | return wdinfo->p2p_state; | ||
| 110 | } | ||
| 111 | |||
| 112 | static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo) | ||
| 113 | { | ||
| 114 | return wdinfo->pre_p2p_state; | ||
| 115 | } | ||
| 116 | |||
| 117 | static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo) | ||
| 118 | { | ||
| 119 | return wdinfo->role; | ||
| 120 | } | ||
| 121 | |||
| 122 | static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, | ||
| 123 | enum P2P_STATE state) | ||
| 124 | { | ||
| 125 | return wdinfo->p2p_state == state; | ||
| 126 | } | ||
| 127 | |||
| 128 | static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, | ||
| 129 | enum P2P_ROLE role) | ||
| 130 | { | ||
| 131 | return wdinfo->role == role; | ||
| 132 | } | ||
| 133 | |||
| 134 | #define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) | ||
| 135 | #define rtw_p2p_set_pre_state(wdinfo, state) \ | ||
| 136 | _rtw_p2p_set_pre_state(wdinfo, state) | ||
| 137 | #define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) | ||
| 138 | |||
| 139 | #define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo) | ||
| 140 | #define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo) | ||
| 141 | #define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo) | ||
| 142 | #define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state) | ||
| 143 | #define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role) | ||
| 144 | |||
| 145 | #define rtw_p2p_findphase_ex_set(wdinfo, value) \ | ||
| 146 | ((wdinfo)->find_phase_state_exchange_cnt = (value)) | ||
| 147 | |||
| 148 | /* is this find phase exchange for social channel scan? */ | ||
| 149 | #define rtw_p2p_findphase_ex_is_social(wdinfo) \ | ||
| 150 | ((wdinfo)->find_phase_state_exchange_cnt >= \ | ||
| 151 | P2P_FINDPHASE_EX_SOCIAL_FIRST) | ||
| 152 | |||
| 153 | /* should we need find phase exchange anymore? */ | ||
| 154 | #define rtw_p2p_findphase_ex_is_needed(wdinfo) \ | ||
| 155 | ((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \ | ||
| 156 | (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE) | ||
| 157 | |||
| 158 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_pwrctrl.h b/drivers/staging/rtl8723au/include/rtw_pwrctrl.h new file mode 100644 index 000000000000..b42e14198e8d --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_pwrctrl.h | |||
| @@ -0,0 +1,265 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_PWRCTRL_H_ | ||
| 16 | #define __RTW_PWRCTRL_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | #define FW_PWR0 0 | ||
| 22 | #define FW_PWR1 1 | ||
| 23 | #define FW_PWR2 2 | ||
| 24 | #define FW_PWR3 3 | ||
| 25 | |||
| 26 | |||
| 27 | #define HW_PWR0 7 | ||
| 28 | #define HW_PWR1 6 | ||
| 29 | #define HW_PWR2 2 | ||
| 30 | #define HW_PWR3 0 | ||
| 31 | #define HW_PWR4 8 | ||
| 32 | |||
| 33 | #define FW_PWRMSK 0x7 | ||
| 34 | |||
| 35 | |||
| 36 | #define XMIT_ALIVE BIT(0) | ||
| 37 | #define RECV_ALIVE BIT(1) | ||
| 38 | #define CMD_ALIVE BIT(2) | ||
| 39 | #define EVT_ALIVE BIT(3) | ||
| 40 | |||
| 41 | enum Power_Mgnt { | ||
| 42 | PS_MODE_ACTIVE = 0, | ||
| 43 | PS_MODE_MIN, | ||
| 44 | PS_MODE_MAX, | ||
| 45 | PS_MODE_DTIM, | ||
| 46 | PS_MODE_VOIP, | ||
| 47 | PS_MODE_UAPSD_WMM, | ||
| 48 | PS_MODE_UAPSD, | ||
| 49 | PS_MODE_IBSS, | ||
| 50 | PS_MODE_WWLAN, | ||
| 51 | PM_Radio_Off, | ||
| 52 | PM_Card_Disable, | ||
| 53 | PS_MODE_NUM | ||
| 54 | }; | ||
| 55 | |||
| 56 | |||
| 57 | /* BIT[2:0] = HW state | ||
| 58 | * BIT[3] = Protocol PS state, 0: active, 1: sleep state | ||
| 59 | * BIT[4] = sub-state | ||
| 60 | */ | ||
| 61 | |||
| 62 | #define PS_DPS BIT(0) | ||
| 63 | #define PS_LCLK (PS_DPS) | ||
| 64 | #define PS_RF_OFF BIT(1) | ||
| 65 | #define PS_ALL_ON BIT(2) | ||
| 66 | #define PS_ST_ACTIVE BIT(3) | ||
| 67 | |||
| 68 | #define PS_ISR_ENABLE BIT(4) | ||
| 69 | #define PS_IMR_ENABLE BIT(5) | ||
| 70 | #define PS_ACK BIT(6) | ||
| 71 | #define PS_TOGGLE BIT(7) | ||
| 72 | |||
| 73 | #define PS_STATE_MASK (0x0F) | ||
| 74 | #define PS_STATE_HW_MASK (0x07) | ||
| 75 | #define PS_SEQ_MASK (0xc0) | ||
| 76 | |||
| 77 | #define PS_STATE(x) (PS_STATE_MASK & (x)) | ||
| 78 | #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) | ||
| 79 | #define PS_SEQ(x) (PS_SEQ_MASK & (x)) | ||
| 80 | |||
| 81 | #define PS_STATE_S0 (PS_DPS) | ||
| 82 | #define PS_STATE_S1 (PS_LCLK) | ||
| 83 | #define PS_STATE_S2 (PS_RF_OFF) | ||
| 84 | #define PS_STATE_S3 (PS_ALL_ON) | ||
| 85 | #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) | ||
| 86 | |||
| 87 | |||
| 88 | #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) | ||
| 89 | #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) | ||
| 90 | #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) | ||
| 91 | |||
| 92 | |||
| 93 | struct reportpwrstate_parm { | ||
| 94 | unsigned char mode; | ||
| 95 | unsigned char state; /* the CPWM value */ | ||
| 96 | unsigned short rsvd; | ||
| 97 | }; | ||
| 98 | |||
| 99 | #define LPS_DELAY_TIME (1*HZ) /* 1 sec */ | ||
| 100 | |||
| 101 | #define EXE_PWR_NONE 0x01 | ||
| 102 | #define EXE_PWR_IPS 0x02 | ||
| 103 | #define EXE_PWR_LPS 0x04 | ||
| 104 | |||
| 105 | /* RF state. */ | ||
| 106 | enum rt_rf_power_state { | ||
| 107 | rf_on, /* RF is on after RFSleep or RFOff */ | ||
| 108 | rf_sleep, /* 802.11 Power Save mode */ | ||
| 109 | rf_off, /* HW/SW Radio OFF or Inactive Power Save */ | ||
| 110 | /* Add the new RF state above this line===== */ | ||
| 111 | rf_max | ||
| 112 | }; | ||
| 113 | |||
| 114 | /* RF Off Level for IPS or HW/SW radio off */ | ||
| 115 | #define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */ | ||
| 116 | #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */ | ||
| 117 | #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */ | ||
| 118 | /* NIC halt, re-init hw params */ | ||
| 119 | #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) | ||
| 120 | /* FW free, re-download the FW */ | ||
| 121 | #define RT_RF_OFF_LEVL_FREE_FW BIT(4) | ||
| 122 | #define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */ | ||
| 123 | /* Always enable ASPM and Clock Req in initialization. */ | ||
| 124 | #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) | ||
| 125 | /* When LPS is on, disable 2R if no packet is received or transmittd. */ | ||
| 126 | #define RT_RF_LPS_DISALBE_2R BIT(30) | ||
| 127 | #define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */ | ||
| 128 | |||
| 129 | #define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) \ | ||
| 130 | ((ppsc->cur_ps_level & _PS_FLAG) ? true : false) | ||
| 131 | #define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) \ | ||
| 132 | (ppsc->cur_ps_level &= (~(_PS_FLAG))) | ||
| 133 | #define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) \ | ||
| 134 | (ppsc->cur_ps_level |= _PS_FLAG) | ||
| 135 | |||
| 136 | |||
| 137 | enum { | ||
| 138 | PSBBREG_RF0 = 0, | ||
| 139 | PSBBREG_RF1, | ||
| 140 | PSBBREG_RF2, | ||
| 141 | PSBBREG_AFE0, | ||
| 142 | PSBBREG_TOTALCNT | ||
| 143 | }; | ||
| 144 | |||
| 145 | enum { /* for ips_mode */ | ||
| 146 | IPS_NONE = 0, | ||
| 147 | IPS_NORMAL, | ||
| 148 | IPS_LEVEL_2, | ||
| 149 | }; | ||
| 150 | |||
| 151 | struct pwrctrl_priv { | ||
| 152 | struct semaphore lock; | ||
| 153 | volatile u8 rpwm; /* requested power state for fw */ | ||
| 154 | volatile u8 cpwm; /* fw current power state. updated when 1. | ||
| 155 | * read from HCPWM 2. driver lowers power level | ||
| 156 | */ | ||
| 157 | volatile u8 tog; /* toggling */ | ||
| 158 | volatile u8 cpwm_tog; /* toggling */ | ||
| 159 | |||
| 160 | u8 pwr_mode; | ||
| 161 | u8 smart_ps; | ||
| 162 | u8 bcn_ant_mode; | ||
| 163 | |||
| 164 | u32 alives; | ||
| 165 | struct work_struct cpwm_event; | ||
| 166 | u8 bpower_saving; | ||
| 167 | |||
| 168 | u8 b_hw_radio_off; | ||
| 169 | u8 reg_rfoff; | ||
| 170 | u8 reg_pdnmode; /* powerdown mode */ | ||
| 171 | u32 rfoff_reason; | ||
| 172 | |||
| 173 | /* RF OFF Level */ | ||
| 174 | u32 cur_ps_level; | ||
| 175 | u32 reg_rfps_level; | ||
| 176 | |||
| 177 | uint ips_enter23a_cnts; | ||
| 178 | uint ips_leave23a_cnts; | ||
| 179 | |||
| 180 | u8 ips_mode; | ||
| 181 | u8 ips_mode_req; /* used to accept the mode setting request */ | ||
| 182 | uint bips_processing; | ||
| 183 | u32 ips_deny_time; /* will deny IPS when system time is smaller */ | ||
| 184 | u8 ps_processing; /* used to mark whether in rtw_ps_processor23a */ | ||
| 185 | |||
| 186 | u8 bLeisurePs; | ||
| 187 | u8 LpsIdleCount; | ||
| 188 | u8 power_mgnt; | ||
| 189 | u8 bFwCurrentInPSMode; | ||
| 190 | unsigned long DelayLPSLastTimeStamp; | ||
| 191 | u8 btcoex_rfon; | ||
| 192 | s32 pnp_current_pwr_state; | ||
| 193 | u8 pnp_bstop_trx; | ||
| 194 | |||
| 195 | u8 bInternalAutoSuspend; | ||
| 196 | u8 bInSuspend; | ||
| 197 | #ifdef CONFIG_8723AU_BT_COEXIST | ||
| 198 | u8 bAutoResume; | ||
| 199 | u8 autopm_cnt; | ||
| 200 | #endif | ||
| 201 | u8 bSupportRemoteWakeup; | ||
| 202 | struct timer_list pwr_state_check_timer; | ||
| 203 | int pwr_state_check_interval; | ||
| 204 | u8 pwr_state_check_cnts; | ||
| 205 | |||
| 206 | int ps_flag; | ||
| 207 | |||
| 208 | enum rt_rf_power_state rf_pwrstate;/* cur power state */ | ||
| 209 | enum rt_rf_power_state change_rfpwrstate; | ||
| 210 | |||
| 211 | u8 wepkeymask; | ||
| 212 | u8 bHWPowerdown;/* if support hw power down */ | ||
| 213 | u8 bHWPwrPindetect; | ||
| 214 | u8 bkeepfwalive; | ||
| 215 | u8 brfoffbyhw; | ||
| 216 | unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; | ||
| 217 | }; | ||
| 218 | |||
| 219 | #define rtw_get_ips_mode_req(pwrctrlpriv) \ | ||
| 220 | ((pwrctrlpriv)->ips_mode_req) | ||
| 221 | |||
| 222 | #define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \ | ||
| 223 | ((pwrctrlpriv)->ips_mode_req = (ips_mode)) | ||
| 224 | |||
| 225 | #define RTW_PWR_STATE_CHK_INTERVAL 2000 | ||
| 226 | |||
| 227 | #define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \ | ||
| 228 | (mod_timer(&pwrctrlpriv->pwr_state_check_timer, jiffies + \ | ||
| 229 | msecs_to_jiffies(ms))) | ||
| 230 | |||
| 231 | #define rtw_set_pwr_state_check_timer(pwrctrlpriv) \ | ||
| 232 | (_rtw_set_pwr_state_check_timer((pwrctrlpriv), \ | ||
| 233 | (pwrctrlpriv)->pwr_state_check_interval)) | ||
| 234 | |||
| 235 | void rtw_init_pwrctrl_priv23a(struct rtw_adapter *adapter); | ||
| 236 | void rtw_free_pwrctrl_priv(struct rtw_adapter *adapter); | ||
| 237 | |||
| 238 | void rtw_set_ps_mode23a(struct rtw_adapter *padapter, u8 ps_mode, | ||
| 239 | u8 smart_ps, u8 bcn_ant_mode); | ||
| 240 | void rtw_set_rpwm23a(struct rtw_adapter *padapter, u8 val8); | ||
| 241 | void LeaveAllPowerSaveMode23a(struct rtw_adapter *adapter); | ||
| 242 | void ips_enter23a(struct rtw_adapter *padapter); | ||
| 243 | int ips_leave23a(struct rtw_adapter *padapter); | ||
| 244 | |||
| 245 | void rtw_ps_processor23a(struct rtw_adapter *padapter); | ||
| 246 | |||
| 247 | enum rt_rf_power_state RfOnOffDetect23a(struct rtw_adapter *adapter); | ||
| 248 | |||
| 249 | s32 LPS_RF_ON_check23a(struct rtw_adapter *padapter, u32 delay_ms); | ||
| 250 | void LPS_Enter23a(struct rtw_adapter *padapter); | ||
| 251 | void LPS_Leave23a(struct rtw_adapter *padapter); | ||
| 252 | |||
| 253 | u8 rtw_interface_ps_func23a(struct rtw_adapter *padapter, | ||
| 254 | enum hal_intf_ps_func efunc_id, u8 *val); | ||
| 255 | void rtw_set_ips_deny23a(struct rtw_adapter *padapter, u32 ms); | ||
| 256 | int _rtw_pwr_wakeup23a(struct rtw_adapter *padapter, u32 ips_deffer_ms, | ||
| 257 | const char *caller); | ||
| 258 | #define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup23a(adapter, \ | ||
| 259 | RTW_PWR_STATE_CHK_INTERVAL, __func__) | ||
| 260 | #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) \ | ||
| 261 | _rtw_pwr_wakeup23a(adapter, ips_deffer_ms, __func__) | ||
| 262 | int rtw_pm_set_ips23a(struct rtw_adapter *padapter, u8 mode); | ||
| 263 | int rtw_pm_set_lps23a(struct rtw_adapter *padapter, u8 mode); | ||
| 264 | |||
| 265 | #endif /* __RTL871X_PWRCTRL_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_qos.h b/drivers/staging/rtl8723au/include/rtw_qos.h new file mode 100644 index 000000000000..68fc5ba1844a --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_qos.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef _RTW_QOS_H_ | ||
| 17 | #define _RTW_QOS_H_ | ||
| 18 | |||
| 19 | #include <osdep_service.h> | ||
| 20 | |||
| 21 | struct qos_priv { | ||
| 22 | /* bit mask option: u-apsd, s-apsd, ts, block ack... */ | ||
| 23 | unsigned int qos_option; | ||
| 24 | }; | ||
| 25 | |||
| 26 | #endif /* _RTL871X_QOS_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_recv.h b/drivers/staging/rtl8723au/include/rtw_recv.h new file mode 100644 index 000000000000..e2462e052e44 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_recv.h | |||
| @@ -0,0 +1,319 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _RTW_RECV_H_ | ||
| 16 | #define _RTW_RECV_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | #define NR_RECVFRAME 256 | ||
| 22 | |||
| 23 | #define MAX_RXFRAME_CNT 512 | ||
| 24 | #define MAX_RX_NUMBLKS (32) | ||
| 25 | #define RECVFRAME_HDR_ALIGN 128 | ||
| 26 | |||
| 27 | #define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) | ||
| 28 | |||
| 29 | #define MAX_SUBFRAME_COUNT 64 | ||
| 30 | |||
| 31 | /* for Rx reordering buffer control */ | ||
| 32 | struct recv_reorder_ctrl { | ||
| 33 | struct rtw_adapter *padapter; | ||
| 34 | u8 enable; | ||
| 35 | u16 indicate_seq;/* wstart_b, init_value=0xffff */ | ||
| 36 | u16 wend_b; | ||
| 37 | u8 wsize_b; | ||
| 38 | struct rtw_queue pending_recvframe_queue; | ||
| 39 | struct timer_list reordering_ctrl_timer; | ||
| 40 | }; | ||
| 41 | |||
| 42 | struct stainfo_rxcache { | ||
| 43 | u16 tid_rxseq[16]; | ||
| 44 | /* | ||
| 45 | unsigned short tid0_rxseq; | ||
| 46 | unsigned short tid1_rxseq; | ||
| 47 | unsigned short tid2_rxseq; | ||
| 48 | unsigned short tid3_rxseq; | ||
| 49 | unsigned short tid4_rxseq; | ||
| 50 | unsigned short tid5_rxseq; | ||
| 51 | unsigned short tid6_rxseq; | ||
| 52 | unsigned short tid7_rxseq; | ||
| 53 | unsigned short tid8_rxseq; | ||
| 54 | unsigned short tid9_rxseq; | ||
| 55 | unsigned short tid10_rxseq; | ||
| 56 | unsigned short tid11_rxseq; | ||
| 57 | unsigned short tid12_rxseq; | ||
| 58 | unsigned short tid13_rxseq; | ||
| 59 | unsigned short tid14_rxseq; | ||
| 60 | unsigned short tid15_rxseq; | ||
| 61 | */ | ||
| 62 | }; | ||
| 63 | |||
| 64 | struct smooth_rssi_data { | ||
| 65 | u32 elements[100]; /* array to store values */ | ||
| 66 | u32 index; /* index to current array to store */ | ||
| 67 | u32 total_num; /* num of valid elements */ | ||
| 68 | u32 total_val; /* sum of valid elements */ | ||
| 69 | }; | ||
| 70 | |||
| 71 | struct signal_stat { | ||
| 72 | u8 update_req; /* used to indicate */ | ||
| 73 | u8 avg_val; /* avg of valid elements */ | ||
| 74 | u32 total_num; /* num of valid elements */ | ||
| 75 | u32 total_val; /* sum of valid elements */ | ||
| 76 | }; | ||
| 77 | |||
| 78 | #define MAX_PATH_NUM_92CS 2 | ||
| 79 | |||
| 80 | struct phy_info { | ||
| 81 | u8 RxPWDBAll; | ||
| 82 | u8 SignalQuality; /* in 0-100 index. */ | ||
| 83 | u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ | ||
| 84 | u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* 0~100 */ | ||
| 85 | s8 RxPower; /* in dBm Translate from PWdB */ | ||
| 86 | /* Real power in dBm for this packet, no beautification and aggregation. | ||
| 87 | * Keep this raw info to be used for the other procedures. | ||
| 88 | */ | ||
| 89 | s8 RecvSignalPower; | ||
| 90 | u8 BTRxRSSIPercentage; | ||
| 91 | u8 SignalStrength; /* in 0-100 index. */ | ||
| 92 | u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ | ||
| 93 | u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ | ||
| 94 | }; | ||
| 95 | |||
| 96 | |||
| 97 | struct rx_pkt_attrib { | ||
| 98 | u16 pkt_len; | ||
| 99 | u8 physt; | ||
| 100 | u8 drvinfo_sz; | ||
| 101 | u8 shift_sz; | ||
| 102 | u8 hdrlen; /* the WLAN Header Len */ | ||
| 103 | u8 to_fr_ds; | ||
| 104 | u8 amsdu; | ||
| 105 | u8 qos; | ||
| 106 | u8 priority; | ||
| 107 | u8 pw_save; | ||
| 108 | u8 mdata; | ||
| 109 | u16 seq_num; | ||
| 110 | u8 frag_num; | ||
| 111 | u8 mfrag; | ||
| 112 | u8 order; | ||
| 113 | u8 privacy; /* in frame_ctrl field */ | ||
| 114 | u8 bdecrypted; | ||
| 115 | /* when 0 indicate no encrypt. when non-zero, indicate the algorith */ | ||
| 116 | u8 encrypt; | ||
| 117 | u8 iv_len; | ||
| 118 | u8 icv_len; | ||
| 119 | u8 crc_err; | ||
| 120 | u8 icv_err; | ||
| 121 | |||
| 122 | u16 eth_type; | ||
| 123 | |||
| 124 | u8 dst[ETH_ALEN]; | ||
| 125 | u8 src[ETH_ALEN]; | ||
| 126 | u8 ta[ETH_ALEN]; | ||
| 127 | u8 ra[ETH_ALEN]; | ||
| 128 | u8 bssid[ETH_ALEN]; | ||
| 129 | |||
| 130 | u8 ack_policy; | ||
| 131 | |||
| 132 | u8 tcpchk_valid; /* 0: invalid, 1: valid */ | ||
| 133 | u8 ip_chkrpt; /* 0: incorrect, 1: correct */ | ||
| 134 | u8 tcp_chkrpt; /* 0: incorrect, 1: correct */ | ||
| 135 | u8 key_index; | ||
| 136 | |||
| 137 | u8 mcs_rate; | ||
| 138 | u8 rxht; | ||
| 139 | u8 sgi; | ||
| 140 | u8 pkt_rpt_type; | ||
| 141 | u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */ | ||
| 142 | struct phy_info phy_info; | ||
| 143 | }; | ||
| 144 | |||
| 145 | /* These definition is used for Rx packet reordering. */ | ||
| 146 | #define SN_LESS(a, b) (((a-b) & 0x800) != 0) | ||
| 147 | #define SN_EQUAL(a, b) (a == b) | ||
| 148 | #define REORDER_WAIT_TIME (50) /* (ms) */ | ||
| 149 | |||
| 150 | #define RECVBUFF_ALIGN_SZ 8 | ||
| 151 | |||
| 152 | #define RXDESC_SIZE 24 | ||
| 153 | #define RXDESC_OFFSET RXDESC_SIZE | ||
| 154 | |||
| 155 | struct recv_stat { | ||
| 156 | unsigned int rxdw0; | ||
| 157 | unsigned int rxdw1; | ||
| 158 | unsigned int rxdw2; | ||
| 159 | unsigned int rxdw3; | ||
| 160 | unsigned int rxdw4; | ||
| 161 | unsigned int rxdw5; | ||
| 162 | }; | ||
| 163 | |||
| 164 | /* accesser of recv_priv: rtw_recv_entry23a(dispatch / passive level); \ | ||
| 165 | * recv_thread(passive) ; returnpkt(dispatch) ; halt(passive) ; | ||
| 166 | * | ||
| 167 | * using enter_critical section to protect | ||
| 168 | */ | ||
| 169 | struct recv_priv { | ||
| 170 | spinlock_t lock; | ||
| 171 | |||
| 172 | struct rtw_queue free_recv_queue; | ||
| 173 | struct rtw_queue recv_pending_queue; | ||
| 174 | struct rtw_queue uc_swdec_pending_queue; | ||
| 175 | |||
| 176 | void *pallocated_frame_buf; | ||
| 177 | |||
| 178 | uint free_recvframe_cnt; | ||
| 179 | |||
| 180 | struct rtw_adapter *adapter; | ||
| 181 | |||
| 182 | u32 bIsAnyNonBEPkts; | ||
| 183 | u64 rx_bytes; | ||
| 184 | u64 rx_pkts; | ||
| 185 | u64 rx_drop; | ||
| 186 | u64 last_rx_bytes; | ||
| 187 | |||
| 188 | uint rx_icv_err; | ||
| 189 | uint rx_largepacket_crcerr; | ||
| 190 | uint rx_smallpacket_crcerr; | ||
| 191 | uint rx_middlepacket_crcerr; | ||
| 192 | |||
| 193 | /* u8 *pallocated_urb_buf; */ | ||
| 194 | struct semaphore allrxreturnevt; | ||
| 195 | uint ff_hwaddr; | ||
| 196 | u8 rx_pending_cnt; | ||
| 197 | |||
| 198 | struct urb *int_in_urb; | ||
| 199 | |||
| 200 | u8 *int_in_buf; | ||
| 201 | |||
| 202 | struct tasklet_struct irq_prepare_beacon_tasklet; | ||
| 203 | struct tasklet_struct recv_tasklet; | ||
| 204 | struct sk_buff_head free_recv_skb_queue; | ||
| 205 | struct sk_buff_head rx_skb_queue; | ||
| 206 | u8 *precv_buf; | ||
| 207 | struct rtw_queue free_recv_buf_queue; | ||
| 208 | u32 free_recv_buf_queue_cnt; | ||
| 209 | |||
| 210 | /* For display the phy informatiom */ | ||
| 211 | u8 is_signal_dbg; /* for debug */ | ||
| 212 | u8 signal_strength_dbg; /* for debug */ | ||
| 213 | s8 rssi; | ||
| 214 | s8 rxpwdb; | ||
| 215 | u8 signal_strength; | ||
| 216 | u8 signal_qual; | ||
| 217 | u8 noise; | ||
| 218 | int RxSNRdB[2]; | ||
| 219 | s8 RxRssi[2]; | ||
| 220 | int FalseAlmCnt_all; | ||
| 221 | |||
| 222 | struct timer_list signal_stat_timer; | ||
| 223 | u32 signal_stat_sampling_interval; | ||
| 224 | /* u32 signal_stat_converging_constant; */ | ||
| 225 | struct signal_stat signal_qual_data; | ||
| 226 | struct signal_stat signal_strength_data; | ||
| 227 | }; | ||
| 228 | |||
| 229 | #define rtw_set_signal_stat_timer(recvpriv) \ | ||
| 230 | mod_timer(&(recvpriv)->signal_stat_timer, jiffies + \ | ||
| 231 | msecs_to_jiffies((recvpriv)->signal_stat_sampling_interval)) | ||
| 232 | |||
| 233 | struct sta_recv_priv { | ||
| 234 | spinlock_t lock; | ||
| 235 | int option; | ||
| 236 | |||
| 237 | /* struct rtw_queue blk_strms[MAX_RX_NUMBLKS]; */ | ||
| 238 | struct rtw_queue defrag_q; /* keeping the fragment frame until defrag */ | ||
| 239 | |||
| 240 | struct stainfo_rxcache rxcache; | ||
| 241 | |||
| 242 | /* uint sta_rx_bytes; */ | ||
| 243 | /* uint sta_rx_pkts; */ | ||
| 244 | /* uint sta_rx_fail; */ | ||
| 245 | |||
| 246 | }; | ||
| 247 | |||
| 248 | |||
| 249 | struct recv_buf { | ||
| 250 | struct list_head list; | ||
| 251 | |||
| 252 | struct rtw_adapter *adapter; | ||
| 253 | |||
| 254 | struct urb *purb; | ||
| 255 | struct sk_buff *pskb; | ||
| 256 | }; | ||
| 257 | |||
| 258 | /* head -----> | ||
| 259 | * | ||
| 260 | * data -----> | ||
| 261 | * | ||
| 262 | * payload | ||
| 263 | * | ||
| 264 | * tail -----> | ||
| 265 | * | ||
| 266 | * end -----> | ||
| 267 | * | ||
| 268 | * len = (unsigned int )(tail - data); | ||
| 269 | * | ||
| 270 | */ | ||
| 271 | struct recv_frame { | ||
| 272 | struct list_head list; | ||
| 273 | struct sk_buff *pkt; | ||
| 274 | |||
| 275 | struct rtw_adapter *adapter; | ||
| 276 | |||
| 277 | struct rx_pkt_attrib attrib; | ||
| 278 | |||
| 279 | struct sta_info *psta; | ||
| 280 | |||
| 281 | /* for A-MPDU Rx reordering buffer control */ | ||
| 282 | struct recv_reorder_ctrl *preorder_ctrl; | ||
| 283 | }; | ||
| 284 | |||
| 285 | /* get a free recv_frame from pfree_recv_queue */ | ||
| 286 | struct recv_frame *rtw_alloc_recvframe23a(struct rtw_queue *pfree_recv_queue); | ||
| 287 | int rtw_free_recvframe23a(struct recv_frame *precvframe, struct rtw_queue *pfree_recv_queue); | ||
| 288 | |||
| 289 | int rtw_enqueue_recvframe23a(struct recv_frame *precvframe, struct rtw_queue *queue); | ||
| 290 | |||
| 291 | void rtw_free_recvframe23a_queue(struct rtw_queue *pframequeue, struct rtw_queue *pfree_recv_queue); | ||
| 292 | u32 rtw_free_uc_swdec_pending_queue23a(struct rtw_adapter *adapter); | ||
| 293 | |||
| 294 | int rtw_enqueue_recvbuf23a_to_head(struct recv_buf *precvbuf, struct rtw_queue *queue); | ||
| 295 | int rtw_enqueue_recvbuf23a(struct recv_buf *precvbuf, struct rtw_queue *queue); | ||
| 296 | struct recv_buf *rtw_dequeue_recvbuf23a(struct rtw_queue *queue); | ||
| 297 | |||
| 298 | void rtw_reordering_ctrl_timeout_handler23a(unsigned long pcontext); | ||
| 299 | |||
| 300 | static inline s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) | ||
| 301 | { | ||
| 302 | s32 SignalPower; /* in dBm. */ | ||
| 303 | |||
| 304 | /* Translate to dBm (x=0.5y-95). */ | ||
| 305 | SignalPower = (s32)((SignalStrengthIndex + 1) >> 1); | ||
| 306 | SignalPower -= 95; | ||
| 307 | |||
| 308 | return SignalPower; | ||
| 309 | } | ||
| 310 | |||
| 311 | |||
| 312 | struct sta_info; | ||
| 313 | |||
| 314 | void _rtw_init_sta_recv_priv23a(struct sta_recv_priv *psta_recvpriv); | ||
| 315 | |||
| 316 | void mgt_dispatcher23a(struct rtw_adapter *padapter, | ||
| 317 | struct recv_frame *precv_frame); | ||
| 318 | |||
| 319 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_rf.h b/drivers/staging/rtl8723au/include/rtw_rf.h new file mode 100644 index 000000000000..91a0a22a2709 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_rf.h | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_RF_H_ | ||
| 16 | #define __RTW_RF_H_ | ||
| 17 | |||
| 18 | #include <rtw_cmd.h> | ||
| 19 | |||
| 20 | #define OFDM_PHY 1 | ||
| 21 | #define MIXED_PHY 2 | ||
| 22 | #define CCK_PHY 3 | ||
| 23 | |||
| 24 | #define NumRates (13) | ||
| 25 | |||
| 26 | /* slot time for 11g */ | ||
| 27 | #define SHORT_SLOT_TIME 9 | ||
| 28 | #define NON_SHORT_SLOT_TIME 20 | ||
| 29 | |||
| 30 | /* We now define the max channels in each channel plan. */ | ||
| 31 | #define MAX_CHANNEL_NUM_2G 14 | ||
| 32 | #define MAX_CHANNEL_NUM_5G 24 | ||
| 33 | #define MAX_CHANNEL_NUM 38/* 14+24 */ | ||
| 34 | |||
| 35 | /* define NUM_REGULATORYS 21 */ | ||
| 36 | #define NUM_REGULATORYS 1 | ||
| 37 | |||
| 38 | /* Country codes */ | ||
| 39 | #define USA 0x555320 | ||
| 40 | #define EUROPE 0x1 /* temp, should be provided later */ | ||
| 41 | #define JAPAN 0x2 /* temp, should be provided later */ | ||
| 42 | |||
| 43 | struct regulatory_class { | ||
| 44 | u32 starting_freq; /* MHz, */ | ||
| 45 | u8 channel_set[MAX_CHANNEL_NUM]; | ||
| 46 | u8 channel_cck_power[MAX_CHANNEL_NUM];/* dbm */ | ||
| 47 | u8 channel_ofdm_power[MAX_CHANNEL_NUM];/* dbm */ | ||
| 48 | u8 txpower_limit; /* dbm */ | ||
| 49 | u8 channel_spacing; /* MHz */ | ||
| 50 | u8 modem; | ||
| 51 | }; | ||
| 52 | |||
| 53 | enum { | ||
| 54 | cESS = 0x0001, | ||
| 55 | cIBSS = 0x0002, | ||
| 56 | cPollable = 0x0004, | ||
| 57 | cPollReq = 0x0008, | ||
| 58 | cPrivacy = 0x0010, | ||
| 59 | cShortPreamble = 0x0020, | ||
| 60 | cPBCC = 0x0040, | ||
| 61 | cChannelAgility = 0x0080, | ||
| 62 | cSpectrumMgnt = 0x0100, | ||
| 63 | cQos = 0x0200, /* For HCCA, use with CF-Pollable and CF-PollReq */ | ||
| 64 | cShortSlotTime = 0x0400, | ||
| 65 | cAPSD = 0x0800, | ||
| 66 | cRM = 0x1000, /* RRM (Radio Request Measurement) */ | ||
| 67 | cDSSS_OFDM = 0x2000, | ||
| 68 | cDelayedBA = 0x4000, | ||
| 69 | cImmediateBA = 0x8000, | ||
| 70 | }; | ||
| 71 | |||
| 72 | enum { | ||
| 73 | PREAMBLE_LONG = 1, | ||
| 74 | PREAMBLE_AUTO = 2, | ||
| 75 | PREAMBLE_SHORT = 3, | ||
| 76 | }; | ||
| 77 | |||
| 78 | /* Bandwidth Offset */ | ||
| 79 | #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 | ||
| 80 | #define HAL_PRIME_CHNL_OFFSET_LOWER 1 | ||
| 81 | #define HAL_PRIME_CHNL_OFFSET_UPPER 2 | ||
| 82 | |||
| 83 | /* Represent Channel Width in HT Capabilities */ | ||
| 84 | enum ht_channel_width { | ||
| 85 | HT_CHANNEL_WIDTH_20 = 0, | ||
| 86 | HT_CHANNEL_WIDTH_40 = 1, | ||
| 87 | HT_CHANNEL_WIDTH_80 = 2, | ||
| 88 | HT_CHANNEL_WIDTH_160 = 3, | ||
| 89 | HT_CHANNEL_WIDTH_10 = 4, | ||
| 90 | }; | ||
| 91 | |||
| 92 | /* */ | ||
| 93 | /* Represent Extention Channel Offset in HT Capabilities */ | ||
| 94 | /* This is available only in 40Mhz mode. */ | ||
| 95 | /* */ | ||
| 96 | enum { | ||
| 97 | HT_EXTCHNL_OFFSET_NO_EXT = 0, | ||
| 98 | HT_EXTCHNL_OFFSET_UPPER = 1, | ||
| 99 | HT_EXTCHNL_OFFSET_NO_DEF = 2, | ||
| 100 | HT_EXTCHNL_OFFSET_LOWER = 3, | ||
| 101 | }; | ||
| 102 | |||
| 103 | /* 2007/11/15 MH Define different RF type. */ | ||
| 104 | enum { | ||
| 105 | RF_1T2R = 0, | ||
| 106 | RF_2T4R = 1, | ||
| 107 | RF_2T2R = 2, | ||
| 108 | RF_1T1R = 3, | ||
| 109 | RF_2T2R_GREEN = 4, | ||
| 110 | RF_819X_MAX_TYPE = 5, | ||
| 111 | }; | ||
| 112 | |||
| 113 | #endif /* _RTL8711_RF_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_security.h b/drivers/staging/rtl8723au/include/rtw_security.h new file mode 100644 index 000000000000..75bbb934a53c --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_security.h | |||
| @@ -0,0 +1,357 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __RTW_SECURITY_H_ | ||
| 16 | #define __RTW_SECURITY_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | |||
| 22 | #define _NO_PRIVACY_ 0x0 | ||
| 23 | #define _WEP40_ 0x1 | ||
| 24 | #define _TKIP_ 0x2 | ||
| 25 | #define _TKIP_WTMIC_ 0x3 | ||
| 26 | #define _AES_ 0x4 | ||
| 27 | #define _WEP104_ 0x5 | ||
| 28 | #define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */ | ||
| 29 | #define _SMS4_ 0x06 | ||
| 30 | |||
| 31 | #define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) | ||
| 32 | |||
| 33 | #define _WPA_IE_ID_ 0xdd | ||
| 34 | #define _WPA2_IE_ID_ 0x30 | ||
| 35 | |||
| 36 | #define SHA256_MAC_LEN 32 | ||
| 37 | #define AES_BLOCK_SIZE 16 | ||
| 38 | #define AES_PRIV_SIZE (4 * 44) | ||
| 39 | |||
| 40 | enum ENCRYP_PROTOCOL { | ||
| 41 | ENCRYP_PROTOCOL_OPENSYS, /* open system */ | ||
| 42 | ENCRYP_PROTOCOL_WEP, /* WEP */ | ||
| 43 | ENCRYP_PROTOCOL_WPA, /* WPA */ | ||
| 44 | ENCRYP_PROTOCOL_WPA2, /* WPA2 */ | ||
| 45 | ENCRYP_PROTOCOL_MAX | ||
| 46 | }; | ||
| 47 | |||
| 48 | #ifndef Ndis802_11AuthModeWPA2 | ||
| 49 | #define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) | ||
| 50 | #endif | ||
| 51 | |||
| 52 | #ifndef Ndis802_11AuthModeWPA2PSK | ||
| 53 | #define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | union pn48 { | ||
| 57 | u64 val; | ||
| 58 | |||
| 59 | #ifdef __LITTLE_ENDIAN | ||
| 60 | |||
| 61 | struct { | ||
| 62 | u8 TSC0; | ||
| 63 | u8 TSC1; | ||
| 64 | u8 TSC2; | ||
| 65 | u8 TSC3; | ||
| 66 | u8 TSC4; | ||
| 67 | u8 TSC5; | ||
| 68 | u8 TSC6; | ||
| 69 | u8 TSC7; | ||
| 70 | } _byte_; | ||
| 71 | |||
| 72 | #elif defined(__BIG_ENDIAN) | ||
| 73 | |||
| 74 | struct { | ||
| 75 | u8 TSC7; | ||
| 76 | u8 TSC6; | ||
| 77 | u8 TSC5; | ||
| 78 | u8 TSC4; | ||
| 79 | u8 TSC3; | ||
| 80 | u8 TSC2; | ||
| 81 | u8 TSC1; | ||
| 82 | u8 TSC0; | ||
| 83 | } _byte_; | ||
| 84 | #else | ||
| 85 | #error Need BIG or LITTLE endian | ||
| 86 | |||
| 87 | #endif | ||
| 88 | |||
| 89 | }; | ||
| 90 | |||
| 91 | union Keytype { | ||
| 92 | u8 skey[16]; | ||
| 93 | u32 lkey[4]; | ||
| 94 | }; | ||
| 95 | |||
| 96 | |||
| 97 | struct rt_pmkid_list { | ||
| 98 | u8 bUsed; | ||
| 99 | u8 Bssid[6]; | ||
| 100 | u8 PMKID[16]; | ||
| 101 | u8 SsidBuf[33]; | ||
| 102 | u8 *ssid_octet; | ||
| 103 | u16 ssid_length; | ||
| 104 | }; | ||
| 105 | |||
| 106 | struct security_priv { | ||
| 107 | u32 dot11AuthAlgrthm; /* 802.11 auth, could be open, shared, | ||
| 108 | * 8021x and authswitch */ | ||
| 109 | u32 dot11PrivacyAlgrthm; /* This specifies the privacy for | ||
| 110 | * shared auth. algorithm. | ||
| 111 | */ | ||
| 112 | /* WEP */ | ||
| 113 | u32 dot11PrivacyKeyIndex; /* this is only valid for legendary | ||
| 114 | * wep, 0~3 for key id. (tx key index) | ||
| 115 | */ | ||
| 116 | union Keytype dot11DefKey[4]; /* this is only valid for def. key */ | ||
| 117 | u32 dot11DefKeylen[4]; | ||
| 118 | |||
| 119 | u32 dot118021XGrpPrivacy; /* specify the privacy algthm. | ||
| 120 | * used for Grp key | ||
| 121 | */ | ||
| 122 | u32 dot118021XGrpKeyid; /* key id used for Grp Key | ||
| 123 | * (tx key index) | ||
| 124 | */ | ||
| 125 | union Keytype dot118021XGrpKey[4];/* 802.1x Grp Key, inx0 and inx1 */ | ||
| 126 | union Keytype dot118021XGrptxmickey[4]; | ||
| 127 | union Keytype dot118021XGrprxmickey[4]; | ||
| 128 | union pn48 dot11Grptxpn; /* PN48 used for Grp Key xmit.*/ | ||
| 129 | union pn48 dot11Grprxpn; /* PN48 used for Grp Key recv.*/ | ||
| 130 | |||
| 131 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 132 | /* extend security capabilities for AP_MODE */ | ||
| 133 | unsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */ | ||
| 134 | unsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */ | ||
| 135 | unsigned int wpa_group_cipher; | ||
| 136 | unsigned int wpa2_group_cipher; | ||
| 137 | unsigned int wpa_pairwise_cipher; | ||
| 138 | unsigned int wpa2_pairwise_cipher; | ||
| 139 | #endif | ||
| 140 | |||
| 141 | u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */ | ||
| 142 | int wps_ie_len; | ||
| 143 | u8 binstallGrpkey; | ||
| 144 | u8 busetkipkey; | ||
| 145 | u8 bcheck_grpkey; | ||
| 146 | u8 bgrpkey_handshake; | ||
| 147 | s32 hw_decrypted; | ||
| 148 | u32 ndisauthtype; /* enum ndis_802_11_auth_mode */ | ||
| 149 | u32 ndisencryptstatus; /* NDIS_802_11_ENCRYPTION_STATUS */ | ||
| 150 | struct wlan_bssid_ex sec_bss; /* for joinbss (h2c buffer) usage */ | ||
| 151 | struct ndis_802_11_wep ndiswep; | ||
| 152 | u8 assoc_info[600]; | ||
| 153 | u8 szofcapability[256]; /* for wpa2 usage */ | ||
| 154 | u8 oidassociation[512]; /* for wpa/wpa2 usage */ | ||
| 155 | u8 authenticator_ie[256]; /* store ap security information element */ | ||
| 156 | u8 supplicant_ie[256]; /* store sta security information element */ | ||
| 157 | |||
| 158 | /* for tkip countermeasure */ | ||
| 159 | unsigned long last_mic_err_time; | ||
| 160 | u8 btkip_countermeasure; | ||
| 161 | u8 btkip_wait_report; | ||
| 162 | unsigned long btkip_countermeasure_time; | ||
| 163 | |||
| 164 | /* For WPA2 Pre-Authentication. */ | ||
| 165 | struct rt_pmkid_list PMKIDList[NUM_PMKID_CACHE]; | ||
| 166 | u8 PMKIDIndex; | ||
| 167 | u8 bWepDefaultKeyIdxSet; | ||
| 168 | }; | ||
| 169 | |||
| 170 | struct sha256_state { | ||
| 171 | u64 length; | ||
| 172 | u32 state[8], curlen; | ||
| 173 | u8 buf[64]; | ||
| 174 | }; | ||
| 175 | |||
| 176 | #define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\ | ||
| 177 | do {\ | ||
| 178 | switch (psecuritypriv->dot11AuthAlgrthm) {\ | ||
| 179 | case dot11AuthAlgrthm_Open:\ | ||
| 180 | case dot11AuthAlgrthm_Shared:\ | ||
| 181 | case dot11AuthAlgrthm_Auto:\ | ||
| 182 | encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ | ||
| 183 | break;\ | ||
| 184 | case dot11AuthAlgrthm_8021X:\ | ||
| 185 | if (bmcst)\ | ||
| 186 | encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\ | ||
| 187 | else\ | ||
| 188 | encry_algo = (u8)psta->dot118021XPrivacy;\ | ||
| 189 | break;\ | ||
| 190 | } \ | ||
| 191 | } while (0) | ||
| 192 | |||
| 193 | #define GET_TKIP_PN(iv, dot11txpn)\ | ||
| 194 | do {\ | ||
| 195 | dot11txpn._byte_.TSC0 = iv[2];\ | ||
| 196 | dot11txpn._byte_.TSC1 = iv[0];\ | ||
| 197 | dot11txpn._byte_.TSC2 = iv[4];\ | ||
| 198 | dot11txpn._byte_.TSC3 = iv[5];\ | ||
| 199 | dot11txpn._byte_.TSC4 = iv[6];\ | ||
| 200 | dot11txpn._byte_.TSC5 = iv[7];\ | ||
| 201 | } while (0) | ||
| 202 | |||
| 203 | #define ROL32(A, n) (((A) << (n)) | (((A)>>(32-(n))) & ((1UL << (n)) - 1))) | ||
| 204 | #define ROR32(A, n) ROL32((A), 32-(n)) | ||
| 205 | |||
| 206 | struct mic_data { | ||
| 207 | u32 K0, K1; /* Key */ | ||
| 208 | u32 L, R; /* Current state */ | ||
| 209 | u32 M; /* Message accumulator (single word) */ | ||
| 210 | u32 nBytesInM; /* # bytes in M */ | ||
| 211 | }; | ||
| 212 | |||
| 213 | extern const u32 Te0[256]; | ||
| 214 | extern const u32 Te1[256]; | ||
| 215 | extern const u32 Te2[256]; | ||
| 216 | extern const u32 Te3[256]; | ||
| 217 | extern const u32 Te4[256]; | ||
| 218 | extern const u32 Td0[256]; | ||
| 219 | extern const u32 Td1[256]; | ||
| 220 | extern const u32 Td2[256]; | ||
| 221 | extern const u32 Td3[256]; | ||
| 222 | extern const u32 Td4[256]; | ||
| 223 | extern const u32 rcon[10]; | ||
| 224 | extern const u8 Td4s[256]; | ||
| 225 | extern const u8 rcons[10]; | ||
| 226 | |||
| 227 | #define RCON(i) (rcons[(i)] << 24) | ||
| 228 | |||
| 229 | static inline u32 rotr(u32 val, int bits) | ||
| 230 | { | ||
| 231 | return (val >> bits) | (val << (32 - bits)); | ||
| 232 | } | ||
| 233 | |||
| 234 | #define TE0(i) Te0[((i) >> 24) & 0xff] | ||
| 235 | #define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) | ||
| 236 | #define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) | ||
| 237 | #define TE3(i) rotr(Te0[(i) & 0xff], 24) | ||
| 238 | #define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000) | ||
| 239 | #define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000) | ||
| 240 | #define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00) | ||
| 241 | #define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff) | ||
| 242 | #define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000) | ||
| 243 | #define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000) | ||
| 244 | #define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00) | ||
| 245 | #define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff) | ||
| 246 | #define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff) | ||
| 247 | |||
| 248 | #define TD0(i) Td0[((i) >> 24) & 0xff] | ||
| 249 | #define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8) | ||
| 250 | #define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16) | ||
| 251 | #define TD3(i) rotr(Td0[(i) & 0xff], 24) | ||
| 252 | #define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24) | ||
| 253 | #define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16) | ||
| 254 | #define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8) | ||
| 255 | #define TD44(i) (Td4s[(i) & 0xff]) | ||
| 256 | #define TD0_(i) Td0[(i) & 0xff] | ||
| 257 | #define TD1_(i) rotr(Td0[(i) & 0xff], 8) | ||
| 258 | #define TD2_(i) rotr(Td0[(i) & 0xff], 16) | ||
| 259 | #define TD3_(i) rotr(Td0[(i) & 0xff], 24) | ||
| 260 | |||
| 261 | #define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \ | ||
| 262 | ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3])) | ||
| 263 | |||
| 264 | #define PUTU32(ct, st) { \ | ||
| 265 | (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \ | ||
| 266 | (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); } | ||
| 267 | |||
| 268 | #define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ | ||
| 269 | (((u32) (a)[2]) << 8) | ((u32) (a)[3])) | ||
| 270 | |||
| 271 | #define WPA_PUT_LE16(a, val) \ | ||
| 272 | do { \ | ||
| 273 | (a)[1] = ((u16) (val)) >> 8; \ | ||
| 274 | (a)[0] = ((u16) (val)) & 0xff; \ | ||
| 275 | } while (0) | ||
| 276 | |||
| 277 | #define WPA_PUT_BE32(a, val) \ | ||
| 278 | do { \ | ||
| 279 | (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ | ||
| 280 | (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ | ||
| 281 | (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ | ||
| 282 | (a)[3] = (u8) (((u32) (val)) & 0xff); \ | ||
| 283 | } while (0) | ||
| 284 | |||
| 285 | #define WPA_PUT_BE64(a, val) \ | ||
| 286 | do { \ | ||
| 287 | (a)[0] = (u8) (((u64) (val)) >> 56); \ | ||
| 288 | (a)[1] = (u8) (((u64) (val)) >> 48); \ | ||
| 289 | (a)[2] = (u8) (((u64) (val)) >> 40); \ | ||
| 290 | (a)[3] = (u8) (((u64) (val)) >> 32); \ | ||
| 291 | (a)[4] = (u8) (((u64) (val)) >> 24); \ | ||
| 292 | (a)[5] = (u8) (((u64) (val)) >> 16); \ | ||
| 293 | (a)[6] = (u8) (((u64) (val)) >> 8); \ | ||
| 294 | (a)[7] = (u8) (((u64) (val)) & 0xff); \ | ||
| 295 | } while (0) | ||
| 296 | |||
| 297 | /* ===== start - public domain SHA256 implementation ===== */ | ||
| 298 | |||
| 299 | /* This is based on SHA256 implementation in LibTomCrypt that was released into | ||
| 300 | * public domain by Tom St Denis. */ | ||
| 301 | |||
| 302 | /* the K array */ | ||
| 303 | static const unsigned long K[64] = { | ||
| 304 | 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, | ||
| 305 | 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, | ||
| 306 | 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, | ||
| 307 | 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, | ||
| 308 | 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, | ||
| 309 | 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, | ||
| 310 | 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, | ||
| 311 | 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, | ||
| 312 | 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, | ||
| 313 | 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, | ||
| 314 | 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, | ||
| 315 | 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, | ||
| 316 | 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL | ||
| 317 | }; | ||
| 318 | |||
| 319 | /* Various logical functions */ | ||
| 320 | #define RORc(x, y) \ | ||
| 321 | (((((unsigned long)(x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \ | ||
| 322 | ((unsigned long)(x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL) | ||
| 323 | #define Ch(x, y, z) (z ^ (x & (y ^ z))) | ||
| 324 | #define Maj(x, y, z) (((x | y) & z) | (x & y)) | ||
| 325 | #define S(x, n) RORc((x), (n)) | ||
| 326 | #define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) | ||
| 327 | #define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) | ||
| 328 | #define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) | ||
| 329 | #define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) | ||
| 330 | #define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) | ||
| 331 | #ifndef MIN | ||
| 332 | #define MIN(x, y) (((x) < (y)) ? (x) : (y)) | ||
| 333 | #endif | ||
| 334 | |||
| 335 | void rtw_secmicsetkey23a(struct mic_data *pmicdata, u8 *key); | ||
| 336 | void rtw_secmicappend23abyte23a(struct mic_data *pmicdata, u8 b); | ||
| 337 | void rtw_secmicappend23a(struct mic_data *pmicdata, u8 *src, u32 nbBytes); | ||
| 338 | void rtw_secgetmic23a(struct mic_data *pmicdata, u8 *dst); | ||
| 339 | |||
| 340 | void rtw_seccalctkipmic23a(u8 *key, u8 *header, u8 *data, u32 data_len, | ||
| 341 | u8 *Miccode, u8 priorityi); | ||
| 342 | |||
| 343 | u32 rtw_aes_encrypt23a(struct rtw_adapter *padapter, | ||
| 344 | struct xmit_frame *pxmitframe); | ||
| 345 | u32 rtw_tkip_encrypt23a(struct rtw_adapter *padapter, | ||
| 346 | struct xmit_frame *pxmitframe); | ||
| 347 | void rtw_wep_encrypt23a(struct rtw_adapter *padapter, | ||
| 348 | struct xmit_frame *pxmitframe); | ||
| 349 | u32 rtw_aes_decrypt23a(struct rtw_adapter *padapter, | ||
| 350 | struct recv_frame *precvframe); | ||
| 351 | u32 rtw_tkip_decrypt23a(struct rtw_adapter *padapter, | ||
| 352 | struct recv_frame *precvframe); | ||
| 353 | void rtw_wep_decrypt23a(struct rtw_adapter *padapter, struct recv_frame *precvframe); | ||
| 354 | |||
| 355 | void rtw_use_tkipkey_handler23a(void *FunctionContext); | ||
| 356 | |||
| 357 | #endif /* __RTL871X_SECURITY_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_sreset.h b/drivers/staging/rtl8723au/include/rtw_sreset.h new file mode 100644 index 000000000000..4c523722dd14 --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_sreset.h | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _RTW_SRESET_C_ | ||
| 16 | #define _RTW_SRESET_C_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | enum { | ||
| 22 | SRESET_TGP_NULL = 0, | ||
| 23 | SRESET_TGP_XMIT_STATUS = 1, | ||
| 24 | SRESET_TGP_LINK_STATUS = 2, | ||
| 25 | }; | ||
| 26 | |||
| 27 | struct sreset_priv { | ||
| 28 | struct mutex silentreset_mutex; | ||
| 29 | u8 silent_reset_inprogress; | ||
| 30 | u8 Wifi_Error_Status; | ||
| 31 | unsigned long last_tx_time; | ||
| 32 | unsigned long last_tx_complete_time; | ||
| 33 | |||
| 34 | s32 dbg_trigger_point; | ||
| 35 | }; | ||
| 36 | |||
| 37 | #include <rtl8723a_hal.h> | ||
| 38 | |||
| 39 | #define WIFI_STATUS_SUCCESS 0 | ||
| 40 | #define USB_VEN_REQ_CMD_FAIL BIT0 | ||
| 41 | #define USB_READ_PORT_FAIL BIT1 | ||
| 42 | #define USB_WRITE_PORT_FAIL BIT2 | ||
| 43 | #define WIFI_MAC_TXDMA_ERROR BIT3 | ||
| 44 | #define WIFI_TX_HANG BIT4 | ||
| 45 | #define WIFI_RX_HANG BIT5 | ||
| 46 | #define WIFI_IF_NOT_EXIST BIT6 | ||
| 47 | |||
| 48 | void sreset_init_value23a(struct rtw_adapter *padapter); | ||
| 49 | void sreset_reset_value23a(struct rtw_adapter *padapter); | ||
| 50 | u8 sreset_get_wifi_status23a(struct rtw_adapter *padapter); | ||
| 51 | void sreset_set_wifi_error_status23a(struct rtw_adapter *padapter, u32 status); | ||
| 52 | void sreset_set_trigger_point(struct rtw_adapter *padapter, s32 tgp); | ||
| 53 | bool sreset_inprogress(struct rtw_adapter *padapter); | ||
| 54 | void sreset_reset(struct rtw_adapter *padapter); | ||
| 55 | |||
| 56 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/rtw_version.h b/drivers/staging/rtl8723au/include/rtw_version.h new file mode 100644 index 000000000000..c947733a3e3e --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_version.h | |||
| @@ -0,0 +1 @@ | |||
| #define DRIVERVERSION "v4.1.6_7336.20130426" | |||
diff --git a/drivers/staging/rtl8723au/include/rtw_xmit.h b/drivers/staging/rtl8723au/include/rtw_xmit.h new file mode 100644 index 000000000000..65a33a07c8ee --- /dev/null +++ b/drivers/staging/rtl8723au/include/rtw_xmit.h | |||
| @@ -0,0 +1,407 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _RTW_XMIT_H_ | ||
| 16 | #define _RTW_XMIT_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | #define MAX_XMITBUF_SZ 2048 | ||
| 22 | #define NR_XMITBUFF 4 | ||
| 23 | |||
| 24 | #define XMITBUF_ALIGN_SZ 512 | ||
| 25 | |||
| 26 | /* xmit extension buff defination */ | ||
| 27 | #define MAX_XMIT_EXTBUF_SZ 1536 | ||
| 28 | #define NR_XMIT_EXTBUFF 32 | ||
| 29 | |||
| 30 | #define MAX_NUMBLKS 1 | ||
| 31 | |||
| 32 | #define XMIT_VO_QUEUE 0 | ||
| 33 | #define XMIT_VI_QUEUE 1 | ||
| 34 | #define XMIT_BE_QUEUE 2 | ||
| 35 | #define XMIT_BK_QUEUE 3 | ||
| 36 | |||
| 37 | #define VO_QUEUE_INX 0 | ||
| 38 | #define VI_QUEUE_INX 1 | ||
| 39 | #define BE_QUEUE_INX 2 | ||
| 40 | #define BK_QUEUE_INX 3 | ||
| 41 | #define BCN_QUEUE_INX 4 | ||
| 42 | #define MGT_QUEUE_INX 5 | ||
| 43 | #define HIGH_QUEUE_INX 6 | ||
| 44 | #define TXCMD_QUEUE_INX 7 | ||
| 45 | |||
| 46 | #define HW_QUEUE_ENTRY 8 | ||
| 47 | |||
| 48 | #define WEP_IV(pattrib_iv, dot11txpn, keyidx) \ | ||
| 49 | do { \ | ||
| 50 | pattrib_iv[0] = dot11txpn._byte_.TSC0; \ | ||
| 51 | pattrib_iv[1] = dot11txpn._byte_.TSC1; \ | ||
| 52 | pattrib_iv[2] = dot11txpn._byte_.TSC2; \ | ||
| 53 | pattrib_iv[3] = ((keyidx & 0x3) << 6); \ | ||
| 54 | dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : \ | ||
| 55 | (dot11txpn.val+1); \ | ||
| 56 | } while (0) | ||
| 57 | |||
| 58 | #define TKIP_IV(pattrib_iv, dot11txpn, keyidx) \ | ||
| 59 | do { \ | ||
| 60 | pattrib_iv[0] = dot11txpn._byte_.TSC1; \ | ||
| 61 | pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f; \ | ||
| 62 | pattrib_iv[2] = dot11txpn._byte_.TSC0; \ | ||
| 63 | pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6); \ | ||
| 64 | pattrib_iv[4] = dot11txpn._byte_.TSC2; \ | ||
| 65 | pattrib_iv[5] = dot11txpn._byte_.TSC3; \ | ||
| 66 | pattrib_iv[6] = dot11txpn._byte_.TSC4; \ | ||
| 67 | pattrib_iv[7] = dot11txpn._byte_.TSC5; \ | ||
| 68 | dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : \ | ||
| 69 | (dot11txpn.val+1); \ | ||
| 70 | } while (0) | ||
| 71 | |||
| 72 | #define AES_IV(pattrib_iv, dot11txpn, keyidx)\ | ||
| 73 | do { \ | ||
| 74 | pattrib_iv[0] = dot11txpn._byte_.TSC0; \ | ||
| 75 | pattrib_iv[1] = dot11txpn._byte_.TSC1; \ | ||
| 76 | pattrib_iv[2] = 0; \ | ||
| 77 | pattrib_iv[3] = BIT(5) | ((keyidx & 0x3) << 6); \ | ||
| 78 | pattrib_iv[4] = dot11txpn._byte_.TSC2; \ | ||
| 79 | pattrib_iv[5] = dot11txpn._byte_.TSC3; \ | ||
| 80 | pattrib_iv[6] = dot11txpn._byte_.TSC4; \ | ||
| 81 | pattrib_iv[7] = dot11txpn._byte_.TSC5; \ | ||
| 82 | dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : \ | ||
| 83 | (dot11txpn.val+1); \ | ||
| 84 | } while (0) | ||
| 85 | |||
| 86 | #define HWXMIT_ENTRY 4 | ||
| 87 | |||
| 88 | #define TXDESC_SIZE 32 | ||
| 89 | |||
| 90 | #define PACKET_OFFSET_SZ 8 | ||
| 91 | #define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ) | ||
| 92 | |||
| 93 | struct tx_desc { | ||
| 94 | /* DWORD 0 */ | ||
| 95 | unsigned int txdw0; | ||
| 96 | unsigned int txdw1; | ||
| 97 | unsigned int txdw2; | ||
| 98 | unsigned int txdw3; | ||
| 99 | unsigned int txdw4; | ||
| 100 | unsigned int txdw5; | ||
| 101 | unsigned int txdw6; | ||
| 102 | unsigned int txdw7; | ||
| 103 | }; | ||
| 104 | |||
| 105 | union txdesc { | ||
| 106 | struct tx_desc txdesc; | ||
| 107 | unsigned int value[TXDESC_SIZE>>2]; | ||
| 108 | }; | ||
| 109 | |||
| 110 | struct hw_xmit { | ||
| 111 | struct rtw_queue *sta_queue; | ||
| 112 | int accnt; | ||
| 113 | }; | ||
| 114 | |||
| 115 | /* reduce size */ | ||
| 116 | struct pkt_attrib { | ||
| 117 | u8 type; | ||
| 118 | u8 subtype; | ||
| 119 | u8 bswenc; | ||
| 120 | u8 dhcp_pkt; | ||
| 121 | u16 ether_type; | ||
| 122 | u16 seqnum; | ||
| 123 | u16 pkt_hdrlen; /* the original 802.3 pkt header len */ | ||
| 124 | u16 hdrlen; /* the WLAN Header Len */ | ||
| 125 | u32 pktlen; /* the original 802.3 pkt raw_data len */ | ||
| 126 | u32 last_txcmdsz; | ||
| 127 | u8 nr_frags; | ||
| 128 | u8 encrypt; /* when 0 indicate no encrypt. */ | ||
| 129 | u8 iv_len; | ||
| 130 | u8 icv_len; | ||
| 131 | u8 iv[18]; | ||
| 132 | u8 icv[16]; | ||
| 133 | u8 priority; | ||
| 134 | u8 ack_policy; | ||
| 135 | u8 mac_id; | ||
| 136 | u8 vcs_mode; /* virtual carrier sense method */ | ||
| 137 | u8 dst[ETH_ALEN]; | ||
| 138 | u8 src[ETH_ALEN]; | ||
| 139 | u8 ta[ETH_ALEN]; | ||
| 140 | u8 ra[ETH_ALEN]; | ||
| 141 | u8 key_idx; | ||
| 142 | u8 qos_en; | ||
| 143 | u8 ht_en; | ||
| 144 | u8 raid;/* rate adpative id */ | ||
| 145 | u8 bwmode; | ||
| 146 | u8 ch_offset;/* PRIME_CHNL_OFFSET */ | ||
| 147 | u8 sgi;/* short GI */ | ||
| 148 | u8 ampdu_en;/* tx ampdu enable */ | ||
| 149 | u8 mdata;/* more data bit */ | ||
| 150 | u8 pctrl;/* per packet txdesc control enable */ | ||
| 151 | u8 triggered;/* for ap mode handling Power Saving sta */ | ||
| 152 | u8 qsel; | ||
| 153 | u8 eosp; | ||
| 154 | u8 rate; | ||
| 155 | u8 retry_ctrl; | ||
| 156 | struct sta_info *psta; | ||
| 157 | }; | ||
| 158 | |||
| 159 | #define WLANHDR_OFFSET 64 | ||
| 160 | |||
| 161 | #define NULL_FRAMETAG 0x0 | ||
| 162 | #define DATA_FRAMETAG 0x01 | ||
| 163 | #define L2_FRAMETAG 0x02 | ||
| 164 | #define MGNT_FRAMETAG 0x03 | ||
| 165 | #define AMSDU_FRAMETAG 0x04 | ||
| 166 | |||
| 167 | #define EII_FRAMETAG 0x05 | ||
| 168 | #define IEEE8023_FRAMETAG 0x06 | ||
| 169 | |||
| 170 | #define MP_FRAMETAG 0x07 | ||
| 171 | |||
| 172 | #define TXAGG_FRAMETAG 0x08 | ||
| 173 | |||
| 174 | struct submit_ctx { | ||
| 175 | u32 timeout_ms; /* <0: not synchronous, 0: wait forever, | ||
| 176 | * >0: up to ms waiting | ||
| 177 | */ | ||
| 178 | int status; /* status for operation */ | ||
| 179 | struct completion done; | ||
| 180 | }; | ||
| 181 | |||
| 182 | enum { | ||
| 183 | RTW_SCTX_SUBMITTED = -1, | ||
| 184 | RTW_SCTX_DONE_SUCCESS = 0, | ||
| 185 | RTW_SCTX_DONE_UNKNOWN, | ||
| 186 | RTW_SCTX_DONE_TIMEOUT, | ||
| 187 | RTW_SCTX_DONE_BUF_ALLOC, | ||
| 188 | RTW_SCTX_DONE_BUF_FREE, | ||
| 189 | RTW_SCTX_DONE_WRITE_PORT_ERR, | ||
| 190 | RTW_SCTX_DONE_TX_DESC_NA, | ||
| 191 | RTW_SCTX_DONE_TX_DENY, | ||
| 192 | RTW_SCTX_DONE_CCX_PKT_FAIL, | ||
| 193 | RTW_SCTX_DONE_DRV_STOP, | ||
| 194 | RTW_SCTX_DONE_DEV_REMOVE, | ||
| 195 | }; | ||
| 196 | |||
| 197 | void rtw_sctx_init23a(struct submit_ctx *sctx, int timeout_ms); | ||
| 198 | int rtw_sctx_wait23a(struct submit_ctx *sctx); | ||
| 199 | void rtw23a_sctx_done_err(struct submit_ctx **sctx, int status); | ||
| 200 | void rtw_sctx_done23a(struct submit_ctx **sctx); | ||
| 201 | |||
| 202 | struct xmit_buf { | ||
| 203 | struct list_head list, list2; | ||
| 204 | struct rtw_adapter *padapter; | ||
| 205 | |||
| 206 | u8 *pallocated_buf; | ||
| 207 | u8 *pbuf; | ||
| 208 | void *priv_data; | ||
| 209 | |||
| 210 | u16 ext_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf. */ | ||
| 211 | u16 flags; | ||
| 212 | u32 alloc_sz; | ||
| 213 | u32 len; | ||
| 214 | struct submit_ctx *sctx; | ||
| 215 | u32 ff_hwaddr; | ||
| 216 | struct urb *pxmit_urb[8]; | ||
| 217 | u8 bpending[8]; | ||
| 218 | int last[8]; | ||
| 219 | #if defined(DBG_XMIT_BUF) || defined(DBG_XMIT_BUF_EXT) | ||
| 220 | u8 no; | ||
| 221 | #endif | ||
| 222 | }; | ||
| 223 | |||
| 224 | struct xmit_frame { | ||
| 225 | struct list_head list; | ||
| 226 | struct pkt_attrib attrib; | ||
| 227 | struct sk_buff *pkt; | ||
| 228 | int frame_tag; | ||
| 229 | struct rtw_adapter *padapter; | ||
| 230 | u8 *buf_addr; | ||
| 231 | struct xmit_buf *pxmitbuf; | ||
| 232 | |||
| 233 | s8 pkt_offset; | ||
| 234 | |||
| 235 | u8 ack_report; | ||
| 236 | |||
| 237 | u8 ext_tag; /* 0:data, 1:mgmt */ | ||
| 238 | }; | ||
| 239 | |||
| 240 | struct tx_servq { | ||
| 241 | struct list_head tx_pending; | ||
| 242 | struct rtw_queue sta_pending; | ||
| 243 | int qcnt; | ||
| 244 | }; | ||
| 245 | |||
| 246 | struct sta_xmit_priv { | ||
| 247 | spinlock_t lock; | ||
| 248 | int option; | ||
| 249 | int apsd_setting; /* When bit mask is on, the associated edca | ||
| 250 | * queue supports APSD. | ||
| 251 | */ | ||
| 252 | struct tx_servq be_q; /* priority == 0,3 */ | ||
| 253 | struct tx_servq bk_q; /* priority == 1,2 */ | ||
| 254 | struct tx_servq vi_q; /* priority == 4,5 */ | ||
| 255 | struct tx_servq vo_q; /* priority == 6,7 */ | ||
| 256 | struct list_head legacy_dz; | ||
| 257 | struct list_head apsd; | ||
| 258 | u16 txseq_tid[16]; | ||
| 259 | }; | ||
| 260 | |||
| 261 | struct hw_txqueue { | ||
| 262 | volatile int head; | ||
| 263 | volatile int tail; | ||
| 264 | volatile int free_sz; /* in units of 64 bytes */ | ||
| 265 | volatile int free_cmdsz; | ||
| 266 | volatile int txsz[8]; | ||
| 267 | uint ff_hwaddr; | ||
| 268 | uint cmd_hwaddr; | ||
| 269 | int ac_tag; | ||
| 270 | }; | ||
| 271 | |||
| 272 | struct agg_pkt_info { | ||
| 273 | u16 offset; | ||
| 274 | u16 pkt_len; | ||
| 275 | }; | ||
| 276 | |||
| 277 | struct xmit_priv { | ||
| 278 | spinlock_t lock; | ||
| 279 | |||
| 280 | struct semaphore xmit_sema; | ||
| 281 | struct semaphore terminate_xmitthread_sema; | ||
| 282 | |||
| 283 | struct rtw_queue be_pending; | ||
| 284 | struct rtw_queue bk_pending; | ||
| 285 | struct rtw_queue vi_pending; | ||
| 286 | struct rtw_queue vo_pending; | ||
| 287 | struct rtw_queue bm_pending; | ||
| 288 | |||
| 289 | u8 *pallocated_frame_buf; | ||
| 290 | u8 *pxmit_frame_buf; | ||
| 291 | uint free_xmitframe_cnt; | ||
| 292 | struct rtw_queue free_xmit_queue; | ||
| 293 | |||
| 294 | u8 *xframe_ext_alloc_addr; | ||
| 295 | u8 *xframe_ext; | ||
| 296 | uint free_xframe_ext_cnt; | ||
| 297 | struct rtw_queue free_xframe_ext_queue; | ||
| 298 | |||
| 299 | uint frag_len; | ||
| 300 | |||
| 301 | struct rtw_adapter *adapter; | ||
| 302 | |||
| 303 | u8 vcs_setting; | ||
| 304 | u8 vcs; | ||
| 305 | u8 vcs_type; | ||
| 306 | |||
| 307 | u64 tx_bytes; | ||
| 308 | u64 tx_pkts; | ||
| 309 | u64 tx_drop; | ||
| 310 | u64 last_tx_bytes; | ||
| 311 | u64 last_tx_pkts; | ||
| 312 | |||
| 313 | struct hw_xmit *hwxmits; | ||
| 314 | u8 hwxmit_entry; | ||
| 315 | |||
| 316 | u8 wmm_para_seq[4];/* sequence for wmm ac parameter strength from | ||
| 317 | * large to small. it's value is 0->vo, 1->vi, | ||
| 318 | * 2->be, 3->bk. | ||
| 319 | */ | ||
| 320 | |||
| 321 | struct semaphore tx_retevt;/* all tx return event; */ | ||
| 322 | u8 txirp_cnt;/* */ | ||
| 323 | |||
| 324 | struct tasklet_struct xmit_tasklet; | ||
| 325 | /* per AC pending irp */ | ||
| 326 | int beq_cnt; | ||
| 327 | int bkq_cnt; | ||
| 328 | int viq_cnt; | ||
| 329 | int voq_cnt; | ||
| 330 | |||
| 331 | struct rtw_queue free_xmitbuf_queue; | ||
| 332 | struct list_head xmitbuf_list; /* track buffers for cleanup */ | ||
| 333 | struct rtw_queue pending_xmitbuf_queue; | ||
| 334 | uint free_xmitbuf_cnt; | ||
| 335 | |||
| 336 | struct rtw_queue free_xmit_extbuf_queue; | ||
| 337 | struct list_head xmitextbuf_list; /* track buffers for cleanup */ | ||
| 338 | uint free_xmit_extbuf_cnt; | ||
| 339 | |||
| 340 | u16 nqos_ssn; | ||
| 341 | int ack_tx; | ||
| 342 | struct mutex ack_tx_mutex; | ||
| 343 | struct submit_ctx ack_tx_ops; | ||
| 344 | spinlock_t lock_sctx; | ||
| 345 | }; | ||
| 346 | |||
| 347 | struct xmit_buf *rtw_alloc_xmitbuf23a_ext(struct xmit_priv *pxmitpriv); | ||
| 348 | s32 rtw_free_xmitbuf_ext23a(struct xmit_priv *pxmitpriv, | ||
| 349 | struct xmit_buf *pxmitbuf); | ||
| 350 | |||
| 351 | struct xmit_buf *rtw_alloc_xmitbuf23a(struct xmit_priv *pxmitpriv); | ||
| 352 | s32 rtw_free_xmitbuf23a(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); | ||
| 353 | |||
| 354 | void rtw_count_tx_stats23a(struct rtw_adapter *padapter, | ||
| 355 | struct xmit_frame *pxmitframe, int sz); | ||
| 356 | void rtw_update_protection23a(struct rtw_adapter *padapter, u8 *ie, uint ie_len); | ||
| 357 | s32 rtw_make_wlanhdr23a(struct rtw_adapter *padapter, u8 *hdr, | ||
| 358 | struct pkt_attrib *pattrib); | ||
| 359 | s32 rtw_put_snap23a(u8 *data, u16 h_proto); | ||
| 360 | struct xmit_frame *rtw_alloc_xmitframe23a(struct xmit_priv *pxmitpriv); | ||
| 361 | struct xmit_frame *rtw_alloc_xmitframe23a_ext(struct xmit_priv *pxmitpriv); | ||
| 362 | struct xmit_frame *rtw_alloc_xmitframe23a_once(struct xmit_priv *pxmitpriv); | ||
| 363 | s32 rtw_free_xmitframe23a(struct xmit_priv *pxmitpriv, | ||
| 364 | struct xmit_frame *pxmitframe); | ||
| 365 | void rtw_free_xmitframe_queue23a(struct xmit_priv *pxmitpriv, struct rtw_queue *pframequeue); | ||
| 366 | struct tx_servq *rtw_get_sta_pending23a(struct rtw_adapter *padapter, | ||
| 367 | struct sta_info *psta, int up, u8 *ac); | ||
| 368 | s32 rtw_xmitframe_enqueue23a(struct rtw_adapter *padapter, | ||
| 369 | struct xmit_frame *pxmitframe); | ||
| 370 | struct xmit_frame *rtw_dequeue_xframe23a(struct xmit_priv *pxmitpriv, | ||
| 371 | struct hw_xmit *phwxmit_i, int entry); | ||
| 372 | s32 rtw_xmit23a_classifier(struct rtw_adapter *padapter, | ||
| 373 | struct xmit_frame *pxmitframe); | ||
| 374 | u32 rtw_calculate_wlan_pkt_size_by_attribue23a(struct pkt_attrib *pattrib); | ||
| 375 | #define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue23a(&f->attrib) | ||
| 376 | s32 rtw_xmitframe_coalesce23a(struct rtw_adapter *padapter, struct sk_buff *pkt, | ||
| 377 | struct xmit_frame *pxmitframe); | ||
| 378 | s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag); | ||
| 379 | void _rtw_init_sta_xmit_priv23a(struct sta_xmit_priv *psta_xmitpriv); | ||
| 380 | |||
| 381 | s32 rtw_txframes_pending23a(struct rtw_adapter *padapter); | ||
| 382 | s32 rtw_txframes_sta_ac_pending23a(struct rtw_adapter *padapter, | ||
| 383 | struct pkt_attrib *pattrib); | ||
| 384 | void rtw_init_hwxmits23a(struct hw_xmit *phwxmit, int entry); | ||
| 385 | s32 _rtw_init_xmit_priv23a(struct xmit_priv *pxmitpriv, | ||
| 386 | struct rtw_adapter *padapter); | ||
| 387 | void _rtw_free_xmit_priv23a(struct xmit_priv *pxmitpriv); | ||
| 388 | void rtw_alloc_hwxmits23a(struct rtw_adapter *padapter); | ||
| 389 | void rtw_free_hwxmits23a(struct rtw_adapter *padapter); | ||
| 390 | int rtw_xmit23a(struct rtw_adapter *padapter, struct sk_buff *pkt); | ||
| 391 | #if defined(CONFIG_8723AU_AP_MODE) | ||
| 392 | int xmitframe_enqueue_for_sleeping_sta23a(struct rtw_adapter *padapter, | ||
| 393 | struct xmit_frame *pxmitframe); | ||
| 394 | void stop_sta_xmit23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 395 | void wakeup_sta_to_xmit23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 396 | void xmit_delivery_enabled_frames23a(struct rtw_adapter *padapter, | ||
| 397 | struct sta_info *psta); | ||
| 398 | #endif | ||
| 399 | u8 qos_acm23a(u8 acm_mask, u8 priority); | ||
| 400 | u32 rtw_get_ff_hwaddr23a(struct xmit_frame *pxmitframe); | ||
| 401 | int rtw_ack_tx_wait23a(struct xmit_priv *pxmitpriv, u32 timeout_ms); | ||
| 402 | void rtw_ack_tx_done23a(struct xmit_priv *pxmitpriv, int status); | ||
| 403 | |||
| 404 | /* include after declaring struct xmit_buf, in order to avoid warning */ | ||
| 405 | #include <xmit_osdep.h> | ||
| 406 | |||
| 407 | #endif /* _RTL871X_XMIT_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/sta_info.h b/drivers/staging/rtl8723au/include/sta_info.h new file mode 100644 index 000000000000..8af98ee77b07 --- /dev/null +++ b/drivers/staging/rtl8723au/include/sta_info.h | |||
| @@ -0,0 +1,396 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __STA_INFO_H_ | ||
| 16 | #define __STA_INFO_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | #include <wifi.h> | ||
| 21 | |||
| 22 | #define IBSS_START_MAC_ID 2 | ||
| 23 | #define NUM_STA 32 | ||
| 24 | #define NUM_ACL 16 | ||
| 25 | |||
| 26 | |||
| 27 | /* if mode ==0, then the sta is allowed once the addr is hit. */ | ||
| 28 | /* if mode ==1, then the sta is rejected once the addr is non-hit. */ | ||
| 29 | struct rtw_wlan_acl_node { | ||
| 30 | struct list_head list; | ||
| 31 | u8 addr[ETH_ALEN]; | ||
| 32 | u8 valid; | ||
| 33 | }; | ||
| 34 | |||
| 35 | /* mode=0, disable */ | ||
| 36 | /* mode=1, accept unless in deny list */ | ||
| 37 | /* mode=2, deny unless in accept list */ | ||
| 38 | struct wlan_acl_pool { | ||
| 39 | int mode; | ||
| 40 | int num; | ||
| 41 | struct rtw_wlan_acl_node aclnode[NUM_ACL]; | ||
| 42 | struct rtw_queue acl_node_q; | ||
| 43 | }; | ||
| 44 | |||
| 45 | struct rssi_sta { | ||
| 46 | s32 UndecoratedSmoothedPWDB; | ||
| 47 | s32 UndecoratedSmoothedCCK; | ||
| 48 | s32 UndecoratedSmoothedOFDM; | ||
| 49 | u64 PacketMap; | ||
| 50 | u8 ValidBit; | ||
| 51 | }; | ||
| 52 | |||
| 53 | struct stainfo_stats { | ||
| 54 | u64 rx_mgnt_pkts; | ||
| 55 | u64 rx_beacon_pkts; | ||
| 56 | u64 rx_probereq_pkts; | ||
| 57 | u64 rx_probersp_pkts; | ||
| 58 | u64 rx_probersp_bm_pkts; | ||
| 59 | u64 rx_probersp_uo_pkts; | ||
| 60 | u64 rx_ctrl_pkts; | ||
| 61 | u64 rx_data_pkts; | ||
| 62 | |||
| 63 | u64 last_rx_mgnt_pkts; | ||
| 64 | u64 last_rx_beacon_pkts; | ||
| 65 | u64 last_rx_probereq_pkts; | ||
| 66 | u64 last_rx_probersp_pkts; | ||
| 67 | u64 last_rx_probersp_bm_pkts; | ||
| 68 | u64 last_rx_probersp_uo_pkts; | ||
| 69 | u64 last_rx_ctrl_pkts; | ||
| 70 | u64 last_rx_data_pkts; | ||
| 71 | |||
| 72 | u64 rx_bytes; | ||
| 73 | u64 rx_drops; | ||
| 74 | |||
| 75 | u64 tx_pkts; | ||
| 76 | u64 tx_bytes; | ||
| 77 | u64 tx_drops; | ||
| 78 | |||
| 79 | }; | ||
| 80 | |||
| 81 | struct sta_info { | ||
| 82 | spinlock_t lock; | ||
| 83 | struct list_head list; /* free_sta_queue */ | ||
| 84 | struct list_head hash_list; /* sta_hash */ | ||
| 85 | struct rtw_adapter *padapter; | ||
| 86 | |||
| 87 | struct sta_xmit_priv sta_xmitpriv; | ||
| 88 | struct sta_recv_priv sta_recvpriv; | ||
| 89 | |||
| 90 | struct rtw_queue sleep_q; | ||
| 91 | unsigned int sleepq_len; | ||
| 92 | |||
| 93 | uint state; | ||
| 94 | uint aid; | ||
| 95 | uint mac_id; | ||
| 96 | uint qos_option; | ||
| 97 | u8 hwaddr[ETH_ALEN]; | ||
| 98 | |||
| 99 | uint ieee8021x_blocked; /* 0: allowed, 1:blocked */ | ||
| 100 | uint dot118021XPrivacy; /* aes, tkip... */ | ||
| 101 | union Keytype dot11tkiptxmickey; | ||
| 102 | union Keytype dot11tkiprxmickey; | ||
| 103 | union Keytype dot118021x_UncstKey; | ||
| 104 | union pn48 dot11txpn; /* PN48 used for Unicast xmit. */ | ||
| 105 | union pn48 dot11rxpn; /* PN48 used for Unicast recv. */ | ||
| 106 | |||
| 107 | |||
| 108 | u8 bssrateset[16]; | ||
| 109 | u32 bssratelen; | ||
| 110 | s32 rssi; | ||
| 111 | s32 signal_quality; | ||
| 112 | |||
| 113 | u8 cts2self; | ||
| 114 | u8 rtsen; | ||
| 115 | |||
| 116 | u8 raid; | ||
| 117 | u8 init_rate; | ||
| 118 | u32 ra_mask; | ||
| 119 | u8 wireless_mode; /* NETWORK_TYPE */ | ||
| 120 | struct stainfo_stats sta_stats; | ||
| 121 | |||
| 122 | /* for A-MPDU TX, ADDBA timeout check */ | ||
| 123 | struct timer_list addba_retry_timer; | ||
| 124 | |||
| 125 | /* for A-MPDU Rx reordering buffer control */ | ||
| 126 | struct recv_reorder_ctrl recvreorder_ctrl[16]; | ||
| 127 | |||
| 128 | /* for A-MPDU Tx */ | ||
| 129 | /* unsigned char ampdu_txen_bitmap; */ | ||
| 130 | u16 BA_starting_seqctrl[16]; | ||
| 131 | |||
| 132 | struct ht_priv htpriv; | ||
| 133 | |||
| 134 | /* Notes: */ | ||
| 135 | /* STA_Mode: */ | ||
| 136 | /* curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO */ | ||
| 137 | /* scan_q: AP CAP/INFO */ | ||
| 138 | |||
| 139 | /* AP_Mode: */ | ||
| 140 | /* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */ | ||
| 141 | /* sta_info: (AP & STA) CAP/INFO */ | ||
| 142 | |||
| 143 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 144 | |||
| 145 | struct list_head asoc_list; | ||
| 146 | struct list_head auth_list; | ||
| 147 | |||
| 148 | unsigned int expire_to; | ||
| 149 | unsigned int auth_seq; | ||
| 150 | unsigned int authalg; | ||
| 151 | unsigned char chg_txt[128]; | ||
| 152 | |||
| 153 | u16 capability; | ||
| 154 | int flags; | ||
| 155 | |||
| 156 | int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */ | ||
| 157 | int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */ | ||
| 158 | int wpa_group_cipher; | ||
| 159 | int wpa2_group_cipher; | ||
| 160 | int wpa_pairwise_cipher; | ||
| 161 | int wpa2_pairwise_cipher; | ||
| 162 | |||
| 163 | u8 bpairwise_key_installed; | ||
| 164 | |||
| 165 | u8 wpa_ie[32]; | ||
| 166 | |||
| 167 | u8 nonerp_set; | ||
| 168 | u8 no_short_slot_time_set; | ||
| 169 | u8 no_short_preamble_set; | ||
| 170 | u8 no_ht_gf_set; | ||
| 171 | u8 no_ht_set; | ||
| 172 | u8 ht_20mhz_set; | ||
| 173 | |||
| 174 | unsigned int tx_ra_bitmap; | ||
| 175 | u8 qos_info; | ||
| 176 | |||
| 177 | u8 max_sp_len; | ||
| 178 | u8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */ | ||
| 179 | u8 uapsd_be; | ||
| 180 | u8 uapsd_vi; | ||
| 181 | u8 uapsd_vo; | ||
| 182 | |||
| 183 | u8 has_legacy_ac; | ||
| 184 | unsigned int sleepq_ac_len; | ||
| 185 | |||
| 186 | #ifdef CONFIG_8723AU_P2P | ||
| 187 | /* p2p priv data */ | ||
| 188 | u8 is_p2p_device; | ||
| 189 | u8 p2p_status_code; | ||
| 190 | |||
| 191 | /* p2p client info */ | ||
| 192 | u8 dev_addr[ETH_ALEN]; | ||
| 193 | u8 dev_cap; | ||
| 194 | u16 config_methods; | ||
| 195 | u8 primary_dev_type[8]; | ||
| 196 | u8 num_of_secdev_type; | ||
| 197 | u8 secdev_types_list[32];/* 32/8 == 4; */ | ||
| 198 | u16 dev_name_len; | ||
| 199 | u8 dev_name[32]; | ||
| 200 | #endif /* CONFIG_8723AU_P2P */ | ||
| 201 | |||
| 202 | u8 keep_alive_trycnt; | ||
| 203 | |||
| 204 | #endif /* CONFIG_8723AU_AP_MODE */ | ||
| 205 | |||
| 206 | u8 *passoc_req; | ||
| 207 | u32 assoc_req_len; | ||
| 208 | |||
| 209 | /* for DM */ | ||
| 210 | struct rssi_sta rssi_stat; | ||
| 211 | |||
| 212 | /* */ | ||
| 213 | /* ================ODM Relative Info======================= */ | ||
| 214 | /* Please be care, dont declare too much structure here. It will cost memory * STA support num. */ | ||
| 215 | /* */ | ||
| 216 | /* */ | ||
| 217 | /* 2011/10/20 MH Add for ODM STA info. */ | ||
| 218 | /* */ | ||
| 219 | /* Driver Write */ | ||
| 220 | u8 bValid; /* record the sta status link or not? */ | ||
| 221 | u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ | ||
| 222 | u8 rssi_level; /* for Refresh RA mask */ | ||
| 223 | /* ODM Write */ | ||
| 224 | /* 1 PHY_STATUS_INFO */ | ||
| 225 | u8 RSSI_Path[4]; /* */ | ||
| 226 | u8 RSSI_Ave; | ||
| 227 | u8 RXEVM[4]; | ||
| 228 | u8 RXSNR[4]; | ||
| 229 | |||
| 230 | /* ODM Write */ | ||
| 231 | /* 1 TX_INFO (may changed by IC) */ | ||
| 232 | /* ================ODM Relative Info======================= */ | ||
| 233 | /* */ | ||
| 234 | |||
| 235 | /* To store the sequence number of received management frame */ | ||
| 236 | u16 RxMgmtFrameSeqNum; | ||
| 237 | }; | ||
| 238 | |||
| 239 | #define sta_rx_pkts(sta) \ | ||
| 240 | (sta->sta_stats.rx_mgnt_pkts \ | ||
| 241 | + sta->sta_stats.rx_ctrl_pkts \ | ||
| 242 | + sta->sta_stats.rx_data_pkts) | ||
| 243 | |||
| 244 | #define sta_last_rx_pkts(sta) \ | ||
| 245 | (sta->sta_stats.last_rx_mgnt_pkts \ | ||
| 246 | + sta->sta_stats.last_rx_ctrl_pkts \ | ||
| 247 | + sta->sta_stats.last_rx_data_pkts) | ||
| 248 | |||
| 249 | #define sta_rx_data_pkts(sta) \ | ||
| 250 | (sta->sta_stats.rx_data_pkts) | ||
| 251 | |||
| 252 | #define sta_last_rx_data_pkts(sta) \ | ||
| 253 | (sta->sta_stats.last_rx_data_pkts) | ||
| 254 | |||
| 255 | #define sta_rx_mgnt_pkts(sta) \ | ||
| 256 | (sta->sta_stats.rx_mgnt_pkts) | ||
| 257 | |||
| 258 | #define sta_last_rx_mgnt_pkts(sta) \ | ||
| 259 | (sta->sta_stats.last_rx_mgnt_pkts) | ||
| 260 | |||
| 261 | #define sta_rx_beacon_pkts(sta) \ | ||
| 262 | (sta->sta_stats.rx_beacon_pkts) | ||
| 263 | |||
| 264 | #define sta_last_rx_beacon_pkts(sta) \ | ||
| 265 | (sta->sta_stats.last_rx_beacon_pkts) | ||
| 266 | |||
| 267 | #define sta_rx_probereq_pkts(sta) \ | ||
| 268 | (sta->sta_stats.rx_probereq_pkts) | ||
| 269 | |||
| 270 | #define sta_last_rx_probereq_pkts(sta) \ | ||
| 271 | (sta->sta_stats.last_rx_probereq_pkts) | ||
| 272 | |||
| 273 | #define sta_rx_probersp_pkts(sta) \ | ||
| 274 | (sta->sta_stats.rx_probersp_pkts) | ||
| 275 | |||
| 276 | #define sta_last_rx_probersp_pkts(sta) \ | ||
| 277 | (sta->sta_stats.last_rx_probersp_pkts) | ||
| 278 | |||
| 279 | #define sta_rx_probersp_bm_pkts(sta) \ | ||
| 280 | (sta->sta_stats.rx_probersp_bm_pkts) | ||
| 281 | |||
| 282 | #define sta_last_rx_probersp_bm_pkts(sta) \ | ||
| 283 | (sta->sta_stats.last_rx_probersp_bm_pkts) | ||
| 284 | |||
| 285 | #define sta_rx_probersp_uo_pkts(sta) \ | ||
| 286 | (sta->sta_stats.rx_probersp_uo_pkts) | ||
| 287 | |||
| 288 | #define sta_last_rx_probersp_uo_pkts(sta) \ | ||
| 289 | (sta->sta_stats.last_rx_probersp_uo_pkts) | ||
| 290 | |||
| 291 | #define sta_update_last_rx_pkts(sta) \ | ||
| 292 | do { \ | ||
| 293 | sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ | ||
| 294 | sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \ | ||
| 295 | sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \ | ||
| 296 | sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \ | ||
| 297 | sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \ | ||
| 298 | sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \ | ||
| 299 | sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ | ||
| 300 | sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ | ||
| 301 | } while (0) | ||
| 302 | |||
| 303 | #define STA_RX_PKTS_ARG(sta) \ | ||
| 304 | sta->sta_stats.rx_mgnt_pkts \ | ||
| 305 | , sta->sta_stats.rx_ctrl_pkts \ | ||
| 306 | , sta->sta_stats.rx_data_pkts | ||
| 307 | |||
| 308 | #define STA_LAST_RX_PKTS_ARG(sta) \ | ||
| 309 | sta->sta_stats.last_rx_mgnt_pkts, \ | ||
| 310 | sta->sta_stats.last_rx_ctrl_pkts, \ | ||
| 311 | sta->sta_stats.last_rx_data_pkts | ||
| 312 | |||
| 313 | #define STA_RX_PKTS_DIFF_ARG(sta) \ | ||
| 314 | sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts, \ | ||
| 315 | sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts, \ | ||
| 316 | sta->sta_stats.rx_data_pkts - sta->sta_stats.last_rx_data_pkts | ||
| 317 | |||
| 318 | #define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" | ||
| 319 | |||
| 320 | struct sta_priv { | ||
| 321 | u8 *pallocated_stainfo_buf; | ||
| 322 | u8 *pstainfo_buf; | ||
| 323 | struct rtw_queue free_sta_queue; | ||
| 324 | |||
| 325 | spinlock_t sta_hash_lock; | ||
| 326 | struct list_head sta_hash[NUM_STA]; | ||
| 327 | int asoc_sta_count; | ||
| 328 | struct rtw_queue sleep_q; | ||
| 329 | struct rtw_queue wakeup_q; | ||
| 330 | |||
| 331 | struct rtw_adapter *padapter; | ||
| 332 | |||
| 333 | |||
| 334 | #ifdef CONFIG_8723AU_AP_MODE | ||
| 335 | struct list_head asoc_list; | ||
| 336 | struct list_head auth_list; | ||
| 337 | spinlock_t asoc_list_lock; | ||
| 338 | spinlock_t auth_list_lock; | ||
| 339 | u8 asoc_list_cnt; | ||
| 340 | u8 auth_list_cnt; | ||
| 341 | |||
| 342 | unsigned int auth_to; /* sec, time to expire in authenticating. */ | ||
| 343 | unsigned int assoc_to; /* sec, time to expire before associating. */ | ||
| 344 | unsigned int expire_to; /* sec , time to expire after associated. */ | ||
| 345 | |||
| 346 | /* pointers to STA info; based on allocated AID or NULL if AID free | ||
| 347 | * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 | ||
| 348 | * and so on | ||
| 349 | */ | ||
| 350 | struct sta_info *sta_aid[NUM_STA]; | ||
| 351 | |||
| 352 | u16 sta_dz_bitmap;/* only support 15 stations, staion aid bitmap | ||
| 353 | * for sleeping sta. */ | ||
| 354 | u16 tim_bitmap;/* only support 15 stations, | ||
| 355 | * aid=0~15 mapping bit0~bit15 */ | ||
| 356 | |||
| 357 | u16 max_num_sta; | ||
| 358 | |||
| 359 | struct wlan_acl_pool acl_list; | ||
| 360 | #endif | ||
| 361 | }; | ||
| 362 | |||
| 363 | static inline u32 wifi_mac_hash(u8 *mac) | ||
| 364 | { | ||
| 365 | u32 x; | ||
| 366 | |||
| 367 | x = mac[0]; | ||
| 368 | x = (x << 2) ^ mac[1]; | ||
| 369 | x = (x << 2) ^ mac[2]; | ||
| 370 | x = (x << 2) ^ mac[3]; | ||
| 371 | x = (x << 2) ^ mac[4]; | ||
| 372 | x = (x << 2) ^ mac[5]; | ||
| 373 | |||
| 374 | x ^= x >> 8; | ||
| 375 | x = x & (NUM_STA - 1); | ||
| 376 | |||
| 377 | return x; | ||
| 378 | } | ||
| 379 | |||
| 380 | u32 _rtw_init_sta_priv23a(struct sta_priv *pstapriv); | ||
| 381 | u32 _rtw_free_sta_priv23a(struct sta_priv *pstapriv); | ||
| 382 | |||
| 383 | #define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0) | ||
| 384 | int rtw_stainfo_offset23a(struct sta_priv *stapriv, struct sta_info *sta); | ||
| 385 | struct sta_info *rtw_get_stainfo23a_by_offset23a(struct sta_priv *stapriv, | ||
| 386 | int offset); | ||
| 387 | |||
| 388 | struct sta_info *rtw_alloc_stainfo23a(struct sta_priv *pstapriv, u8 *hwaddr); | ||
| 389 | u32 rtw_free_stainfo23a(struct rtw_adapter *padapter, struct sta_info *psta); | ||
| 390 | void rtw_free_all_stainfo23a(struct rtw_adapter *padapter); | ||
| 391 | struct sta_info *rtw_get_stainfo23a(struct sta_priv *pstapriv, u8 *hwaddr); | ||
| 392 | u32 rtw_init_bcmc_stainfo23a(struct rtw_adapter *padapter); | ||
| 393 | struct sta_info *rtw_get_bcmc_stainfo23a(struct rtw_adapter *padapter); | ||
| 394 | u8 rtw_access_ctrl23a(struct rtw_adapter *padapter, u8 *mac_addr); | ||
| 395 | |||
| 396 | #endif /* _STA_INFO_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/usb_hal.h b/drivers/staging/rtl8723au/include/usb_hal.h new file mode 100644 index 000000000000..4edec3b539b7 --- /dev/null +++ b/drivers/staging/rtl8723au/include/usb_hal.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __USB_HAL_H__ | ||
| 16 | #define __USB_HAL_H__ | ||
| 17 | |||
| 18 | int rtl8723au_set_hal_ops(struct rtw_adapter *padapter); | ||
| 19 | |||
| 20 | #endif /* __USB_HAL_H__ */ | ||
diff --git a/drivers/staging/rtl8723au/include/usb_ops.h b/drivers/staging/rtl8723au/include/usb_ops.h new file mode 100644 index 000000000000..55d1380f9036 --- /dev/null +++ b/drivers/staging/rtl8723au/include/usb_ops.h | |||
| @@ -0,0 +1,97 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __USB_OPS_H_ | ||
| 16 | #define __USB_OPS_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | #include <osdep_intf.h> | ||
| 21 | #include <usb_ops_linux.h> | ||
| 22 | |||
| 23 | #define REALTEK_USB_VENQT_READ 0xC0 | ||
| 24 | #define REALTEK_USB_VENQT_WRITE 0x40 | ||
| 25 | #define REALTEK_USB_VENQT_CMD_REQ 0x05 | ||
| 26 | #define REALTEK_USB_VENQT_CMD_IDX 0x00 | ||
| 27 | |||
| 28 | enum { | ||
| 29 | VENDOR_WRITE = 0x00, | ||
| 30 | VENDOR_READ = 0x01, | ||
| 31 | }; | ||
| 32 | |||
| 33 | #define ALIGNMENT_UNIT 16 | ||
| 34 | #define MAX_VENDOR_REQ_CMD_SIZE 254 /* 8188cu SIE Support */ | ||
| 35 | #define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE +ALIGNMENT_UNIT) | ||
| 36 | |||
| 37 | #define rtw_usb_control_msg(dev, pipe, request, requesttype, value, \ | ||
| 38 | index, data, size, timeout_ms) \ | ||
| 39 | usb_control_msg((dev), (pipe), (request), (requesttype), \ | ||
| 40 | (value), (index), (data), (size), (timeout_ms)) | ||
| 41 | #define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \ | ||
| 42 | usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \ | ||
| 43 | (timeout_ms)) | ||
| 44 | |||
| 45 | void rtl8723au_set_hw_type(struct rtw_adapter *padapter); | ||
| 46 | #define hal_set_hw_type rtl8723au_set_hw_type | ||
| 47 | |||
| 48 | void rtl8723au_set_intf_ops(struct _io_ops *pops); | ||
| 49 | #define usb_set_intf_ops rtl8723au_set_intf_ops | ||
| 50 | |||
| 51 | void rtl8723au_recv_tasklet(void *priv); | ||
| 52 | |||
| 53 | void rtl8723au_xmit_tasklet(void *priv); | ||
| 54 | |||
| 55 | /* Increase and check if the continual_urb_error of this @param dvobjprive is | ||
| 56 | * larger than MAX_CONTINUAL_URB_ERR. Return result | ||
| 57 | */ | ||
| 58 | static inline int rtw_inc_and_chk_continual_urb_error(struct dvobj_priv *dvobj) | ||
| 59 | { | ||
| 60 | int ret = false; | ||
| 61 | int value; | ||
| 62 | |||
| 63 | value = atomic_inc_return(&dvobj->continual_urb_error); | ||
| 64 | if (value > MAX_CONTINUAL_URB_ERR) { | ||
| 65 | DBG_8723A("[dvobj:%p][ERROR] continual_urb_error:%d > %d\n", | ||
| 66 | dvobj, value, MAX_CONTINUAL_URB_ERR); | ||
| 67 | ret = true; | ||
| 68 | } | ||
| 69 | return ret; | ||
| 70 | } | ||
| 71 | |||
| 72 | /* Set the continual_urb_error of this @param dvobjprive to 0 */ | ||
| 73 | static inline void rtw_reset_continual_urb_error(struct dvobj_priv *dvobj) | ||
| 74 | { | ||
| 75 | atomic_set(&dvobj->continual_urb_error, 0); | ||
| 76 | } | ||
| 77 | |||
| 78 | #define USB_HIGH_SPEED_BULK_SIZE 512 | ||
| 79 | #define USB_FULL_SPEED_BULK_SIZE 64 | ||
| 80 | |||
| 81 | static inline u8 rtw_usb_bulk_size_boundary(struct rtw_adapter *padapter, | ||
| 82 | int buf_len) | ||
| 83 | { | ||
| 84 | u8 rst = true; | ||
| 85 | struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); | ||
| 86 | |||
| 87 | if (pdvobjpriv->ishighspeed) | ||
| 88 | rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE) ? | ||
| 89 | true : false; | ||
| 90 | else | ||
| 91 | rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE) ? | ||
| 92 | true : false; | ||
| 93 | return rst; | ||
| 94 | } | ||
| 95 | |||
| 96 | |||
| 97 | #endif /* __USB_OPS_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/usb_ops_linux.h b/drivers/staging/rtl8723au/include/usb_ops_linux.h new file mode 100644 index 000000000000..8f5c59eace5a --- /dev/null +++ b/drivers/staging/rtl8723au/include/usb_ops_linux.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __USB_OPS_LINUX_H__ | ||
| 16 | #define __USB_OPS_LINUX_H__ | ||
| 17 | |||
| 18 | #define VENDOR_CMD_MAX_DATA_LEN 254 | ||
| 19 | |||
| 20 | #define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10/* ms */ | ||
| 21 | #define RTW_USB_CONTROL_MSG_TIMEOUT 500/* ms */ | ||
| 22 | |||
| 23 | #define MAX_USBCTRL_VENDORREQ_TIMES 10 | ||
| 24 | |||
| 25 | #define RTW_USB_BULKOUT_TIMEOUT 5000/* ms */ | ||
| 26 | |||
| 27 | #define _usbctrl_vendorreq_async_callback(urb, regs) \ | ||
| 28 | _usbctrl_vendorreq_async_callback(urb) | ||
| 29 | #define usb_write_mem23a_complete(purb, regs) usb_write_mem23a_complete(purb) | ||
| 30 | #define usb_write_port23a_complete(purb, regs) usb_write_port23a_complete(purb) | ||
| 31 | #define usb_read_port_complete(purb, regs) usb_read_port_complete(purb) | ||
| 32 | #define usb_read_interrupt_complete(purb, regs) \ | ||
| 33 | usb_read_interrupt_complete(purb) | ||
| 34 | |||
| 35 | unsigned int ffaddr2pipehdl23a(struct dvobj_priv *pdvobj, u32 addr); | ||
| 36 | |||
| 37 | void usb_read_mem23a(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); | ||
| 38 | void usb_write_mem23a(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); | ||
| 39 | |||
| 40 | void usb_read_port_cancel23a(struct intf_hdl *pintfhdl); | ||
| 41 | |||
| 42 | u32 usb_write_port23a(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, | ||
| 43 | struct xmit_buf *wmem); | ||
| 44 | void usb_write_port23a_cancel(struct intf_hdl *pintfhdl); | ||
| 45 | |||
| 46 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/usb_osintf.h b/drivers/staging/rtl8723au/include/usb_osintf.h new file mode 100644 index 000000000000..46087662834e --- /dev/null +++ b/drivers/staging/rtl8723au/include/usb_osintf.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __USB_OSINTF_H | ||
| 16 | #define __USB_OSINTF_H | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | #include <usb_vendor_req.h> | ||
| 21 | |||
| 22 | #define USBD_HALTED(_status) ((u32)(_status) >> 30 == 3) | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/usb_vendor_req.h b/drivers/staging/rtl8723au/include/usb_vendor_req.h new file mode 100644 index 000000000000..eb4508ef191e --- /dev/null +++ b/drivers/staging/rtl8723au/include/usb_vendor_req.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _USB_VENDOR_REQUEST_H_ | ||
| 16 | #define _USB_VENDOR_REQUEST_H_ | ||
| 17 | |||
| 18 | /* 4 Set/Get Register related wIndex/Data */ | ||
| 19 | #define RT_USB_RESET_MASK_OFF 0 | ||
| 20 | #define RT_USB_RESET_MASK_ON 1 | ||
| 21 | #define RT_USB_SLEEP_MASK_OFF 0 | ||
| 22 | #define RT_USB_SLEEP_MASK_ON 1 | ||
| 23 | #define RT_USB_LDO_ON 1 | ||
| 24 | #define RT_USB_LDO_OFF 0 | ||
| 25 | |||
| 26 | /* 4 Set/Get SYSCLK related wValue or Data */ | ||
| 27 | #define RT_USB_SYSCLK_32KHZ 0 | ||
| 28 | #define RT_USB_SYSCLK_40MHZ 1 | ||
| 29 | #define RT_USB_SYSCLK_60MHZ 2 | ||
| 30 | |||
| 31 | #endif | ||
diff --git a/drivers/staging/rtl8723au/include/wifi.h b/drivers/staging/rtl8723au/include/wifi.h new file mode 100644 index 000000000000..b5034c6ef1dc --- /dev/null +++ b/drivers/staging/rtl8723au/include/wifi.h | |||
| @@ -0,0 +1,707 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef _WIFI_H_ | ||
| 16 | #define _WIFI_H_ | ||
| 17 | |||
| 18 | #define P80211CAPTURE_VERSION 0x80211001 | ||
| 19 | |||
| 20 | /* This value is tested by WiFi 11n Test Plan 5.2.3. | ||
| 21 | * This test verifies the WLAN NIC can update the NAV through sending | ||
| 22 | * the CTS with large duration. | ||
| 23 | */ | ||
| 24 | #define WiFiNavUpperUs 30000 /* 30 ms */ | ||
| 25 | |||
| 26 | enum WIFI_FRAME_TYPE { | ||
| 27 | WIFI_MGT_TYPE = (0), | ||
| 28 | WIFI_CTRL_TYPE = (BIT(2)), | ||
| 29 | WIFI_DATA_TYPE = (BIT(3)), | ||
| 30 | WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /* QoS Data */ | ||
| 31 | }; | ||
| 32 | |||
| 33 | enum WIFI_FRAME_SUBTYPE { | ||
| 34 | /* below is for mgt frame */ | ||
| 35 | WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE), | ||
| 36 | WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), | ||
| 37 | WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), | ||
| 38 | WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), | ||
| 39 | WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), | ||
| 40 | WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), | ||
| 41 | WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), | ||
| 42 | WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), | ||
| 43 | WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), | ||
| 44 | WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), | ||
| 45 | WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), | ||
| 46 | WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), | ||
| 47 | |||
| 48 | /* below is for control frame */ | ||
| 49 | WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), | ||
| 50 | WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), | ||
| 51 | WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), | ||
| 52 | WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), | ||
| 53 | WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), | ||
| 54 | WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), | ||
| 55 | |||
| 56 | /* below is for data frame */ | ||
| 57 | WIFI_DATA = (0 | WIFI_DATA_TYPE), | ||
| 58 | WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), | ||
| 59 | WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), | ||
| 60 | WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), | ||
| 61 | WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), | ||
| 62 | WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), | ||
| 63 | WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), | ||
| 64 | WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), | ||
| 65 | WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), | ||
| 66 | }; | ||
| 67 | |||
| 68 | |||
| 69 | enum WIFI_REG_DOMAIN { | ||
| 70 | DOMAIN_FCC = 1, | ||
| 71 | DOMAIN_IC = 2, | ||
| 72 | DOMAIN_ETSI = 3, | ||
| 73 | DOMAIN_SPAIN = 4, | ||
| 74 | DOMAIN_FRANCE = 5, | ||
| 75 | DOMAIN_MKK = 6, | ||
| 76 | DOMAIN_ISRAEL = 7, | ||
| 77 | DOMAIN_MKK1 = 8, | ||
| 78 | DOMAIN_MKK2 = 9, | ||
| 79 | DOMAIN_MKK3 = 10, | ||
| 80 | DOMAIN_MAX | ||
| 81 | }; | ||
| 82 | |||
| 83 | |||
| 84 | #define SetToDs(pbuf) \ | ||
| 85 | (*(unsigned short *)(pbuf) |= cpu_to_le16(IEEE80211_FCTL_TODS)) | ||
| 86 | |||
| 87 | #define SetFrDs(pbuf) \ | ||
| 88 | (*(unsigned short *)(pbuf) |= cpu_to_le16(IEEE80211_FCTL_FROMDS)) | ||
| 89 | |||
| 90 | #define get_tofr_ds(pframe) ((ieee80211_has_tods(pframe) << 1) | \ | ||
| 91 | ieee80211_has_fromds(pframe)) | ||
| 92 | |||
| 93 | #define SetMFrag(pbuf) \ | ||
| 94 | (*(unsigned short *)(pbuf) |= cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) | ||
| 95 | |||
| 96 | #define ClearMFrag(pbuf) \ | ||
| 97 | (*(unsigned short *)(pbuf) &= (~cpu_to_le16(IEEE80211_FCTL_MOREFRAGS))) | ||
| 98 | |||
| 99 | #define SetRetry(pbuf) \ | ||
| 100 | (*(unsigned short *)(pbuf) |= cpu_to_le16(IEEE80211_FCTL_RETRY)) | ||
| 101 | |||
| 102 | #define SetPwrMgt(pbuf) \ | ||
| 103 | (*(unsigned short *)(pbuf) |= cpu_to_le16(IEEE80211_FCTL_PM)) | ||
| 104 | |||
| 105 | #define SetMData(pbuf) \ | ||
| 106 | (*(unsigned short *)(pbuf) |= cpu_to_le16(IEEE80211_FCTL_MOREDATA)) | ||
| 107 | |||
| 108 | #define SetPrivacy(pbuf) \ | ||
| 109 | (*(unsigned short *)(pbuf) |= cpu_to_le16(IEEE80211_FCTL_PROTECTED)) | ||
| 110 | |||
| 111 | #define SetFrameType(pbuf, type) \ | ||
| 112 | do { \ | ||
| 113 | *(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \ | ||
| 114 | *(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \ | ||
| 115 | } while (0) | ||
| 116 | |||
| 117 | #define SetFrameSubType(pbuf, type) \ | ||
| 118 | do { \ | ||
| 119 | *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ | ||
| 120 | *(unsigned short *)(pbuf) |= cpu_to_le16(type); \ | ||
| 121 | } while (0) | ||
| 122 | |||
| 123 | #define GetTupleCache(pbuf) (cpu_to_le16(*(unsigned short *)((unsigned long)(pbuf) + 22))) | ||
| 124 | |||
| 125 | #define SetFragNum(pbuf, num) \ | ||
| 126 | do { \ | ||
| 127 | *(unsigned short *)((unsigned long)(pbuf) + 22) = \ | ||
| 128 | ((*(unsigned short *)((unsigned long)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \ | ||
| 129 | cpu_to_le16(0x0f & (num)); \ | ||
| 130 | } while (0) | ||
| 131 | |||
| 132 | #define SetSeqNum(pbuf, num) \ | ||
| 133 | do { \ | ||
| 134 | *(unsigned short *)((unsigned long)(pbuf) + 22) = \ | ||
| 135 | ((*(unsigned short *)((unsigned long)(pbuf) + 22)) & le16_to_cpu((unsigned short)0x000f)) | \ | ||
| 136 | le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \ | ||
| 137 | } while (0) | ||
| 138 | |||
| 139 | #define SetDuration(pbuf, dur) \ | ||
| 140 | (*(unsigned short *)((unsigned long)(pbuf) + 2) = \ | ||
| 141 | cpu_to_le16(0xffff & (dur))) | ||
| 142 | |||
| 143 | #define SetPriority(pbuf, tid) \ | ||
| 144 | (*(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf)) | ||
| 145 | |||
| 146 | #define SetEOSP(pbuf, eosp) \ | ||
| 147 | (*(unsigned short *)(pbuf) |= cpu_to_le16((eosp & 1) << 4)) | ||
| 148 | |||
| 149 | #define SetAckpolicy(pbuf, ack) \ | ||
| 150 | (*(unsigned short *)(pbuf) |= cpu_to_le16((ack & 3) << 5)) | ||
| 151 | |||
| 152 | #define SetAMsdu(pbuf, amsdu) \ | ||
| 153 | (*(unsigned short *)(pbuf) |= cpu_to_le16((amsdu & 1) << 7)) | ||
| 154 | |||
| 155 | #define GetAid(pbuf) \ | ||
| 156 | (cpu_to_le16(*(unsigned short *)((unsigned long)(pbuf) + 2)) & \ | ||
| 157 | 0x3fff) | ||
| 158 | |||
| 159 | #define GetTid(pbuf) \ | ||
| 160 | (cpu_to_le16(*(unsigned short *)((unsigned long)(pbuf) + \ | ||
| 161 | (((ieee80211_has_tods(pbuf)<<1) | \ | ||
| 162 | ieee80211_has_fromds(pbuf)) == 3 ? 30 : 24))) & 0x000f) | ||
| 163 | |||
| 164 | static inline unsigned char *get_hdr_bssid(unsigned char *pframe) | ||
| 165 | { | ||
| 166 | unsigned char *sa; | ||
| 167 | unsigned int to_fr_ds; | ||
| 168 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) pframe; | ||
| 169 | |||
| 170 | to_fr_ds = (ieee80211_has_tods(hdr->frame_control) << 1) | | ||
| 171 | ieee80211_has_fromds(hdr->frame_control); | ||
| 172 | |||
| 173 | switch (to_fr_ds) { | ||
| 174 | case 0x00: /* ToDs=0, FromDs=0 */ | ||
| 175 | sa = hdr->addr3; | ||
| 176 | break; | ||
| 177 | case 0x01: /* ToDs=0, FromDs=1 */ | ||
| 178 | sa = hdr->addr2; | ||
| 179 | break; | ||
| 180 | case 0x02: /* ToDs=1, FromDs=0 */ | ||
| 181 | sa = hdr->addr1; | ||
| 182 | break; | ||
| 183 | case 0x03: /* ToDs=1, FromDs=1 */ | ||
| 184 | sa = hdr->addr1; | ||
| 185 | break; | ||
| 186 | default: | ||
| 187 | sa = NULL; /* */ | ||
| 188 | break; | ||
| 189 | } | ||
| 190 | return sa; | ||
| 191 | } | ||
| 192 | |||
| 193 | /*----------------------------------------------------------------------------- | ||
| 194 | Below is for the security related definition | ||
| 195 | ------------------------------------------------------------------------------*/ | ||
| 196 | #define _RESERVED_FRAME_TYPE_ 0 | ||
| 197 | #define _SKB_FRAME_TYPE_ 2 | ||
| 198 | #define _PRE_ALLOCMEM_ 1 | ||
| 199 | #define _PRE_ALLOCHDR_ 3 | ||
| 200 | #define _PRE_ALLOCLLCHDR_ 4 | ||
| 201 | #define _PRE_ALLOCICVHDR_ 5 | ||
| 202 | #define _PRE_ALLOCMICHDR_ 6 | ||
| 203 | |||
| 204 | #define _SIFSTIME_ \ | ||
| 205 | ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) ? 16 : 10) | ||
| 206 | #define _ACKCTSLNG_ 14 /* 14 bytes long, including crclng */ | ||
| 207 | #define _CRCLNG_ 4 | ||
| 208 | |||
| 209 | #define _ASOCREQ_IE_OFFSET_ 4 /* excluding wlan_hdr */ | ||
| 210 | #define _ASOCRSP_IE_OFFSET_ 6 | ||
| 211 | #define _REASOCREQ_IE_OFFSET_ 10 | ||
| 212 | #define _REASOCRSP_IE_OFFSET_ 6 | ||
| 213 | #define _PROBEREQ_IE_OFFSET_ 0 | ||
| 214 | #define _PROBERSP_IE_OFFSET_ 12 | ||
| 215 | #define _AUTH_IE_OFFSET_ 6 | ||
| 216 | #define _DEAUTH_IE_OFFSET_ 0 | ||
| 217 | #define _BEACON_IE_OFFSET_ 12 | ||
| 218 | #define _PUBLIC_ACTION_IE_OFFSET_ 8 | ||
| 219 | |||
| 220 | #define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_ | ||
| 221 | |||
| 222 | #define _SSID_IE_ 0 | ||
| 223 | #define _SUPPORTEDRATES_IE_ 1 | ||
| 224 | #define _DSSET_IE_ 3 | ||
| 225 | #define _TIM_IE_ 5 | ||
| 226 | #define _IBSS_PARA_IE_ 6 | ||
| 227 | #define _COUNTRY_IE_ 7 | ||
| 228 | #define _CHLGETXT_IE_ 16 | ||
| 229 | #define _SUPPORTED_CH_IE_ 36 | ||
| 230 | #define _CH_SWTICH_ANNOUNCE_ 37 /* Secondary Channel Offset */ | ||
| 231 | #define _RSN_IE_2_ 48 | ||
| 232 | #define _SSN_IE_1_ 221 | ||
| 233 | #define _ERPINFO_IE_ 42 | ||
| 234 | #define _EXT_SUPPORTEDRATES_IE_ 50 | ||
| 235 | |||
| 236 | #define _HT_CAPABILITY_IE_ 45 | ||
| 237 | #define _FTIE_ 55 | ||
| 238 | #define _TIMEOUT_ITVL_IE_ 56 | ||
| 239 | #define _SRC_IE_ 59 | ||
| 240 | #define _HT_EXTRA_INFO_IE_ 61 | ||
| 241 | #define _HT_ADD_INFO_IE_ 61 /* _HT_EXTRA_INFO_IE_ */ | ||
| 242 | |||
| 243 | |||
| 244 | #define EID_BSSCoexistence 72 /* 20/40 BSS Coexistence */ | ||
| 245 | #define EID_BSSIntolerantChlReport 73 | ||
| 246 | #define _RIC_Descriptor_IE_ 75 | ||
| 247 | |||
| 248 | #define _LINK_ID_IE_ 101 | ||
| 249 | #define _CH_SWITCH_TIMING_ 104 | ||
| 250 | #define _PTI_BUFFER_STATUS_ 106 | ||
| 251 | #define _EXT_CAP_IE_ 127 | ||
| 252 | #define _VENDOR_SPECIFIC_IE_ 221 | ||
| 253 | |||
| 254 | #define _RESERVED47_ 47 | ||
| 255 | |||
| 256 | /* --------------------------------------------------------------------------- | ||
| 257 | Below is the fixed elements... | ||
| 258 | -----------------------------------------------------------------------------*/ | ||
| 259 | #define _AUTH_ALGM_NUM_ 2 | ||
| 260 | #define _AUTH_SEQ_NUM_ 2 | ||
| 261 | #define _BEACON_ITERVAL_ 2 | ||
| 262 | #define _CAPABILITY_ 2 | ||
| 263 | #define _CURRENT_APADDR_ 6 | ||
| 264 | #define _LISTEN_INTERVAL_ 2 | ||
| 265 | #define _ASOC_ID_ 2 | ||
| 266 | #define _STATUS_CODE_ 2 | ||
| 267 | #define _TIMESTAMP_ 8 | ||
| 268 | |||
| 269 | #define AUTH_ODD_TO 0 | ||
| 270 | #define AUTH_EVEN_TO 1 | ||
| 271 | |||
| 272 | #define WLAN_ETHCONV_ENCAP 1 | ||
| 273 | #define WLAN_ETHCONV_RFC1042 2 | ||
| 274 | #define WLAN_ETHCONV_8021h 3 | ||
| 275 | |||
| 276 | #define cap_ESS BIT(0) | ||
| 277 | #define cap_IBSS BIT(1) | ||
| 278 | #define cap_CFPollable BIT(2) | ||
| 279 | #define cap_CFRequest BIT(3) | ||
| 280 | #define cap_Privacy BIT(4) | ||
| 281 | #define cap_ShortPremble BIT(5) | ||
| 282 | #define cap_PBCC BIT(6) | ||
| 283 | #define cap_ChAgility BIT(7) | ||
| 284 | #define cap_SpecMgmt BIT(8) | ||
| 285 | #define cap_QoS BIT(9) | ||
| 286 | #define cap_ShortSlot BIT(10) | ||
| 287 | |||
| 288 | /*----------------------------------------------------------------------------- | ||
| 289 | Below is the definition for 802.11i / 802.1x | ||
| 290 | ------------------------------------------------------------------------------*/ | ||
| 291 | #define _IEEE8021X_MGT_ 1 /* WPA */ | ||
| 292 | #define _IEEE8021X_PSK_ 2 /* WPA with pre-shared key */ | ||
| 293 | |||
| 294 | /* | ||
| 295 | #define _NO_PRIVACY_ 0 | ||
| 296 | #define _WEP_40_PRIVACY_ 1 | ||
| 297 | #define _TKIP_PRIVACY_ 2 | ||
| 298 | #define _WRAP_PRIVACY_ 3 | ||
| 299 | #define _CCMP_PRIVACY_ 4 | ||
| 300 | #define _WEP_104_PRIVACY_ 5 | ||
| 301 | #define _WEP_WPA_MIXED_PRIVACY_ 6 WEP + WPA | ||
| 302 | */ | ||
| 303 | |||
| 304 | /*----------------------------------------------------------------------------- | ||
| 305 | Below is the definition for WMM | ||
| 306 | ------------------------------------------------------------------------------*/ | ||
| 307 | #define _WMM_IE_Length_ 7 /* for WMM STA */ | ||
| 308 | #define _WMM_Para_Element_Length_ 24 | ||
| 309 | |||
| 310 | |||
| 311 | /*----------------------------------------------------------------------------- | ||
| 312 | Below is the definition for 802.11n | ||
| 313 | ------------------------------------------------------------------------------*/ | ||
| 314 | |||
| 315 | #define SetOrderBit(pbuf) \ | ||
| 316 | (*(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_)) | ||
| 317 | |||
| 318 | #define GetOrderBit(pbuf) \ | ||
| 319 | (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) | ||
| 320 | |||
| 321 | |||
| 322 | /* struct rtw_ieee80211_ht_cap - HT additional information | ||
| 323 | * | ||
| 324 | * This structure refers to "HT information element" as | ||
| 325 | * described in 802.11n draft section 7.3.2.53 | ||
| 326 | */ | ||
| 327 | struct ieee80211_ht_addt_info { | ||
| 328 | unsigned char control_chan; | ||
| 329 | unsigned char ht_param; | ||
| 330 | unsigned short operation_mode; | ||
| 331 | unsigned short stbc_param; | ||
| 332 | unsigned char basic_set[16]; | ||
| 333 | } __packed; | ||
| 334 | |||
| 335 | struct HT_caps_element { | ||
| 336 | union { | ||
| 337 | struct { | ||
| 338 | unsigned short HT_caps_info; | ||
| 339 | unsigned char AMPDU_para; | ||
| 340 | unsigned char MCS_rate[16]; | ||
| 341 | unsigned short HT_ext_caps; | ||
| 342 | unsigned int Beamforming_caps; | ||
| 343 | unsigned char ASEL_caps; | ||
| 344 | } HT_cap_element; | ||
| 345 | unsigned char HT_cap[26]; | ||
| 346 | } u; | ||
| 347 | } __packed; | ||
| 348 | |||
| 349 | struct HT_info_element { | ||
| 350 | unsigned char primary_channel; | ||
| 351 | unsigned char infos[5]; | ||
| 352 | unsigned char MCS_rate[16]; | ||
| 353 | } __packed; | ||
| 354 | |||
| 355 | struct AC_param { | ||
| 356 | unsigned char ACI_AIFSN; | ||
| 357 | unsigned char CW; | ||
| 358 | unsigned short TXOP_limit; | ||
| 359 | } __packed; | ||
| 360 | |||
| 361 | struct WMM_para_element { | ||
| 362 | unsigned char QoS_info; | ||
| 363 | unsigned char reserved; | ||
| 364 | struct AC_param ac_param[4]; | ||
| 365 | } __packed; | ||
| 366 | |||
| 367 | struct ADDBA_request { | ||
| 368 | unsigned char dialog_token; | ||
| 369 | unsigned short BA_para_set; | ||
| 370 | unsigned short BA_timeout_value; | ||
| 371 | unsigned short BA_starting_seqctrl; | ||
| 372 | } __packed; | ||
| 373 | |||
| 374 | |||
| 375 | #define OP_MODE_PURE 0 | ||
| 376 | #define OP_MODE_MAY_BE_LEGACY_STAS 1 | ||
| 377 | #define OP_MODE_20MHZ_HT_STA_ASSOCED 2 | ||
| 378 | #define OP_MODE_MIXED 3 | ||
| 379 | |||
| 380 | #define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1)) | ||
| 381 | #define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0)) | ||
| 382 | #define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1)) | ||
| 383 | #define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2)) | ||
| 384 | #define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3)) | ||
| 385 | #define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4)) | ||
| 386 | #define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5)) | ||
| 387 | |||
| 388 | #define HT_INFO_OPERATION_MODE_OP_MODE_MASK \ | ||
| 389 | ((u16) (0x0001 | 0x0002)) | ||
| 390 | #define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0 | ||
| 391 | #define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2)) | ||
| 392 | #define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3)) | ||
| 393 | #define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4)) | ||
| 394 | |||
| 395 | #define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6)) | ||
| 396 | #define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7)) | ||
| 397 | #define HT_INFO_STBC_PARAM_SECONDARY_BCN ((u16) BIT(8)) | ||
| 398 | #define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9)) | ||
| 399 | #define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10)) | ||
| 400 | #define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11)) | ||
| 401 | |||
| 402 | |||
| 403 | |||
| 404 | /* ===============WPS Section=============== */ | ||
| 405 | /* For WPSv1.0 */ | ||
| 406 | #define WPSOUI 0x0050f204 | ||
| 407 | /* WPS attribute ID */ | ||
| 408 | #define WPS_ATTR_VER1 0x104A | ||
| 409 | #define WPS_ATTR_SIMPLE_CONF_STATE 0x1044 | ||
| 410 | #define WPS_ATTR_RESP_TYPE 0x103B | ||
| 411 | #define WPS_ATTR_UUID_E 0x1047 | ||
| 412 | #define WPS_ATTR_MANUFACTURER 0x1021 | ||
| 413 | #define WPS_ATTR_MODEL_NAME 0x1023 | ||
| 414 | #define WPS_ATTR_MODEL_NUMBER 0x1024 | ||
| 415 | #define WPS_ATTR_SERIAL_NUMBER 0x1042 | ||
| 416 | #define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054 | ||
| 417 | #define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055 | ||
| 418 | #define WPS_ATTR_DEVICE_NAME 0x1011 | ||
| 419 | #define WPS_ATTR_CONF_METHOD 0x1008 | ||
| 420 | #define WPS_ATTR_RF_BANDS 0x103C | ||
| 421 | #define WPS_ATTR_DEVICE_PWID 0x1012 | ||
| 422 | #define WPS_ATTR_REQUEST_TYPE 0x103A | ||
| 423 | #define WPS_ATTR_ASSOCIATION_STATE 0x1002 | ||
| 424 | #define WPS_ATTR_CONFIG_ERROR 0x1009 | ||
| 425 | #define WPS_ATTR_VENDOR_EXT 0x1049 | ||
| 426 | #define WPS_ATTR_SELECTED_REGISTRAR 0x1041 | ||
| 427 | |||
| 428 | /* Value of WPS attribute "WPS_ATTR_DEVICE_NAME */ | ||
| 429 | #define WPS_MAX_DEVICE_NAME_LEN 32 | ||
| 430 | |||
| 431 | /* Value of WPS Request Type Attribute */ | ||
| 432 | #define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00 | ||
| 433 | #define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01 | ||
| 434 | #define WPS_REQ_TYPE_REGISTRAR 0x02 | ||
| 435 | #define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03 | ||
| 436 | |||
| 437 | /* Value of WPS Response Type Attribute */ | ||
| 438 | #define WPS_RESPONSE_TYPE_INFO_ONLY 0x00 | ||
| 439 | #define WPS_RESPONSE_TYPE_8021X 0x01 | ||
| 440 | #define WPS_RESPONSE_TYPE_REGISTRAR 0x02 | ||
| 441 | #define WPS_RESPONSE_TYPE_AP 0x03 | ||
| 442 | |||
| 443 | /* Value of WPS WiFi Simple Configuration State Attribute */ | ||
| 444 | #define WPS_WSC_STATE_NOT_CONFIG 0x01 | ||
| 445 | #define WPS_WSC_STATE_CONFIG 0x02 | ||
| 446 | |||
| 447 | /* Value of WPS Version Attribute */ | ||
| 448 | #define WPS_VERSION_1 0x10 | ||
| 449 | |||
| 450 | /* Value of WPS Configuration Method Attribute */ | ||
| 451 | #define WPS_CONFIG_METHOD_FLASH 0x0001 | ||
| 452 | #define WPS_CONFIG_METHOD_ETHERNET 0x0002 | ||
| 453 | #define WPS_CONFIG_METHOD_LABEL 0x0004 | ||
| 454 | #define WPS_CONFIG_METHOD_DISPLAY 0x0008 | ||
| 455 | #define WPS_CONFIG_METHOD_E_NFC 0x0010 | ||
| 456 | #define WPS_CONFIG_METHOD_I_NFC 0x0020 | ||
| 457 | #define WPS_CONFIG_METHOD_NFC 0x0040 | ||
| 458 | #define WPS_CONFIG_METHOD_PBC 0x0080 | ||
| 459 | #define WPS_CONFIG_METHOD_KEYPAD 0x0100 | ||
| 460 | #define WPS_CONFIG_METHOD_VPBC 0x0280 | ||
| 461 | #define WPS_CONFIG_METHOD_PPBC 0x0480 | ||
| 462 | #define WPS_CONFIG_METHOD_VDISPLAY 0x2008 | ||
| 463 | #define WPS_CONFIG_METHOD_PDISPLAY 0x4008 | ||
| 464 | |||
| 465 | /* Value of Category ID of WPS Primary Device Type Attribute */ | ||
| 466 | #define WPS_PDT_CID_DISPLAYS 0x0007 | ||
| 467 | #define WPS_PDT_CID_MULIT_MEDIA 0x0008 | ||
| 468 | #define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA | ||
| 469 | |||
| 470 | /* Value of Sub Category ID of WPS Primary Device Type Attribute */ | ||
| 471 | #define WPS_PDT_SCID_MEDIA_SERVER 0x0005 | ||
| 472 | #define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER | ||
| 473 | |||
| 474 | /* Value of Device Password ID */ | ||
| 475 | #define WPS_DPID_PIN 0x0000 | ||
| 476 | #define WPS_DPID_USER_SPEC 0x0001 | ||
| 477 | #define WPS_DPID_MACHINE_SPEC 0x0002 | ||
| 478 | #define WPS_DPID_REKEY 0x0003 | ||
| 479 | #define WPS_DPID_PBC 0x0004 | ||
| 480 | #define WPS_DPID_REGISTRAR_SPEC 0x0005 | ||
| 481 | |||
| 482 | /* Value of WPS RF Bands Attribute */ | ||
| 483 | #define WPS_RF_BANDS_2_4_GHZ 0x01 | ||
| 484 | #define WPS_RF_BANDS_5_GHZ 0x02 | ||
| 485 | |||
| 486 | /* Value of WPS Association State Attribute */ | ||
| 487 | #define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00 | ||
| 488 | #define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01 | ||
| 489 | #define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02 | ||
| 490 | #define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03 | ||
| 491 | #define WPS_ASSOC_STATE_IP_FAILURE 0x04 | ||
| 492 | |||
| 493 | /* =====================P2P Section===================== */ | ||
| 494 | /* For P2P */ | ||
| 495 | #define P2POUI 0x506F9A09 | ||
| 496 | |||
| 497 | /* P2P Attribute ID */ | ||
| 498 | #define P2P_ATTR_STATUS 0x00 | ||
| 499 | #define P2P_ATTR_MINOR_REASON_CODE 0x01 | ||
| 500 | #define P2P_ATTR_CAPABILITY 0x02 | ||
| 501 | #define P2P_ATTR_DEVICE_ID 0x03 | ||
| 502 | #define P2P_ATTR_GO_INTENT 0x04 | ||
| 503 | #define P2P_ATTR_CONF_TIMEOUT 0x05 | ||
| 504 | #define P2P_ATTR_LISTEN_CH 0x06 | ||
| 505 | #define P2P_ATTR_GROUP_BSSID 0x07 | ||
| 506 | #define P2P_ATTR_EX_LISTEN_TIMING 0x08 | ||
| 507 | #define P2P_ATTR_INTENTED_IF_ADDR 0x09 | ||
| 508 | #define P2P_ATTR_MANAGEABILITY 0x0A | ||
| 509 | #define P2P_ATTR_CH_LIST 0x0B | ||
| 510 | #define P2P_ATTR_NOA 0x0C | ||
| 511 | #define P2P_ATTR_DEVICE_INFO 0x0D | ||
| 512 | #define P2P_ATTR_GROUP_INFO 0x0E | ||
| 513 | #define P2P_ATTR_GROUP_ID 0x0F | ||
| 514 | #define P2P_ATTR_INTERFACE 0x10 | ||
| 515 | #define P2P_ATTR_OPERATING_CH 0x11 | ||
| 516 | #define P2P_ATTR_INVITATION_FLAGS 0x12 | ||
| 517 | |||
| 518 | /* Value of Status Attribute */ | ||
| 519 | #define P2P_STATUS_SUCCESS 0x00 | ||
| 520 | #define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01 | ||
| 521 | #define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02 | ||
| 522 | #define P2P_STATUS_FAIL_LIMIT_REACHED 0x03 | ||
| 523 | #define P2P_STATUS_FAIL_INVALID_PARAM 0x04 | ||
| 524 | #define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05 | ||
| 525 | #define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06 | ||
| 526 | #define P2P_STATUS_FAIL_NO_COMMON_CH 0x07 | ||
| 527 | #define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08 | ||
| 528 | #define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09 | ||
| 529 | #define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A | ||
| 530 | #define P2P_STATUS_FAIL_USER_REJECT 0x0B | ||
| 531 | |||
| 532 | /* Value of Inviation Flags Attribute */ | ||
| 533 | #define P2P_INVITATION_FLAGS_PERSISTENT BIT(0) | ||
| 534 | |||
| 535 | #define DMP_P2P_DEVCAP_SUPPORT (P2P_DEVCAP_SERVICE_DISCOVERY | \ | ||
| 536 | P2P_DEVCAP_CLIENT_DISCOVERABILITY | \ | ||
| 537 | P2P_DEVCAP_CONCURRENT_OPERATION | \ | ||
| 538 | P2P_DEVCAP_INVITATION_PROC) | ||
| 539 | |||
| 540 | #define DMP_P2P_GRPCAP_SUPPORT (P2P_GRPCAP_INTRABSS) | ||
| 541 | |||
| 542 | /* Value of Device Capability Bitmap */ | ||
| 543 | #define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) | ||
| 544 | #define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) | ||
| 545 | #define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) | ||
| 546 | #define P2P_DEVCAP_INFRA_MANAGED BIT(3) | ||
| 547 | #define P2P_DEVCAP_DEVICE_LIMIT BIT(4) | ||
| 548 | #define P2P_DEVCAP_INVITATION_PROC BIT(5) | ||
| 549 | |||
| 550 | /* Value of Group Capability Bitmap */ | ||
| 551 | #define P2P_GRPCAP_GO BIT(0) | ||
| 552 | #define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) | ||
| 553 | #define P2P_GRPCAP_GROUP_LIMIT BIT(2) | ||
| 554 | #define P2P_GRPCAP_INTRABSS BIT(3) | ||
| 555 | #define P2P_GRPCAP_CROSS_CONN BIT(4) | ||
| 556 | #define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) | ||
| 557 | #define P2P_GRPCAP_GROUP_FORMATION BIT(6) | ||
| 558 | |||
| 559 | /* P2P Public Action Frame ( Management Frame ) */ | ||
| 560 | #define P2P_PUB_ACTION_ACTION 0x09 | ||
| 561 | |||
| 562 | /* P2P Public Action Frame Type */ | ||
| 563 | #define P2P_GO_NEGO_REQ 0 | ||
| 564 | #define P2P_GO_NEGO_RESP 1 | ||
| 565 | #define P2P_GO_NEGO_CONF 2 | ||
| 566 | #define P2P_INVIT_REQ 3 | ||
| 567 | #define P2P_INVIT_RESP 4 | ||
| 568 | #define P2P_DEVDISC_REQ 5 | ||
| 569 | #define P2P_DEVDISC_RESP 6 | ||
| 570 | #define P2P_PROVISION_DISC_REQ 7 | ||
| 571 | #define P2P_PROVISION_DISC_RESP 8 | ||
| 572 | |||
| 573 | /* P2P Action Frame Type */ | ||
| 574 | #define P2P_NOTICE_OF_ABSENCE 0 | ||
| 575 | #define P2P_PRESENCE_REQUEST 1 | ||
| 576 | #define P2P_PRESENCE_RESPONSE 2 | ||
| 577 | #define P2P_GO_DISC_REQUEST 3 | ||
| 578 | |||
| 579 | |||
| 580 | #define P2P_MAX_PERSISTENT_GROUP_NUM 10 | ||
| 581 | |||
| 582 | #define P2P_PROVISIONING_SCAN_CNT 3 | ||
| 583 | |||
| 584 | #define P2P_WILDCARD_SSID_LEN 7 | ||
| 585 | |||
| 586 | #define P2P_FINDPHASE_EX_NONE 0 /* default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase */ | ||
| 587 | #define P2P_FINDPHASE_EX_FULL 1 /* used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase */ | ||
| 588 | #define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1) | ||
| 589 | #define P2P_FINDPHASE_EX_MAX 4 | ||
| 590 | #define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX | ||
| 591 | |||
| 592 | #define P2P_PROVISION_TIMEOUT 5000 /*5 sec timeout for sending the provision discovery request */ | ||
| 593 | #define P2P_CONCURRENT_PROVISION_TIMEOUT 3000 /*3 sec timeout for sending the provision discovery request under concurrent mode */ | ||
| 594 | #define P2P_GO_NEGO_TIMEOUT 5000 /*5 sec timeout for receiving the group negotation response */ | ||
| 595 | #define P2P_CONCURRENT_GO_NEGO_TIMEOUT 3000 /*3 sec timeout for sending the negotiation request under concurrent mode */ | ||
| 596 | #define P2P_TX_PRESCAN_TIMEOUT 100 /*100ms */ | ||
| 597 | #define P2P_INVITE_TIMEOUT 5000 /*5 sec timeout for sending the invitation request */ | ||
| 598 | #define P2P_CONCURRENT_INVITE_TIMEOUT 3000 /*3 sec timeout for sending the invitation request under concurrent mode */ | ||
| 599 | #define P2P_RESET_SCAN_CH 25000 /*25 sec t/o to reset the scan channel ( based on channel plan ) */ | ||
| 600 | #define P2P_MAX_INTENT 15 | ||
| 601 | |||
| 602 | #define P2P_MAX_NOA_NUM 2 | ||
| 603 | |||
| 604 | /* WPS Configuration Method */ | ||
| 605 | #define WPS_CM_NONE 0x0000 | ||
| 606 | #define WPS_CM_LABEL 0x0004 | ||
| 607 | #define WPS_CM_DISPLYA 0x0008 | ||
| 608 | #define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010 | ||
| 609 | #define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020 | ||
| 610 | #define WPS_CM_NFC_INTERFACE 0x0040 | ||
| 611 | #define WPS_CM_PUSH_BUTTON 0x0080 | ||
| 612 | #define WPS_CM_KEYPAD 0x0100 | ||
| 613 | #define WPS_CM_SW_PUHS_BUTTON 0x0280 | ||
| 614 | #define WPS_CM_HW_PUHS_BUTTON 0x0480 | ||
| 615 | #define WPS_CM_SW_DISPLAY_PIN 0x2008 | ||
| 616 | #define WPS_CM_LCD_DISPLAY_PIN 0x4008 | ||
| 617 | |||
| 618 | enum P2P_ROLE { | ||
| 619 | P2P_ROLE_DISABLE = 0, | ||
| 620 | P2P_ROLE_DEVICE = 1, | ||
| 621 | P2P_ROLE_CLIENT = 2, | ||
| 622 | P2P_ROLE_GO = 3 | ||
| 623 | }; | ||
| 624 | |||
| 625 | enum P2P_STATE { | ||
| 626 | P2P_STATE_NONE = 0, /*P2P disable */ | ||
| 627 | P2P_STATE_IDLE = 1, /*P2P had enabled and do nothing */ | ||
| 628 | P2P_STATE_LISTEN = 2, /*In pure listen state */ | ||
| 629 | P2P_STATE_SCAN = 3, /*In scan phase */ | ||
| 630 | P2P_STATE_FIND_PHASE_LISTEN = 4, /*In the listen state of find phase */ | ||
| 631 | P2P_STATE_FIND_PHASE_SEARCH = 5, /*In the search state of find phase */ | ||
| 632 | P2P_STATE_TX_PROVISION_DIS_REQ = 6, /*In P2P provisioning discovery */ | ||
| 633 | P2P_STATE_RX_PROVISION_DIS_RSP = 7, | ||
| 634 | P2P_STATE_RX_PROVISION_DIS_REQ = 8, | ||
| 635 | P2P_STATE_GONEGO_ING = 9, /*Doing the group owner negoitation handshake */ | ||
| 636 | P2P_STATE_GONEGO_OK = 10, /*finish the group negoitation handshake with success */ | ||
| 637 | P2P_STATE_GONEGO_FAIL = 11, /*finish the group negoitation handshake with failure */ | ||
| 638 | P2P_STATE_RECV_INVITE_REQ_MATCH = 12, /*receiving the P2P Inviation request and match with the profile. */ | ||
| 639 | P2P_STATE_PROVISIONING_ING = 13, /*Doing the P2P WPS */ | ||
| 640 | P2P_STATE_PROVISIONING_DONE = 14, /*Finish the P2P WPS */ | ||
| 641 | P2P_STATE_TX_INVITE_REQ = 15, /*Transmit the P2P Invitation request */ | ||
| 642 | P2P_STATE_RX_INVITE_RESP_OK = 16, /*Receiving the P2P Invitation response */ | ||
| 643 | P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17,/*receiving the P2P Inviation request and dismatch with the profile. */ | ||
| 644 | P2P_STATE_RECV_INVITE_REQ_GO = 18, /*receiving the P2P Inviation request and this wifi is GO. */ | ||
| 645 | P2P_STATE_RECV_INVITE_REQ_JOIN = 19, /*receiving the P2P Inviation request to join an existing P2P Group. */ | ||
| 646 | P2P_STATE_RX_INVITE_RESP_FAIL = 20, /*receiving the P2P Inviation response with failure */ | ||
| 647 | P2P_STATE_RX_INFOR_NOREADY = 21, /*receiving p2p negotiation response with information is not available */ | ||
| 648 | P2P_STATE_TX_INFOR_NOREADY = 22, /*sending p2p negotiation response with information is not available */ | ||
| 649 | }; | ||
| 650 | |||
| 651 | enum P2P_WPSINFO { | ||
| 652 | P2P_NO_WPSINFO = 0, | ||
| 653 | P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1, | ||
| 654 | P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2, | ||
| 655 | P2P_GOT_WPSINFO_PBC = 3, | ||
| 656 | }; | ||
| 657 | |||
| 658 | #define P2P_PRIVATE_IOCTL_SET_LEN 64 | ||
| 659 | |||
| 660 | enum P2P_PROTO_WK_ID { | ||
| 661 | P2P_FIND_PHASE_WK = 0, | ||
| 662 | P2P_RESTORE_STATE_WK = 1, | ||
| 663 | P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, | ||
| 664 | P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, | ||
| 665 | P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, | ||
| 666 | P2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5, | ||
| 667 | P2P_RO_CH_WK = 6, | ||
| 668 | }; | ||
| 669 | |||
| 670 | #ifdef CONFIG_8723AU_P2P | ||
| 671 | enum P2P_PS_STATE { | ||
| 672 | P2P_PS_DISABLE = 0, | ||
| 673 | P2P_PS_ENABLE = 1, | ||
| 674 | P2P_PS_SCAN = 2, | ||
| 675 | P2P_PS_SCAN_DONE = 3, | ||
| 676 | P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ | ||
| 677 | }; | ||
| 678 | |||
| 679 | enum P2P_PS_MODE { | ||
| 680 | P2P_PS_NONE = 0, | ||
| 681 | P2P_PS_CTWINDOW = 1, | ||
| 682 | P2P_PS_NOA = 2, | ||
| 683 | P2P_PS_MIX = 3, /* CTWindow and NoA */ | ||
| 684 | }; | ||
| 685 | #endif /* CONFIG_8723AU_P2P */ | ||
| 686 | |||
| 687 | /* =====================WFD Section===================== */ | ||
| 688 | /* For Wi-Fi Display */ | ||
| 689 | #define WFD_ATTR_DEVICE_INFO 0x00 | ||
| 690 | #define WFD_ATTR_ASSOC_BSSID 0x01 | ||
| 691 | #define WFD_ATTR_COUPLED_SINK_INFO 0x06 | ||
| 692 | #define WFD_ATTR_LOCAL_IP_ADDR 0x08 | ||
| 693 | #define WFD_ATTR_SESSION_INFO 0x09 | ||
| 694 | #define WFD_ATTR_ALTER_MAC 0x0a | ||
| 695 | |||
| 696 | /* For WFD Device Information Attribute */ | ||
| 697 | #define WFD_DEVINFO_SOURCE 0x0000 | ||
| 698 | #define WFD_DEVINFO_PSINK 0x0001 | ||
| 699 | #define WFD_DEVINFO_SSINK 0x0002 | ||
| 700 | #define WFD_DEVINFO_DUAL 0x0003 | ||
| 701 | |||
| 702 | #define WFD_DEVINFO_SESSION_AVAIL 0x0010 | ||
| 703 | #define WFD_DEVINFO_WSD 0x0040 | ||
| 704 | #define WFD_DEVINFO_PC_TDLS 0x0080 | ||
| 705 | #define WFD_DEVINFO_HDCP_SUPPORT 0x0100 | ||
| 706 | |||
| 707 | #endif /* _WIFI_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/wlan_bssdef.h b/drivers/staging/rtl8723au/include/wlan_bssdef.h new file mode 100644 index 000000000000..92287ebe5b9b --- /dev/null +++ b/drivers/staging/rtl8723au/include/wlan_bssdef.h | |||
| @@ -0,0 +1,215 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __WLAN_BSSDEF_H__ | ||
| 16 | #define __WLAN_BSSDEF_H__ | ||
| 17 | |||
| 18 | |||
| 19 | #define MAX_IE_SZ 768 | ||
| 20 | |||
| 21 | |||
| 22 | #define NDIS_802_11_LENGTH_RATES 8 | ||
| 23 | #define NDIS_802_11_LENGTH_RATES_EX 16 | ||
| 24 | |||
| 25 | enum ndis_802_11_net_type { | ||
| 26 | Ndis802_11FH, | ||
| 27 | Ndis802_11DS, | ||
| 28 | Ndis802_11OFDM5, | ||
| 29 | Ndis802_11OFDM24, | ||
| 30 | Ndis802_11NetworkTypeMax /* just an upper bound */ | ||
| 31 | }; | ||
| 32 | |||
| 33 | struct ndis_802_11_configuration_fh { | ||
| 34 | u32 Length; /* Length of structure */ | ||
| 35 | u32 HopPattern; /* As defined by 802.11, MSB set */ | ||
| 36 | u32 HopSet; /* to one if non-802.11 */ | ||
| 37 | u32 DwellTime; /* units are Kusec */ | ||
| 38 | }; | ||
| 39 | |||
| 40 | |||
| 41 | /* | ||
| 42 | FW will only save the channel number in DSConfig. | ||
| 43 | ODI Handler will convert the channel number to freq. number. | ||
| 44 | */ | ||
| 45 | struct ndis_802_11_config { | ||
| 46 | u32 Length; /* Length of structure */ | ||
| 47 | u32 BeaconPeriod; /* units are Kusec */ | ||
| 48 | u32 ATIMWindow; /* units are Kusec */ | ||
| 49 | u32 DSConfig; /* Frequency, units are kHz */ | ||
| 50 | struct ndis_802_11_configuration_fh FHConfig; | ||
| 51 | }; | ||
| 52 | |||
| 53 | enum ndis_802_11_net_infra { | ||
| 54 | Ndis802_11IBSS, | ||
| 55 | Ndis802_11Infrastructure, | ||
| 56 | Ndis802_11AutoUnknown, | ||
| 57 | Ndis802_11InfrastructureMax, /* Not a real value, defined as upper bound */ | ||
| 58 | Ndis802_11APMode | ||
| 59 | }; | ||
| 60 | |||
| 61 | struct ndis_802_11_fixed_ies { | ||
| 62 | u8 Timestamp[8]; | ||
| 63 | u16 BeaconInterval; | ||
| 64 | u16 Capabilities; | ||
| 65 | }; | ||
| 66 | |||
| 67 | struct ndis_802_11_var_ies { | ||
| 68 | u8 ElementID; | ||
| 69 | u8 Length; | ||
| 70 | u8 data[1]; | ||
| 71 | }; | ||
| 72 | |||
| 73 | /* Length is the 4 bytes multiples of the sum of | ||
| 74 | * sizeof(6 * sizeof(unsigned char)) + 2 + sizeof(struct ndis_802_11_ssid) + | ||
| 75 | * sizeof(u32) + sizeof(long) + sizeof(enum ndis_802_11_net_type) + | ||
| 76 | * sizeof(struct ndis_802_11_config) + sizeof(sizeof(unsigned char) * | ||
| 77 | * NDIS_802_11_LENGTH_RATES_EX) + IELength | ||
| 78 | * | ||
| 79 | * Except the IELength, all other fields are fixed length. Therefore, | ||
| 80 | * we can define a macro to present the partial sum. | ||
| 81 | */ | ||
| 82 | |||
| 83 | enum ndis_802_11_auth_mode { | ||
| 84 | Ndis802_11AuthModeOpen, | ||
| 85 | Ndis802_11AuthModeShared, | ||
| 86 | Ndis802_11AuthModeAutoSwitch, | ||
| 87 | Ndis802_11AuthModeWPA, | ||
| 88 | Ndis802_11AuthModeWPAPSK, | ||
| 89 | Ndis802_11AuthModeWPANone, | ||
| 90 | dis802_11AuthModeMax /* upper bound */ | ||
| 91 | }; | ||
| 92 | |||
| 93 | enum { | ||
| 94 | Ndis802_11WEPEnabled, | ||
| 95 | Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, | ||
| 96 | Ndis802_11WEPDisabled, | ||
| 97 | Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, | ||
| 98 | Ndis802_11WEPKeyAbsent, | ||
| 99 | Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, | ||
| 100 | Ndis802_11WEPNotSupported, | ||
| 101 | Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, | ||
| 102 | Ndis802_11Encryption2Enabled, | ||
| 103 | Ndis802_11Encryption2KeyAbsent, | ||
| 104 | Ndis802_11Encryption3Enabled, | ||
| 105 | Ndis802_11Encryption3KeyAbsent, | ||
| 106 | }; | ||
| 107 | |||
| 108 | /* Key mapping keys require a BSSID */ | ||
| 109 | struct ndis_802_11_key { | ||
| 110 | u32 Length; /* Length of this structure */ | ||
| 111 | u32 KeyIndex; | ||
| 112 | u32 KeyLength; /* length of key in bytes */ | ||
| 113 | unsigned char BSSID[6]; | ||
| 114 | unsigned long long KeyRSC; | ||
| 115 | u8 KeyMaterial[32]; /* variable length depending on above field */ | ||
| 116 | }; | ||
| 117 | |||
| 118 | struct ndis_802_11_wep { | ||
| 119 | u32 Length; /* Length of this structure */ | ||
| 120 | u32 KeyIndex; /* 0 is the per-client key, 1-N are global */ | ||
| 121 | u32 KeyLength; /* length of key in bytes */ | ||
| 122 | u8 KeyMaterial[16];/* variable length depending on above field */ | ||
| 123 | }; | ||
| 124 | |||
| 125 | enum NDIS_802_11_STATUS_TYPE { | ||
| 126 | Ndis802_11StatusType_Authentication, | ||
| 127 | Ndis802_11StatusType_MediaStreamMode, | ||
| 128 | Ndis802_11StatusType_PMKID_CandidateList, | ||
| 129 | Ndis802_11StatusTypeMax /* not a real type, just an upper bound */ | ||
| 130 | }; | ||
| 131 | |||
| 132 | /* mask for authentication/integrity fields */ | ||
| 133 | #define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f | ||
| 134 | #define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 | ||
| 135 | #define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 | ||
| 136 | #define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 | ||
| 137 | #define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E | ||
| 138 | |||
| 139 | /* MIC check time, 60 seconds. */ | ||
| 140 | #define MIC_CHECK_TIME 60000000 | ||
| 141 | |||
| 142 | #ifndef Ndis802_11APMode | ||
| 143 | #define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) | ||
| 144 | #endif | ||
| 145 | |||
| 146 | struct wlan_phy_info { | ||
| 147 | u8 SignalStrength;/* in percentage) */ | ||
| 148 | u8 SignalQuality;/* in percentage) */ | ||
| 149 | u8 Optimum_antenna; /* for Antenna diversity */ | ||
| 150 | u8 Reserved_0; | ||
| 151 | }; | ||
| 152 | |||
| 153 | struct wlan_bcn_info { | ||
| 154 | /* these infor get from rtw_get_encrypt_info when | ||
| 155 | * * translate scan to UI */ | ||
| 156 | u8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2 */ | ||
| 157 | int group_cipher; /* WPA/WPA2 group cipher */ | ||
| 158 | int pairwise_cipher;/* WPA/WPA2/WEP pairwise cipher */ | ||
| 159 | int is_8021x; | ||
| 160 | |||
| 161 | /* bwmode 20/40 and ch_offset UP/LOW */ | ||
| 162 | unsigned short ht_cap_info; | ||
| 163 | unsigned char ht_info_infos_0; | ||
| 164 | }; | ||
| 165 | |||
| 166 | struct wlan_bssid_ex { | ||
| 167 | u32 Length; | ||
| 168 | u8 MacAddress[ETH_ALEN]; | ||
| 169 | u16 reserved; | ||
| 170 | struct cfg80211_ssid Ssid; | ||
| 171 | u32 Privacy; | ||
| 172 | long Rssi;/* in dBM, raw data , get from PHY) */ | ||
| 173 | enum ndis_802_11_net_type NetworkTypeInUse; | ||
| 174 | struct ndis_802_11_config Configuration; | ||
| 175 | enum ndis_802_11_net_infra InfrastructureMode; | ||
| 176 | unsigned char SupportedRates[NDIS_802_11_LENGTH_RATES_EX]; | ||
| 177 | struct wlan_phy_info PhyInfo; | ||
| 178 | u32 IELength; | ||
| 179 | u8 IEs[MAX_IE_SZ]; /* timestamp, beacon interval, and capability info*/ | ||
| 180 | } __packed; | ||
| 181 | |||
| 182 | static inline uint get_wlan_bssid_ex_sz(struct wlan_bssid_ex *bss) | ||
| 183 | { | ||
| 184 | return sizeof(struct wlan_bssid_ex) - MAX_IE_SZ + bss->IELength; | ||
| 185 | } | ||
| 186 | |||
| 187 | struct wlan_network { | ||
| 188 | struct list_head list; | ||
| 189 | int network_type; /* refer to ieee80211.h for 11A/B/G */ | ||
| 190 | /* set to fixed when not to be removed as site-surveying */ | ||
| 191 | int fixed; | ||
| 192 | unsigned long last_scanned; /* timestamp for the network */ | ||
| 193 | int aid; /* will only be valid when a BSS is joined. */ | ||
| 194 | int join_res; | ||
| 195 | struct wlan_bssid_ex network; /* must be the last item */ | ||
| 196 | struct wlan_bcn_info BcnInfo; | ||
| 197 | }; | ||
| 198 | |||
| 199 | enum VRTL_CARRIER_SENSE { | ||
| 200 | DISABLE_VCS, | ||
| 201 | ENABLE_VCS, | ||
| 202 | AUTO_VCS | ||
| 203 | }; | ||
| 204 | |||
| 205 | enum VCS_TYPE { | ||
| 206 | NONE_VCS, | ||
| 207 | RTS_CTS, | ||
| 208 | CTS_TO_SELF | ||
| 209 | }; | ||
| 210 | |||
| 211 | /* john */ | ||
| 212 | #define NUM_PRE_AUTH_KEY 16 | ||
| 213 | #define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY | ||
| 214 | |||
| 215 | #endif /* ifndef WLAN_BSSDEF_H_ */ | ||
diff --git a/drivers/staging/rtl8723au/include/xmit_osdep.h b/drivers/staging/rtl8723au/include/xmit_osdep.h new file mode 100644 index 000000000000..0eca53ece75d --- /dev/null +++ b/drivers/staging/rtl8723au/include/xmit_osdep.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /****************************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of version 2 of the GNU General Public License as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | ******************************************************************************/ | ||
| 15 | #ifndef __XMIT_OSDEP_H_ | ||
| 16 | #define __XMIT_OSDEP_H_ | ||
| 17 | |||
| 18 | #include <osdep_service.h> | ||
| 19 | #include <drv_types.h> | ||
| 20 | |||
| 21 | struct pkt_file { | ||
| 22 | struct sk_buff *pkt; | ||
| 23 | __kernel_size_t pkt_len; /* the remainder length of the open_file */ | ||
| 24 | unsigned char *cur_buffer; | ||
| 25 | u8 *buf_start; | ||
| 26 | u8 *cur_addr; | ||
| 27 | __kernel_size_t buf_len; | ||
| 28 | }; | ||
| 29 | |||
| 30 | |||
| 31 | #define NR_XMITFRAME 256 | ||
| 32 | |||
| 33 | struct xmit_priv; | ||
| 34 | struct pkt_attrib; | ||
| 35 | struct sta_xmit_priv; | ||
| 36 | struct xmit_frame; | ||
| 37 | struct xmit_buf; | ||
| 38 | |||
| 39 | int rtw_xmit23a_entry23a(struct sk_buff *pkt, struct net_device *pnetdev); | ||
| 40 | |||
| 41 | void rtw_os_xmit_schedule23a(struct rtw_adapter *padapter); | ||
| 42 | |||
| 43 | int rtw_os_xmit_resource_alloc23a(struct rtw_adapter *padapter, | ||
| 44 | struct xmit_buf *pxmitbuf, u32 alloc_sz); | ||
| 45 | void rtw_os_xmit_resource_free23a(struct rtw_adapter *padapter, | ||
| 46 | struct xmit_buf *pxmitbuf); | ||
| 47 | uint rtw_remainder_len23a(struct pkt_file *pfile); | ||
| 48 | void _rtw_open_pktfile23a(struct sk_buff *pkt, struct pkt_file *pfile); | ||
| 49 | uint _rtw_pktfile_read23a(struct pkt_file *pfile, u8 *rmem, uint rlen); | ||
| 50 | int rtw_endofpktfile23a(struct pkt_file *pfile); | ||
| 51 | |||
| 52 | void rtw_os_pkt_complete23a(struct rtw_adapter *padapter, struct sk_buff *pkt); | ||
| 53 | void rtw_os_xmit_complete23a(struct rtw_adapter *padapter, | ||
| 54 | struct xmit_frame *pxframe); | ||
| 55 | int netdev_open23a(struct net_device *pnetdev); | ||
| 56 | |||
| 57 | #endif /* __XMIT_OSDEP_H_ */ | ||