diff options
-rw-r--r-- | drivers/scsi/qla2xxx/qla_inline.h | 11 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_isr.c | 27 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_mbx.c | 2 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_mr.c | 10 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_nx.c | 26 |
5 files changed, 27 insertions, 49 deletions
diff --git a/drivers/scsi/qla2xxx/qla_inline.h b/drivers/scsi/qla2xxx/qla_inline.h index 98ab921070d2..0a5c8951cebb 100644 --- a/drivers/scsi/qla2xxx/qla_inline.h +++ b/drivers/scsi/qla2xxx/qla_inline.h | |||
@@ -278,3 +278,14 @@ qla2x00_do_host_ramp_up(scsi_qla_host_t *vha) | |||
278 | 278 | ||
279 | set_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags); | 279 | set_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags); |
280 | } | 280 | } |
281 | |||
282 | static inline void | ||
283 | qla2x00_handle_mbx_completion(struct qla_hw_data *ha, int status) | ||
284 | { | ||
285 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | ||
286 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | ||
287 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | ||
288 | clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); | ||
289 | complete(&ha->mbx_intr_comp); | ||
290 | } | ||
291 | } | ||
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index 259d9205d876..d2a4c75e5b8f 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c | |||
@@ -104,14 +104,9 @@ qla2100_intr_handler(int irq, void *dev_id) | |||
104 | RD_REG_WORD(®->hccr); | 104 | RD_REG_WORD(®->hccr); |
105 | } | 105 | } |
106 | } | 106 | } |
107 | qla2x00_handle_mbx_completion(ha, status); | ||
107 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | 108 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
108 | 109 | ||
109 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | ||
110 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | ||
111 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | ||
112 | complete(&ha->mbx_intr_comp); | ||
113 | } | ||
114 | |||
115 | return (IRQ_HANDLED); | 110 | return (IRQ_HANDLED); |
116 | } | 111 | } |
117 | 112 | ||
@@ -221,14 +216,9 @@ qla2300_intr_handler(int irq, void *dev_id) | |||
221 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | 216 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); |
222 | RD_REG_WORD_RELAXED(®->hccr); | 217 | RD_REG_WORD_RELAXED(®->hccr); |
223 | } | 218 | } |
219 | qla2x00_handle_mbx_completion(ha, status); | ||
224 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | 220 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
225 | 221 | ||
226 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | ||
227 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | ||
228 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | ||
229 | complete(&ha->mbx_intr_comp); | ||
230 | } | ||
231 | |||
232 | return (IRQ_HANDLED); | 222 | return (IRQ_HANDLED); |
233 | } | 223 | } |
234 | 224 | ||
@@ -2613,14 +2603,9 @@ qla24xx_intr_handler(int irq, void *dev_id) | |||
2613 | if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1))) | 2603 | if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1))) |
2614 | ndelay(3500); | 2604 | ndelay(3500); |
2615 | } | 2605 | } |
2606 | qla2x00_handle_mbx_completion(ha, status); | ||
2616 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | 2607 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
2617 | 2608 | ||
2618 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | ||
2619 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | ||
2620 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | ||
2621 | complete(&ha->mbx_intr_comp); | ||
2622 | } | ||
2623 | |||
2624 | return IRQ_HANDLED; | 2609 | return IRQ_HANDLED; |
2625 | } | 2610 | } |
2626 | 2611 | ||
@@ -2763,13 +2748,9 @@ qla24xx_msix_default(int irq, void *dev_id) | |||
2763 | } | 2748 | } |
2764 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | 2749 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); |
2765 | } while (0); | 2750 | } while (0); |
2751 | qla2x00_handle_mbx_completion(ha, status); | ||
2766 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | 2752 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
2767 | 2753 | ||
2768 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | ||
2769 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | ||
2770 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | ||
2771 | complete(&ha->mbx_intr_comp); | ||
2772 | } | ||
2773 | return IRQ_HANDLED; | 2754 | return IRQ_HANDLED; |
2774 | } | 2755 | } |
2775 | 2756 | ||
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c index 9e5d89db7272..3587ec267fa6 100644 --- a/drivers/scsi/qla2xxx/qla_mbx.c +++ b/drivers/scsi/qla2xxx/qla_mbx.c | |||
@@ -179,8 +179,6 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) | |||
179 | 179 | ||
180 | wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ); | 180 | wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ); |
181 | 181 | ||
182 | clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); | ||
183 | |||
184 | } else { | 182 | } else { |
185 | ql_dbg(ql_dbg_mbx, vha, 0x1011, | 183 | ql_dbg(ql_dbg_mbx, vha, 0x1011, |
186 | "Cmd=%x Polling Mode.\n", command); | 184 | "Cmd=%x Polling Mode.\n", command); |
diff --git a/drivers/scsi/qla2xxx/qla_mr.c b/drivers/scsi/qla2xxx/qla_mr.c index 937fed8cb038..a6df55838365 100644 --- a/drivers/scsi/qla2xxx/qla_mr.c +++ b/drivers/scsi/qla2xxx/qla_mr.c | |||
@@ -148,9 +148,6 @@ qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp) | |||
148 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | 148 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
149 | 149 | ||
150 | wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ); | 150 | wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ); |
151 | |||
152 | clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); | ||
153 | |||
154 | } else { | 151 | } else { |
155 | ql_dbg(ql_dbg_mbx, vha, 0x112c, | 152 | ql_dbg(ql_dbg_mbx, vha, 0x112c, |
156 | "Cmd=%x Polling Mode.\n", command); | 153 | "Cmd=%x Polling Mode.\n", command); |
@@ -2934,13 +2931,10 @@ qlafx00_intr_handler(int irq, void *dev_id) | |||
2934 | QLAFX00_CLR_INTR_REG(ha, clr_intr); | 2931 | QLAFX00_CLR_INTR_REG(ha, clr_intr); |
2935 | QLAFX00_RD_INTR_REG(ha); | 2932 | QLAFX00_RD_INTR_REG(ha); |
2936 | } | 2933 | } |
2934 | |||
2935 | qla2x00_handle_mbx_completion(ha, status); | ||
2937 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | 2936 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
2938 | 2937 | ||
2939 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | ||
2940 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | ||
2941 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | ||
2942 | complete(&ha->mbx_intr_comp); | ||
2943 | } | ||
2944 | return IRQ_HANDLED; | 2938 | return IRQ_HANDLED; |
2945 | } | 2939 | } |
2946 | 2940 | ||
diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c index 10754f518303..cce0cd0d7ec4 100644 --- a/drivers/scsi/qla2xxx/qla_nx.c +++ b/drivers/scsi/qla2xxx/qla_nx.c | |||
@@ -2074,9 +2074,6 @@ qla82xx_intr_handler(int irq, void *dev_id) | |||
2074 | } | 2074 | } |
2075 | WRT_REG_DWORD(®->host_int, 0); | 2075 | WRT_REG_DWORD(®->host_int, 0); |
2076 | } | 2076 | } |
2077 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
2078 | if (!ha->flags.msi_enabled) | ||
2079 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); | ||
2080 | 2077 | ||
2081 | #ifdef QL_DEBUG_LEVEL_17 | 2078 | #ifdef QL_DEBUG_LEVEL_17 |
2082 | if (!irq && ha->flags.eeh_busy) | 2079 | if (!irq && ha->flags.eeh_busy) |
@@ -2085,11 +2082,12 @@ qla82xx_intr_handler(int irq, void *dev_id) | |||
2085 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); | 2082 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); |
2086 | #endif | 2083 | #endif |
2087 | 2084 | ||
2088 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | 2085 | qla2x00_handle_mbx_completion(ha, status); |
2089 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | 2086 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
2090 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | 2087 | |
2091 | complete(&ha->mbx_intr_comp); | 2088 | if (!ha->flags.msi_enabled) |
2092 | } | 2089 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); |
2090 | |||
2093 | return IRQ_HANDLED; | 2091 | return IRQ_HANDLED; |
2094 | } | 2092 | } |
2095 | 2093 | ||
@@ -2149,8 +2147,6 @@ qla82xx_msix_default(int irq, void *dev_id) | |||
2149 | WRT_REG_DWORD(®->host_int, 0); | 2147 | WRT_REG_DWORD(®->host_int, 0); |
2150 | } while (0); | 2148 | } while (0); |
2151 | 2149 | ||
2152 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
2153 | |||
2154 | #ifdef QL_DEBUG_LEVEL_17 | 2150 | #ifdef QL_DEBUG_LEVEL_17 |
2155 | if (!irq && ha->flags.eeh_busy) | 2151 | if (!irq && ha->flags.eeh_busy) |
2156 | ql_log(ql_log_warn, vha, 0x5044, | 2152 | ql_log(ql_log_warn, vha, 0x5044, |
@@ -2158,11 +2154,9 @@ qla82xx_msix_default(int irq, void *dev_id) | |||
2158 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); | 2154 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); |
2159 | #endif | 2155 | #endif |
2160 | 2156 | ||
2161 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | 2157 | qla2x00_handle_mbx_completion(ha, status); |
2162 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | 2158 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
2163 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | 2159 | |
2164 | complete(&ha->mbx_intr_comp); | ||
2165 | } | ||
2166 | return IRQ_HANDLED; | 2160 | return IRQ_HANDLED; |
2167 | } | 2161 | } |
2168 | 2162 | ||
@@ -3345,7 +3339,7 @@ void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) | |||
3345 | ha->flags.mbox_busy = 0; | 3339 | ha->flags.mbox_busy = 0; |
3346 | ql_log(ql_log_warn, vha, 0x6010, | 3340 | ql_log(ql_log_warn, vha, 0x6010, |
3347 | "Doing premature completion of mbx command.\n"); | 3341 | "Doing premature completion of mbx command.\n"); |
3348 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) | 3342 | if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) |
3349 | complete(&ha->mbx_intr_comp); | 3343 | complete(&ha->mbx_intr_comp); |
3350 | } | 3344 | } |
3351 | } | 3345 | } |