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-rw-r--r--arch/arm/boot/compressed/head.S14
-rw-r--r--arch/arm/mm/proc-v6.S2
2 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 90275f036cd1..49ca86e37b8d 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
652 mov pc, lr 652 mov pc, lr
653ENDPROC(__setup_mmu) 653ENDPROC(__setup_mmu)
654 654
655@ Enable unaligned access on v6, to allow better code generation
656@ for the decompressor C code:
657__armv6_mmu_cache_on:
658 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
659 bic r0, r0, #2 @ A (no unaligned access fault)
660 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
661 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
662 b __armv4_mmu_cache_on
663
655__arm926ejs_mmu_cache_on: 664__arm926ejs_mmu_cache_on:
656#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 665#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
657 mov r0, #4 @ put dcache in WT mode 666 mov r0, #4 @ put dcache in WT mode
@@ -694,6 +703,9 @@ __armv7_mmu_cache_on:
694 bic r0, r0, #1 << 28 @ clear SCTLR.TRE 703 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
695 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 704 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
696 orr r0, r0, #0x003c @ write buffer 705 orr r0, r0, #0x003c @ write buffer
706 bic r0, r0, #2 @ A (no unaligned access fault)
707 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
708 @ (needed for ARM1176)
697#ifdef CONFIG_MMU 709#ifdef CONFIG_MMU
698#ifdef CONFIG_CPU_ENDIAN_BE8 710#ifdef CONFIG_CPU_ENDIAN_BE8
699 orr r0, r0, #1 << 25 @ big-endian page tables 711 orr r0, r0, #1 << 25 @ big-endian page tables
@@ -914,7 +926,7 @@ proc_types:
914 926
915 .word 0x0007b000 @ ARMv6 927 .word 0x0007b000 @ ARMv6
916 .word 0x000ff000 928 .word 0x000ff000
917 W(b) __armv4_mmu_cache_on 929 W(b) __armv6_mmu_cache_on
918 W(b) __armv4_mmu_cache_off 930 W(b) __armv4_mmu_cache_off
919 W(b) __armv6_mmu_cache_flush 931 W(b) __armv6_mmu_cache_flush
920 932
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 86b8b480634f..09c5233f4dfc 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -89,7 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area)
89 mov pc, lr 89 mov pc, lr
90 90
91/* 91/*
92 * cpu_arm926_switch_mm(pgd_phys, tsk) 92 * cpu_v6_switch_mm(pgd_phys, tsk)
93 * 93 *
94 * Set the translation table base pointer to be pgd_phys 94 * Set the translation table base pointer to be pgd_phys
95 * 95 *