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-rw-r--r--drivers/gpu/drm/ast/ast_post.c476
1 files changed, 173 insertions, 303 deletions
diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
index 4718e76847b0..667fabfee91d 100644
--- a/drivers/gpu/drm/ast/ast_post.c
+++ b/drivers/gpu/drm/ast/ast_post.c
@@ -109,16 +109,25 @@ ast_set_def_ext_reg(struct drm_device *dev)
109 109
110static inline u32 mindwm(struct ast_private *ast, u32 r) 110static inline u32 mindwm(struct ast_private *ast, u32 r)
111{ 111{
112 uint32_t data;
113
112 ast_write32(ast, 0xf004, r & 0xffff0000); 114 ast_write32(ast, 0xf004, r & 0xffff0000);
113 ast_write32(ast, 0xf000, 0x1); 115 ast_write32(ast, 0xf000, 0x1);
114 116
117 do {
118 data = ast_read32(ast, 0xf004) & 0xffff0000;
119 } while (data != (r & 0xffff0000));
115 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); 120 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
116} 121}
117 122
118static inline void moutdwm(struct ast_private *ast, u32 r, u32 v) 123static inline void moutdwm(struct ast_private *ast, u32 r, u32 v)
119{ 124{
125 uint32_t data;
120 ast_write32(ast, 0xf004, r & 0xffff0000); 126 ast_write32(ast, 0xf004, r & 0xffff0000);
121 ast_write32(ast, 0xf000, 0x1); 127 ast_write32(ast, 0xf000, 0x1);
128 do {
129 data = ast_read32(ast, 0xf004) & 0xffff0000;
130 } while (data != (r & 0xffff0000));
122 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); 131 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
123} 132}
124 133
@@ -403,6 +412,7 @@ struct ast2300_dram_param {
403/* 412/*
404 * DQSI DLL CBR Setting 413 * DQSI DLL CBR Setting
405 */ 414 */
415#define CBR_SIZE0 ((1 << 10) - 1)
406#define CBR_SIZE1 ((4 << 10) - 1) 416#define CBR_SIZE1 ((4 << 10) - 1)
407#define CBR_SIZE2 ((64 << 10) - 1) 417#define CBR_SIZE2 ((64 << 10) - 1)
408#define CBR_PASSNUM 5 418#define CBR_PASSNUM 5
@@ -423,7 +433,6 @@ static const u32 pattern[8] = {
423 0x7C61D253 433 0x7C61D253
424}; 434};
425 435
426#if 0 /* unused in DDX, included for completeness */
427static int mmc_test_burst(struct ast_private *ast, u32 datagen) 436static int mmc_test_burst(struct ast_private *ast, u32 datagen)
428{ 437{
429 u32 data, timeout; 438 u32 data, timeout;
@@ -444,7 +453,6 @@ static int mmc_test_burst(struct ast_private *ast, u32 datagen)
444 moutdwm(ast, 0x1e6e0070, 0x00000000); 453 moutdwm(ast, 0x1e6e0070, 0x00000000);
445 return 1; 454 return 1;
446} 455}
447#endif
448 456
449static int mmc_test_burst2(struct ast_private *ast, u32 datagen) 457static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
450{ 458{
@@ -466,7 +474,6 @@ static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
466 return data; 474 return data;
467} 475}
468 476
469#if 0 /* Unused in DDX here for completeness */
470static int mmc_test_single(struct ast_private *ast, u32 datagen) 477static int mmc_test_single(struct ast_private *ast, u32 datagen)
471{ 478{
472 u32 data, timeout; 479 u32 data, timeout;
@@ -486,7 +493,6 @@ static int mmc_test_single(struct ast_private *ast, u32 datagen)
486 moutdwm(ast, 0x1e6e0070, 0x0); 493 moutdwm(ast, 0x1e6e0070, 0x0);
487 return 1; 494 return 1;
488} 495}
489#endif
490 496
491static int mmc_test_single2(struct ast_private *ast, u32 datagen) 497static int mmc_test_single2(struct ast_private *ast, u32 datagen)
492{ 498{
@@ -583,106 +589,35 @@ static u32 cbr_scan2(struct ast_private *ast)
583 return data2; 589 return data2;
584} 590}
585 591
586#if 0 /* unused in DDX - added for completeness */ 592static u32 cbr_test3(struct ast_private *ast)
587static void finetuneDQI(struct ast_private *ast, struct ast2300_dram_param *param)
588{ 593{
589 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt; 594 if (!mmc_test_burst(ast, 0))
590 595 return 0;
591 gold_sadj[0] = (mindwm(ast, 0x1E6E0024) >> 16) & 0xffff; 596 if (!mmc_test_single(ast, 0))
592 gold_sadj[1] = gold_sadj[0] >> 8; 597 return 0;
593 gold_sadj[0] = gold_sadj[0] & 0xff; 598 return 1;
594 gold_sadj[0] = (gold_sadj[0] + gold_sadj[1]) >> 1; 599}
595 gold_sadj[1] = gold_sadj[0];
596
597 for (cnt = 0; cnt < 16; cnt++) {
598 dllmin[cnt] = 0xff;
599 dllmax[cnt] = 0x0;
600 }
601 passcnt = 0;
602 for (dlli = 0; dlli < 76; dlli++) {
603 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
604 /* Wait DQSI latch phase calibration */
605 moutdwm(ast, 0x1E6E0074, 0x00000010);
606 moutdwm(ast, 0x1E6E0070, 0x00000003);
607 do {
608 data = mindwm(ast, 0x1E6E0070);
609 } while (!(data & 0x00001000));
610 moutdwm(ast, 0x1E6E0070, 0x00000000);
611 600
612 moutdwm(ast, 0x1E6E0074, CBR_SIZE1); 601static u32 cbr_scan3(struct ast_private *ast)
613 data = cbr_scan2(ast); 602{
614 if (data != 0) { 603 u32 patcnt, loop;
615 mask = 0x00010001;
616 for (cnt = 0; cnt < 16; cnt++) {
617 if (data & mask) {
618 if (dllmin[cnt] > dlli) {
619 dllmin[cnt] = dlli;
620 }
621 if (dllmax[cnt] < dlli) {
622 dllmax[cnt] = dlli;
623 }
624 }
625 mask <<= 1;
626 }
627 passcnt++;
628 } else if (passcnt >= CBR_THRESHOLD) {
629 break;
630 }
631 }
632 data = 0;
633 for (cnt = 0; cnt < 8; cnt++) {
634 data >>= 3;
635 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) {
636 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
637 if (gold_sadj[0] >= dlli) {
638 dlli = (gold_sadj[0] - dlli) >> 1;
639 if (dlli > 3) {
640 dlli = 3;
641 }
642 } else {
643 dlli = (dlli - gold_sadj[0]) >> 1;
644 if (dlli > 4) {
645 dlli = 4;
646 }
647 dlli = (8 - dlli) & 0x7;
648 }
649 data |= dlli << 21;
650 }
651 }
652 moutdwm(ast, 0x1E6E0080, data);
653 604
654 data = 0; 605 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
655 for (cnt = 8; cnt < 16; cnt++) { 606 moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
656 data >>= 3; 607 for (loop = 0; loop < 2; loop++) {
657 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) { 608 if (cbr_test3(ast))
658 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; 609 break;
659 if (gold_sadj[1] >= dlli) {
660 dlli = (gold_sadj[1] - dlli) >> 1;
661 if (dlli > 3) {
662 dlli = 3;
663 } else {
664 dlli = (dlli - 1) & 0x7;
665 }
666 } else {
667 dlli = (dlli - gold_sadj[1]) >> 1;
668 dlli += 1;
669 if (dlli > 4) {
670 dlli = 4;
671 }
672 dlli = (8 - dlli) & 0x7;
673 }
674 data |= dlli << 21;
675 } 610 }
611 if (loop == 2)
612 return 0;
676 } 613 }
677 moutdwm(ast, 0x1E6E0084, data); 614 return 1;
678 615}
679} /* finetuneDQI */
680#endif
681 616
682static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) 617static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
683{ 618{
684 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt; 619 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
685 620 bool status = false;
686FINETUNE_START: 621FINETUNE_START:
687 for (cnt = 0; cnt < 16; cnt++) { 622 for (cnt = 0; cnt < 16; cnt++) {
688 dllmin[cnt] = 0xff; 623 dllmin[cnt] = 0xff;
@@ -691,14 +626,6 @@ FINETUNE_START:
691 passcnt = 0; 626 passcnt = 0;
692 for (dlli = 0; dlli < 76; dlli++) { 627 for (dlli = 0; dlli < 76; dlli++) {
693 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); 628 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
694 /* Wait DQSI latch phase calibration */
695 moutdwm(ast, 0x1E6E0074, 0x00000010);
696 moutdwm(ast, 0x1E6E0070, 0x00000003);
697 do {
698 data = mindwm(ast, 0x1E6E0070);
699 } while (!(data & 0x00001000));
700 moutdwm(ast, 0x1E6E0070, 0x00000000);
701
702 moutdwm(ast, 0x1E6E0074, CBR_SIZE1); 629 moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
703 data = cbr_scan2(ast); 630 data = cbr_scan2(ast);
704 if (data != 0) { 631 if (data != 0) {
@@ -727,9 +654,13 @@ FINETUNE_START:
727 passcnt++; 654 passcnt++;
728 } 655 }
729 } 656 }
657 if (retry++ > 10)
658 goto FINETUNE_DONE;
730 if (passcnt != 16) { 659 if (passcnt != 16) {
731 goto FINETUNE_START; 660 goto FINETUNE_START;
732 } 661 }
662 status = true;
663FINETUNE_DONE:
733 gold_sadj[0] = gold_sadj[0] >> 4; 664 gold_sadj[0] = gold_sadj[0] >> 4;
734 gold_sadj[1] = gold_sadj[0]; 665 gold_sadj[1] = gold_sadj[0];
735 666
@@ -779,145 +710,107 @@ FINETUNE_START:
779 } 710 }
780 } 711 }
781 moutdwm(ast, 0x1E6E0084, data); 712 moutdwm(ast, 0x1E6E0084, data);
782 713 return status;
783} /* finetuneDQI_L */ 714} /* finetuneDQI_L */
784 715
785static void finetuneDQI_L2(struct ast_private *ast, struct ast2300_dram_param *param) 716static void finetuneDQSI(struct ast_private *ast)
786{ 717{
787 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, data2; 718 u32 dlli, dqsip, dqidly;
719 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
720 u32 g_dqidly, g_dqsip, g_margin, g_side;
721 u16 pass[32][2][2];
722 char tag[2][76];
723
724 /* Disable DQI CBR */
725 reg_mcr0c = mindwm(ast, 0x1E6E000C);
726 reg_mcr18 = mindwm(ast, 0x1E6E0018);
727 reg_mcr18 &= 0x0000ffff;
728 moutdwm(ast, 0x1E6E0018, reg_mcr18);
788 729
789 for (cnt = 0; cnt < 16; cnt++) {
790 dllmin[cnt] = 0xff;
791 dllmax[cnt] = 0x0;
792 }
793 passcnt = 0;
794 for (dlli = 0; dlli < 76; dlli++) { 730 for (dlli = 0; dlli < 76; dlli++) {
795 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); 731 tag[0][dlli] = 0x0;
796 /* Wait DQSI latch phase calibration */ 732 tag[1][dlli] = 0x0;
797 moutdwm(ast, 0x1E6E0074, 0x00000010);
798 moutdwm(ast, 0x1E6E0070, 0x00000003);
799 do {
800 data = mindwm(ast, 0x1E6E0070);
801 } while (!(data & 0x00001000));
802 moutdwm(ast, 0x1E6E0070, 0x00000000);
803
804 moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
805 data = cbr_scan2(ast);
806 if (data != 0) {
807 mask = 0x00010001;
808 for (cnt = 0; cnt < 16; cnt++) {
809 if (data & mask) {
810 if (dllmin[cnt] > dlli) {
811 dllmin[cnt] = dlli;
812 }
813 if (dllmax[cnt] < dlli) {
814 dllmax[cnt] = dlli;
815 }
816 }
817 mask <<= 1;
818 }
819 passcnt++;
820 } else if (passcnt >= CBR_THRESHOLD2) {
821 break;
822 }
823 } 733 }
824 gold_sadj[0] = 0x0; 734 for (dqidly = 0; dqidly < 32; dqidly++) {
825 gold_sadj[1] = 0xFF; 735 pass[dqidly][0][0] = 0xff;
826 for (cnt = 0; cnt < 8; cnt++) { 736 pass[dqidly][0][1] = 0x0;
827 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 737 pass[dqidly][1][0] = 0xff;
828 if (gold_sadj[0] < dllmin[cnt]) { 738 pass[dqidly][1][1] = 0x0;
829 gold_sadj[0] = dllmin[cnt];
830 }
831 if (gold_sadj[1] > dllmax[cnt]) {
832 gold_sadj[1] = dllmax[cnt];
833 }
834 }
835 } 739 }
836 gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1; 740 for (dqidly = 0; dqidly < 32; dqidly++) {
837 gold_sadj[1] = mindwm(ast, 0x1E6E0080); 741 passcnt[0] = passcnt[1] = 0;
838 742 for (dqsip = 0; dqsip < 2; dqsip++) {
839 data = 0; 743 moutdwm(ast, 0x1E6E000C, 0);
840 for (cnt = 0; cnt < 8; cnt++) { 744 moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
841 data >>= 3; 745 moutdwm(ast, 0x1E6E000C, reg_mcr0c);
842 data2 = gold_sadj[1] & 0x7; 746 for (dlli = 0; dlli < 76; dlli++) {
843 gold_sadj[1] >>= 3; 747 moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
844 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 748 moutdwm(ast, 0x1E6E0070, 0);
845 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; 749 moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
846 if (gold_sadj[0] >= dlli) { 750 if (cbr_scan3(ast)) {
847 dlli = (gold_sadj[0] - dlli) >> 1; 751 if (dlli == 0)
848 if (dlli > 0) { 752 break;
849 dlli = 1; 753 passcnt[dqsip]++;
850 } 754 tag[dqsip][dlli] = 'P';
851 if (data2 != 3) { 755 if (dlli < pass[dqidly][dqsip][0])
852 data2 = (data2 + dlli) & 0x7; 756 pass[dqidly][dqsip][0] = (u16) dlli;
853 } 757 if (dlli > pass[dqidly][dqsip][1])
854 } else { 758 pass[dqidly][dqsip][1] = (u16) dlli;
855 dlli = (dlli - gold_sadj[0]) >> 1; 759 } else if (passcnt[dqsip] >= 5)
856 if (dlli > 0) { 760 break;
857 dlli = 1; 761 else {
858 } 762 pass[dqidly][dqsip][0] = 0xff;
859 if (data2 != 4) { 763 pass[dqidly][dqsip][1] = 0x0;
860 data2 = (data2 - dlli) & 0x7;
861 } 764 }
862 } 765 }
863 } 766 }
864 data |= data2 << 21; 767 if (passcnt[0] == 0 && passcnt[1] == 0)
768 dqidly++;
865 } 769 }
866 moutdwm(ast, 0x1E6E0080, data); 770 /* Search margin */
867 771 g_dqidly = g_dqsip = g_margin = g_side = 0;
868 gold_sadj[0] = 0x0; 772
869 gold_sadj[1] = 0xFF; 773 for (dqidly = 0; dqidly < 32; dqidly++) {
870 for (cnt = 8; cnt < 16; cnt++) { 774 for (dqsip = 0; dqsip < 2; dqsip++) {
871 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 775 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
872 if (gold_sadj[0] < dllmin[cnt]) { 776 continue;
873 gold_sadj[0] = dllmin[cnt]; 777 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
874 } 778 if ((diff+2) < g_margin)
875 if (gold_sadj[1] > dllmax[cnt]) { 779 continue;
876 gold_sadj[1] = dllmax[cnt]; 780 passcnt[0] = passcnt[1] = 0;
877 } 781 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
878 } 782 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
879 } 783 if (passcnt[0] > passcnt[1])
880 gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1; 784 passcnt[0] = passcnt[1];
881 gold_sadj[1] = mindwm(ast, 0x1E6E0084); 785 passcnt[1] = 0;
882 786 if (passcnt[0] > g_side)
883 data = 0; 787 passcnt[1] = passcnt[0] - g_side;
884 for (cnt = 8; cnt < 16; cnt++) { 788 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
885 data >>= 3; 789 g_margin = diff;
886 data2 = gold_sadj[1] & 0x7; 790 g_dqidly = dqidly;
887 gold_sadj[1] >>= 3; 791 g_dqsip = dqsip;
888 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 792 g_side = passcnt[0];
889 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; 793 } else if (passcnt[1] > 1 && g_side < 8) {
890 if (gold_sadj[0] >= dlli) { 794 if (diff > g_margin)
891 dlli = (gold_sadj[0] - dlli) >> 1; 795 g_margin = diff;
892 if (dlli > 0) { 796 g_dqidly = dqidly;
893 dlli = 1; 797 g_dqsip = dqsip;
894 } 798 g_side = passcnt[0];
895 if (data2 != 3) {
896 data2 = (data2 + dlli) & 0x7;
897 }
898 } else {
899 dlli = (dlli - gold_sadj[0]) >> 1;
900 if (dlli > 0) {
901 dlli = 1;
902 }
903 if (data2 != 4) {
904 data2 = (data2 - dlli) & 0x7;
905 }
906 } 799 }
907 } 800 }
908 data |= data2 << 21;
909 } 801 }
910 moutdwm(ast, 0x1E6E0084, data); 802 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
911 803 moutdwm(ast, 0x1E6E0018, reg_mcr18);
912} /* finetuneDQI_L2 */
913 804
914static void cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param) 805}
806static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
915{ 807{
916 u32 dllmin[2], dllmax[2], dlli, data, data2, passcnt; 808 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
809 bool status = false;
917 810
918 811 finetuneDQSI(ast);
919 finetuneDQI_L(ast, param); 812 if (finetuneDQI_L(ast, param) == false)
920 finetuneDQI_L2(ast, param); 813 return status;
921 814
922CBR_START2: 815CBR_START2:
923 dllmin[0] = dllmin[1] = 0xff; 816 dllmin[0] = dllmin[1] = 0xff;
@@ -925,14 +818,6 @@ CBR_START2:
925 passcnt = 0; 818 passcnt = 0;
926 for (dlli = 0; dlli < 76; dlli++) { 819 for (dlli = 0; dlli < 76; dlli++) {
927 moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); 820 moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
928 /* Wait DQSI latch phase calibration */
929 moutdwm(ast, 0x1E6E0074, 0x00000010);
930 moutdwm(ast, 0x1E6E0070, 0x00000003);
931 do {
932 data = mindwm(ast, 0x1E6E0070);
933 } while (!(data & 0x00001000));
934 moutdwm(ast, 0x1E6E0070, 0x00000000);
935
936 moutdwm(ast, 0x1E6E0074, CBR_SIZE2); 821 moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
937 data = cbr_scan(ast); 822 data = cbr_scan(ast);
938 if (data != 0) { 823 if (data != 0) {
@@ -957,34 +842,21 @@ CBR_START2:
957 break; 842 break;
958 } 843 }
959 } 844 }
845 if (retry++ > 10)
846 goto CBR_DONE2;
960 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) { 847 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
961 goto CBR_START2; 848 goto CBR_START2;
962 } 849 }
963 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) { 850 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
964 goto CBR_START2; 851 goto CBR_START2;
965 } 852 }
853 status = true;
854CBR_DONE2:
966 dlli = (dllmin[1] + dllmax[1]) >> 1; 855 dlli = (dllmin[1] + dllmax[1]) >> 1;
967 dlli <<= 8; 856 dlli <<= 8;
968 dlli += (dllmin[0] + dllmax[0]) >> 1; 857 dlli += (dllmin[0] + dllmax[0]) >> 1;
969 moutdwm(ast, 0x1E6E0068, (mindwm(ast, 0x1E6E0068) & 0xFFFF) | (dlli << 16)); 858 moutdwm(ast, 0x1E6E0068, mindwm(ast, 0x1E720058) | (dlli << 16));
970 859 return status;
971 data = (mindwm(ast, 0x1E6E0080) >> 24) & 0x1F;
972 data2 = (mindwm(ast, 0x1E6E0018) & 0xff80ffff) | (data << 16);
973 moutdwm(ast, 0x1E6E0018, data2);
974 moutdwm(ast, 0x1E6E0024, 0x8001 | (data << 1) | (param->dll2_finetune_step << 8));
975
976 /* Wait DQSI latch phase calibration */
977 moutdwm(ast, 0x1E6E0074, 0x00000010);
978 moutdwm(ast, 0x1E6E0070, 0x00000003);
979 do {
980 data = mindwm(ast, 0x1E6E0070);
981 } while (!(data & 0x00001000));
982 moutdwm(ast, 0x1E6E0070, 0x00000000);
983 moutdwm(ast, 0x1E6E0070, 0x00000003);
984 do {
985 data = mindwm(ast, 0x1E6E0070);
986 } while (!(data & 0x00001000));
987 moutdwm(ast, 0x1E6E0070, 0x00000000);
988} /* CBRDLL2 */ 860} /* CBRDLL2 */
989 861
990static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param) 862static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
@@ -1015,11 +887,24 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1015 param->reg_DQSIC = 0x000000BA; 887 param->reg_DQSIC = 0x000000BA;
1016 param->reg_MRS = 0x04001400 | trap_MRS; 888 param->reg_MRS = 0x04001400 | trap_MRS;
1017 param->reg_EMRS = 0x00000000; 889 param->reg_EMRS = 0x00000000;
1018 param->reg_IOZ = 0x00000034; 890 param->reg_IOZ = 0x00000023;
1019 param->reg_DQIDLY = 0x00000074; 891 param->reg_DQIDLY = 0x00000074;
1020 param->reg_FREQ = 0x00004DC0; 892 param->reg_FREQ = 0x00004DC0;
1021 param->madj_max = 96; 893 param->madj_max = 96;
1022 param->dll2_finetune_step = 3; 894 param->dll2_finetune_step = 3;
895 switch (param->dram_chipid) {
896 default:
897 case AST_DRAM_512Mx16:
898 case AST_DRAM_1Gx16:
899 param->reg_AC2 = 0xAA007613 | trap_AC2;
900 break;
901 case AST_DRAM_2Gx16:
902 param->reg_AC2 = 0xAA00761C | trap_AC2;
903 break;
904 case AST_DRAM_4Gx16:
905 param->reg_AC2 = 0xAA007636 | trap_AC2;
906 break;
907 }
1023 break; 908 break;
1024 default: 909 default:
1025 case 396: 910 case 396:
@@ -1033,7 +918,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1033 param->reg_IOZ = 0x00000034; 918 param->reg_IOZ = 0x00000034;
1034 param->reg_DRV = 0x000000FA; 919 param->reg_DRV = 0x000000FA;
1035 param->reg_DQIDLY = 0x00000089; 920 param->reg_DQIDLY = 0x00000089;
1036 param->reg_FREQ = 0x000050C0; 921 param->reg_FREQ = 0x00005040;
1037 param->madj_max = 96; 922 param->madj_max = 96;
1038 param->dll2_finetune_step = 4; 923 param->dll2_finetune_step = 4;
1039 924
@@ -1060,7 +945,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1060 param->reg_DQSIC = 0x000000E2; 945 param->reg_DQSIC = 0x000000E2;
1061 param->reg_MRS = 0x04001600 | trap_MRS; 946 param->reg_MRS = 0x04001600 | trap_MRS;
1062 param->reg_EMRS = 0x00000000; 947 param->reg_EMRS = 0x00000000;
1063 param->reg_IOZ = 0x00000034; 948 param->reg_IOZ = 0x00000023;
1064 param->reg_DRV = 0x000000FA; 949 param->reg_DRV = 0x000000FA;
1065 param->reg_DQIDLY = 0x00000089; 950 param->reg_DQIDLY = 0x00000089;
1066 param->reg_FREQ = 0x000050C0; 951 param->reg_FREQ = 0x000050C0;
@@ -1218,8 +1103,9 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1218 1103
1219static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param) 1104static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1220{ 1105{
1221 u32 data, data2; 1106 u32 data, data2, retry = 0;
1222 1107
1108ddr3_init_start:
1223 moutdwm(ast, 0x1E6E0000, 0xFC600309); 1109 moutdwm(ast, 0x1E6E0000, 0xFC600309);
1224 moutdwm(ast, 0x1E6E0018, 0x00000100); 1110 moutdwm(ast, 0x1E6E0018, 0x00000100);
1225 moutdwm(ast, 0x1E6E0024, 0x00000000); 1111 moutdwm(ast, 0x1E6E0024, 0x00000000);
@@ -1239,8 +1125,8 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1239 moutdwm(ast, 0x1E6E0080, 0x00000000); 1125 moutdwm(ast, 0x1E6E0080, 0x00000000);
1240 moutdwm(ast, 0x1E6E0084, 0x00000000); 1126 moutdwm(ast, 0x1E6E0084, 0x00000000);
1241 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1127 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1242 moutdwm(ast, 0x1E6E0018, 0x4040A170); 1128 moutdwm(ast, 0x1E6E0018, 0x4000A170);
1243 moutdwm(ast, 0x1E6E0018, 0x20402370); 1129 moutdwm(ast, 0x1E6E0018, 0x00002370);
1244 moutdwm(ast, 0x1E6E0038, 0x00000000); 1130 moutdwm(ast, 0x1E6E0038, 0x00000000);
1245 moutdwm(ast, 0x1E6E0040, 0xFF444444); 1131 moutdwm(ast, 0x1E6E0040, 0xFF444444);
1246 moutdwm(ast, 0x1E6E0044, 0x22222222); 1132 moutdwm(ast, 0x1E6E0044, 0x22222222);
@@ -1259,11 +1145,6 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1259 do { 1145 do {
1260 data = mindwm(ast, 0x1E6E001C); 1146 data = mindwm(ast, 0x1E6E001C);
1261 } while (!(data & 0x08000000)); 1147 } while (!(data & 0x08000000));
1262 moutdwm(ast, 0x1E6E0034, 0x00000001);
1263 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1264 udelay(10);
1265 moutdwm(ast, 0x1E6E000C, 0x00000000);
1266 moutdwm(ast, 0x1E6E0034, 0x00000000);
1267 data = mindwm(ast, 0x1E6E001C); 1148 data = mindwm(ast, 0x1E6E001C);
1268 data = (data >> 8) & 0xff; 1149 data = (data >> 8) & 0xff;
1269 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1150 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
@@ -1292,14 +1173,10 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1292 data = mindwm(ast, 0x1E6E001C); 1173 data = mindwm(ast, 0x1E6E001C);
1293 } while (!(data & 0x08000000)); 1174 } while (!(data & 0x08000000));
1294 1175
1295 moutdwm(ast, 0x1E6E0034, 0x00000001);
1296 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1297 udelay(10);
1298 moutdwm(ast, 0x1E6E000C, 0x00000000);
1299 moutdwm(ast, 0x1E6E0034, 0x00000000);
1300 data = mindwm(ast, 0x1E6E001C); 1176 data = mindwm(ast, 0x1E6E001C);
1301 data = (data >> 8) & 0xff; 1177 data = (data >> 8) & 0xff;
1302 } 1178 }
1179 moutdwm(ast, 0x1E720058, mindwm(ast, 0x1E6E0068) & 0xffff);
1303 data = mindwm(ast, 0x1E6E0018) | 0xC00; 1180 data = mindwm(ast, 0x1E6E0018) | 0xC00;
1304 moutdwm(ast, 0x1E6E0018, data); 1181 moutdwm(ast, 0x1E6E0018, data);
1305 1182
@@ -1317,7 +1194,7 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1317 moutdwm(ast, 0x1E6E000C, 0x00005C08); 1194 moutdwm(ast, 0x1E6E000C, 0x00005C08);
1318 moutdwm(ast, 0x1E6E0028, 0x00000001); 1195 moutdwm(ast, 0x1E6E0028, 0x00000001);
1319 1196
1320 moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); 1197 moutdwm(ast, 0x1E6E000C, 0x00005C01);
1321 data = 0; 1198 data = 0;
1322 if (param->wodt) { 1199 if (param->wodt) {
1323 data = 0x300; 1200 data = 0x300;
@@ -1327,16 +1204,9 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1327 } 1204 }
1328 moutdwm(ast, 0x1E6E0034, data | 0x3); 1205 moutdwm(ast, 0x1E6E0034, data | 0x3);
1329 1206
1330 /* Wait DQI delay lock */
1331 do {
1332 data = mindwm(ast, 0x1E6E0080);
1333 } while (!(data & 0x40000000));
1334 /* Wait DQSI delay lock */
1335 do {
1336 data = mindwm(ast, 0x1E6E0020);
1337 } while (!(data & 0x00000800));
1338 /* Calibrate the DQSI delay */ 1207 /* Calibrate the DQSI delay */
1339 cbr_dll2(ast, param); 1208 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1209 goto ddr3_init_start;
1340 1210
1341 moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1211 moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1342 /* ECC Memory Initialization */ 1212 /* ECC Memory Initialization */
@@ -1403,6 +1273,21 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1403 param->reg_FREQ = 0x00004DC0; 1273 param->reg_FREQ = 0x00004DC0;
1404 param->madj_max = 96; 1274 param->madj_max = 96;
1405 param->dll2_finetune_step = 3; 1275 param->dll2_finetune_step = 3;
1276 switch (param->dram_chipid) {
1277 default:
1278 case AST_DRAM_512Mx16:
1279 param->reg_AC2 = 0xAA009012 | trap_AC2;
1280 break;
1281 case AST_DRAM_1Gx16:
1282 param->reg_AC2 = 0xAA009016 | trap_AC2;
1283 break;
1284 case AST_DRAM_2Gx16:
1285 param->reg_AC2 = 0xAA009023 | trap_AC2;
1286 break;
1287 case AST_DRAM_4Gx16:
1288 param->reg_AC2 = 0xAA00903B | trap_AC2;
1289 break;
1290 }
1406 break; 1291 break;
1407 default: 1292 default:
1408 case 396: 1293 case 396:
@@ -1417,7 +1302,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1417 param->reg_DRV = 0x000000FA; 1302 param->reg_DRV = 0x000000FA;
1418 param->reg_IOZ = 0x00000034; 1303 param->reg_IOZ = 0x00000034;
1419 param->reg_DQIDLY = 0x00000089; 1304 param->reg_DQIDLY = 0x00000089;
1420 param->reg_FREQ = 0x000050C0; 1305 param->reg_FREQ = 0x00005040;
1421 param->madj_max = 96; 1306 param->madj_max = 96;
1422 param->dll2_finetune_step = 4; 1307 param->dll2_finetune_step = 4;
1423 1308
@@ -1588,8 +1473,9 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1588 1473
1589static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param) 1474static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1590{ 1475{
1591 u32 data, data2; 1476 u32 data, data2, retry = 0;
1592 1477
1478ddr2_init_start:
1593 moutdwm(ast, 0x1E6E0000, 0xFC600309); 1479 moutdwm(ast, 0x1E6E0000, 0xFC600309);
1594 moutdwm(ast, 0x1E6E0018, 0x00000100); 1480 moutdwm(ast, 0x1E6E0018, 0x00000100);
1595 moutdwm(ast, 0x1E6E0024, 0x00000000); 1481 moutdwm(ast, 0x1E6E0024, 0x00000000);
@@ -1607,8 +1493,8 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1607 moutdwm(ast, 0x1E6E0080, 0x00000000); 1493 moutdwm(ast, 0x1E6E0080, 0x00000000);
1608 moutdwm(ast, 0x1E6E0084, 0x00000000); 1494 moutdwm(ast, 0x1E6E0084, 0x00000000);
1609 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1495 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1610 moutdwm(ast, 0x1E6E0018, 0x4040A130); 1496 moutdwm(ast, 0x1E6E0018, 0x4000A130);
1611 moutdwm(ast, 0x1E6E0018, 0x20402330); 1497 moutdwm(ast, 0x1E6E0018, 0x00002330);
1612 moutdwm(ast, 0x1E6E0038, 0x00000000); 1498 moutdwm(ast, 0x1E6E0038, 0x00000000);
1613 moutdwm(ast, 0x1E6E0040, 0xFF808000); 1499 moutdwm(ast, 0x1E6E0040, 0xFF808000);
1614 moutdwm(ast, 0x1E6E0044, 0x88848466); 1500 moutdwm(ast, 0x1E6E0044, 0x88848466);
@@ -1628,11 +1514,6 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1628 do { 1514 do {
1629 data = mindwm(ast, 0x1E6E001C); 1515 data = mindwm(ast, 0x1E6E001C);
1630 } while (!(data & 0x08000000)); 1516 } while (!(data & 0x08000000));
1631 moutdwm(ast, 0x1E6E0034, 0x00000001);
1632 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1633 udelay(10);
1634 moutdwm(ast, 0x1E6E000C, 0x00000000);
1635 moutdwm(ast, 0x1E6E0034, 0x00000000);
1636 data = mindwm(ast, 0x1E6E001C); 1517 data = mindwm(ast, 0x1E6E001C);
1637 data = (data >> 8) & 0xff; 1518 data = (data >> 8) & 0xff;
1638 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1519 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
@@ -1661,14 +1542,10 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1661 data = mindwm(ast, 0x1E6E001C); 1542 data = mindwm(ast, 0x1E6E001C);
1662 } while (!(data & 0x08000000)); 1543 } while (!(data & 0x08000000));
1663 1544
1664 moutdwm(ast, 0x1E6E0034, 0x00000001);
1665 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1666 udelay(10);
1667 moutdwm(ast, 0x1E6E000C, 0x00000000);
1668 moutdwm(ast, 0x1E6E0034, 0x00000000);
1669 data = mindwm(ast, 0x1E6E001C); 1545 data = mindwm(ast, 0x1E6E001C);
1670 data = (data >> 8) & 0xff; 1546 data = (data >> 8) & 0xff;
1671 } 1547 }
1548 moutdwm(ast, 0x1E720058, mindwm(ast, 0x1E6E0008) & 0xffff);
1672 data = mindwm(ast, 0x1E6E0018) | 0xC00; 1549 data = mindwm(ast, 0x1E6E0018) | 0xC00;
1673 moutdwm(ast, 0x1E6E0018, data); 1550 moutdwm(ast, 0x1E6E0018, data);
1674 1551
@@ -1702,16 +1579,9 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1702 moutdwm(ast, 0x1E6E0034, data | 0x3); 1579 moutdwm(ast, 0x1E6E0034, data | 0x3);
1703 moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1580 moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1704 1581
1705 /* Wait DQI delay lock */
1706 do {
1707 data = mindwm(ast, 0x1E6E0080);
1708 } while (!(data & 0x40000000));
1709 /* Wait DQSI delay lock */
1710 do {
1711 data = mindwm(ast, 0x1E6E0020);
1712 } while (!(data & 0x00000800));
1713 /* Calibrate the DQSI delay */ 1582 /* Calibrate the DQSI delay */
1714 cbr_dll2(ast, param); 1583 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1584 goto ddr2_init_start;
1715 1585
1716 /* ECC Memory Initialization */ 1586 /* ECC Memory Initialization */
1717#ifdef ECC 1587#ifdef ECC
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-15 14:10:04 -0400